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Merge branch 'osd-devel' into nfs-for-next
[linux.git] / arch / arm / mach-at91 / at91sam9260_devices.c
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86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9260_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
c6686ff9 15#include <linux/dma-mapping.h>
2f8163ba 16#include <linux/gpio.h>
86ad76bb 17#include <linux/platform_device.h>
f230d3f5 18#include <linux/i2c-gpio.h>
86ad76bb 19
a09e64fb 20#include <mach/board.h>
a09e64fb
RK		 21#include <mach/cpu.h>
22#include <mach/at91sam9260.h>
23#include <mach/at91sam9260_matrix.h>
24#include <mach/at91sam9_smc.h>
86ad76bb
AV		 25
26#include "generic.h"
27
86ad76bb
AV		 28
29/* --------------------------------------------------------------------
30 * USB Host
31 * -------------------------------------------------------------------- */
32
33#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 34static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 35static struct at91_usbh_data usbh_data;
36
37static struct resource usbh_resources[] = {
38 [0] = {
39 .start = AT91SAM9260_UHP_BASE,
40 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
44 .start = AT91SAM9260_ID_UHP,
45 .end = AT91SAM9260_ID_UHP,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static struct platform_device at91_usbh_device = {
51 .name = "at91_ohci",
52 .id = -1,
53 .dev = {
54 .dma_mask = &ohci_dmamask,
c6686ff9 55 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 56 .platform_data = &usbh_data,
57 },
58 .resource = usbh_resources,
59 .num_resources = ARRAY_SIZE(usbh_resources),
60};
61
62void __init at91_add_device_usbh(struct at91_usbh_data *data)
63{
1fcaea7e
TP		 64 int i;
65
86ad76bb
AV		 66 if (!data)
67 return;
68
1fcaea7e
TP		 69 /* Enable overcurrent notification */
70 for (i = 0; i < data->ports; i++) {
71 if (data->overcurrent_pin[i])
72 at91_set_gpio_input(data->overcurrent_pin[i], 1);
73 }
74
86ad76bb
AV		 75 usbh_data = *data;
76 platform_device_register(&at91_usbh_device);
77}
78#else
79void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
80#endif
81
82
83/* --------------------------------------------------------------------
84 * USB Device (Gadget)
85 * -------------------------------------------------------------------- */
86
87#ifdef CONFIG_USB_GADGET_AT91
88static struct at91_udc_data udc_data;
89
90static struct resource udc_resources[] = {
91 [0] = {
92 .start = AT91SAM9260_BASE_UDP,
93 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91SAM9260_ID_UDP,
98 .end = AT91SAM9260_ID_UDP,
99 .flags = IORESOURCE_IRQ,
100 },
101};
102
103static struct platform_device at91_udc_device = {
104 .name = "at91_udc",
105 .id = -1,
106 .dev = {
107 .platform_data = &udc_data,
108 },
109 .resource = udc_resources,
110 .num_resources = ARRAY_SIZE(udc_resources),
111};
112
113void __init at91_add_device_udc(struct at91_udc_data *data)
114{
115 if (!data)
116 return;
117
118 if (data->vbus_pin) {
119 at91_set_gpio_input(data->vbus_pin, 0);
120 at91_set_deglitch(data->vbus_pin, 1);
121 }
122
123 /* Pullup pin is handled internally by USB device peripheral */
124
125 udc_data = *data;
126 platform_device_register(&at91_udc_device);
127}
128#else
129void __init at91_add_device_udc(struct at91_udc_data *data) {}
130#endif
131
132
133/* --------------------------------------------------------------------
134 * Ethernet
135 * -------------------------------------------------------------------- */
136
137#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
c6686ff9 138static u64 eth_dmamask = DMA_BIT_MASK(32);
a93d48cc 139static struct at91_eth_data eth_data;
86ad76bb
AV		 140
141static struct resource eth_resources[] = {
142 [0] = {
143 .start = AT91SAM9260_BASE_EMAC,
144 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 [1] = {
148 .start = AT91SAM9260_ID_EMAC,
149 .end = AT91SAM9260_ID_EMAC,
150 .flags = IORESOURCE_IRQ,
151 },
152};
153
154static struct platform_device at91sam9260_eth_device = {
155 .name = "macb",
156 .id = -1,
157 .dev = {
158 .dma_mask = &eth_dmamask,
c6686ff9 159 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 160 .platform_data = &eth_data,
161 },
162 .resource = eth_resources,
163 .num_resources = ARRAY_SIZE(eth_resources),
164};
165
a93d48cc 166void __init at91_add_device_eth(struct at91_eth_data *data)
86ad76bb
AV		 167{
168 if (!data)
169 return;
170
171 if (data->phy_irq_pin) {
172 at91_set_gpio_input(data->phy_irq_pin, 0);
173 at91_set_deglitch(data->phy_irq_pin, 1);
174 }
175
176 /* Pins used for MII and RMII */
177 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
178 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
179 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
180 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
181 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
182 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
183 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
184 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
185 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
186 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
187
188 if (!data->is_rmii) {
189 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
190 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
191 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
192 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
193 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
194 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
195 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
196 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
197 }
198
199 eth_data = *data;
200 platform_device_register(&at91sam9260_eth_device);
201}
202#else
a93d48cc 203void __init at91_add_device_eth(struct at91_eth_data *data) {}
86ad76bb
AV		 204#endif
205
206
207/* --------------------------------------------------------------------
208 * MMC / SD
209 * -------------------------------------------------------------------- */
210
211#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 212static u64 mmc_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 213static struct at91_mmc_data mmc_data;
214
215static struct resource mmc_resources[] = {
216 [0] = {
217 .start = AT91SAM9260_BASE_MCI,
218 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 [1] = {
222 .start = AT91SAM9260_ID_MCI,
223 .end = AT91SAM9260_ID_MCI,
224 .flags = IORESOURCE_IRQ,
225 },
226};
227
228static struct platform_device at91sam9260_mmc_device = {
229 .name = "at91_mci",
230 .id = -1,
231 .dev = {
232 .dma_mask = &mmc_dmamask,
c6686ff9 233 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 234 .platform_data = &mmc_data,
235 },
236 .resource = mmc_resources,
237 .num_resources = ARRAY_SIZE(mmc_resources),
238};
239
d0760b3b 240void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
86ad76bb
AV		 241{
242 if (!data)
243 return;
244
245 /* input/irq */
246 if (data->det_pin) {
247 at91_set_gpio_input(data->det_pin, 1);
248 at91_set_deglitch(data->det_pin, 1);
249 }
250 if (data->wp_pin)
251 at91_set_gpio_input(data->wp_pin, 1);
252 if (data->vcc_pin)
253 at91_set_gpio_output(data->vcc_pin, 0);
254
255 /* CLK */
256 at91_set_A_periph(AT91_PIN_PA8, 0);
257
258 if (data->slot_b) {
259 /* CMD */
260 at91_set_B_periph(AT91_PIN_PA1, 1);
261
262 /* DAT0, maybe DAT1..DAT3 */
263 at91_set_B_periph(AT91_PIN_PA0, 1);
264 if (data->wire4) {
265 at91_set_B_periph(AT91_PIN_PA5, 1);
266 at91_set_B_periph(AT91_PIN_PA4, 1);
267 at91_set_B_periph(AT91_PIN_PA3, 1);
268 }
269 } else {
270 /* CMD */
271 at91_set_A_periph(AT91_PIN_PA7, 1);
272
273 /* DAT0, maybe DAT1..DAT3 */
274 at91_set_A_periph(AT91_PIN_PA6, 1);
275 if (data->wire4) {
276 at91_set_A_periph(AT91_PIN_PA9, 1);
277 at91_set_A_periph(AT91_PIN_PA10, 1);
278 at91_set_A_periph(AT91_PIN_PA11, 1);
279 }
280 }
281
282 mmc_data = *data;
283 platform_device_register(&at91sam9260_mmc_device);
284}
285#else
d0760b3b 286void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
86ad76bb
AV		 287#endif
288
864f38eb
RE		 289/* --------------------------------------------------------------------
290 * MMC / SD Slot for Atmel MCI Driver
291 * -------------------------------------------------------------------- */
292
293#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
294static u64 mmc_dmamask = DMA_BIT_MASK(32);
295static struct mci_platform_data mmc_data;
296
297static struct resource mmc_resources[] = {
298 [0] = {
299 .start = AT91SAM9260_BASE_MCI,
300 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
301 .flags = IORESOURCE_MEM,
302 },
303 [1] = {
304 .start = AT91SAM9260_ID_MCI,
305 .end = AT91SAM9260_ID_MCI,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310static struct platform_device at91sam9260_mmc_device = {
311 .name = "atmel_mci",
312 .id = -1,
313 .dev = {
314 .dma_mask = &mmc_dmamask,
315 .coherent_dma_mask = DMA_BIT_MASK(32),
316 .platform_data = &mmc_data,
317 },
318 .resource = mmc_resources,
319 .num_resources = ARRAY_SIZE(mmc_resources),
320};
321
322void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
323{
324 unsigned int i;
325 unsigned int slot_count = 0;
326
327 if (!data)
328 return;
329
2c96a293 330 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
864f38eb
RE		 331 if (data->slot[i].bus_width) {
332 /* input/irq */
333 if (data->slot[i].detect_pin) {
334 at91_set_gpio_input(data->slot[i].detect_pin, 1);
335 at91_set_deglitch(data->slot[i].detect_pin, 1);
336 }
337 if (data->slot[i].wp_pin)
338 at91_set_gpio_input(data->slot[i].wp_pin, 1);
339
340 switch (i) {
341 case 0:
342 /* CMD */
343 at91_set_A_periph(AT91_PIN_PA7, 1);
344 /* DAT0, maybe DAT1..DAT3 */
345 at91_set_A_periph(AT91_PIN_PA6, 1);
346 if (data->slot[i].bus_width == 4) {
347 at91_set_A_periph(AT91_PIN_PA9, 1);
348 at91_set_A_periph(AT91_PIN_PA10, 1);
349 at91_set_A_periph(AT91_PIN_PA11, 1);
350 }
351 slot_count++;
352 break;
353 case 1:
354 /* CMD */
355 at91_set_B_periph(AT91_PIN_PA1, 1);
356 /* DAT0, maybe DAT1..DAT3 */
357 at91_set_B_periph(AT91_PIN_PA0, 1);
358 if (data->slot[i].bus_width == 4) {
359 at91_set_B_periph(AT91_PIN_PA5, 1);
360 at91_set_B_periph(AT91_PIN_PA4, 1);
361 at91_set_B_periph(AT91_PIN_PA3, 1);
362 }
363 slot_count++;
364 break;
365 default:
366 printk(KERN_ERR
367 "AT91: SD/MMC slot %d not available\n", i);
368 break;
369 }
370 }
371 }
372
373 if (slot_count) {
374 /* CLK */
375 at91_set_A_periph(AT91_PIN_PA8, 0);
376
377 mmc_data = *data;
378 platform_device_register(&at91sam9260_mmc_device);
379 }
380}
381#else
382void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
383#endif
384
86ad76bb
AV		 385
386/* --------------------------------------------------------------------
387 * NAND / SmartMedia
388 * -------------------------------------------------------------------- */
389
f6ed6f78 390#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 391static struct atmel_nand_data nand_data;
86ad76bb
AV		 392
393#define NAND_BASE AT91_CHIPSELECT_3
394
395static struct resource nand_resources[] = {
d7a2415f 396 [0] = {
86ad76bb 397 .start = NAND_BASE,
22823558 398 .end = NAND_BASE + SZ_256M - 1,
86ad76bb 399 .flags = IORESOURCE_MEM,
d7a2415f
AV		 400 },
401 [1] = {
402 .start = AT91_BASE_SYS + AT91_ECC,
403 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
404 .flags = IORESOURCE_MEM,
86ad76bb
AV		 405 }
406};
407
408static struct platform_device at91sam9260_nand_device = {
3c3796cc 409 .name = "atmel_nand",
86ad76bb
AV		 410 .id = -1,
411 .dev = {
412 .platform_data = &nand_data,
413 },
414 .resource = nand_resources,
415 .num_resources = ARRAY_SIZE(nand_resources),
416};
417
3c3796cc 418void __init at91_add_device_nand(struct atmel_nand_data *data)
86ad76bb 419{
461d3b4d 420 unsigned long csa;
86ad76bb
AV		 421
422 if (!data)
423 return;
424
425 csa = at91_sys_read(AT91_MATRIX_EBICSA);
22823558 426 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb 427
86ad76bb
AV		 428 /* enable pin */
429 if (data->enable_pin)
430 at91_set_gpio_output(data->enable_pin, 1);
431
432 /* ready/busy pin */
433 if (data->rdy_pin)
434 at91_set_gpio_input(data->rdy_pin, 1);
435
436 /* card detect pin */
437 if (data->det_pin)
438 at91_set_gpio_input(data->det_pin, 1);
439
440 nand_data = *data;
441 platform_device_register(&at91sam9260_nand_device);
442}
443#else
3c3796cc 444void __init at91_add_device_nand(struct atmel_nand_data *data) {}
86ad76bb
AV		 445#endif
446
447
448/* --------------------------------------------------------------------
449 * TWI (i2c)
450 * -------------------------------------------------------------------- */
451
f230d3f5
AV		 452/*
453 * Prefer the GPIO code since the TWI controller isn't robust
454 * (gets overruns and underruns under load) and can only issue
455 * repeated STARTs in one scenario (the driver doesn't yet handle them).
456 */
457
458#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
459
460static struct i2c_gpio_platform_data pdata = {
461 .sda_pin = AT91_PIN_PA23,
462 .sda_is_open_drain = 1,
463 .scl_pin = AT91_PIN_PA24,
464 .scl_is_open_drain = 1,
465 .udelay = 2, /* ~100 kHz */
466};
467
468static struct platform_device at91sam9260_twi_device = {
469 .name = "i2c-gpio",
470 .id = -1,
471 .dev.platform_data = &pdata,
472};
473
474void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
475{
476 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
477 at91_set_multi_drive(AT91_PIN_PA23, 1);
478
479 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
480 at91_set_multi_drive(AT91_PIN_PA24, 1);
481
482 i2c_register_board_info(0, devices, nr_devices);
483 platform_device_register(&at91sam9260_twi_device);
484}
485
486#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 487
488static struct resource twi_resources[] = {
489 [0] = {
490 .start = AT91SAM9260_BASE_TWI,
491 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
492 .flags = IORESOURCE_MEM,
493 },
494 [1] = {
495 .start = AT91SAM9260_ID_TWI,
496 .end = AT91SAM9260_ID_TWI,
497 .flags = IORESOURCE_IRQ,
498 },
499};
500
501static struct platform_device at91sam9260_twi_device = {
502 .name = "at91_i2c",
503 .id = -1,
504 .resource = twi_resources,
505 .num_resources = ARRAY_SIZE(twi_resources),
506};
507
f230d3f5 508void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb
AV		 509{
510 /* pins used for TWI interface */
511 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
512 at91_set_multi_drive(AT91_PIN_PA23, 1);
513
514 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
515 at91_set_multi_drive(AT91_PIN_PA24, 1);
516
f230d3f5 517 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 518 platform_device_register(&at91sam9260_twi_device);
519}
520#else
f230d3f5 521void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 522#endif
523
524
525/* --------------------------------------------------------------------
526 * SPI
527 * -------------------------------------------------------------------- */
528
529#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 530static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 531
532static struct resource spi0_resources[] = {
533 [0] = {
534 .start = AT91SAM9260_BASE_SPI0,
535 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
536 .flags = IORESOURCE_MEM,
537 },
538 [1] = {
539 .start = AT91SAM9260_ID_SPI0,
540 .end = AT91SAM9260_ID_SPI0,
541 .flags = IORESOURCE_IRQ,
542 },
543};
544
545static struct platform_device at91sam9260_spi0_device = {
546 .name = "atmel_spi",
547 .id = 0,
548 .dev = {
549 .dma_mask = &spi_dmamask,
c6686ff9 550 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 551 },
552 .resource = spi0_resources,
553 .num_resources = ARRAY_SIZE(spi0_resources),
554};
555
556static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
557
558static struct resource spi1_resources[] = {
559 [0] = {
560 .start = AT91SAM9260_BASE_SPI1,
561 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 [1] = {
565 .start = AT91SAM9260_ID_SPI1,
566 .end = AT91SAM9260_ID_SPI1,
567 .flags = IORESOURCE_IRQ,
568 },
569};
570
571static struct platform_device at91sam9260_spi1_device = {
572 .name = "atmel_spi",
573 .id = 1,
574 .dev = {
575 .dma_mask = &spi_dmamask,
c6686ff9 576 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 577 },
578 .resource = spi1_resources,
579 .num_resources = ARRAY_SIZE(spi1_resources),
580};
581
582static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
583
584void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
585{
586 int i;
587 unsigned long cs_pin;
588 short enable_spi0 = 0;
589 short enable_spi1 = 0;
590
591 /* Choose SPI chip-selects */
592 for (i = 0; i < nr_devices; i++) {
593 if (devices[i].controller_data)
594 cs_pin = (unsigned long) devices[i].controller_data;
595 else if (devices[i].bus_num == 0)
596 cs_pin = spi0_standard_cs[devices[i].chip_select];
597 else
598 cs_pin = spi1_standard_cs[devices[i].chip_select];
599
600 if (devices[i].bus_num == 0)
601 enable_spi0 = 1;
602 else
603 enable_spi1 = 1;
604
605 /* enable chip-select pin */
606 at91_set_gpio_output(cs_pin, 1);
607
608 /* pass chip-select pin to driver */
609 devices[i].controller_data = (void *) cs_pin;
610 }
611
612 spi_register_board_info(devices, nr_devices);
613
614 /* Configure SPI bus(es) */
615 if (enable_spi0) {
616 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
617 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
618 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
619
86ad76bb
AV		 620 platform_device_register(&at91sam9260_spi0_device);
621 }
622 if (enable_spi1) {
623 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
624 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
625 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
626
86ad76bb
AV		 627 platform_device_register(&at91sam9260_spi1_device);
628 }
629}
630#else
631void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
632#endif
633
634
e5f40bfa
AV		 635/* --------------------------------------------------------------------
636 * Timer/Counter blocks
637 * -------------------------------------------------------------------- */
638
639#ifdef CONFIG_ATMEL_TCLIB
640
641static struct resource tcb0_resources[] = {
642 [0] = {
643 .start = AT91SAM9260_BASE_TCB0,
644 .end = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
645 .flags = IORESOURCE_MEM,
646 },
647 [1] = {
648 .start = AT91SAM9260_ID_TC0,
649 .end = AT91SAM9260_ID_TC0,
650 .flags = IORESOURCE_IRQ,
651 },
652 [2] = {
653 .start = AT91SAM9260_ID_TC1,
654 .end = AT91SAM9260_ID_TC1,
655 .flags = IORESOURCE_IRQ,
656 },
657 [3] = {
658 .start = AT91SAM9260_ID_TC2,
659 .end = AT91SAM9260_ID_TC2,
660 .flags = IORESOURCE_IRQ,
661 },
662};
663
664static struct platform_device at91sam9260_tcb0_device = {
665 .name = "atmel_tcb",
666 .id = 0,
667 .resource = tcb0_resources,
668 .num_resources = ARRAY_SIZE(tcb0_resources),
669};
670
671static struct resource tcb1_resources[] = {
672 [0] = {
673 .start = AT91SAM9260_BASE_TCB1,
674 .end = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
675 .flags = IORESOURCE_MEM,
676 },
677 [1] = {
678 .start = AT91SAM9260_ID_TC3,
679 .end = AT91SAM9260_ID_TC3,
680 .flags = IORESOURCE_IRQ,
681 },
682 [2] = {
683 .start = AT91SAM9260_ID_TC4,
684 .end = AT91SAM9260_ID_TC4,
685 .flags = IORESOURCE_IRQ,
686 },
687 [3] = {
688 .start = AT91SAM9260_ID_TC5,
689 .end = AT91SAM9260_ID_TC5,
690 .flags = IORESOURCE_IRQ,
691 },
692};
693
694static struct platform_device at91sam9260_tcb1_device = {
695 .name = "atmel_tcb",
696 .id = 1,
697 .resource = tcb1_resources,
698 .num_resources = ARRAY_SIZE(tcb1_resources),
699};
700
701static void __init at91_add_device_tc(void)
702{
e5f40bfa 703 platform_device_register(&at91sam9260_tcb0_device);
e5f40bfa
AV		 704 platform_device_register(&at91sam9260_tcb1_device);
705}
706#else
707static void __init at91_add_device_tc(void) { }
708#endif
709
710
884f5a6a
AV		 711/* --------------------------------------------------------------------
712 * RTT
713 * -------------------------------------------------------------------- */
714
715static struct resource rtt_resources[] = {
716 {
717 .start = AT91_BASE_SYS + AT91_RTT,
718 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
719 .flags = IORESOURCE_MEM,
720 }
721};
722
723static struct platform_device at91sam9260_rtt_device = {
724 .name = "at91_rtt",
4fd9212c 725 .id = 0,
884f5a6a
AV		 726 .resource = rtt_resources,
727 .num_resources = ARRAY_SIZE(rtt_resources),
728};
729
730static void __init at91_add_device_rtt(void)
731{
732 platform_device_register(&at91sam9260_rtt_device);
733}
734
735
736/* --------------------------------------------------------------------
737 * Watchdog
738 * -------------------------------------------------------------------- */
739
2af29b78 740#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
884f5a6a
AV		 741static struct platform_device at91sam9260_wdt_device = {
742 .name = "at91_wdt",
743 .id = -1,
744 .num_resources = 0,
745};
746
747static void __init at91_add_device_watchdog(void)
748{
749 platform_device_register(&at91sam9260_wdt_device);
750}
751#else
752static void __init at91_add_device_watchdog(void) {}
753#endif
754
755
bfbc3266
AV		 756/* --------------------------------------------------------------------
757 * SSC -- Synchronous Serial Controller
758 * -------------------------------------------------------------------- */
759
760#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
761static u64 ssc_dmamask = DMA_BIT_MASK(32);
762
763static struct resource ssc_resources[] = {
764 [0] = {
765 .start = AT91SAM9260_BASE_SSC,
766 .end = AT91SAM9260_BASE_SSC + SZ_16K - 1,
767 .flags = IORESOURCE_MEM,
768 },
769 [1] = {
770 .start = AT91SAM9260_ID_SSC,
771 .end = AT91SAM9260_ID_SSC,
772 .flags = IORESOURCE_IRQ,
773 },
774};
775
776static struct platform_device at91sam9260_ssc_device = {
777 .name = "ssc",
778 .id = 0,
779 .dev = {
780 .dma_mask = &ssc_dmamask,
781 .coherent_dma_mask = DMA_BIT_MASK(32),
782 },
783 .resource = ssc_resources,
784 .num_resources = ARRAY_SIZE(ssc_resources),
785};
786
787static inline void configure_ssc_pins(unsigned pins)
788{
789 if (pins & ATMEL_SSC_TF)
790 at91_set_A_periph(AT91_PIN_PB17, 1);
791 if (pins & ATMEL_SSC_TK)
792 at91_set_A_periph(AT91_PIN_PB16, 1);
793 if (pins & ATMEL_SSC_TD)
794 at91_set_A_periph(AT91_PIN_PB18, 1);
795 if (pins & ATMEL_SSC_RD)
796 at91_set_A_periph(AT91_PIN_PB19, 1);
797 if (pins & ATMEL_SSC_RK)
798 at91_set_A_periph(AT91_PIN_PB20, 1);
799 if (pins & ATMEL_SSC_RF)
800 at91_set_A_periph(AT91_PIN_PB21, 1);
801}
802
803/*
804 * SSC controllers are accessed through library code, instead of any
805 * kind of all-singing/all-dancing driver. For example one could be
806 * used by a particular I2S audio codec's driver, while another one
807 * on the same system might be used by a custom data capture driver.
808 */
809void __init at91_add_device_ssc(unsigned id, unsigned pins)
810{
811 struct platform_device *pdev;
812
813 /*
814 * NOTE: caller is responsible for passing information matching
815 * "pins" to whatever will be using each particular controller.
816 */
817 switch (id) {
818 case AT91SAM9260_ID_SSC:
819 pdev = &at91sam9260_ssc_device;
820 configure_ssc_pins(pins);
bfbc3266
AV		 821 break;
822 default:
823 return;
824 }
825
826 platform_device_register(pdev);
827}
828
829#else
830void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
831#endif
832
833
86ad76bb
AV		 834/* --------------------------------------------------------------------
835 * UART
836 * -------------------------------------------------------------------- */
837#if defined(CONFIG_SERIAL_ATMEL)
838static struct resource dbgu_resources[] = {
839 [0] = {
840 .start = AT91_VA_BASE_SYS + AT91_DBGU,
841 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
845 .start = AT91_ID_SYS,
846 .end = AT91_ID_SYS,
847 .flags = IORESOURCE_IRQ,
848 },
849};
850
851static struct atmel_uart_data dbgu_data = {
852 .use_dma_tx = 0,
853 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
854 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
855};
856
c6686ff9
AV		 857static u64 dbgu_dmamask = DMA_BIT_MASK(32);
858
86ad76bb
AV		 859static struct platform_device at91sam9260_dbgu_device = {
860 .name = "atmel_usart",
861 .id = 0,
862 .dev = {
c6686ff9
AV		 863 .dma_mask = &dbgu_dmamask,
864 .coherent_dma_mask = DMA_BIT_MASK(32),
865 .platform_data = &dbgu_data,
86ad76bb
AV		 866 },
867 .resource = dbgu_resources,
868 .num_resources = ARRAY_SIZE(dbgu_resources),
869};
870
871static inline void configure_dbgu_pins(void)
872{
873 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
874 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
875}
876
877static struct resource uart0_resources[] = {
878 [0] = {
879 .start = AT91SAM9260_BASE_US0,
880 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
881 .flags = IORESOURCE_MEM,
882 },
883 [1] = {
884 .start = AT91SAM9260_ID_US0,
885 .end = AT91SAM9260_ID_US0,
886 .flags = IORESOURCE_IRQ,
887 },
888};
889
890static struct atmel_uart_data uart0_data = {
891 .use_dma_tx = 1,
892 .use_dma_rx = 1,
893};
894
c6686ff9
AV		 895static u64 uart0_dmamask = DMA_BIT_MASK(32);
896
86ad76bb
AV		 897static struct platform_device at91sam9260_uart0_device = {
898 .name = "atmel_usart",
899 .id = 1,
900 .dev = {
c6686ff9
AV		 901 .dma_mask = &uart0_dmamask,
902 .coherent_dma_mask = DMA_BIT_MASK(32),
903 .platform_data = &uart0_data,
86ad76bb
AV		 904 },
905 .resource = uart0_resources,
906 .num_resources = ARRAY_SIZE(uart0_resources),
907};
908
c8f385a6 909static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 910{
911 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
912 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
c8f385a6
AV		 913
914 if (pins & ATMEL_UART_RTS)
915 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
916 if (pins & ATMEL_UART_CTS)
917 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
918 if (pins & ATMEL_UART_DTR)
919 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
920 if (pins & ATMEL_UART_DSR)
921 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
922 if (pins & ATMEL_UART_DCD)
923 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
924 if (pins & ATMEL_UART_RI)
925 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
86ad76bb
AV		 926}
927
928static struct resource uart1_resources[] = {
929 [0] = {
930 .start = AT91SAM9260_BASE_US1,
931 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
932 .flags = IORESOURCE_MEM,
933 },
934 [1] = {
935 .start = AT91SAM9260_ID_US1,
936 .end = AT91SAM9260_ID_US1,
937 .flags = IORESOURCE_IRQ,
938 },
939};
940
941static struct atmel_uart_data uart1_data = {
942 .use_dma_tx = 1,
943 .use_dma_rx = 1,
944};
945
c6686ff9
AV		 946static u64 uart1_dmamask = DMA_BIT_MASK(32);
947
86ad76bb
AV		 948static struct platform_device at91sam9260_uart1_device = {
949 .name = "atmel_usart",
950 .id = 2,
951 .dev = {
c6686ff9
AV		 952 .dma_mask = &uart1_dmamask,
953 .coherent_dma_mask = DMA_BIT_MASK(32),
954 .platform_data = &uart1_data,
86ad76bb
AV		 955 },
956 .resource = uart1_resources,
957 .num_resources = ARRAY_SIZE(uart1_resources),
958};
959
c8f385a6 960static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 961{
962 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
963 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
c8f385a6
AV		 964
965 if (pins & ATMEL_UART_RTS)
966 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
967 if (pins & ATMEL_UART_CTS)
968 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
86ad76bb
AV		 969}
970
971static struct resource uart2_resources[] = {
972 [0] = {
973 .start = AT91SAM9260_BASE_US2,
974 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
975 .flags = IORESOURCE_MEM,
976 },
977 [1] = {
978 .start = AT91SAM9260_ID_US2,
979 .end = AT91SAM9260_ID_US2,
980 .flags = IORESOURCE_IRQ,
981 },
982};
983
984static struct atmel_uart_data uart2_data = {
985 .use_dma_tx = 1,
986 .use_dma_rx = 1,
987};
988
c6686ff9
AV		 989static u64 uart2_dmamask = DMA_BIT_MASK(32);
990
86ad76bb
AV		 991static struct platform_device at91sam9260_uart2_device = {
992 .name = "atmel_usart",
993 .id = 3,
994 .dev = {
c6686ff9
AV		 995 .dma_mask = &uart2_dmamask,
996 .coherent_dma_mask = DMA_BIT_MASK(32),
997 .platform_data = &uart2_data,
86ad76bb
AV		 998 },
999 .resource = uart2_resources,
1000 .num_resources = ARRAY_SIZE(uart2_resources),
1001};
1002
c8f385a6 1003static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 1004{
1005 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
1006 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
c8f385a6
AV		 1007
1008 if (pins & ATMEL_UART_RTS)
1009 at91_set_A_periph(AT91_PIN_PA4, 0); /* RTS2 */
1010 if (pins & ATMEL_UART_CTS)
1011 at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
86ad76bb
AV		 1012}
1013
1014static struct resource uart3_resources[] = {
1015 [0] = {
1016 .start = AT91SAM9260_BASE_US3,
1017 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
1018 .flags = IORESOURCE_MEM,
1019 },
1020 [1] = {
1021 .start = AT91SAM9260_ID_US3,
1022 .end = AT91SAM9260_ID_US3,
1023 .flags = IORESOURCE_IRQ,
1024 },
1025};
1026
1027static struct atmel_uart_data uart3_data = {
1028 .use_dma_tx = 1,
1029 .use_dma_rx = 1,
1030};
1031
c6686ff9
AV		 1032static u64 uart3_dmamask = DMA_BIT_MASK(32);
1033
86ad76bb
AV		 1034static struct platform_device at91sam9260_uart3_device = {
1035 .name = "atmel_usart",
1036 .id = 4,
1037 .dev = {
c6686ff9
AV		 1038 .dma_mask = &uart3_dmamask,
1039 .coherent_dma_mask = DMA_BIT_MASK(32),
1040 .platform_data = &uart3_data,
86ad76bb
AV		 1041 },
1042 .resource = uart3_resources,
1043 .num_resources = ARRAY_SIZE(uart3_resources),
1044};
1045
c8f385a6 1046static inline void configure_usart3_pins(unsigned pins)
86ad76bb
AV		 1047{
1048 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
1049 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
c8f385a6
AV		 1050
1051 if (pins & ATMEL_UART_RTS)
1052 at91_set_B_periph(AT91_PIN_PC8, 0); /* RTS3 */
1053 if (pins & ATMEL_UART_CTS)
1054 at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
86ad76bb
AV		 1055}
1056
1057static struct resource uart4_resources[] = {
1058 [0] = {
1059 .start = AT91SAM9260_BASE_US4,
1060 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
1061 .flags = IORESOURCE_MEM,
1062 },
1063 [1] = {
1064 .start = AT91SAM9260_ID_US4,
1065 .end = AT91SAM9260_ID_US4,
1066 .flags = IORESOURCE_IRQ,
1067 },
1068};
1069
1070static struct atmel_uart_data uart4_data = {
1071 .use_dma_tx = 1,
1072 .use_dma_rx = 1,
1073};
1074
c6686ff9
AV		 1075static u64 uart4_dmamask = DMA_BIT_MASK(32);
1076
86ad76bb
AV		 1077static struct platform_device at91sam9260_uart4_device = {
1078 .name = "atmel_usart",
1079 .id = 5,
1080 .dev = {
c6686ff9
AV		 1081 .dma_mask = &uart4_dmamask,
1082 .coherent_dma_mask = DMA_BIT_MASK(32),
1083 .platform_data = &uart4_data,
86ad76bb
AV		 1084 },
1085 .resource = uart4_resources,
1086 .num_resources = ARRAY_SIZE(uart4_resources),
1087};
1088
1089static inline void configure_usart4_pins(void)
1090{
1091 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
1092 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
1093}
1094
1095static struct resource uart5_resources[] = {
1096 [0] = {
1097 .start = AT91SAM9260_BASE_US5,
1098 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
1099 .flags = IORESOURCE_MEM,
1100 },
1101 [1] = {
1102 .start = AT91SAM9260_ID_US5,
1103 .end = AT91SAM9260_ID_US5,
1104 .flags = IORESOURCE_IRQ,
1105 },
1106};
1107
1108static struct atmel_uart_data uart5_data = {
1109 .use_dma_tx = 1,
1110 .use_dma_rx = 1,
1111};
1112
c6686ff9
AV		 1113static u64 uart5_dmamask = DMA_BIT_MASK(32);
1114
86ad76bb
AV		 1115static struct platform_device at91sam9260_uart5_device = {
1116 .name = "atmel_usart",
1117 .id = 6,
1118 .dev = {
c6686ff9
AV		 1119 .dma_mask = &uart5_dmamask,
1120 .coherent_dma_mask = DMA_BIT_MASK(32),
1121 .platform_data = &uart5_data,
86ad76bb
AV		 1122 },
1123 .resource = uart5_resources,
1124 .num_resources = ARRAY_SIZE(uart5_resources),
1125};
1126
1127static inline void configure_usart5_pins(void)
1128{
1129 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
1130 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
1131}
1132
11aadac4 1133static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb
AV		 1134struct platform_device *atmel_default_console_device; /* the serial console device */
1135
c8f385a6
AV		 1136void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1137{
1138 struct platform_device *pdev;
2b348e2f 1139 struct atmel_uart_data *pdata;
c8f385a6
AV		 1140
1141 switch (id) {
1142 case 0: /* DBGU */
1143 pdev = &at91sam9260_dbgu_device;
1144 configure_dbgu_pins();
c8f385a6
AV		 1145 break;
1146 case AT91SAM9260_ID_US0:
1147 pdev = &at91sam9260_uart0_device;
1148 configure_usart0_pins(pins);
c8f385a6
AV		 1149 break;
1150 case AT91SAM9260_ID_US1:
1151 pdev = &at91sam9260_uart1_device;
1152 configure_usart1_pins(pins);
c8f385a6
AV		 1153 break;
1154 case AT91SAM9260_ID_US2:
1155 pdev = &at91sam9260_uart2_device;
1156 configure_usart2_pins(pins);
c8f385a6
AV		 1157 break;
1158 case AT91SAM9260_ID_US3:
1159 pdev = &at91sam9260_uart3_device;
1160 configure_usart3_pins(pins);
c8f385a6
AV		 1161 break;
1162 case AT91SAM9260_ID_US4:
1163 pdev = &at91sam9260_uart4_device;
1164 configure_usart4_pins();
c8f385a6
AV		 1165 break;
1166 case AT91SAM9260_ID_US5:
1167 pdev = &at91sam9260_uart5_device;
1168 configure_usart5_pins();
c8f385a6
AV		 1169 break;
1170 default:
1171 return;
1172 }
2b348e2f
JCPV		 1173 pdata = pdev->dev.platform_data;
1174 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1175
1176 if (portnr < ATMEL_MAX_UART)
1177 at91_uarts[portnr] = pdev;
1178}
1179
1180void __init at91_set_serial_console(unsigned portnr)
1181{
bd602995 1182 if (portnr < ATMEL_MAX_UART) {
c8f385a6 1183 atmel_default_console_device = at91_uarts[portnr];
5c1f9668 1184 at91sam9260_set_console_clock(at91_uarts[portnr]->id);
bd602995 1185 }
c8f385a6
AV		 1186}
1187
86ad76bb
AV		 1188void __init at91_add_device_serial(void)
1189{
1190 int i;
1191
1192 for (i = 0; i < ATMEL_MAX_UART; i++) {
1193 if (at91_uarts[i])
1194 platform_device_register(at91_uarts[i]);
1195 }
11aadac4
AV		 1196
1197 if (!atmel_default_console_device)
1198 printk(KERN_INFO "AT91: No default serial console defined.\n");
86ad76bb
AV		 1199}
1200#else
c8f385a6
AV		 1201void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1202void __init at91_set_serial_console(unsigned portnr) {}
86ad76bb
AV		 1203void __init at91_add_device_serial(void) {}
1204#endif
1205
fb85205a
SM		 1206/* --------------------------------------------------------------------
1207 * CF/IDE
1208 * -------------------------------------------------------------------- */
1209
1210#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \
1211 defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1212 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1213
1214static struct at91_cf_data cf0_data;
1215
1216static struct resource cf0_resources[] = {
1217 [0] = {
1218 .start = AT91_CHIPSELECT_4,
1219 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
1220 .flags = IORESOURCE_MEM,
1221 }
1222};
1223
1224static struct platform_device cf0_device = {
1225 .id = 0,
1226 .dev = {
1227 .platform_data = &cf0_data,
1228 },
1229 .resource = cf0_resources,
1230 .num_resources = ARRAY_SIZE(cf0_resources),
1231};
1232
1233static struct at91_cf_data cf1_data;
1234
1235static struct resource cf1_resources[] = {
1236 [0] = {
1237 .start = AT91_CHIPSELECT_5,
1238 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
1239 .flags = IORESOURCE_MEM,
1240 }
1241};
1242
1243static struct platform_device cf1_device = {
1244 .id = 1,
1245 .dev = {
1246 .platform_data = &cf1_data,
1247 },
1248 .resource = cf1_resources,
1249 .num_resources = ARRAY_SIZE(cf1_resources),
1250};
1251
1252void __init at91_add_device_cf(struct at91_cf_data *data)
1253{
1254 struct platform_device *pdev;
1255 unsigned long csa;
1256
1257 if (!data)
1258 return;
1259
1260 csa = at91_sys_read(AT91_MATRIX_EBICSA);
1261
1262 switch (data->chipselect) {
1263 case 4:
1264 at91_set_multi_drive(AT91_PIN_PC8, 0);
1265 at91_set_A_periph(AT91_PIN_PC8, 0);
1266 csa |= AT91_MATRIX_CS4A_SMC_CF1;
1267 cf0_data = *data;
1268 pdev = &cf0_device;
1269 break;
1270 case 5:
1271 at91_set_multi_drive(AT91_PIN_PC9, 0);
1272 at91_set_A_periph(AT91_PIN_PC9, 0);
1273 csa |= AT91_MATRIX_CS5A_SMC_CF2;
1274 cf1_data = *data;
1275 pdev = &cf1_device;
1276 break;
1277 default:
1278 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
1279 data->chipselect);
1280 return;
1281 }
1282
1283 at91_sys_write(AT91_MATRIX_EBICSA, csa);
1284
1285 if (data->rst_pin) {
1286 at91_set_multi_drive(data->rst_pin, 0);
1287 at91_set_gpio_output(data->rst_pin, 1);
1288 }
1289
1290 if (data->irq_pin) {
1291 at91_set_gpio_input(data->irq_pin, 0);
1292 at91_set_deglitch(data->irq_pin, 1);
1293 }
1294
1295 if (data->det_pin) {
1296 at91_set_gpio_input(data->det_pin, 0);
1297 at91_set_deglitch(data->det_pin, 1);
1298 }
1299
1300 at91_set_B_periph(AT91_PIN_PC6, 0); /* CFCE1 */
1301 at91_set_B_periph(AT91_PIN_PC7, 0); /* CFCE2 */
1302 at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */
1303 at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */
1304
1305 if (data->flags & AT91_CF_TRUE_IDE)
1306#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
1307 pdev->name = "pata_at91";
1308#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
1309 pdev->name = "at91_ide";
1310#else
1311#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
1312#endif
1313 else
1314 pdev->name = "at91_cf";
1315
1316 platform_device_register(pdev);
1317}
1318
1319#else
1320void __init at91_add_device_cf(struct at91_cf_data * data) {}
1321#endif
86ad76bb
AV		 1322
1323/* -------------------------------------------------------------------- */
1324/*
1325 * These devices are always present and don't need any board-specific
1326 * setup.
1327 */
1328static int __init at91_add_standard_devices(void)
1329{
884f5a6a
AV		 1330 at91_add_device_rtt();
1331 at91_add_device_watchdog();
e5f40bfa 1332 at91_add_device_tc();
86ad76bb
AV		 1333 return 0;
1334}
1335
1336arch_initcall(at91_add_standard_devices);
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