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[linux.git] / drivers / net / qla3xxx.c
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5a4faa87
RM		 1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
bd36b0ac 25#include <linux/in.h>
5a4faa87
RM		 26#include <linux/if_arp.h>
27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/skbuff.h>
32#include <linux/rtnetlink.h>
33#include <linux/if_vlan.h>
34#include <linux/init.h>
35#include <linux/delay.h>
36#include <linux/mm.h>
37
38#include "qla3xxx.h"
39
40#define DRV_NAME "qla3xxx"
41#define DRV_STRING "QLogic ISP3XXX Network Driver"
201f27e6 42#define DRV_VERSION "v2.03.00-k4"
5a4faa87
RM		 43#define PFX DRV_NAME " "
44
45static const char ql3xxx_driver_name[] = DRV_NAME;
46static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48MODULE_AUTHOR("QLogic Corporation");
49MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50MODULE_LICENSE("GPL");
51MODULE_VERSION(DRV_VERSION);
52
53static const u32 default_msg
54 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57static int debug = -1; /* defaults above */
58module_param(debug, int, 0);
59MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61static int msi;
62module_param(msi, int, 0);
63MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
bd36b0ac 67 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
5a4faa87
RM		 68 /* required last entry */
69 {0,}
70};
71
72MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
3efedf2e
RM		 74/*
75 * These are the known PHY's which are used
76 */
77typedef enum {
78 PHY_TYPE_UNKNOWN = 0,
79 PHY_VITESSE_VSC8211,
80 PHY_AGERE_ET1011C,
81 MAX_PHY_DEV_TYPES
82} PHY_DEVICE_et;
83
84typedef struct {
85 PHY_DEVICE_et phyDevice;
86 u32 phyIdOUI;
87 u16 phyIdModel;
88 char *name;
89} PHY_DEVICE_INFO_t;
90
b1fc1fa9 91static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
3efedf2e
RM		 92 {{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
93 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
94 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
95};
96
97
5a4faa87
RM		 98/*
99 * Caller must take hw_lock.
100 */
101static int ql_sem_spinlock(struct ql3_adapter *qdev,
102 u32 sem_mask, u32 sem_bits)
103{
104 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105 u32 value;
106 unsigned int seconds = 3;
107
108 do {
109 writel((sem_mask | sem_bits),
110 &port_regs->CommonRegs.semaphoreReg);
111 value = readl(&port_regs->CommonRegs.semaphoreReg);
112 if ((value & (sem_mask >> 16)) == sem_bits)
113 return 0;
114 ssleep(1);
115 } while(--seconds);
116 return -1;
117}
118
119static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
120{
121 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
122 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
123 readl(&port_regs->CommonRegs.semaphoreReg);
124}
125
126static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
127{
128 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
129 u32 value;
130
131 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
132 value = readl(&port_regs->CommonRegs.semaphoreReg);
133 return ((value & (sem_mask >> 16)) == sem_bits);
134}
135
136/*
137 * Caller holds hw_lock.
138 */
139static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
140{
141 int i = 0;
142
143 while (1) {
144 if (!ql_sem_lock(qdev,
145 QL_DRVR_SEM_MASK,
146 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
147 * 2) << 1)) {
148 if (i < 10) {
149 ssleep(1);
150 i++;
151 } else {
152 printk(KERN_ERR PFX "%s: Timed out waiting for "
153 "driver lock...\n",
154 qdev->ndev->name);
155 return 0;
156 }
157 } else {
158 printk(KERN_DEBUG PFX
159 "%s: driver lock acquired.\n",
160 qdev->ndev->name);
161 return 1;
162 }
163 }
164}
165
166static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
167{
168 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
169
170 writel(((ISP_CONTROL_NP_MASK << 16) | page),
171 &port_regs->CommonRegs.ispControlStatus);
172 readl(&port_regs->CommonRegs.ispControlStatus);
173 qdev->current_page = page;
174}
175
176static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
177 u32 __iomem * reg)
178{
179 u32 value;
180 unsigned long hw_flags;
181
182 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
183 value = readl(reg);
184 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
185
186 return value;
187}
188
189static u32 ql_read_common_reg(struct ql3_adapter *qdev,
190 u32 __iomem * reg)
191{
192 return readl(reg);
193}
194
195static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
196{
197 u32 value;
198 unsigned long hw_flags;
199
200 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
201
202 if (qdev->current_page != 0)
203 ql_set_register_page(qdev,0);
204 value = readl(reg);
205
206 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
207 return value;
208}
209
210static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
211{
212 if (qdev->current_page != 0)
213 ql_set_register_page(qdev,0);
214 return readl(reg);
215}
216
217static void ql_write_common_reg_l(struct ql3_adapter *qdev,
ee111d11 218 u32 __iomem *reg, u32 value)
5a4faa87
RM		 219{
220 unsigned long hw_flags;
221
222 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
ee111d11 223 writel(value, reg);
5a4faa87
RM		 224 readl(reg);
225 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
226 return;
227}
228
229static void ql_write_common_reg(struct ql3_adapter *qdev,
ee111d11 230 u32 __iomem *reg, u32 value)
5a4faa87 231{
ee111d11 232 writel(value, reg);
5a4faa87
RM		 233 readl(reg);
234 return;
235}
236
80b02e59
RM		 237static void ql_write_nvram_reg(struct ql3_adapter *qdev,
238 u32 __iomem *reg, u32 value)
239{
240 writel(value, reg);
241 readl(reg);
242 udelay(1);
243 return;
244}
245
5a4faa87 246static void ql_write_page0_reg(struct ql3_adapter *qdev,
ee111d11 247 u32 __iomem *reg, u32 value)
5a4faa87
RM		 248{
249 if (qdev->current_page != 0)
250 ql_set_register_page(qdev,0);
ee111d11 251 writel(value, reg);
5a4faa87
RM		 252 readl(reg);
253 return;
254}
255
256/*
257 * Caller holds hw_lock. Only called during init.
258 */
259static void ql_write_page1_reg(struct ql3_adapter *qdev,
ee111d11 260 u32 __iomem *reg, u32 value)
5a4faa87
RM		 261{
262 if (qdev->current_page != 1)
263 ql_set_register_page(qdev,1);
ee111d11 264 writel(value, reg);
5a4faa87
RM		 265 readl(reg);
266 return;
267}
268
269/*
270 * Caller holds hw_lock. Only called during init.
271 */
272static void ql_write_page2_reg(struct ql3_adapter *qdev,
ee111d11 273 u32 __iomem *reg, u32 value)
5a4faa87
RM		 274{
275 if (qdev->current_page != 2)
276 ql_set_register_page(qdev,2);
ee111d11 277 writel(value, reg);
5a4faa87
RM		 278 readl(reg);
279 return;
280}
281
282static void ql_disable_interrupts(struct ql3_adapter *qdev)
283{
284 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
285
286 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
287 (ISP_IMR_ENABLE_INT << 16));
288
289}
290
291static void ql_enable_interrupts(struct ql3_adapter *qdev)
292{
293 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
294
295 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
296 ((0xff << 16) | ISP_IMR_ENABLE_INT));
297
298}
299
300static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
301 struct ql_rcv_buf_cb *lrg_buf_cb)
302{
0f8ab89e
BL		 303 dma_addr_t map;
304 int err;
5a4faa87
RM		 305 lrg_buf_cb->next = NULL;
306
307 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
308 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
309 } else {
310 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
311 qdev->lrg_buf_free_tail = lrg_buf_cb;
312 }
313
314 if (!lrg_buf_cb->skb) {
cd238faa
BL		 315 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
316 qdev->lrg_buffer_len);
5a4faa87 317 if (unlikely(!lrg_buf_cb->skb)) {
cd238faa 318 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
5a4faa87
RM		 319 qdev->ndev->name);
320 qdev->lrg_buf_skb_check++;
321 } else {
322 /*
323 * We save some space to copy the ethhdr from first
324 * buffer
325 */
326 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
327 map = pci_map_single(qdev->pdev,
328 lrg_buf_cb->skb->data,
329 qdev->lrg_buffer_len -
330 QL_HEADER_SPACE,
331 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 332 err = pci_dma_mapping_error(map);
333 if(err) {
334 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
335 qdev->ndev->name, err);
336 dev_kfree_skb(lrg_buf_cb->skb);
337 lrg_buf_cb->skb = NULL;
338
339 qdev->lrg_buf_skb_check++;
340 return;
341 }
342
5a4faa87
RM		 343 lrg_buf_cb->buf_phy_addr_low =
344 cpu_to_le32(LS_64BITS(map));
345 lrg_buf_cb->buf_phy_addr_high =
346 cpu_to_le32(MS_64BITS(map));
347 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
348 pci_unmap_len_set(lrg_buf_cb, maplen,
349 qdev->lrg_buffer_len -
350 QL_HEADER_SPACE);
351 }
352 }
353
354 qdev->lrg_buf_free_count++;
355}
356
357static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
358 *qdev)
359{
360 struct ql_rcv_buf_cb *lrg_buf_cb;
361
362 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
363 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
364 qdev->lrg_buf_free_tail = NULL;
365 qdev->lrg_buf_free_count--;
366 }
367
368 return lrg_buf_cb;
369}
370
371static u32 addrBits = EEPROM_NO_ADDR_BITS;
372static u32 dataBits = EEPROM_NO_DATA_BITS;
373
374static void fm93c56a_deselect(struct ql3_adapter *qdev);
375static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
376 unsigned short *value);
377
378/*
379 * Caller holds hw_lock.
380 */
381static void fm93c56a_select(struct ql3_adapter *qdev)
382{
383 struct ql3xxx_port_registers __iomem *port_regs =
384 qdev->mem_map_registers;
385
386 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
80b02e59 387 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87 388 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
80b02e59 389 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 390 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
391}
392
393/*
394 * Caller holds hw_lock.
395 */
396static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
397{
398 int i;
399 u32 mask;
400 u32 dataBit;
401 u32 previousBit;
402 struct ql3xxx_port_registers __iomem *port_regs =
403 qdev->mem_map_registers;
404
405 /* Clock in a zero, then do the start bit */
80b02e59 406 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 407 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
408 AUBURN_EEPROM_DO_1);
80b02e59 409 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 410 ISP_NVRAM_MASK | qdev->
411 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
412 AUBURN_EEPROM_CLK_RISE);
80b02e59 413 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 414 ISP_NVRAM_MASK | qdev->
415 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
416 AUBURN_EEPROM_CLK_FALL);
417
418 mask = 1 << (FM93C56A_CMD_BITS - 1);
419 /* Force the previous data bit to be different */
420 previousBit = 0xffff;
421 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
422 dataBit =
423 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
424 if (previousBit != dataBit) {
425 /*
426 * If the bit changed, then change the DO state to
427 * match
428 */
80b02e59 429 ql_write_nvram_reg(qdev,
5a4faa87
RM		 430 &port_regs->CommonRegs.
431 serialPortInterfaceReg,
432 ISP_NVRAM_MASK | qdev->
433 eeprom_cmd_data | dataBit);
434 previousBit = dataBit;
435 }
80b02e59 436 ql_write_nvram_reg(qdev,
5a4faa87
RM		 437 &port_regs->CommonRegs.
438 serialPortInterfaceReg,
439 ISP_NVRAM_MASK | qdev->
440 eeprom_cmd_data | dataBit |
441 AUBURN_EEPROM_CLK_RISE);
80b02e59 442 ql_write_nvram_reg(qdev,
5a4faa87
RM		 443 &port_regs->CommonRegs.
444 serialPortInterfaceReg,
445 ISP_NVRAM_MASK | qdev->
446 eeprom_cmd_data | dataBit |
447 AUBURN_EEPROM_CLK_FALL);
448 cmd = cmd << 1;
449 }
450
451 mask = 1 << (addrBits - 1);
452 /* Force the previous data bit to be different */
453 previousBit = 0xffff;
454 for (i = 0; i < addrBits; i++) {
455 dataBit =
456 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
457 AUBURN_EEPROM_DO_0;
458 if (previousBit != dataBit) {
459 /*
460 * If the bit changed, then change the DO state to
461 * match
462 */
80b02e59 463 ql_write_nvram_reg(qdev,
5a4faa87
RM		 464 &port_regs->CommonRegs.
465 serialPortInterfaceReg,
466 ISP_NVRAM_MASK | qdev->
467 eeprom_cmd_data | dataBit);
468 previousBit = dataBit;
469 }
80b02e59 470 ql_write_nvram_reg(qdev,
5a4faa87
RM		 471 &port_regs->CommonRegs.
472 serialPortInterfaceReg,
473 ISP_NVRAM_MASK | qdev->
474 eeprom_cmd_data | dataBit |
475 AUBURN_EEPROM_CLK_RISE);
80b02e59 476 ql_write_nvram_reg(qdev,
5a4faa87
RM		 477 &port_regs->CommonRegs.
478 serialPortInterfaceReg,
479 ISP_NVRAM_MASK | qdev->
480 eeprom_cmd_data | dataBit |
481 AUBURN_EEPROM_CLK_FALL);
482 eepromAddr = eepromAddr << 1;
483 }
484}
485
486/*
487 * Caller holds hw_lock.
488 */
489static void fm93c56a_deselect(struct ql3_adapter *qdev)
490{
491 struct ql3xxx_port_registers __iomem *port_regs =
492 qdev->mem_map_registers;
493 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
80b02e59 494 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 495 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
496}
497
498/*
499 * Caller holds hw_lock.
500 */
501static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
502{
503 int i;
504 u32 data = 0;
505 u32 dataBit;
506 struct ql3xxx_port_registers __iomem *port_regs =
507 qdev->mem_map_registers;
508
509 /* Read the data bits */
510 /* The first bit is a dummy. Clock right over it. */
511 for (i = 0; i < dataBits; i++) {
80b02e59 512 ql_write_nvram_reg(qdev,
5a4faa87
RM		 513 &port_regs->CommonRegs.
514 serialPortInterfaceReg,
515 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
516 AUBURN_EEPROM_CLK_RISE);
80b02e59 517 ql_write_nvram_reg(qdev,
5a4faa87
RM		 518 &port_regs->CommonRegs.
519 serialPortInterfaceReg,
520 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
521 AUBURN_EEPROM_CLK_FALL);
522 dataBit =
523 (ql_read_common_reg
524 (qdev,
525 &port_regs->CommonRegs.
526 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
527 data = (data << 1) | dataBit;
528 }
529 *value = (u16) data;
530}
531
532/*
533 * Caller holds hw_lock.
534 */
535static void eeprom_readword(struct ql3_adapter *qdev,
536 u32 eepromAddr, unsigned short *value)
537{
538 fm93c56a_select(qdev);
539 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
540 fm93c56a_datain(qdev, value);
541 fm93c56a_deselect(qdev);
542}
543
544static void ql_swap_mac_addr(u8 * macAddress)
545{
546#ifdef __BIG_ENDIAN
547 u8 temp;
548 temp = macAddress[0];
549 macAddress[0] = macAddress[1];
550 macAddress[1] = temp;
551 temp = macAddress[2];
552 macAddress[2] = macAddress[3];
553 macAddress[3] = temp;
554 temp = macAddress[4];
555 macAddress[4] = macAddress[5];
556 macAddress[5] = temp;
557#endif
558}
559
560static int ql_get_nvram_params(struct ql3_adapter *qdev)
561{
562 u16 *pEEPROMData;
563 u16 checksum = 0;
564 u32 index;
565 unsigned long hw_flags;
566
567 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
568
569 pEEPROMData = (u16 *) & qdev->nvram_data;
570 qdev->eeprom_cmd_data = 0;
571 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
572 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
573 2) << 10)) {
574 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
575 __func__);
576 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
577 return -1;
578 }
579
580 for (index = 0; index < EEPROM_SIZE; index++) {
581 eeprom_readword(qdev, index, pEEPROMData);
582 checksum += *pEEPROMData;
583 pEEPROMData++;
584 }
585 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
586
587 if (checksum != 0) {
588 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
589 qdev->ndev->name, checksum);
590 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
591 return -1;
592 }
593
594 /*
595 * We have a problem with endianness for the MAC addresses
596 * and the two 8-bit values version, and numPorts. We
597 * have to swap them on big endian systems.
598 */
599 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
600 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
601 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
602 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
603 pEEPROMData = (u16 *) & qdev->nvram_data.version;
604 *pEEPROMData = le16_to_cpu(*pEEPROMData);
605
606 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
607 return checksum;
608}
609
610static const u32 PHYAddr[2] = {
611 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
612};
613
614static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
615{
616 struct ql3xxx_port_registers __iomem *port_regs =
617 qdev->mem_map_registers;
618 u32 temp;
619 int count = 1000;
620
621 while (count) {
622 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
623 if (!(temp & MAC_MII_STATUS_BSY))
624 return 0;
625 udelay(10);
626 count--;
627 }
628 return -1;
629}
630
631static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
632{
633 struct ql3xxx_port_registers __iomem *port_regs =
634 qdev->mem_map_registers;
635 u32 scanControl;
636
637 if (qdev->numPorts > 1) {
638 /* Auto scan will cycle through multiple ports */
639 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
640 } else {
641 scanControl = MAC_MII_CONTROL_SC;
642 }
643
644 /*
645 * Scan register 1 of PHY/PETBI,
646 * Set up to scan both devices
647 * The autoscan starts from the first register, completes
648 * the last one before rolling over to the first
649 */
650 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
651 PHYAddr[0] | MII_SCAN_REGISTER);
652
653 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
654 (scanControl) |
655 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
656}
657
658static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
659{
660 u8 ret;
661 struct ql3xxx_port_registers __iomem *port_regs =
662 qdev->mem_map_registers;
663
664 /* See if scan mode is enabled before we turn it off */
665 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
666 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
667 /* Scan is enabled */
668 ret = 1;
669 } else {
670 /* Scan is disabled */
671 ret = 0;
672 }
673
674 /*
675 * When disabling scan mode you must first change the MII register
676 * address
677 */
678 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
679 PHYAddr[0] | MII_SCAN_REGISTER);
680
681 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
682 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
683 MAC_MII_CONTROL_RC) << 16));
684
685 return ret;
686}
687
688static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
3efedf2e 689 u16 regAddr, u16 value, u32 phyAddr)
5a4faa87
RM		 690{
691 struct ql3xxx_port_registers __iomem *port_regs =
692 qdev->mem_map_registers;
693 u8 scanWasEnabled;
694
695 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
696
697 if (ql_wait_for_mii_ready(qdev)) {
698 if (netif_msg_link(qdev))
699 printk(KERN_WARNING PFX
700 "%s Timed out waiting for management port to "
701 "get free before issuing command.\n",
702 qdev->ndev->name);
703 return -1;
704 }
705
706 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 707 phyAddr | regAddr);
5a4faa87
RM		 708
709 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
710
711 /* Wait for write to complete 9/10/04 SJP */
712 if (ql_wait_for_mii_ready(qdev)) {
713 if (netif_msg_link(qdev))
714 printk(KERN_WARNING PFX
715 "%s: Timed out waiting for management port to"
716 "get free before issuing command.\n",
717 qdev->ndev->name);
718 return -1;
719 }
720
721 if (scanWasEnabled)
722 ql_mii_enable_scan_mode(qdev);
723
724 return 0;
725}
726
727static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
3efedf2e 728 u16 * value, u32 phyAddr)
5a4faa87
RM		 729{
730 struct ql3xxx_port_registers __iomem *port_regs =
731 qdev->mem_map_registers;
732 u8 scanWasEnabled;
733 u32 temp;
734
735 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
736
737 if (ql_wait_for_mii_ready(qdev)) {
738 if (netif_msg_link(qdev))
739 printk(KERN_WARNING PFX
740 "%s: Timed out waiting for management port to "
741 "get free before issuing command.\n",
742 qdev->ndev->name);
743 return -1;
744 }
745
746 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 747 phyAddr | regAddr);
5a4faa87
RM		 748
749 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
750 (MAC_MII_CONTROL_RC << 16));
751
752 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
753 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
754
755 /* Wait for the read to complete */
756 if (ql_wait_for_mii_ready(qdev)) {
757 if (netif_msg_link(qdev))
758 printk(KERN_WARNING PFX
759 "%s: Timed out waiting for management port to "
760 "get free after issuing command.\n",
761 qdev->ndev->name);
762 return -1;
763 }
764
765 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
766 *value = (u16) temp;
767
768 if (scanWasEnabled)
769 ql_mii_enable_scan_mode(qdev);
770
771 return 0;
772}
773
774static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
775{
776 struct ql3xxx_port_registers __iomem *port_regs =
777 qdev->mem_map_registers;
778
779 ql_mii_disable_scan_mode(qdev);
780
781 if (ql_wait_for_mii_ready(qdev)) {
782 if (netif_msg_link(qdev))
783 printk(KERN_WARNING PFX
784 "%s: Timed out waiting for management port to "
785 "get free before issuing command.\n",
786 qdev->ndev->name);
787 return -1;
788 }
789
790 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
791 qdev->PHYAddr | regAddr);
792
793 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
794
795 /* Wait for write to complete. */
796 if (ql_wait_for_mii_ready(qdev)) {
797 if (netif_msg_link(qdev))
798 printk(KERN_WARNING PFX
799 "%s: Timed out waiting for management port to "
800 "get free before issuing command.\n",
801 qdev->ndev->name);
802 return -1;
803 }
804
805 ql_mii_enable_scan_mode(qdev);
806
807 return 0;
808}
809
810static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
811{
812 u32 temp;
813 struct ql3xxx_port_registers __iomem *port_regs =
814 qdev->mem_map_registers;
815
816 ql_mii_disable_scan_mode(qdev);
817
818 if (ql_wait_for_mii_ready(qdev)) {
819 if (netif_msg_link(qdev))
820 printk(KERN_WARNING PFX
821 "%s: Timed out waiting for management port to "
822 "get free before issuing command.\n",
823 qdev->ndev->name);
824 return -1;
825 }
826
827 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
828 qdev->PHYAddr | regAddr);
829
830 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
831 (MAC_MII_CONTROL_RC << 16));
832
833 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
834 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
835
836 /* Wait for the read to complete */
837 if (ql_wait_for_mii_ready(qdev)) {
838 if (netif_msg_link(qdev))
839 printk(KERN_WARNING PFX
840 "%s: Timed out waiting for management port to "
841 "get free before issuing command.\n",
842 qdev->ndev->name);
843 return -1;
844 }
845
846 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
847 *value = (u16) temp;
848
849 ql_mii_enable_scan_mode(qdev);
850
851 return 0;
852}
853
854static void ql_petbi_reset(struct ql3_adapter *qdev)
855{
856 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
857}
858
859static void ql_petbi_start_neg(struct ql3_adapter *qdev)
860{
861 u16 reg;
862
863 /* Enable Auto-negotiation sense */
864 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
865 reg |= PETBI_TBI_AUTO_SENSE;
866 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
867
868 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
869 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
870
871 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
872 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
873 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
874
875}
876
3efedf2e 877static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 878{
879 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
3efedf2e 880 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 881}
882
3efedf2e 883static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 884{
885 u16 reg;
886
887 /* Enable Auto-negotiation sense */
3efedf2e
RM		 888 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
889 PHYAddr[qdev->mac_index]);
5a4faa87 890 reg |= PETBI_TBI_AUTO_SENSE;
3efedf2e
RM		 891 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
892 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 893
894 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
3efedf2e
RM		 895 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
896 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 897
898 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
899 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
900 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
3efedf2e 901 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 902}
903
904static void ql_petbi_init(struct ql3_adapter *qdev)
905{
906 ql_petbi_reset(qdev);
907 ql_petbi_start_neg(qdev);
908}
909
3efedf2e 910static void ql_petbi_init_ex(struct ql3_adapter *qdev)
5a4faa87 911{
3efedf2e
RM		 912 ql_petbi_reset_ex(qdev);
913 ql_petbi_start_neg_ex(qdev);
5a4faa87
RM		 914}
915
916static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
917{
918 u16 reg;
919
920 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
921 return 0;
922
923 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
924}
925
3efedf2e
RM		 926static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
927{
928 printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
929 /* power down device bit 11 = 1 */
930 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
931 /* enable diagnostic mode bit 2 = 1 */
932 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
933 /* 1000MB amplitude adjust (see Agere errata) */
934 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
935 /* 1000MB amplitude adjust (see Agere errata) */
936 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
937 /* 100MB amplitude adjust (see Agere errata) */
938 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
939 /* 100MB amplitude adjust (see Agere errata) */
940 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
941 /* 10MB amplitude adjust (see Agere errata) */
942 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
943 /* 10MB amplitude adjust (see Agere errata) */
944 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
945 /* point to hidden reg 0x2806 */
946 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
947 /* Write new PHYAD w/bit 5 set */
948 ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
949 /*
950 * Disable diagnostic mode bit 2 = 0
951 * Power up device bit 11 = 0
952 * Link up (on) and activity (blink)
953 */
954 ql_mii_write_reg(qdev, 0x12, 0x840a);
955 ql_mii_write_reg(qdev, 0x00, 0x1140);
956 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
957}
958
959static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
960 u16 phyIdReg0, u16 phyIdReg1)
961{
962 PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
963 u32 oui;
964 u16 model;
965 int i;
966
967 if (phyIdReg0 == 0xffff) {
968 return result;
969 }
970
971 if (phyIdReg1 == 0xffff) {
972 return result;
973 }
974
975 /* oui is split between two registers */
976 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
977
978 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
979
980 /* Scan table for this PHY */
981 for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
982 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
983 {
984 result = PHY_DEVICES[i].phyDevice;
985
986 printk(KERN_INFO "%s: Phy: %s\n",
987 qdev->ndev->name, PHY_DEVICES[i].name);
988
989 break;
990 }
991 }
992
993 return result;
994}
995
5a4faa87
RM		 996static int ql_phy_get_speed(struct ql3_adapter *qdev)
997{
998 u16 reg;
999
3efedf2e
RM		 1000 switch(qdev->phyType) {
1001 case PHY_AGERE_ET1011C:
1002 {
1003 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
1004 return 0;
1005
1006 reg = (reg >> 8) & 3;
1007 break;
1008 }
1009 default:
5a4faa87
RM		 1010 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1011 return 0;
1012
1013 reg = (((reg & 0x18) >> 3) & 3);
3efedf2e 1014 }
5a4faa87 1015
3efedf2e
RM		 1016 switch(reg) {
1017 case 2:
5a4faa87 1018 return SPEED_1000;
3efedf2e 1019 case 1:
5a4faa87 1020 return SPEED_100;
3efedf2e 1021 case 0:
5a4faa87 1022 return SPEED_10;
3efedf2e 1023 default:
5a4faa87 1024 return -1;
3efedf2e 1025 }
5a4faa87
RM		 1026}
1027
1028static int ql_is_full_dup(struct ql3_adapter *qdev)
1029{
1030 u16 reg;
1031
3efedf2e
RM		 1032 switch(qdev->phyType) {
1033 case PHY_AGERE_ET1011C:
1034 {
1035 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1036 return 0;
1037
1038 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1039 }
1040 case PHY_VITESSE_VSC8211:
1041 default:
1042 {
1043 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1044 return 0;
1045 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1046 }
1047 }
5a4faa87
RM		 1048}
1049
1050static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1051{
1052 u16 reg;
1053
1054 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1055 return 0;
1056
1057 return (reg & PHY_NEG_PAUSE) != 0;
1058}
1059
3efedf2e
RM		 1060static int PHY_Setup(struct ql3_adapter *qdev)
1061{
1062 u16 reg1;
1063 u16 reg2;
1064 bool agereAddrChangeNeeded = false;
1065 u32 miiAddr = 0;
1066 int err;
1067
1068 /* Determine the PHY we are using by reading the ID's */
1069 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1070 if(err != 0) {
1071 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1072 qdev->ndev->name);
1073 return err;
1074 }
1075
1076 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1077 if(err != 0) {
1078 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1079 qdev->ndev->name);
1080 return err;
1081 }
1082
1083 /* Check if we have a Agere PHY */
1084 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1085
1086 /* Determine which MII address we should be using
1087 determined by the index of the card */
1088 if (qdev->mac_index == 0) {
1089 miiAddr = MII_AGERE_ADDR_1;
1090 } else {
1091 miiAddr = MII_AGERE_ADDR_2;
1092 }
1093
1094 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1095 if(err != 0) {
1096 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1097 qdev->ndev->name);
1098 return err;
1099 }
1100
1101 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1102 if(err != 0) {
1103 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1104 qdev->ndev->name);
1105 return err;
1106 }
1107
1108 /* We need to remember to initialize the Agere PHY */
1109 agereAddrChangeNeeded = true;
1110 }
1111
1112 /* Determine the particular PHY we have on board to apply
1113 PHY specific initializations */
1114 qdev->phyType = getPhyType(qdev, reg1, reg2);
1115
1116 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1117 /* need this here so address gets changed */
1118 phyAgereSpecificInit(qdev, miiAddr);
1119 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1120 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1121 return -EIO;
1122 }
1123
1124 return 0;
1125}
1126
5a4faa87
RM		 1127/*
1128 * Caller holds hw_lock.
1129 */
1130static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1131{
1132 struct ql3xxx_port_registers __iomem *port_regs =
1133 qdev->mem_map_registers;
1134 u32 value;
1135
1136 if (enable)
1137 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1138 else
1139 value = (MAC_CONFIG_REG_PE << 16);
1140
1141 if (qdev->mac_index)
1142 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1143 else
1144 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1145}
1146
1147/*
1148 * Caller holds hw_lock.
1149 */
1150static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1151{
1152 struct ql3xxx_port_registers __iomem *port_regs =
1153 qdev->mem_map_registers;
1154 u32 value;
1155
1156 if (enable)
1157 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1158 else
1159 value = (MAC_CONFIG_REG_SR << 16);
1160
1161 if (qdev->mac_index)
1162 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1163 else
1164 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1165}
1166
1167/*
1168 * Caller holds hw_lock.
1169 */
1170static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1171{
1172 struct ql3xxx_port_registers __iomem *port_regs =
1173 qdev->mem_map_registers;
1174 u32 value;
1175
1176 if (enable)
1177 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1178 else
1179 value = (MAC_CONFIG_REG_GM << 16);
1180
1181 if (qdev->mac_index)
1182 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1183 else
1184 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1185}
1186
1187/*
1188 * Caller holds hw_lock.
1189 */
1190static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1191{
1192 struct ql3xxx_port_registers __iomem *port_regs =
1193 qdev->mem_map_registers;
1194 u32 value;
1195
1196 if (enable)
1197 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1198 else
1199 value = (MAC_CONFIG_REG_FD << 16);
1200
1201 if (qdev->mac_index)
1202 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1203 else
1204 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1205}
1206
1207/*
1208 * Caller holds hw_lock.
1209 */
1210static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1211{
1212 struct ql3xxx_port_registers __iomem *port_regs =
1213 qdev->mem_map_registers;
1214 u32 value;
1215
1216 if (enable)
1217 value =
1218 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1219 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1220 else
1221 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1222
1223 if (qdev->mac_index)
1224 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1225 else
1226 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1227}
1228
1229/*
1230 * Caller holds hw_lock.
1231 */
1232static int ql_is_fiber(struct ql3_adapter *qdev)
1233{
1234 struct ql3xxx_port_registers __iomem *port_regs =
1235 qdev->mem_map_registers;
1236 u32 bitToCheck = 0;
1237 u32 temp;
1238
1239 switch (qdev->mac_index) {
1240 case 0:
1241 bitToCheck = PORT_STATUS_SM0;
1242 break;
1243 case 1:
1244 bitToCheck = PORT_STATUS_SM1;
1245 break;
1246 }
1247
1248 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1249 return (temp & bitToCheck) != 0;
1250}
1251
1252static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1253{
1254 u16 reg;
1255 ql_mii_read_reg(qdev, 0x00, &reg);
1256 return (reg & 0x1000) != 0;
1257}
1258
1259/*
1260 * Caller holds hw_lock.
1261 */
1262static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1263{
1264 struct ql3xxx_port_registers __iomem *port_regs =
1265 qdev->mem_map_registers;
1266 u32 bitToCheck = 0;
1267 u32 temp;
1268
1269 switch (qdev->mac_index) {
1270 case 0:
1271 bitToCheck = PORT_STATUS_AC0;
1272 break;
1273 case 1:
1274 bitToCheck = PORT_STATUS_AC1;
1275 break;
1276 }
1277
1278 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1279 if (temp & bitToCheck) {
1280 if (netif_msg_link(qdev))
1281 printk(KERN_INFO PFX
1282 "%s: Auto-Negotiate complete.\n",
1283 qdev->ndev->name);
1284 return 1;
1285 } else {
1286 if (netif_msg_link(qdev))
1287 printk(KERN_WARNING PFX
1288 "%s: Auto-Negotiate incomplete.\n",
1289 qdev->ndev->name);
1290 return 0;
1291 }
1292}
1293
1294/*
1295 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1296 */
1297static int ql_is_neg_pause(struct ql3_adapter *qdev)
1298{
1299 if (ql_is_fiber(qdev))
1300 return ql_is_petbi_neg_pause(qdev);
1301 else
1302 return ql_is_phy_neg_pause(qdev);
1303}
1304
1305static int ql_auto_neg_error(struct ql3_adapter *qdev)
1306{
1307 struct ql3xxx_port_registers __iomem *port_regs =
1308 qdev->mem_map_registers;
1309 u32 bitToCheck = 0;
1310 u32 temp;
1311
1312 switch (qdev->mac_index) {
1313 case 0:
1314 bitToCheck = PORT_STATUS_AE0;
1315 break;
1316 case 1:
1317 bitToCheck = PORT_STATUS_AE1;
1318 break;
1319 }
1320 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1321 return (temp & bitToCheck) != 0;
1322}
1323
1324static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1325{
1326 if (ql_is_fiber(qdev))
1327 return SPEED_1000;
1328 else
1329 return ql_phy_get_speed(qdev);
1330}
1331
1332static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1333{
1334 if (ql_is_fiber(qdev))
1335 return 1;
1336 else
1337 return ql_is_full_dup(qdev);
1338}
1339
1340/*
1341 * Caller holds hw_lock.
1342 */
1343static int ql_link_down_detect(struct ql3_adapter *qdev)
1344{
1345 struct ql3xxx_port_registers __iomem *port_regs =
1346 qdev->mem_map_registers;
1347 u32 bitToCheck = 0;
1348 u32 temp;
1349
1350 switch (qdev->mac_index) {
1351 case 0:
1352 bitToCheck = ISP_CONTROL_LINK_DN_0;
1353 break;
1354 case 1:
1355 bitToCheck = ISP_CONTROL_LINK_DN_1;
1356 break;
1357 }
1358
1359 temp =
1360 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1361 return (temp & bitToCheck) != 0;
1362}
1363
1364/*
1365 * Caller holds hw_lock.
1366 */
1367static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1368{
1369 struct ql3xxx_port_registers __iomem *port_regs =
1370 qdev->mem_map_registers;
1371
1372 switch (qdev->mac_index) {
1373 case 0:
1374 ql_write_common_reg(qdev,
1375 &port_regs->CommonRegs.ispControlStatus,
1376 (ISP_CONTROL_LINK_DN_0) |
1377 (ISP_CONTROL_LINK_DN_0 << 16));
1378 break;
1379
1380 case 1:
1381 ql_write_common_reg(qdev,
1382 &port_regs->CommonRegs.ispControlStatus,
1383 (ISP_CONTROL_LINK_DN_1) |
1384 (ISP_CONTROL_LINK_DN_1 << 16));
1385 break;
1386
1387 default:
1388 return 1;
1389 }
1390
1391 return 0;
1392}
1393
1394/*
1395 * Caller holds hw_lock.
1396 */
3efedf2e 1397static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
5a4faa87
RM		 1398{
1399 struct ql3xxx_port_registers __iomem *port_regs =
1400 qdev->mem_map_registers;
1401 u32 bitToCheck = 0;
1402 u32 temp;
1403
3efedf2e 1404 switch (qdev->mac_index) {
5a4faa87
RM		 1405 case 0:
1406 bitToCheck = PORT_STATUS_F1_ENABLED;
1407 break;
1408 case 1:
1409 bitToCheck = PORT_STATUS_F3_ENABLED;
1410 break;
1411 default:
1412 break;
1413 }
1414
1415 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1416 if (temp & bitToCheck) {
1417 if (netif_msg_link(qdev))
1418 printk(KERN_DEBUG PFX
1419 "%s: is not link master.\n", qdev->ndev->name);
1420 return 0;
1421 } else {
1422 if (netif_msg_link(qdev))
1423 printk(KERN_DEBUG PFX
1424 "%s: is link master.\n", qdev->ndev->name);
1425 return 1;
1426 }
1427}
1428
3efedf2e 1429static void ql_phy_reset_ex(struct ql3_adapter *qdev)
5a4faa87 1430{
3efedf2e
RM		 1431 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1432 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1433}
1434
3efedf2e 1435static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 1436{
1437 u16 reg;
3efedf2e
RM		 1438 u16 portConfiguration;
1439
1440 if(qdev->phyType == PHY_AGERE_ET1011C) {
1441 /* turn off external loopback */
1442 ql_mii_write_reg(qdev, 0x13, 0x0000);
1443 }
5a4faa87 1444
3efedf2e
RM		 1445 if(qdev->mac_index == 0)
1446 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1447 else
1448 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1449
1450 /* Some HBA's in the field are set to 0 and they need to
1451 be reinterpreted with a default value */
1452 if(portConfiguration == 0)
1453 portConfiguration = PORT_CONFIG_DEFAULT;
1454
1455 /* Set the 1000 advertisements */
1456 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
1457 PHYAddr[qdev->mac_index]);
1458 reg &= ~PHY_GIG_ALL_PARAMS;
1459
1460 if(portConfiguration &
1461 PORT_CONFIG_FULL_DUPLEX_ENABLED &
1462 PORT_CONFIG_1000MB_SPEED) {
1463 reg |= PHY_GIG_ADV_1000F;
1464 }
1465
1466 if(portConfiguration &
1467 PORT_CONFIG_HALF_DUPLEX_ENABLED &
1468 PORT_CONFIG_1000MB_SPEED) {
1469 reg |= PHY_GIG_ADV_1000H;
1470 }
1471
1472 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1473 PHYAddr[qdev->mac_index]);
1474
1475 /* Set the 10/100 & pause negotiation advertisements */
1476 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1477 PHYAddr[qdev->mac_index]);
1478 reg &= ~PHY_NEG_ALL_PARAMS;
1479
1480 if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1481 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1482
1483 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1484 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1485 reg |= PHY_NEG_ADV_100F;
1486
1487 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1488 reg |= PHY_NEG_ADV_10F;
1489 }
1490
1491 if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1492 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1493 reg |= PHY_NEG_ADV_100H;
1494
1495 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1496 reg |= PHY_NEG_ADV_10H;
1497 }
1498
1499 if(portConfiguration &
1500 PORT_CONFIG_1000MB_SPEED) {
1501 reg |= 1;
1502 }
1503
1504 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1505 PHYAddr[qdev->mac_index]);
5a4faa87 1506
3efedf2e
RM		 1507 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1508
1509 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1510 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1511 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1512}
1513
3efedf2e 1514static void ql_phy_init_ex(struct ql3_adapter *qdev)
5a4faa87 1515{
3efedf2e
RM		 1516 ql_phy_reset_ex(qdev);
1517 PHY_Setup(qdev);
1518 ql_phy_start_neg_ex(qdev);
5a4faa87
RM		 1519}
1520
1521/*
1522 * Caller holds hw_lock.
1523 */
1524static u32 ql_get_link_state(struct ql3_adapter *qdev)
1525{
1526 struct ql3xxx_port_registers __iomem *port_regs =
1527 qdev->mem_map_registers;
1528 u32 bitToCheck = 0;
1529 u32 temp, linkState;
1530
1531 switch (qdev->mac_index) {
1532 case 0:
1533 bitToCheck = PORT_STATUS_UP0;
1534 break;
1535 case 1:
1536 bitToCheck = PORT_STATUS_UP1;
1537 break;
1538 }
1539 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1540 if (temp & bitToCheck) {
1541 linkState = LS_UP;
1542 } else {
1543 linkState = LS_DOWN;
1544 if (netif_msg_link(qdev))
1545 printk(KERN_WARNING PFX
1546 "%s: Link is down.\n", qdev->ndev->name);
1547 }
1548 return linkState;
1549}
1550
1551static int ql_port_start(struct ql3_adapter *qdev)
1552{
1553 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1554 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3efedf2e
RM		 1555 2) << 7)) {
1556 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1557 qdev->ndev->name);
5a4faa87 1558 return -1;
3efedf2e 1559 }
5a4faa87
RM		 1560
1561 if (ql_is_fiber(qdev)) {
1562 ql_petbi_init(qdev);
1563 } else {
1564 /* Copper port */
3efedf2e 1565 ql_phy_init_ex(qdev);
5a4faa87
RM		 1566 }
1567
1568 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1569 return 0;
1570}
1571
1572static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1573{
1574
1575 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1576 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1577 2) << 7))
1578 return -1;
1579
1580 if (!ql_auto_neg_error(qdev)) {
1581 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1582 /* configure the MAC */
1583 if (netif_msg_link(qdev))
1584 printk(KERN_DEBUG PFX
1585 "%s: Configuring link.\n",
1586 qdev->ndev->
1587 name);
1588 ql_mac_cfg_soft_reset(qdev, 1);
1589 ql_mac_cfg_gig(qdev,
1590 (ql_get_link_speed
1591 (qdev) ==
1592 SPEED_1000));
1593 ql_mac_cfg_full_dup(qdev,
1594 ql_is_link_full_dup
1595 (qdev));
1596 ql_mac_cfg_pause(qdev,
1597 ql_is_neg_pause
1598 (qdev));
1599 ql_mac_cfg_soft_reset(qdev, 0);
1600
1601 /* enable the MAC */
1602 if (netif_msg_link(qdev))
1603 printk(KERN_DEBUG PFX
1604 "%s: Enabling mac.\n",
1605 qdev->ndev->
1606 name);
1607 ql_mac_enable(qdev, 1);
1608 }
1609
1610 if (netif_msg_link(qdev))
1611 printk(KERN_DEBUG PFX
1612 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1613 qdev->ndev->name);
1614 qdev->port_link_state = LS_UP;
1615 netif_start_queue(qdev->ndev);
1616 netif_carrier_on(qdev->ndev);
1617 if (netif_msg_link(qdev))
1618 printk(KERN_INFO PFX
1619 "%s: Link is up at %d Mbps, %s duplex.\n",
1620 qdev->ndev->name,
1621 ql_get_link_speed(qdev),
1622 ql_is_link_full_dup(qdev)
1623 ? "full" : "half");
1624
1625 } else { /* Remote error detected */
1626
1627 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1628 if (netif_msg_link(qdev))
1629 printk(KERN_DEBUG PFX
1630 "%s: Remote error detected. "
1631 "Calling ql_port_start().\n",
1632 qdev->ndev->
1633 name);
1634 /*
1635 * ql_port_start() is shared code and needs
1636 * to lock the PHY on it's own.
1637 */
1638 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1639 if(ql_port_start(qdev)) {/* Restart port */
1640 return -1;
1641 } else
1642 return 0;
1643 }
1644 }
1645 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1646 return 0;
1647}
1648
1649static void ql_link_state_machine(struct ql3_adapter *qdev)
1650{
1651 u32 curr_link_state;
1652 unsigned long hw_flags;
1653
1654 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1655
1656 curr_link_state = ql_get_link_state(qdev);
1657
1658 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1659 if (netif_msg_link(qdev))
1660 printk(KERN_INFO PFX
1661 "%s: Reset in progress, skip processing link "
1662 "state.\n", qdev->ndev->name);
04f10773
BL		 1663
1664 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 1665 return;
1666 }
1667
1668 switch (qdev->port_link_state) {
1669 default:
1670 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1671 ql_port_start(qdev);
1672 }
1673 qdev->port_link_state = LS_DOWN;
1674 /* Fall Through */
1675
1676 case LS_DOWN:
1677 if (netif_msg_link(qdev))
1678 printk(KERN_DEBUG PFX
1679 "%s: port_link_state = LS_DOWN.\n",
1680 qdev->ndev->name);
1681 if (curr_link_state == LS_UP) {
1682 if (netif_msg_link(qdev))
1683 printk(KERN_DEBUG PFX
1684 "%s: curr_link_state = LS_UP.\n",
1685 qdev->ndev->name);
1686 if (ql_is_auto_neg_complete(qdev))
1687 ql_finish_auto_neg(qdev);
1688
1689 if (qdev->port_link_state == LS_UP)
1690 ql_link_down_detect_clear(qdev);
1691
1692 }
1693 break;
1694
1695 case LS_UP:
1696 /*
1697 * See if the link is currently down or went down and came
1698 * back up
1699 */
1700 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1701 if (netif_msg_link(qdev))
1702 printk(KERN_INFO PFX "%s: Link is down.\n",
1703 qdev->ndev->name);
1704 qdev->port_link_state = LS_DOWN;
1705 }
1706 break;
1707 }
1708 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1709}
1710
1711/*
1712 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1713 */
1714static void ql_get_phy_owner(struct ql3_adapter *qdev)
1715{
3efedf2e 1716 if (ql_this_adapter_controls_port(qdev))
5a4faa87
RM		 1717 set_bit(QL_LINK_MASTER,&qdev->flags);
1718 else
1719 clear_bit(QL_LINK_MASTER,&qdev->flags);
1720}
1721
1722/*
1723 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1724 */
1725static void ql_init_scan_mode(struct ql3_adapter *qdev)
1726{
1727 ql_mii_enable_scan_mode(qdev);
1728
1729 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
3efedf2e
RM		 1730 if (ql_this_adapter_controls_port(qdev))
1731 ql_petbi_init_ex(qdev);
5a4faa87 1732 } else {
3efedf2e
RM		 1733 if (ql_this_adapter_controls_port(qdev))
1734 ql_phy_init_ex(qdev);
5a4faa87
RM		 1735 }
1736}
1737
1738/*
1739 * MII_Setup needs to be called before taking the PHY out of reset so that the
1740 * management interface clock speed can be set properly. It would be better if
1741 * we had a way to disable MDC until after the PHY is out of reset, but we
1742 * don't have that capability.
1743 */
1744static int ql_mii_setup(struct ql3_adapter *qdev)
1745{
1746 u32 reg;
1747 struct ql3xxx_port_registers __iomem *port_regs =
1748 qdev->mem_map_registers;
1749
1750 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1751 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1752 2) << 7))
1753 return -1;
1754
bd36b0ac
RM		 1755 if (qdev->device_id == QL3032_DEVICE_ID)
1756 ql_write_page0_reg(qdev,
1757 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1758
5a4faa87
RM		 1759 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1760 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1761
1762 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1763 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1764
1765 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1766 return 0;
1767}
1768
1769static u32 ql_supported_modes(struct ql3_adapter *qdev)
1770{
1771 u32 supported;
1772
1773 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1774 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1775 | SUPPORTED_Autoneg;
1776 } else {
1777 supported = SUPPORTED_10baseT_Half
1778 | SUPPORTED_10baseT_Full
1779 | SUPPORTED_100baseT_Half
1780 | SUPPORTED_100baseT_Full
1781 | SUPPORTED_1000baseT_Half
1782 | SUPPORTED_1000baseT_Full
1783 | SUPPORTED_Autoneg | SUPPORTED_TP;
1784 }
1785
1786 return supported;
1787}
1788
1789static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1790{
1791 int status;
1792 unsigned long hw_flags;
1793 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1794 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1795 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1796 2) << 7)) {
1797 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1798 return 0;
04f10773 1799 }
5a4faa87
RM		 1800 status = ql_is_auto_cfg(qdev);
1801 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1802 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1803 return status;
1804}
1805
1806static u32 ql_get_speed(struct ql3_adapter *qdev)
1807{
1808 u32 status;
1809 unsigned long hw_flags;
1810 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1811 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1812 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1813 2) << 7)) {
1814 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1815 return 0;
04f10773 1816 }
5a4faa87
RM		 1817 status = ql_get_link_speed(qdev);
1818 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1819 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1820 return status;
1821}
1822
1823static int ql_get_full_dup(struct ql3_adapter *qdev)
1824{
1825 int status;
1826 unsigned long hw_flags;
1827 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1828 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1829 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1830 2) << 7)) {
1831 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1832 return 0;
04f10773 1833 }
5a4faa87
RM		 1834 status = ql_is_link_full_dup(qdev);
1835 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1836 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1837 return status;
1838}
1839
1840
1841static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1842{
1843 struct ql3_adapter *qdev = netdev_priv(ndev);
1844
1845 ecmd->transceiver = XCVR_INTERNAL;
1846 ecmd->supported = ql_supported_modes(qdev);
1847
1848 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1849 ecmd->port = PORT_FIBRE;
1850 } else {
1851 ecmd->port = PORT_TP;
1852 ecmd->phy_address = qdev->PHYAddr;
1853 }
1854 ecmd->advertising = ql_supported_modes(qdev);
1855 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1856 ecmd->speed = ql_get_speed(qdev);
1857 ecmd->duplex = ql_get_full_dup(qdev);
1858 return 0;
1859}
1860
1861static void ql_get_drvinfo(struct net_device *ndev,
1862 struct ethtool_drvinfo *drvinfo)
1863{
1864 struct ql3_adapter *qdev = netdev_priv(ndev);
1865 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1866 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1867 strncpy(drvinfo->fw_version, "N/A", 32);
1868 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1869 drvinfo->n_stats = 0;
1870 drvinfo->testinfo_len = 0;
1871 drvinfo->regdump_len = 0;
1872 drvinfo->eedump_len = 0;
1873}
1874
1875static u32 ql_get_msglevel(struct net_device *ndev)
1876{
1877 struct ql3_adapter *qdev = netdev_priv(ndev);
1878 return qdev->msg_enable;
1879}
1880
1881static void ql_set_msglevel(struct net_device *ndev, u32 value)
1882{
1883 struct ql3_adapter *qdev = netdev_priv(ndev);
1884 qdev->msg_enable = value;
1885}
1886
ec826383
RM		 1887static void ql_get_pauseparam(struct net_device *ndev,
1888 struct ethtool_pauseparam *pause)
1889{
1890 struct ql3_adapter *qdev = netdev_priv(ndev);
1891 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1892
1893 u32 reg;
1894 if(qdev->mac_index == 0)
1895 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1896 else
1897 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1898
1899 pause->autoneg = ql_get_auto_cfg_status(qdev);
1900 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1901 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1902}
1903
7282d491 1904static const struct ethtool_ops ql3xxx_ethtool_ops = {
5a4faa87
RM		 1905 .get_settings = ql_get_settings,
1906 .get_drvinfo = ql_get_drvinfo,
5a4faa87
RM		 1907 .get_link = ethtool_op_get_link,
1908 .get_msglevel = ql_get_msglevel,
1909 .set_msglevel = ql_set_msglevel,
ec826383 1910 .get_pauseparam = ql_get_pauseparam,
5a4faa87
RM		 1911};
1912
1913static int ql_populate_free_queue(struct ql3_adapter *qdev)
1914{
1915 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
0f8ab89e
BL		 1916 dma_addr_t map;
1917 int err;
5a4faa87
RM		 1918
1919 while (lrg_buf_cb) {
1920 if (!lrg_buf_cb->skb) {
cd238faa
BL		 1921 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1922 qdev->lrg_buffer_len);
5a4faa87
RM		 1923 if (unlikely(!lrg_buf_cb->skb)) {
1924 printk(KERN_DEBUG PFX
cd238faa 1925 "%s: Failed netdev_alloc_skb().\n",
5a4faa87
RM		 1926 qdev->ndev->name);
1927 break;
1928 } else {
1929 /*
1930 * We save some space to copy the ethhdr from
1931 * first buffer
1932 */
1933 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1934 map = pci_map_single(qdev->pdev,
1935 lrg_buf_cb->skb->data,
1936 qdev->lrg_buffer_len -
1937 QL_HEADER_SPACE,
1938 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 1939
1940 err = pci_dma_mapping_error(map);
1941 if(err) {
1942 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1943 qdev->ndev->name, err);
1944 dev_kfree_skb(lrg_buf_cb->skb);
1945 lrg_buf_cb->skb = NULL;
1946 break;
1947 }
1948
1949
5a4faa87
RM		 1950 lrg_buf_cb->buf_phy_addr_low =
1951 cpu_to_le32(LS_64BITS(map));
1952 lrg_buf_cb->buf_phy_addr_high =
1953 cpu_to_le32(MS_64BITS(map));
1954 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1955 pci_unmap_len_set(lrg_buf_cb, maplen,
1956 qdev->lrg_buffer_len -
1957 QL_HEADER_SPACE);
1958 --qdev->lrg_buf_skb_check;
1959 if (!qdev->lrg_buf_skb_check)
1960 return 1;
1961 }
1962 }
1963 lrg_buf_cb = lrg_buf_cb->next;
1964 }
1965 return 0;
1966}
1967
f67cac01
RM		 1968/*
1969 * Caller holds hw_lock.
1970 */
1971static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1972{
1973 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1974 if (qdev->small_buf_release_cnt >= 16) {
1975 while (qdev->small_buf_release_cnt >= 16) {
1976 qdev->small_buf_q_producer_index++;
1977
1978 if (qdev->small_buf_q_producer_index ==
1979 NUM_SBUFQ_ENTRIES)
1980 qdev->small_buf_q_producer_index = 0;
1981 qdev->small_buf_release_cnt -= 8;
1982 }
1983 wmb();
1984 writel(qdev->small_buf_q_producer_index,
1985 &port_regs->CommonRegs.rxSmallQProducerIndex);
1986 }
1987}
1988
5a4faa87
RM		 1989/*
1990 * Caller holds hw_lock.
1991 */
1992static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1993{
1994 struct bufq_addr_element *lrg_buf_q_ele;
1995 int i;
1996 struct ql_rcv_buf_cb *lrg_buf_cb;
1997 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1998
1999 if ((qdev->lrg_buf_free_count >= 8)
2000 && (qdev->lrg_buf_release_cnt >= 16)) {
2001
2002 if (qdev->lrg_buf_skb_check)
2003 if (!ql_populate_free_queue(qdev))
2004 return;
2005
2006 lrg_buf_q_ele = qdev->lrg_buf_next_free;
2007
2008 while ((qdev->lrg_buf_release_cnt >= 16)
2009 && (qdev->lrg_buf_free_count >= 8)) {
2010
2011 for (i = 0; i < 8; i++) {
2012 lrg_buf_cb =
2013 ql_get_from_lrg_buf_free_list(qdev);
2014 lrg_buf_q_ele->addr_high =
2015 lrg_buf_cb->buf_phy_addr_high;
2016 lrg_buf_q_ele->addr_low =
2017 lrg_buf_cb->buf_phy_addr_low;
2018 lrg_buf_q_ele++;
2019
2020 qdev->lrg_buf_release_cnt--;
2021 }
2022
2023 qdev->lrg_buf_q_producer_index++;
2024
1357bfcf 2025 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
5a4faa87
RM		 2026 qdev->lrg_buf_q_producer_index = 0;
2027
2028 if (qdev->lrg_buf_q_producer_index ==
1357bfcf 2029 (qdev->num_lbufq_entries - 1)) {
5a4faa87
RM		 2030 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2031 }
2032 }
f67cac01 2033 wmb();
5a4faa87 2034 qdev->lrg_buf_next_free = lrg_buf_q_ele;
f67cac01
RM		 2035 writel(qdev->lrg_buf_q_producer_index,
2036 &port_regs->CommonRegs.rxLargeQProducerIndex);
5a4faa87
RM		 2037 }
2038}
2039
2040static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2041 struct ob_mac_iocb_rsp *mac_rsp)
2042{
2043 struct ql_tx_buf_cb *tx_cb;
bd36b0ac 2044 int i;
e8f4df24 2045 int retval = 0;
5a4faa87 2046
e8f4df24
BL		 2047 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2048 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2049 }
2050
5a4faa87 2051 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
e8f4df24
BL		 2052
2053 /* Check the transmit response flags for any errors */
2054 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2055 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2056
2057 qdev->stats.tx_errors++;
2058 retval = -EIO;
2059 goto frame_not_sent;
2060 }
2061
2062 if(tx_cb->seg_count == 0) {
2063 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2064
2065 qdev->stats.tx_errors++;
2066 retval = -EIO;
2067 goto invalid_seg_count;
2068 }
2069
5a4faa87 2070 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 2071 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2072 pci_unmap_len(&tx_cb->map[0], maplen),
2073 PCI_DMA_TODEVICE);
2074 tx_cb->seg_count--;
2075 if (tx_cb->seg_count) {
2076 for (i = 1; i < tx_cb->seg_count; i++) {
2077 pci_unmap_page(qdev->pdev,
2078 pci_unmap_addr(&tx_cb->map[i],
2079 mapaddr),
2080 pci_unmap_len(&tx_cb->map[i], maplen),
2081 PCI_DMA_TODEVICE);
2082 }
2083 }
5a4faa87
RM		 2084 qdev->stats.tx_packets++;
2085 qdev->stats.tx_bytes += tx_cb->skb->len;
e8f4df24
BL		 2086
2087frame_not_sent:
bd36b0ac 2088 dev_kfree_skb_irq(tx_cb->skb);
5a4faa87 2089 tx_cb->skb = NULL;
e8f4df24
BL		 2090
2091invalid_seg_count:
5a4faa87
RM		 2092 atomic_inc(&qdev->tx_count);
2093}
2094
3664006a 2095static void ql_get_sbuf(struct ql3_adapter *qdev)
97916330
RM		 2096{
2097 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2098 qdev->small_buf_index = 0;
2099 qdev->small_buf_release_cnt++;
2100}
2101
3664006a 2102static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
97916330
RM		 2103{
2104 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2105 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2106 qdev->lrg_buf_release_cnt++;
2107 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2108 qdev->lrg_buf_index = 0;
2109 return(lrg_buf_cb);
2110}
2111
bd36b0ac
RM		 2112/*
2113 * The difference between 3022 and 3032 for inbound completions:
2114 * 3022 uses two buffers per completion. The first buffer contains
2115 * (some) header info, the second the remainder of the headers plus
2116 * the data. For this chip we reserve some space at the top of the
2117 * receive buffer so that the header info in buffer one can be
2118 * prepended to the buffer two. Buffer two is the sent up while
2119 * buffer one is returned to the hardware to be reused.
2120 * 3032 receives all of it's data and headers in one buffer for a
2121 * simpler process. 3032 also supports checksum verification as
2122 * can be seen in ql_process_macip_rx_intr().
2123 */
5a4faa87
RM		 2124static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2125 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2126{
5a4faa87
RM		 2127 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2128 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
5a4faa87
RM		 2129 struct sk_buff *skb;
2130 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2131
2132 /*
2133 * Get the inbound address list (small buffer).
2134 */
97916330 2135 ql_get_sbuf(qdev);
5a4faa87 2136
97916330
RM		 2137 if (qdev->device_id == QL3022_DEVICE_ID)
2138 lrg_buf_cb1 = ql_get_lbuf(qdev);
5a4faa87
RM		 2139
2140 /* start of second buffer */
97916330 2141 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87
RM		 2142 skb = lrg_buf_cb2->skb;
2143
2144 qdev->stats.rx_packets++;
2145 qdev->stats.rx_bytes += length;
2146
2147 skb_put(skb, length);
2148 pci_unmap_single(qdev->pdev,
2149 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2150 pci_unmap_len(lrg_buf_cb2, maplen),
2151 PCI_DMA_FROMDEVICE);
2152 prefetch(skb->data);
5a4faa87
RM		 2153 skb->ip_summed = CHECKSUM_NONE;
2154 skb->protocol = eth_type_trans(skb, qdev->ndev);
2155
2156 netif_receive_skb(skb);
2157 qdev->ndev->last_rx = jiffies;
2158 lrg_buf_cb2->skb = NULL;
2159
bd36b0ac
RM		 2160 if (qdev->device_id == QL3022_DEVICE_ID)
2161 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2162 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2163}
2164
2165static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2166 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2167{
5a4faa87
RM		 2168 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2169 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
bd36b0ac 2170 struct sk_buff *skb1 = NULL, *skb2;
5a4faa87
RM		 2171 struct net_device *ndev = qdev->ndev;
2172 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2173 u16 size = 0;
2174
2175 /*
2176 * Get the inbound address list (small buffer).
2177 */
2178
97916330 2179 ql_get_sbuf(qdev);
5a4faa87 2180
bd36b0ac
RM		 2181 if (qdev->device_id == QL3022_DEVICE_ID) {
2182 /* start of first buffer on 3022 */
97916330 2183 lrg_buf_cb1 = ql_get_lbuf(qdev);
bd36b0ac 2184 skb1 = lrg_buf_cb1->skb;
bd36b0ac
RM		 2185 size = ETH_HLEN;
2186 if (*((u16 *) skb1->data) != 0xFFFF)
2187 size += VLAN_ETH_HLEN - ETH_HLEN;
2188 }
5a4faa87
RM		 2189
2190 /* start of second buffer */
97916330 2191 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87 2192 skb2 = lrg_buf_cb2->skb;
5a4faa87 2193
5a4faa87
RM		 2194 skb_put(skb2, length); /* Just the second buffer length here. */
2195 pci_unmap_single(qdev->pdev,
2196 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2197 pci_unmap_len(lrg_buf_cb2, maplen),
2198 PCI_DMA_FROMDEVICE);
2199 prefetch(skb2->data);
2200
5a4faa87 2201 skb2->ip_summed = CHECKSUM_NONE;
bd36b0ac
RM		 2202 if (qdev->device_id == QL3022_DEVICE_ID) {
2203 /*
2204 * Copy the ethhdr from first buffer to second. This
2205 * is necessary for 3022 IP completions.
2206 */
d626f62b
ACM		 2207 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2208 skb_push(skb2, size), size);
bd36b0ac
RM		 2209 } else {
2210 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2211 if (checksum &
2212 (IB_IP_IOCB_RSP_3032_ICE |
b3b1514c 2213 IB_IP_IOCB_RSP_3032_CE)) {
bd36b0ac
RM		 2214 printk(KERN_ERR
2215 "%s: Bad checksum for this %s packet, checksum = %x.\n",
2216 __func__,
2217 ((checksum &
2218 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2219 "UDP"),checksum);
b3b1514c
RM		 2220 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2221 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2222 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
bd36b0ac 2223 skb2->ip_summed = CHECKSUM_UNNECESSARY;
b3b1514c 2224 }
bd36b0ac 2225 }
5a4faa87
RM		 2226 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2227
2228 netif_receive_skb(skb2);
bd36b0ac
RM		 2229 qdev->stats.rx_packets++;
2230 qdev->stats.rx_bytes += length;
5a4faa87
RM		 2231 ndev->last_rx = jiffies;
2232 lrg_buf_cb2->skb = NULL;
2233
bd36b0ac
RM		 2234 if (qdev->device_id == QL3022_DEVICE_ID)
2235 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2236 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2237}
2238
2239static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2240 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2241{
5a4faa87
RM		 2242 struct net_rsp_iocb *net_rsp;
2243 struct net_device *ndev = qdev->ndev;
63b66d12 2244 int work_done = 0;
5a4faa87
RM		 2245
2246 /* While there are entries in the completion queue. */
f67cac01 2247 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
63b66d12 2248 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
5a4faa87
RM		 2249
2250 net_rsp = qdev->rsp_current;
2251 switch (net_rsp->opcode) {
2252
2253 case OPCODE_OB_MAC_IOCB_FN0:
2254 case OPCODE_OB_MAC_IOCB_FN2:
2255 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2256 net_rsp);
2257 (*tx_cleaned)++;
2258 break;
2259
2260 case OPCODE_IB_MAC_IOCB:
bd36b0ac 2261 case OPCODE_IB_3032_MAC_IOCB:
5a4faa87
RM		 2262 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2263 net_rsp);
2264 (*rx_cleaned)++;
2265 break;
2266
2267 case OPCODE_IB_IP_IOCB:
bd36b0ac 2268 case OPCODE_IB_3032_IP_IOCB:
5a4faa87
RM		 2269 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2270 net_rsp);
2271 (*rx_cleaned)++;
2272 break;
2273 default:
2274 {
2275 u32 *tmp = (u32 *) net_rsp;
2276 printk(KERN_ERR PFX
2277 "%s: Hit default case, not "
2278 "handled!\n"
2279 " dropping the packet, opcode = "
2280 "%x.\n",
2281 ndev->name, net_rsp->opcode);
2282 printk(KERN_ERR PFX
2283 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2284 (unsigned long int)tmp[0],
2285 (unsigned long int)tmp[1],
2286 (unsigned long int)tmp[2],
2287 (unsigned long int)tmp[3]);
2288 }
2289 }
2290
2291 qdev->rsp_consumer_index++;
2292
2293 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2294 qdev->rsp_consumer_index = 0;
2295 qdev->rsp_current = qdev->rsp_q_virt_addr;
2296 } else {
2297 qdev->rsp_current++;
2298 }
63b66d12
RM		 2299
2300 work_done = *tx_cleaned + *rx_cleaned;
5a4faa87
RM		 2301 }
2302
f67cac01 2303 return work_done;
5a4faa87
RM		 2304}
2305
2306static int ql_poll(struct net_device *ndev, int *budget)
2307{
2308 struct ql3_adapter *qdev = netdev_priv(ndev);
2309 int work_to_do = min(*budget, ndev->quota);
2310 int rx_cleaned = 0, tx_cleaned = 0;
63b66d12
RM		 2311 unsigned long hw_flags;
2312 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
5a4faa87
RM		 2313
2314 if (!netif_carrier_ok(ndev))
2315 goto quit_polling;
2316
2317 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2318 *budget -= rx_cleaned;
2319 ndev->quota -= rx_cleaned;
2320
e8f4df24
BL		 2321 if( tx_cleaned + rx_cleaned != work_to_do ||
2322 !netif_running(ndev)) {
5a4faa87
RM		 2323quit_polling:
2324 netif_rx_complete(ndev);
63b66d12
RM		 2325
2326 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
f67cac01
RM		 2327 ql_update_small_bufq_prod_index(qdev);
2328 ql_update_lrg_bufq_prod_index(qdev);
2329 writel(qdev->rsp_consumer_index,
2330 &port_regs->CommonRegs.rspQConsumerIndex);
63b66d12
RM		 2331 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2332
5a4faa87
RM		 2333 ql_enable_interrupts(qdev);
2334 return 0;
2335 }
2336 return 1;
2337}
2338
7d12e780 2339static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
5a4faa87
RM		 2340{
2341
2342 struct net_device *ndev = dev_id;
2343 struct ql3_adapter *qdev = netdev_priv(ndev);
2344 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2345 u32 value;
2346 int handled = 1;
2347 u32 var;
2348
2349 port_regs = qdev->mem_map_registers;
2350
2351 value =
2352 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2353
2354 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2355 spin_lock(&qdev->adapter_lock);
2356 netif_stop_queue(qdev->ndev);
2357 netif_carrier_off(qdev->ndev);
2358 ql_disable_interrupts(qdev);
2359 qdev->port_link_state = LS_DOWN;
2360 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2361
2362 if (value & ISP_CONTROL_FE) {
2363 /*
2364 * Chip Fatal Error.
2365 */
2366 var =
2367 ql_read_page0_reg_l(qdev,
2368 &port_regs->PortFatalErrStatus);
2369 printk(KERN_WARNING PFX
2370 "%s: Resetting chip. PortFatalErrStatus "
2371 "register = 0x%x\n", ndev->name, var);
2372 set_bit(QL_RESET_START,&qdev->flags) ;
2373 } else {
2374 /*
2375 * Soft Reset Requested.
2376 */
2377 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2378 printk(KERN_ERR PFX
2379 "%s: Another function issued a reset to the "
2380 "chip. ISR value = %x.\n", ndev->name, value);
2381 }
c4028958 2382 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
5a4faa87
RM		 2383 spin_unlock(&qdev->adapter_lock);
2384 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
e8f4df24 2385 ql_disable_interrupts(qdev);
63b66d12 2386 if (likely(netif_rx_schedule_prep(ndev))) {
5a4faa87 2387 __netif_rx_schedule(ndev);
63b66d12 2388 }
5a4faa87
RM		 2389 } else {
2390 return IRQ_NONE;
2391 }
2392
2393 return IRQ_RETVAL(handled);
2394}
2395
bd36b0ac
RM		 2396/*
2397 * Get the total number of segments needed for the
2398 * given number of fragments. This is necessary because
2399 * outbound address lists (OAL) will be used when more than
2400 * two frags are given. Each address list has 5 addr/len
2401 * pairs. The 5th pair in each AOL is used to point to
2402 * the next AOL if more frags are coming.
2403 * That is why the frags:segment count ratio is not linear.
2404 */
e8f4df24
BL		 2405static int ql_get_seg_count(struct ql3_adapter *qdev,
2406 unsigned short frags)
bd36b0ac 2407{
e8f4df24
BL		 2408 if (qdev->device_id == QL3022_DEVICE_ID)
2409 return 1;
2410
bd36b0ac
RM		 2411 switch(frags) {
2412 case 0: return 1; /* just the skb->data seg */
2413 case 1: return 2; /* skb->data + 1 frag */
2414 case 2: return 3; /* skb->data + 2 frags */
2415 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2416 case 4: return 6;
2417 case 5: return 7;
2418 case 6: return 8;
2419 case 7: return 10;
2420 case 8: return 11;
2421 case 9: return 12;
2422 case 10: return 13;
2423 case 11: return 15;
2424 case 12: return 16;
2425 case 13: return 17;
2426 case 14: return 18;
2427 case 15: return 20;
2428 case 16: return 21;
2429 case 17: return 22;
2430 case 18: return 23;
2431 }
2432 return -1;
2433}
2434
91e745aa 2435static void ql_hw_csum_setup(const struct sk_buff *skb,
bd36b0ac
RM		 2436 struct ob_mac_iocb_req *mac_iocb_ptr)
2437{
91e745aa 2438 const struct iphdr *ip = ip_hdr(skb);
bd36b0ac 2439
91e745aa
SH		 2440 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2441 mac_iocb_ptr->ip_hdr_len = ip->ihl;
bd36b0ac 2442
91e745aa
SH		 2443 if (ip->protocol == IPPROTO_TCP) {
2444 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
3e71f6dd 2445 OB_3032MAC_IOCB_REQ_IC;
91e745aa
SH		 2446 } else {
2447 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
3e71f6dd 2448 OB_3032MAC_IOCB_REQ_IC;
bd36b0ac 2449 }
91e745aa 2450
bd36b0ac
RM		 2451}
2452
2453/*
3e71f6dd
RM		 2454 * Map the buffers for this transmit. This will return
2455 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
bd36b0ac 2456 */
3e71f6dd
RM		 2457static int ql_send_map(struct ql3_adapter *qdev,
2458 struct ob_mac_iocb_req *mac_iocb_ptr,
2459 struct ql_tx_buf_cb *tx_cb,
2460 struct sk_buff *skb)
5a4faa87 2461{
bd36b0ac
RM		 2462 struct oal *oal;
2463 struct oal_entry *oal_entry;
63f77926 2464 int len = skb_headlen(skb);
0f8ab89e
BL		 2465 dma_addr_t map;
2466 int err;
2467 int completed_segs, i;
bd36b0ac
RM		 2468 int seg_cnt, seg = 0;
2469 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
5a4faa87 2470
b6967eb9 2471 seg_cnt = tx_cb->seg_count;
3e71f6dd
RM		 2472 /*
2473 * Map the skb buffer first.
2474 */
bd36b0ac 2475 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
0f8ab89e
BL		 2476
2477 err = pci_dma_mapping_error(map);
2478 if(err) {
2479 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2480 qdev->ndev->name, err);
2481
2482 return NETDEV_TX_BUSY;
2483 }
2484
bd36b0ac
RM		 2485 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2486 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2487 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2488 oal_entry->len = cpu_to_le32(len);
2489 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2490 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2491 seg++;
2492
e8f4df24 2493 if (seg_cnt == 1) {
bd36b0ac
RM		 2494 /* Terminate the last segment. */
2495 oal_entry->len =
2496 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2497 } else {
bd36b0ac 2498 oal = tx_cb->oal;
0f8ab89e
BL		 2499 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2500 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
bd36b0ac
RM		 2501 oal_entry++;
2502 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2503 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2504 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2505 (seg == 17 && seg_cnt > 18)) {
2506 /* Continuation entry points to outbound address list. */
2507 map = pci_map_single(qdev->pdev, oal,
2508 sizeof(struct oal),
2509 PCI_DMA_TODEVICE);
0f8ab89e
BL		 2510
2511 err = pci_dma_mapping_error(map);
2512 if(err) {
2513
2514 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2515 qdev->ndev->name, err);
2516 goto map_error;
2517 }
2518
bd36b0ac
RM		 2519 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2520 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2521 oal_entry->len =
2522 cpu_to_le32(sizeof(struct oal) |
2523 OAL_CONT_ENTRY);
2524 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2525 map);
2526 pci_unmap_len_set(&tx_cb->map[seg], maplen,
b6967eb9 2527 sizeof(struct oal));
bd36b0ac
RM		 2528 oal_entry = (struct oal_entry *)oal;
2529 oal++;
2530 seg++;
2531 }
5a4faa87 2532
bd36b0ac
RM		 2533 map =
2534 pci_map_page(qdev->pdev, frag->page,
2535 frag->page_offset, frag->size,
2536 PCI_DMA_TODEVICE);
0f8ab89e
BL		 2537
2538 err = pci_dma_mapping_error(map);
2539 if(err) {
2540 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2541 qdev->ndev->name, err);
2542 goto map_error;
2543 }
2544
bd36b0ac
RM		 2545 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2546 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2547 oal_entry->len = cpu_to_le32(frag->size);
2548 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2549 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2550 frag->size);
2551 }
2552 /* Terminate the last segment. */
2553 oal_entry->len =
2554 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2555 }
0f8ab89e 2556
3e71f6dd 2557 return NETDEV_TX_OK;
0f8ab89e
BL		 2558
2559map_error:
2560 /* A PCI mapping failed and now we will need to back out
2561 * We need to traverse through the oal's and associated pages which
2562 * have been mapped and now we must unmap them to clean up properly
2563 */
2564
2565 seg = 1;
2566 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2567 oal = tx_cb->oal;
2568 for (i=0; i<completed_segs; i++,seg++) {
2569 oal_entry++;
2570
2571 if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2572 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2573 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2574 (seg == 17 && seg_cnt > 18)) {
2575 pci_unmap_single(qdev->pdev,
2576 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2577 pci_unmap_len(&tx_cb->map[seg], maplen),
2578 PCI_DMA_TODEVICE);
2579 oal++;
2580 seg++;
2581 }
2582
2583 pci_unmap_page(qdev->pdev,
2584 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2585 pci_unmap_len(&tx_cb->map[seg], maplen),
2586 PCI_DMA_TODEVICE);
2587 }
2588
2589 pci_unmap_single(qdev->pdev,
2590 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2591 pci_unmap_addr(&tx_cb->map[0], maplen),
2592 PCI_DMA_TODEVICE);
2593
2594 return NETDEV_TX_BUSY;
2595
3e71f6dd
RM		 2596}
2597
2598/*
2599 * The difference between 3022 and 3032 sends:
2600 * 3022 only supports a simple single segment transmission.
2601 * 3032 supports checksumming and scatter/gather lists (fragments).
2602 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2603 * in the IOCB plus a chain of outbound address lists (OAL) that
2604 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2605 * will used to point to an OAL when more ALP entries are required.
2606 * The IOCB is always the top of the chain followed by one or more
2607 * OALs (when necessary).
2608 */
2609static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2610{
2611 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2612 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2613 struct ql_tx_buf_cb *tx_cb;
2614 u32 tot_len = skb->len;
2615 struct ob_mac_iocb_req *mac_iocb_ptr;
2616
2617 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
3e71f6dd
RM		 2618 return NETDEV_TX_BUSY;
2619 }
2620
2621 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
e8f4df24
BL		 2622 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2623 (skb_shinfo(skb)->nr_frags))) == -1) {
3e71f6dd
RM		 2624 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2625 return NETDEV_TX_OK;
2626 }
2627
2628 mac_iocb_ptr = tx_cb->queue_entry;
d8a759ff 2629 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
3e71f6dd
RM		 2630 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2631 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2632 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2633 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2634 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2635 tx_cb->skb = skb;
e8f4df24
BL		 2636 if (qdev->device_id == QL3032_DEVICE_ID &&
2637 skb->ip_summed == CHECKSUM_PARTIAL)
3e71f6dd
RM		 2638 ql_hw_csum_setup(skb, mac_iocb_ptr);
2639
2640 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2641 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2642 return NETDEV_TX_BUSY;
2643 }
2644
bd36b0ac 2645 wmb();
5a4faa87
RM		 2646 qdev->req_producer_index++;
2647 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2648 qdev->req_producer_index = 0;
2649 wmb();
2650 ql_write_common_reg_l(qdev,
ee111d11 2651 &port_regs->CommonRegs.reqQProducerIndex,
5a4faa87
RM		 2652 qdev->req_producer_index);
2653
2654 ndev->trans_start = jiffies;
2655 if (netif_msg_tx_queued(qdev))
2656 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2657 ndev->name, qdev->req_producer_index, skb->len);
2658
bd36b0ac 2659 atomic_dec(&qdev->tx_count);
5a4faa87
RM		 2660 return NETDEV_TX_OK;
2661}
bd36b0ac 2662
5a4faa87
RM		 2663static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2664{
2665 qdev->req_q_size =
2666 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2667
2668 qdev->req_q_virt_addr =
2669 pci_alloc_consistent(qdev->pdev,
2670 (size_t) qdev->req_q_size,
2671 &qdev->req_q_phy_addr);
2672
2673 if ((qdev->req_q_virt_addr == NULL) ||
2674 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2675 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2676 qdev->ndev->name);
2677 return -ENOMEM;
2678 }
2679
2680 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2681
2682 qdev->rsp_q_virt_addr =
2683 pci_alloc_consistent(qdev->pdev,
2684 (size_t) qdev->rsp_q_size,
2685 &qdev->rsp_q_phy_addr);
2686
2687 if ((qdev->rsp_q_virt_addr == NULL) ||
2688 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2689 printk(KERN_ERR PFX
2690 "%s: rspQ allocation failed\n",
2691 qdev->ndev->name);
2692 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2693 qdev->req_q_virt_addr,
2694 qdev->req_q_phy_addr);
2695 return -ENOMEM;
2696 }
2697
2698 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2699
2700 return 0;
2701}
2702
2703static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2704{
2705 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2706 printk(KERN_INFO PFX
2707 "%s: Already done.\n", qdev->ndev->name);
2708 return;
2709 }
2710
2711 pci_free_consistent(qdev->pdev,
2712 qdev->req_q_size,
2713 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2714
2715 qdev->req_q_virt_addr = NULL;
2716
2717 pci_free_consistent(qdev->pdev,
2718 qdev->rsp_q_size,
2719 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2720
2721 qdev->rsp_q_virt_addr = NULL;
2722
2723 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2724}
2725
2726static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2727{
2728 /* Create Large Buffer Queue */
2729 qdev->lrg_buf_q_size =
1357bfcf 2730 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
5a4faa87
RM		 2731 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2732 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2733 else
2734 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2735
1357bfcf
RM		 2736 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2737 if (qdev->lrg_buf == NULL) {
2738 printk(KERN_ERR PFX
2739 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2740 return -ENOMEM;
2741 }
2742
5a4faa87
RM		 2743 qdev->lrg_buf_q_alloc_virt_addr =
2744 pci_alloc_consistent(qdev->pdev,
2745 qdev->lrg_buf_q_alloc_size,
2746 &qdev->lrg_buf_q_alloc_phy_addr);
2747
2748 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2749 printk(KERN_ERR PFX
2750 "%s: lBufQ failed\n", qdev->ndev->name);
2751 return -ENOMEM;
2752 }
2753 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2754 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2755
2756 /* Create Small Buffer Queue */
2757 qdev->small_buf_q_size =
2758 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2759 if (qdev->small_buf_q_size < PAGE_SIZE)
2760 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2761 else
2762 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2763
2764 qdev->small_buf_q_alloc_virt_addr =
2765 pci_alloc_consistent(qdev->pdev,
2766 qdev->small_buf_q_alloc_size,
2767 &qdev->small_buf_q_alloc_phy_addr);
2768
2769 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2770 printk(KERN_ERR PFX
2771 "%s: Small Buffer Queue allocation failed.\n",
2772 qdev->ndev->name);
2773 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2774 qdev->lrg_buf_q_alloc_virt_addr,
2775 qdev->lrg_buf_q_alloc_phy_addr);
2776 return -ENOMEM;
2777 }
2778
2779 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2780 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2781 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2782 return 0;
2783}
2784
2785static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2786{
2787 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2788 printk(KERN_INFO PFX
2789 "%s: Already done.\n", qdev->ndev->name);
2790 return;
2791 }
1357bfcf 2792 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
5a4faa87
RM		 2793 pci_free_consistent(qdev->pdev,
2794 qdev->lrg_buf_q_alloc_size,
2795 qdev->lrg_buf_q_alloc_virt_addr,
2796 qdev->lrg_buf_q_alloc_phy_addr);
2797
2798 qdev->lrg_buf_q_virt_addr = NULL;
2799
2800 pci_free_consistent(qdev->pdev,
2801 qdev->small_buf_q_alloc_size,
2802 qdev->small_buf_q_alloc_virt_addr,
2803 qdev->small_buf_q_alloc_phy_addr);
2804
2805 qdev->small_buf_q_virt_addr = NULL;
2806
2807 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2808}
2809
2810static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2811{
2812 int i;
2813 struct bufq_addr_element *small_buf_q_entry;
2814
2815 /* Currently we allocate on one of memory and use it for smallbuffers */
2816 qdev->small_buf_total_size =
2817 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2818 QL_SMALL_BUFFER_SIZE);
2819
2820 qdev->small_buf_virt_addr =
2821 pci_alloc_consistent(qdev->pdev,
2822 qdev->small_buf_total_size,
2823 &qdev->small_buf_phy_addr);
2824
2825 if (qdev->small_buf_virt_addr == NULL) {
2826 printk(KERN_ERR PFX
2827 "%s: Failed to get small buffer memory.\n",
2828 qdev->ndev->name);
2829 return -ENOMEM;
2830 }
2831
2832 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2833 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2834
2835 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2836
5a4faa87
RM		 2837 /* Initialize the small buffer queue. */
2838 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2839 small_buf_q_entry->addr_high =
2840 cpu_to_le32(qdev->small_buf_phy_addr_high);
2841 small_buf_q_entry->addr_low =
2842 cpu_to_le32(qdev->small_buf_phy_addr_low +
2843 (i * QL_SMALL_BUFFER_SIZE));
2844 small_buf_q_entry++;
2845 }
2846 qdev->small_buf_index = 0;
2847 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2848 return 0;
2849}
2850
2851static void ql_free_small_buffers(struct ql3_adapter *qdev)
2852{
2853 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2854 printk(KERN_INFO PFX
2855 "%s: Already done.\n", qdev->ndev->name);
2856 return;
2857 }
2858 if (qdev->small_buf_virt_addr != NULL) {
2859 pci_free_consistent(qdev->pdev,
2860 qdev->small_buf_total_size,
2861 qdev->small_buf_virt_addr,
2862 qdev->small_buf_phy_addr);
2863
2864 qdev->small_buf_virt_addr = NULL;
2865 }
2866}
2867
2868static void ql_free_large_buffers(struct ql3_adapter *qdev)
2869{
2870 int i = 0;
2871 struct ql_rcv_buf_cb *lrg_buf_cb;
2872
1357bfcf 2873 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2874 lrg_buf_cb = &qdev->lrg_buf[i];
2875 if (lrg_buf_cb->skb) {
2876 dev_kfree_skb(lrg_buf_cb->skb);
2877 pci_unmap_single(qdev->pdev,
2878 pci_unmap_addr(lrg_buf_cb, mapaddr),
2879 pci_unmap_len(lrg_buf_cb, maplen),
2880 PCI_DMA_FROMDEVICE);
2881 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2882 } else {
2883 break;
2884 }
2885 }
2886}
2887
2888static void ql_init_large_buffers(struct ql3_adapter *qdev)
2889{
2890 int i;
2891 struct ql_rcv_buf_cb *lrg_buf_cb;
2892 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2893
1357bfcf 2894 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2895 lrg_buf_cb = &qdev->lrg_buf[i];
2896 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2897 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2898 buf_addr_ele++;
2899 }
2900 qdev->lrg_buf_index = 0;
2901 qdev->lrg_buf_skb_check = 0;
2902}
2903
2904static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2905{
2906 int i;
2907 struct ql_rcv_buf_cb *lrg_buf_cb;
2908 struct sk_buff *skb;
0f8ab89e
BL		 2909 dma_addr_t map;
2910 int err;
5a4faa87 2911
1357bfcf 2912 for (i = 0; i < qdev->num_large_buffers; i++) {
cd238faa
BL		 2913 skb = netdev_alloc_skb(qdev->ndev,
2914 qdev->lrg_buffer_len);
5a4faa87
RM		 2915 if (unlikely(!skb)) {
2916 /* Better luck next round */
2917 printk(KERN_ERR PFX
2918 "%s: large buff alloc failed, "
2919 "for %d bytes at index %d.\n",
2920 qdev->ndev->name,
2921 qdev->lrg_buffer_len * 2, i);
2922 ql_free_large_buffers(qdev);
2923 return -ENOMEM;
2924 } else {
2925
2926 lrg_buf_cb = &qdev->lrg_buf[i];
2927 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2928 lrg_buf_cb->index = i;
2929 lrg_buf_cb->skb = skb;
2930 /*
2931 * We save some space to copy the ethhdr from first
2932 * buffer
2933 */
2934 skb_reserve(skb, QL_HEADER_SPACE);
2935 map = pci_map_single(qdev->pdev,
2936 skb->data,
2937 qdev->lrg_buffer_len -
2938 QL_HEADER_SPACE,
2939 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 2940
2941 err = pci_dma_mapping_error(map);
2942 if(err) {
2943 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2944 qdev->ndev->name, err);
2945 ql_free_large_buffers(qdev);
2946 return -ENOMEM;
2947 }
2948
5a4faa87
RM		 2949 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2950 pci_unmap_len_set(lrg_buf_cb, maplen,
2951 qdev->lrg_buffer_len -
2952 QL_HEADER_SPACE);
2953 lrg_buf_cb->buf_phy_addr_low =
2954 cpu_to_le32(LS_64BITS(map));
2955 lrg_buf_cb->buf_phy_addr_high =
2956 cpu_to_le32(MS_64BITS(map));
2957 }
2958 }
2959 return 0;
2960}
2961
bd36b0ac
RM		 2962static void ql_free_send_free_list(struct ql3_adapter *qdev)
2963{
2964 struct ql_tx_buf_cb *tx_cb;
2965 int i;
2966
2967 tx_cb = &qdev->tx_buf[0];
2968 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2969 if (tx_cb->oal) {
2970 kfree(tx_cb->oal);
2971 tx_cb->oal = NULL;
2972 }
2973 tx_cb++;
2974 }
2975}
2976
2977static int ql_create_send_free_list(struct ql3_adapter *qdev)
5a4faa87
RM		 2978{
2979 struct ql_tx_buf_cb *tx_cb;
2980 int i;
2981 struct ob_mac_iocb_req *req_q_curr =
2982 qdev->req_q_virt_addr;
2983
2984 /* Create free list of transmit buffers */
2985 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 2986
5a4faa87
RM		 2987 tx_cb = &qdev->tx_buf[i];
2988 tx_cb->skb = NULL;
2989 tx_cb->queue_entry = req_q_curr;
2990 req_q_curr++;
bd36b0ac
RM		 2991 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2992 if (tx_cb->oal == NULL)
2993 return -1;
5a4faa87 2994 }
bd36b0ac 2995 return 0;
5a4faa87
RM		 2996}
2997
2998static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2999{
1357bfcf
RM		 3000 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
3001 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
5a4faa87 3002 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
1357bfcf 3003 }
5a4faa87 3004 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
1357bfcf
RM		 3005 /*
3006 * Bigger buffers, so less of them.
3007 */
3008 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
5a4faa87
RM		 3009 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
3010 } else {
3011 printk(KERN_ERR PFX
3012 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
3013 qdev->ndev->name);
3014 return -ENOMEM;
3015 }
1357bfcf 3016 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
5a4faa87
RM		 3017 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
3018 qdev->max_frame_size =
3019 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
3020
3021 /*
3022 * First allocate a page of shared memory and use it for shadow
3023 * locations of Network Request Queue Consumer Address Register and
3024 * Network Completion Queue Producer Index Register
3025 */
3026 qdev->shadow_reg_virt_addr =
3027 pci_alloc_consistent(qdev->pdev,
3028 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3029
3030 if (qdev->shadow_reg_virt_addr != NULL) {
3031 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3032 qdev->req_consumer_index_phy_addr_high =
3033 MS_64BITS(qdev->shadow_reg_phy_addr);
3034 qdev->req_consumer_index_phy_addr_low =
3035 LS_64BITS(qdev->shadow_reg_phy_addr);
3036
3037 qdev->prsp_producer_index =
3038 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3039 qdev->rsp_producer_index_phy_addr_high =
3040 qdev->req_consumer_index_phy_addr_high;
3041 qdev->rsp_producer_index_phy_addr_low =
3042 qdev->req_consumer_index_phy_addr_low + 8;
3043 } else {
3044 printk(KERN_ERR PFX
3045 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3046 return -ENOMEM;
3047 }
3048
3049 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3050 printk(KERN_ERR PFX
3051 "%s: ql_alloc_net_req_rsp_queues failed.\n",
3052 qdev->ndev->name);
3053 goto err_req_rsp;
3054 }
3055
3056 if (ql_alloc_buffer_queues(qdev) != 0) {
3057 printk(KERN_ERR PFX
3058 "%s: ql_alloc_buffer_queues failed.\n",
3059 qdev->ndev->name);
3060 goto err_buffer_queues;
3061 }
3062
3063 if (ql_alloc_small_buffers(qdev) != 0) {
3064 printk(KERN_ERR PFX
3065 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3066 goto err_small_buffers;
3067 }
3068
3069 if (ql_alloc_large_buffers(qdev) != 0) {
3070 printk(KERN_ERR PFX
3071 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3072 goto err_small_buffers;
3073 }
3074
3075 /* Initialize the large buffer queue. */
3076 ql_init_large_buffers(qdev);
bd36b0ac
RM		 3077 if (ql_create_send_free_list(qdev))
3078 goto err_free_list;
5a4faa87
RM		 3079
3080 qdev->rsp_current = qdev->rsp_q_virt_addr;
3081
3082 return 0;
bd36b0ac
RM		 3083err_free_list:
3084 ql_free_send_free_list(qdev);
5a4faa87
RM		 3085err_small_buffers:
3086 ql_free_buffer_queues(qdev);
3087err_buffer_queues:
3088 ql_free_net_req_rsp_queues(qdev);
3089err_req_rsp:
3090 pci_free_consistent(qdev->pdev,
3091 PAGE_SIZE,
3092 qdev->shadow_reg_virt_addr,
3093 qdev->shadow_reg_phy_addr);
3094
3095 return -ENOMEM;
3096}
3097
3098static void ql_free_mem_resources(struct ql3_adapter *qdev)
3099{
bd36b0ac 3100 ql_free_send_free_list(qdev);
5a4faa87
RM		 3101 ql_free_large_buffers(qdev);
3102 ql_free_small_buffers(qdev);
3103 ql_free_buffer_queues(qdev);
3104 ql_free_net_req_rsp_queues(qdev);
3105 if (qdev->shadow_reg_virt_addr != NULL) {
3106 pci_free_consistent(qdev->pdev,
3107 PAGE_SIZE,
3108 qdev->shadow_reg_virt_addr,
3109 qdev->shadow_reg_phy_addr);
3110 qdev->shadow_reg_virt_addr = NULL;
3111 }
3112}
3113
3114static int ql_init_misc_registers(struct ql3_adapter *qdev)
3115{
ee111d11
AV		 3116 struct ql3xxx_local_ram_registers __iomem *local_ram =
3117 (void __iomem *)qdev->mem_map_registers;
5a4faa87
RM		 3118
3119 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3120 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3121 2) << 4))
3122 return -1;
3123
3124 ql_write_page2_reg(qdev,
3125 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3126
3127 ql_write_page2_reg(qdev,
3128 &local_ram->maxBufletCount,
3129 qdev->nvram_data.bufletCount);
3130
3131 ql_write_page2_reg(qdev,
3132 &local_ram->freeBufletThresholdLow,
3133 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3134 (qdev->nvram_data.tcpWindowThreshold0));
3135
3136 ql_write_page2_reg(qdev,
3137 &local_ram->freeBufletThresholdHigh,
3138 qdev->nvram_data.tcpWindowThreshold50);
3139
3140 ql_write_page2_reg(qdev,
3141 &local_ram->ipHashTableBase,
3142 (qdev->nvram_data.ipHashTableBaseHi << 16) |
3143 qdev->nvram_data.ipHashTableBaseLo);
3144 ql_write_page2_reg(qdev,
3145 &local_ram->ipHashTableCount,
3146 qdev->nvram_data.ipHashTableSize);
3147 ql_write_page2_reg(qdev,
3148 &local_ram->tcpHashTableBase,
3149 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3150 qdev->nvram_data.tcpHashTableBaseLo);
3151 ql_write_page2_reg(qdev,
3152 &local_ram->tcpHashTableCount,
3153 qdev->nvram_data.tcpHashTableSize);
3154 ql_write_page2_reg(qdev,
3155 &local_ram->ncbBase,
3156 (qdev->nvram_data.ncbTableBaseHi << 16) |
3157 qdev->nvram_data.ncbTableBaseLo);
3158 ql_write_page2_reg(qdev,
3159 &local_ram->maxNcbCount,
3160 qdev->nvram_data.ncbTableSize);
3161 ql_write_page2_reg(qdev,
3162 &local_ram->drbBase,
3163 (qdev->nvram_data.drbTableBaseHi << 16) |
3164 qdev->nvram_data.drbTableBaseLo);
3165 ql_write_page2_reg(qdev,
3166 &local_ram->maxDrbCount,
3167 qdev->nvram_data.drbTableSize);
3168 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3169 return 0;
3170}
3171
3172static int ql_adapter_initialize(struct ql3_adapter *qdev)
3173{
3174 u32 value;
3175 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3176 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
ee111d11 3177 (void __iomem *)port_regs;
5a4faa87
RM		 3178 u32 delay = 10;
3179 int status = 0;
3180
3181 if(ql_mii_setup(qdev))
3182 return -1;
3183
3184 /* Bring out PHY out of reset */
3185 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3186 (ISP_SERIAL_PORT_IF_WE |
3187 (ISP_SERIAL_PORT_IF_WE << 16)));
3188
3189 qdev->port_link_state = LS_DOWN;
3190 netif_carrier_off(qdev->ndev);
3191
3192 /* V2 chip fix for ARS-39168. */
3193 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3194 (ISP_SERIAL_PORT_IF_SDE |
3195 (ISP_SERIAL_PORT_IF_SDE << 16)));
3196
3197 /* Request Queue Registers */
3198 *((u32 *) (qdev->preq_consumer_index)) = 0;
3199 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3200 qdev->req_producer_index = 0;
3201
3202 ql_write_page1_reg(qdev,
3203 &hmem_regs->reqConsumerIndexAddrHigh,
3204 qdev->req_consumer_index_phy_addr_high);
3205 ql_write_page1_reg(qdev,
3206 &hmem_regs->reqConsumerIndexAddrLow,
3207 qdev->req_consumer_index_phy_addr_low);
3208
3209 ql_write_page1_reg(qdev,
3210 &hmem_regs->reqBaseAddrHigh,
3211 MS_64BITS(qdev->req_q_phy_addr));
3212 ql_write_page1_reg(qdev,
3213 &hmem_regs->reqBaseAddrLow,
3214 LS_64BITS(qdev->req_q_phy_addr));
3215 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3216
3217 /* Response Queue Registers */
3218 *((u16 *) (qdev->prsp_producer_index)) = 0;
3219 qdev->rsp_consumer_index = 0;
3220 qdev->rsp_current = qdev->rsp_q_virt_addr;
3221
3222 ql_write_page1_reg(qdev,
3223 &hmem_regs->rspProducerIndexAddrHigh,
3224 qdev->rsp_producer_index_phy_addr_high);
3225
3226 ql_write_page1_reg(qdev,
3227 &hmem_regs->rspProducerIndexAddrLow,
3228 qdev->rsp_producer_index_phy_addr_low);
3229
3230 ql_write_page1_reg(qdev,
3231 &hmem_regs->rspBaseAddrHigh,
3232 MS_64BITS(qdev->rsp_q_phy_addr));
3233
3234 ql_write_page1_reg(qdev,
3235 &hmem_regs->rspBaseAddrLow,
3236 LS_64BITS(qdev->rsp_q_phy_addr));
3237
3238 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3239
3240 /* Large Buffer Queue */
3241 ql_write_page1_reg(qdev,
3242 &hmem_regs->rxLargeQBaseAddrHigh,
3243 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3244
3245 ql_write_page1_reg(qdev,
3246 &hmem_regs->rxLargeQBaseAddrLow,
3247 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3248
1357bfcf 3249 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
5a4faa87
RM		 3250
3251 ql_write_page1_reg(qdev,
3252 &hmem_regs->rxLargeBufferLength,
3253 qdev->lrg_buffer_len);
3254
3255 /* Small Buffer Queue */
3256 ql_write_page1_reg(qdev,
3257 &hmem_regs->rxSmallQBaseAddrHigh,
3258 MS_64BITS(qdev->small_buf_q_phy_addr));
3259
3260 ql_write_page1_reg(qdev,
3261 &hmem_regs->rxSmallQBaseAddrLow,
3262 LS_64BITS(qdev->small_buf_q_phy_addr));
3263
3264 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3265 ql_write_page1_reg(qdev,
3266 &hmem_regs->rxSmallBufferLength,
3267 QL_SMALL_BUFFER_SIZE);
3268
3269 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3270 qdev->small_buf_release_cnt = 8;
1357bfcf 3271 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
5a4faa87
RM		 3272 qdev->lrg_buf_release_cnt = 8;
3273 qdev->lrg_buf_next_free =
3274 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3275 qdev->small_buf_index = 0;
3276 qdev->lrg_buf_index = 0;
3277 qdev->lrg_buf_free_count = 0;
3278 qdev->lrg_buf_free_head = NULL;
3279 qdev->lrg_buf_free_tail = NULL;
3280
3281 ql_write_common_reg(qdev,
ee111d11 3282 &port_regs->CommonRegs.
5a4faa87
RM		 3283 rxSmallQProducerIndex,
3284 qdev->small_buf_q_producer_index);
3285 ql_write_common_reg(qdev,
ee111d11 3286 &port_regs->CommonRegs.
5a4faa87
RM		 3287 rxLargeQProducerIndex,
3288 qdev->lrg_buf_q_producer_index);
3289
3290 /*
3291 * Find out if the chip has already been initialized. If it has, then
3292 * we skip some of the initialization.
3293 */
3294 clear_bit(QL_LINK_MASTER, &qdev->flags);
3295 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3296 if ((value & PORT_STATUS_IC) == 0) {
3297
3298 /* Chip has not been configured yet, so let it rip. */
3299 if(ql_init_misc_registers(qdev)) {
3300 status = -1;
3301 goto out;
3302 }
3303
5a4faa87
RM		 3304 value = qdev->nvram_data.tcpMaxWindowSize;
3305 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3306
3307 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3308
3309 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3310 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3311 * 2) << 13)) {
3312 status = -1;
3313 goto out;
3314 }
3315 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3316 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3317 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3318 16) | (INTERNAL_CHIP_SD |
3319 INTERNAL_CHIP_WE)));
3320 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3321 }
3322
b3b1514c
RM		 3323 if (qdev->mac_index)
3324 ql_write_page0_reg(qdev,
3325 &port_regs->mac1MaxFrameLengthReg,
3326 qdev->max_frame_size);
3327 else
3328 ql_write_page0_reg(qdev,
3329 &port_regs->mac0MaxFrameLengthReg,
3330 qdev->max_frame_size);
5a4faa87
RM		 3331
3332 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3333 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3334 2) << 7)) {
3335 status = -1;
3336 goto out;
3337 }
3338
3efedf2e 3339 PHY_Setup(qdev);
5a4faa87
RM		 3340 ql_init_scan_mode(qdev);
3341 ql_get_phy_owner(qdev);
3342
3343 /* Load the MAC Configuration */
3344
3345 /* Program lower 32 bits of the MAC address */
3346 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3347 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3348 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3349 ((qdev->ndev->dev_addr[2] << 24)
3350 | (qdev->ndev->dev_addr[3] << 16)
3351 | (qdev->ndev->dev_addr[4] << 8)
3352 | qdev->ndev->dev_addr[5]));
3353
3354 /* Program top 16 bits of the MAC address */
3355 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3356 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3357 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3358 ((qdev->ndev->dev_addr[0] << 8)
3359 | qdev->ndev->dev_addr[1]));
3360
3361 /* Enable Primary MAC */
3362 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3363 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3364 MAC_ADDR_INDIRECT_PTR_REG_PE));
3365
3366 /* Clear Primary and Secondary IP addresses */
3367 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3368 ((IP_ADDR_INDEX_REG_MASK << 16) |
3369 (qdev->mac_index << 2)));
3370 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3371
3372 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3373 ((IP_ADDR_INDEX_REG_MASK << 16) |
3374 ((qdev->mac_index << 2) + 1)));
3375 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3376
3377 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3378
3379 /* Indicate Configuration Complete */
3380 ql_write_page0_reg(qdev,
3381 &port_regs->portControl,
3382 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3383
3384 do {
3385 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3386 if (value & PORT_STATUS_IC)
3387 break;
3388 msleep(500);
3389 } while (--delay);
3390
3391 if (delay == 0) {
3392 printk(KERN_ERR PFX
3393 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3394 status = -1;
3395 goto out;
3396 }
3397
3398 /* Enable Ethernet Function */
bd36b0ac
RM		 3399 if (qdev->device_id == QL3032_DEVICE_ID) {
3400 value =
3401 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
b3b1514c
RM		 3402 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3403 QL3032_PORT_CONTROL_ET);
bd36b0ac
RM		 3404 ql_write_page0_reg(qdev, &port_regs->functionControl,
3405 ((value << 16) | value));
3406 } else {
3407 value =
3408 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3409 PORT_CONTROL_HH);
3410 ql_write_page0_reg(qdev, &port_regs->portControl,
3411 ((value << 16) | value));
3412 }
3413
5a4faa87
RM		 3414
3415out:
3416 return status;
3417}
3418
3419/*
3420 * Caller holds hw_lock.
3421 */
3422static int ql_adapter_reset(struct ql3_adapter *qdev)
3423{
3424 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3425 int status = 0;
3426 u16 value;
3427 int max_wait_time;
3428
3429 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3430 clear_bit(QL_RESET_DONE, &qdev->flags);
3431
3432 /*
3433 * Issue soft reset to chip.
3434 */
3435 printk(KERN_DEBUG PFX
3436 "%s: Issue soft reset to chip.\n",
3437 qdev->ndev->name);
3438 ql_write_common_reg(qdev,
ee111d11 3439 &port_regs->CommonRegs.ispControlStatus,
5a4faa87
RM		 3440 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3441
3442 /* Wait 3 seconds for reset to complete. */
3443 printk(KERN_DEBUG PFX
3444 "%s: Wait 10 milliseconds for reset to complete.\n",
3445 qdev->ndev->name);
3446
3447 /* Wait until the firmware tells us the Soft Reset is done */
3448 max_wait_time = 5;
3449 do {
3450 value =
3451 ql_read_common_reg(qdev,
3452 &port_regs->CommonRegs.ispControlStatus);
3453 if ((value & ISP_CONTROL_SR) == 0)
3454 break;
3455
3456 ssleep(1);
3457 } while ((--max_wait_time));
3458
3459 /*
3460 * Also, make sure that the Network Reset Interrupt bit has been
3461 * cleared after the soft reset has taken place.
3462 */
3463 value =
3464 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3465 if (value & ISP_CONTROL_RI) {
3466 printk(KERN_DEBUG PFX
3467 "ql_adapter_reset: clearing RI after reset.\n");
3468 ql_write_common_reg(qdev,
ee111d11 3469 &port_regs->CommonRegs.
5a4faa87
RM		 3470 ispControlStatus,
3471 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3472 }
3473
3474 if (max_wait_time == 0) {
3475 /* Issue Force Soft Reset */
3476 ql_write_common_reg(qdev,
ee111d11 3477 &port_regs->CommonRegs.
5a4faa87
RM		 3478 ispControlStatus,
3479 ((ISP_CONTROL_FSR << 16) |
3480 ISP_CONTROL_FSR));
3481 /*
3482 * Wait until the firmware tells us the Force Soft Reset is
3483 * done
3484 */
3485 max_wait_time = 5;
3486 do {
3487 value =
3488 ql_read_common_reg(qdev,
3489 &port_regs->CommonRegs.
3490 ispControlStatus);
3491 if ((value & ISP_CONTROL_FSR) == 0) {
3492 break;
3493 }
3494 ssleep(1);
3495 } while ((--max_wait_time));
3496 }
3497 if (max_wait_time == 0)
3498 status = 1;
3499
3500 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3501 set_bit(QL_RESET_DONE, &qdev->flags);
3502 return status;
3503}
3504
3505static void ql_set_mac_info(struct ql3_adapter *qdev)
3506{
3507 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3508 u32 value, port_status;
3509 u8 func_number;
3510
3511 /* Get the function number */
3512 value =
3513 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3514 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3515 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3516 switch (value & ISP_CONTROL_FN_MASK) {
3517 case ISP_CONTROL_FN0_NET:
3518 qdev->mac_index = 0;
3519 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3520 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3521 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3522 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3523 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3524 if (port_status & PORT_STATUS_SM0)
3525 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3526 else
3527 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3528 break;
3529
3530 case ISP_CONTROL_FN1_NET:
3531 qdev->mac_index = 1;
3532 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3533 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3534 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3535 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3536 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3537 if (port_status & PORT_STATUS_SM1)
3538 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3539 else
3540 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3541 break;
3542
3543 case ISP_CONTROL_FN0_SCSI:
3544 case ISP_CONTROL_FN1_SCSI:
3545 default:
3546 printk(KERN_DEBUG PFX
3547 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3548 qdev->ndev->name,value);
3549 break;
3550 }
3551 qdev->numPorts = qdev->nvram_data.numPorts;
3552}
3553
3554static void ql_display_dev_info(struct net_device *ndev)
3555{
3556 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3557 struct pci_dev *pdev = qdev->pdev;
3558
3559 printk(KERN_INFO PFX
bd36b0ac
RM		 3560 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3561 DRV_NAME, qdev->index, qdev->chip_rev_id,
3562 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3563 qdev->pci_slot);
5a4faa87
RM		 3564 printk(KERN_INFO PFX
3565 "%s Interface.\n",
3566 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3567
3568 /*
3569 * Print PCI bus width/type.
3570 */
3571 printk(KERN_INFO PFX
3572 "Bus interface is %s %s.\n",
3573 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3574 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3575
3576 printk(KERN_INFO PFX
3577 "mem IO base address adjusted = 0x%p\n",
3578 qdev->mem_map_registers);
3579 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3580
3581 if (netif_msg_probe(qdev))
3582 printk(KERN_INFO PFX
3583 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3584 ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3585 ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3586 ndev->dev_addr[5]);
3587}
3588
3589static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3590{
3591 struct net_device *ndev = qdev->ndev;
3592 int retval = 0;
3593
3594 netif_stop_queue(ndev);
3595 netif_carrier_off(ndev);
3596
3597 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3598 clear_bit(QL_LINK_MASTER,&qdev->flags);
3599
3600 ql_disable_interrupts(qdev);
3601
3602 free_irq(qdev->pdev->irq, ndev);
3603
3604 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3605 printk(KERN_INFO PFX
3606 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3607 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3608 pci_disable_msi(qdev->pdev);
3609 }
3610
3611 del_timer_sync(&qdev->adapter_timer);
3612
3613 netif_poll_disable(ndev);
3614
3615 if (do_reset) {
3616 int soft_reset;
3617 unsigned long hw_flags;
3618
3619 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3620 if (ql_wait_for_drvr_lock(qdev)) {
3621 if ((soft_reset = ql_adapter_reset(qdev))) {
3622 printk(KERN_ERR PFX
3623 "%s: ql_adapter_reset(%d) FAILED!\n",
3624 ndev->name, qdev->index);
3625 }
3626 printk(KERN_ERR PFX
3627 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3628 } else {
3629 printk(KERN_ERR PFX
3630 "%s: Could not acquire driver lock to do "
3631 "reset!\n", ndev->name);
3632 retval = -1;
3633 }
3634 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3635 }
3636 ql_free_mem_resources(qdev);
3637 return retval;
3638}
3639
3640static int ql_adapter_up(struct ql3_adapter *qdev)
3641{
3642 struct net_device *ndev = qdev->ndev;
3643 int err;
38515e90 3644 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
5a4faa87
RM		 3645 unsigned long hw_flags;
3646
3647 if (ql_alloc_mem_resources(qdev)) {
3648 printk(KERN_ERR PFX
3649 "%s Unable to allocate buffers.\n", ndev->name);
3650 return -ENOMEM;
3651 }
3652
3653 if (qdev->msi) {
3654 if (pci_enable_msi(qdev->pdev)) {
3655 printk(KERN_ERR PFX
3656 "%s: User requested MSI, but MSI failed to "
3657 "initialize. Continuing without MSI.\n",
3658 qdev->ndev->name);
3659 qdev->msi = 0;
3660 } else {
3661 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3662 set_bit(QL_MSI_ENABLED,&qdev->flags);
38515e90 3663 irq_flags &= ~IRQF_SHARED;
5a4faa87
RM		 3664 }
3665 }
3666
3667 if ((err = request_irq(qdev->pdev->irq,
3668 ql3xxx_isr,
3669 irq_flags, ndev->name, ndev))) {
3670 printk(KERN_ERR PFX
3671 "%s: Failed to reserve interrupt %d already in use.\n",
3672 ndev->name, qdev->pdev->irq);
3673 goto err_irq;
3674 }
3675
3676 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3677
3678 if ((err = ql_wait_for_drvr_lock(qdev))) {
3679 if ((err = ql_adapter_initialize(qdev))) {
3680 printk(KERN_ERR PFX
3681 "%s: Unable to initialize adapter.\n",
3682 ndev->name);
3683 goto err_init;
3684 }
3685 printk(KERN_ERR PFX
3686 "%s: Releaseing driver lock.\n",ndev->name);
3687 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3688 } else {
3689 printk(KERN_ERR PFX
3690 "%s: Could not aquire driver lock.\n",
3691 ndev->name);
3692 goto err_lock;
3693 }
3694
3695 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3696
3697 set_bit(QL_ADAPTER_UP,&qdev->flags);
3698
3699 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3700
3701 netif_poll_enable(ndev);
3702 ql_enable_interrupts(qdev);
3703 return 0;
3704
3705err_init:
3706 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3707err_lock:
04f10773 3708 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 3709 free_irq(qdev->pdev->irq, ndev);
3710err_irq:
3711 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3712 printk(KERN_INFO PFX
3713 "%s: calling pci_disable_msi().\n",
3714 qdev->ndev->name);
3715 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3716 pci_disable_msi(qdev->pdev);
3717 }
3718 return err;
3719}
3720
3721static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3722{
3723 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3724 printk(KERN_ERR PFX
3725 "%s: Driver up/down cycle failed, "
3726 "closing device\n",qdev->ndev->name);
3727 dev_close(qdev->ndev);
3728 return -1;
3729 }
3730 return 0;
3731}
3732
3733static int ql3xxx_close(struct net_device *ndev)
3734{
3735 struct ql3_adapter *qdev = netdev_priv(ndev);
3736
3737 /*
3738 * Wait for device to recover from a reset.
3739 * (Rarely happens, but possible.)
3740 */
3741 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3742 msleep(50);
3743
3744 ql_adapter_down(qdev,QL_DO_RESET);
3745 return 0;
3746}
3747
3748static int ql3xxx_open(struct net_device *ndev)
3749{
3750 struct ql3_adapter *qdev = netdev_priv(ndev);
3751 return (ql_adapter_up(qdev));
3752}
3753
3754static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3755{
3756 struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3757 return &qdev->stats;
3758}
3759
5a4faa87
RM		 3760static void ql3xxx_set_multicast_list(struct net_device *ndev)
3761{
3762 /*
3763 * We are manually parsing the list in the net_device structure.
3764 */
3765 return;
3766}
3767
3768static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3769{
3770 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3771 struct ql3xxx_port_registers __iomem *port_regs =
3772 qdev->mem_map_registers;
3773 struct sockaddr *addr = p;
3774 unsigned long hw_flags;
3775
3776 if (netif_running(ndev))
3777 return -EBUSY;
3778
3779 if (!is_valid_ether_addr(addr->sa_data))
3780 return -EADDRNOTAVAIL;
3781
3782 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3783
3784 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3785 /* Program lower 32 bits of the MAC address */
3786 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3787 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3788 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3789 ((ndev->dev_addr[2] << 24) | (ndev->
3790 dev_addr[3] << 16) |
3791 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3792
3793 /* Program top 16 bits of the MAC address */
3794 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3795 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3796 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3797 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3798 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3799
3800 return 0;
3801}
3802
3803static void ql3xxx_tx_timeout(struct net_device *ndev)
3804{
3805 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3806
3807 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3808 /*
3809 * Stop the queues, we've got a problem.
3810 */
3811 netif_stop_queue(ndev);
3812
3813 /*
3814 * Wake up the worker to process this event.
3815 */
c4028958 3816 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
5a4faa87
RM		 3817}
3818
c4028958 3819static void ql_reset_work(struct work_struct *work)
5a4faa87 3820{
c4028958
DH		 3821 struct ql3_adapter *qdev =
3822 container_of(work, struct ql3_adapter, reset_work.work);
5a4faa87
RM		 3823 struct net_device *ndev = qdev->ndev;
3824 u32 value;
3825 struct ql_tx_buf_cb *tx_cb;
3826 int max_wait_time, i;
3827 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3828 unsigned long hw_flags;
3829
3830 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3831 clear_bit(QL_LINK_MASTER,&qdev->flags);
3832
3833 /*
3834 * Loop through the active list and return the skb.
3835 */
3836 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 3837 int j;
5a4faa87
RM		 3838 tx_cb = &qdev->tx_buf[i];
3839 if (tx_cb->skb) {
5a4faa87
RM		 3840 printk(KERN_DEBUG PFX
3841 "%s: Freeing lost SKB.\n",
3842 qdev->ndev->name);
3843 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 3844 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3845 pci_unmap_len(&tx_cb->map[0], maplen),
3846 PCI_DMA_TODEVICE);
3847 for(j=1;j<tx_cb->seg_count;j++) {
3848 pci_unmap_page(qdev->pdev,
3849 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3850 pci_unmap_len(&tx_cb->map[j],maplen),
3851 PCI_DMA_TODEVICE);
3852 }
5a4faa87
RM		 3853 dev_kfree_skb(tx_cb->skb);
3854 tx_cb->skb = NULL;
3855 }
3856 }
3857
3858 printk(KERN_ERR PFX
3859 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3860 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3861 ql_write_common_reg(qdev,
3862 &port_regs->CommonRegs.
3863 ispControlStatus,
3864 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3865 /*
3866 * Wait the for Soft Reset to Complete.
3867 */
3868 max_wait_time = 10;
3869 do {
3870 value = ql_read_common_reg(qdev,
3871 &port_regs->CommonRegs.
3872
3873 ispControlStatus);
3874 if ((value & ISP_CONTROL_SR) == 0) {
3875 printk(KERN_DEBUG PFX
3876 "%s: reset completed.\n",
3877 qdev->ndev->name);
3878 break;
3879 }
3880
3881 if (value & ISP_CONTROL_RI) {
3882 printk(KERN_DEBUG PFX
3883 "%s: clearing NRI after reset.\n",
3884 qdev->ndev->name);
3885 ql_write_common_reg(qdev,
ee111d11 3886 &port_regs->
5a4faa87
RM		 3887 CommonRegs.
3888 ispControlStatus,
3889 ((ISP_CONTROL_RI <<
3890 16) | ISP_CONTROL_RI));
3891 }
3892
3893 ssleep(1);
3894 } while (--max_wait_time);
3895 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3896
3897 if (value & ISP_CONTROL_SR) {
3898
3899 /*
3900 * Set the reset flags and clear the board again.
3901 * Nothing else to do...
3902 */
3903 printk(KERN_ERR PFX
3904 "%s: Timed out waiting for reset to "
3905 "complete.\n", ndev->name);
3906 printk(KERN_ERR PFX
3907 "%s: Do a reset.\n", ndev->name);
3908 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3909 clear_bit(QL_RESET_START,&qdev->flags);
3910 ql_cycle_adapter(qdev,QL_DO_RESET);
3911 return;
3912 }
3913
3914 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3915 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3916 clear_bit(QL_RESET_START,&qdev->flags);
3917 ql_cycle_adapter(qdev,QL_NO_RESET);
3918 }
3919}
3920
c4028958 3921static void ql_tx_timeout_work(struct work_struct *work)
5a4faa87 3922{
c4028958
DH		 3923 struct ql3_adapter *qdev =
3924 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3925
3926 ql_cycle_adapter(qdev, QL_DO_RESET);
5a4faa87
RM		 3927}
3928
3929static void ql_get_board_info(struct ql3_adapter *qdev)
3930{
3931 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3932 u32 value;
3933
3934 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3935
3936 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3937 if (value & PORT_STATUS_64)
3938 qdev->pci_width = 64;
3939 else
3940 qdev->pci_width = 32;
3941 if (value & PORT_STATUS_X)
3942 qdev->pci_x = 1;
3943 else
3944 qdev->pci_x = 0;
3945 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3946}
3947
3948static void ql3xxx_timer(unsigned long ptr)
3949{
3950 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3951
3952 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3953 printk(KERN_DEBUG PFX
3954 "%s: Reset in progress.\n",
3955 qdev->ndev->name);
3956 goto end;
3957 }
3958
3959 ql_link_state_machine(qdev);
3960
3961 /* Restart timer on 2 second interval. */
3962end:
3963 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3964}
3965
3966static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3967 const struct pci_device_id *pci_entry)
3968{
3969 struct net_device *ndev = NULL;
3970 struct ql3_adapter *qdev = NULL;
3971 static int cards_found = 0;
3972 int pci_using_dac, err;
3973
3974 err = pci_enable_device(pdev);
3975 if (err) {
3976 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3977 pci_name(pdev));
3978 goto err_out;
3979 }
3980
3981 err = pci_request_regions(pdev, DRV_NAME);
3982 if (err) {
3983 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3984 pci_name(pdev));
3985 goto err_out_disable_pdev;
3986 }
3987
3988 pci_set_master(pdev);
3989
3990 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3991 pci_using_dac = 1;
3992 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3993 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3994 pci_using_dac = 0;
3995 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3996 }
3997
3998 if (err) {
3999 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
4000 pci_name(pdev));
4001 goto err_out_free_regions;
4002 }
4003
4004 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
546faf07
BL		 4005 if (!ndev) {
4006 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
4007 pci_name(pdev));
4008 err = -ENOMEM;
5a4faa87 4009 goto err_out_free_regions;
546faf07 4010 }
5a4faa87
RM		 4011
4012 SET_MODULE_OWNER(ndev);
4013 SET_NETDEV_DEV(ndev, &pdev->dev);
4014
5a4faa87
RM		 4015 pci_set_drvdata(pdev, ndev);
4016
4017 qdev = netdev_priv(ndev);
4018 qdev->index = cards_found;
4019 qdev->ndev = ndev;
4020 qdev->pdev = pdev;
bd36b0ac 4021 qdev->device_id = pci_entry->device;
5a4faa87
RM		 4022 qdev->port_link_state = LS_DOWN;
4023 if (msi)
4024 qdev->msi = 1;
4025
4026 qdev->msg_enable = netif_msg_init(debug, default_msg);
4027
bd36b0ac
RM		 4028 if (pci_using_dac)
4029 ndev->features |= NETIF_F_HIGHDMA;
4030 if (qdev->device_id == QL3032_DEVICE_ID)
e68a8c10 4031 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
bd36b0ac 4032
5a4faa87
RM		 4033 qdev->mem_map_registers =
4034 ioremap_nocache(pci_resource_start(pdev, 1),
4035 pci_resource_len(qdev->pdev, 1));
4036 if (!qdev->mem_map_registers) {
4037 printk(KERN_ERR PFX "%s: cannot map device registers\n",
4038 pci_name(pdev));
546faf07 4039 err = -EIO;
5a4faa87
RM		 4040 goto err_out_free_ndev;
4041 }
4042
4043 spin_lock_init(&qdev->adapter_lock);
4044 spin_lock_init(&qdev->hw_lock);
4045
4046 /* Set driver entry points */
4047 ndev->open = ql3xxx_open;
4048 ndev->hard_start_xmit = ql3xxx_send;
4049 ndev->stop = ql3xxx_close;
4050 ndev->get_stats = ql3xxx_get_stats;
5a4faa87
RM		 4051 ndev->set_multicast_list = ql3xxx_set_multicast_list;
4052 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
4053 ndev->set_mac_address = ql3xxx_set_mac_address;
4054 ndev->tx_timeout = ql3xxx_tx_timeout;
4055 ndev->watchdog_timeo = 5 * HZ;
4056
4057 ndev->poll = &ql_poll;
4058 ndev->weight = 64;
4059
4060 ndev->irq = pdev->irq;
4061
4062 /* make sure the EEPROM is good */
4063 if (ql_get_nvram_params(qdev)) {
4064 printk(KERN_ALERT PFX
4065 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4066 qdev->index);
546faf07 4067 err = -EIO;
5a4faa87
RM		 4068 goto err_out_iounmap;
4069 }
4070
4071 ql_set_mac_info(qdev);
4072
4073 /* Validate and set parameters */
4074 if (qdev->mac_index) {
cb8bac12 4075 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
5a4faa87
RM		 4076 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
4077 ETH_ALEN);
4078 } else {
cb8bac12 4079 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
5a4faa87
RM		 4080 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
4081 ETH_ALEN);
4082 }
4083 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4084
4085 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4086
4087 /* Turn off support for multicasting */
4088 ndev->flags &= ~IFF_MULTICAST;
4089
4090 /* Record PCI bus information. */
4091 ql_get_board_info(qdev);
4092
4093 /*
4094 * Set the Maximum Memory Read Byte Count value. We do this to handle
4095 * jumbo frames.
4096 */
4097 if (qdev->pci_x) {
4098 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4099 }
4100
4101 err = register_netdev(ndev);
4102 if (err) {
4103 printk(KERN_ERR PFX "%s: cannot register net device\n",
4104 pci_name(pdev));
4105 goto err_out_iounmap;
4106 }
4107
4108 /* we're going to reset, so assume we have no link for now */
4109
4110 netif_carrier_off(ndev);
4111 netif_stop_queue(ndev);
4112
4113 qdev->workqueue = create_singlethread_workqueue(ndev->name);
c4028958
DH		 4114 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4115 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
5a4faa87
RM		 4116
4117 init_timer(&qdev->adapter_timer);
4118 qdev->adapter_timer.function = ql3xxx_timer;
4119 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4120 qdev->adapter_timer.data = (unsigned long)qdev;
4121
4122 if(!cards_found) {
4123 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4124 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4125 DRV_NAME, DRV_VERSION);
4126 }
4127 ql_display_dev_info(ndev);
4128
4129 cards_found++;
4130 return 0;
4131
4132err_out_iounmap:
4133 iounmap(qdev->mem_map_registers);
4134err_out_free_ndev:
4135 free_netdev(ndev);
4136err_out_free_regions:
4137 pci_release_regions(pdev);
4138err_out_disable_pdev:
4139 pci_disable_device(pdev);
4140 pci_set_drvdata(pdev, NULL);
4141err_out:
4142 return err;
4143}
4144
4145static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4146{
4147 struct net_device *ndev = pci_get_drvdata(pdev);
4148 struct ql3_adapter *qdev = netdev_priv(ndev);
4149
4150 unregister_netdev(ndev);
4151 qdev = netdev_priv(ndev);
4152
4153 ql_disable_interrupts(qdev);
4154
4155 if (qdev->workqueue) {
4156 cancel_delayed_work(&qdev->reset_work);
4157 cancel_delayed_work(&qdev->tx_timeout_work);
4158 destroy_workqueue(qdev->workqueue);
4159 qdev->workqueue = NULL;
4160 }
4161
855fc73b 4162 iounmap(qdev->mem_map_registers);
5a4faa87
RM		 4163 pci_release_regions(pdev);
4164 pci_set_drvdata(pdev, NULL);
4165 free_netdev(ndev);
4166}
4167
4168static struct pci_driver ql3xxx_driver = {
4169
4170 .name = DRV_NAME,
4171 .id_table = ql3xxx_pci_tbl,
4172 .probe = ql3xxx_probe,
4173 .remove = __devexit_p(ql3xxx_remove),
4174};
4175
4176static int __init ql3xxx_init_module(void)
4177{
4178 return pci_register_driver(&ql3xxx_driver);
4179}
4180
4181static void __exit ql3xxx_exit(void)
4182{
4183 pci_unregister_driver(&ql3xxx_driver);
4184}
4185
4186module_init(ql3xxx_init_module);
4187module_exit(ql3xxx_exit);
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