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perf/x86: Fix shared register mutual exclusion enforcement
[linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7 15
3a632cb2 16#include <asm/cpufeature.h>
de0428a7
KW		 17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
a7e3ed1e 21
f22f54f4 22/*
b622d644 23 * Intel PerfMon, used on Core and later.
f22f54f4 24 */
ec75a716 25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 26{
c3b7cdf1
PE		 27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 35};
36
5c543e3c 37static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46};
47
5c543e3c 48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 49{
b622d644
PZ		 50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64};
65
5c543e3c 66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 67{
b622d644
PZ		 68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80};
81
5c543e3c 82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 83{
efc9f05d 84 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 85 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 86 EVENT_EXTRA_END
87};
88
5c543e3c 89static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 90{
b622d644
PZ		 91 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
92 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 93 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 94 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
95 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
96 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 97 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 98 EVENT_CONSTRAINT_END
99};
100
5c543e3c 101static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 102{
103 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
104 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 105 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 106 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
107 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
108 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 110 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 111 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
112 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
b06b3d49
LM		 115 EVENT_CONSTRAINT_END
116};
117
69943182
SE		 118static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
119{
120 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
121 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
122 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
123 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
124 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
125 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
126 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
127 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
128 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
129 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
741a698f
PZ		 132 /*
133 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
134 * siblings; disable these events because they can corrupt unrelated
135 * counters.
136 */
137 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
138 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
139 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
69943182
SE		 141 EVENT_CONSTRAINT_END
142};
143
5c543e3c 144static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 145{
efc9f05d
SE		 146 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
147 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 148 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 149 EVENT_EXTRA_END
150};
151
0af3ac1f
AK		 152static struct event_constraint intel_v1_event_constraints[] __read_mostly =
153{
154 EVENT_CONSTRAINT_END
155};
156
5c543e3c 157static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 158{
b622d644
PZ		 159 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
160 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 161 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 162 EVENT_CONSTRAINT_END
163};
164
ee89cbc2 165static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
f1923820
SE		 166 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
167 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 169 EVENT_EXTRA_END
170};
171
172static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
173 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
174 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 175 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 176 EVENT_EXTRA_END
177};
178
f20093ee
SE		 179EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
180EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
9ad64c0f 181EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 182
183struct attribute *nhm_events_attrs[] = {
184 EVENT_PTR(mem_ld_nhm),
185 NULL,
186};
187
188struct attribute *snb_events_attrs[] = {
189 EVENT_PTR(mem_ld_snb),
9ad64c0f 190 EVENT_PTR(mem_st_snb),
f20093ee
SE		 191 NULL,
192};
193
3a632cb2
AK		 194static struct event_constraint intel_hsw_event_constraints[] = {
195 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
196 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
197 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
198 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
199 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
200 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
201 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
202 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
203 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
204 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
205 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
206 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
207 EVENT_CONSTRAINT_END
208};
209
f22f54f4
PZ		 210static u64 intel_pmu_event_map(int hw_event)
211{
212 return intel_perfmon_event_map[hw_event];
213}
214
74e6543f
YZ		 215#define SNB_DMND_DATA_RD (1ULL << 0)
216#define SNB_DMND_RFO (1ULL << 1)
217#define SNB_DMND_IFETCH (1ULL << 2)
218#define SNB_DMND_WB (1ULL << 3)
219#define SNB_PF_DATA_RD (1ULL << 4)
220#define SNB_PF_RFO (1ULL << 5)
221#define SNB_PF_IFETCH (1ULL << 6)
222#define SNB_LLC_DATA_RD (1ULL << 7)
223#define SNB_LLC_RFO (1ULL << 8)
224#define SNB_LLC_IFETCH (1ULL << 9)
225#define SNB_BUS_LOCKS (1ULL << 10)
226#define SNB_STRM_ST (1ULL << 11)
227#define SNB_OTHER (1ULL << 15)
228#define SNB_RESP_ANY (1ULL << 16)
229#define SNB_NO_SUPP (1ULL << 17)
230#define SNB_LLC_HITM (1ULL << 18)
231#define SNB_LLC_HITE (1ULL << 19)
232#define SNB_LLC_HITS (1ULL << 20)
233#define SNB_LLC_HITF (1ULL << 21)
234#define SNB_LOCAL (1ULL << 22)
235#define SNB_REMOTE (0xffULL << 23)
236#define SNB_SNP_NONE (1ULL << 31)
237#define SNB_SNP_NOT_NEEDED (1ULL << 32)
238#define SNB_SNP_MISS (1ULL << 33)
239#define SNB_NO_FWD (1ULL << 34)
240#define SNB_SNP_FWD (1ULL << 35)
241#define SNB_HITM (1ULL << 36)
242#define SNB_NON_DRAM (1ULL << 37)
243
244#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
245#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
246#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
247
248#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
249 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
250 SNB_HITM)
251
252#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
253#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
254
255#define SNB_L3_ACCESS SNB_RESP_ANY
256#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
257
258static __initconst const u64 snb_hw_cache_extra_regs
259 [PERF_COUNT_HW_CACHE_MAX]
260 [PERF_COUNT_HW_CACHE_OP_MAX]
261 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
262{
263 [ C(LL ) ] = {
264 [ C(OP_READ) ] = {
265 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
266 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
267 },
268 [ C(OP_WRITE) ] = {
269 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
270 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
271 },
272 [ C(OP_PREFETCH) ] = {
273 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
274 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
275 },
276 },
277 [ C(NODE) ] = {
278 [ C(OP_READ) ] = {
279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
281 },
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
285 },
286 [ C(OP_PREFETCH) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
289 },
290 },
291};
292
b06b3d49
LM		 293static __initconst const u64 snb_hw_cache_event_ids
294 [PERF_COUNT_HW_CACHE_MAX]
295 [PERF_COUNT_HW_CACHE_OP_MAX]
296 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
297{
298 [ C(L1D) ] = {
299 [ C(OP_READ) ] = {
300 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
301 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
302 },
303 [ C(OP_WRITE) ] = {
304 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
305 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
306 },
307 [ C(OP_PREFETCH) ] = {
308 [ C(RESULT_ACCESS) ] = 0x0,
309 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
310 },
311 },
312 [ C(L1I ) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0x0,
315 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = -1,
319 [ C(RESULT_MISS) ] = -1,
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0,
323 [ C(RESULT_MISS) ] = 0x0,
324 },
325 },
326 [ C(LL ) ] = {
b06b3d49 327 [ C(OP_READ) ] = {
63b6a675 328 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 329 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 330 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
331 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 332 },
333 [ C(OP_WRITE) ] = {
63b6a675 334 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 335 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 336 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
337 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 338 },
339 [ C(OP_PREFETCH) ] = {
63b6a675 340 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 341 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 342 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
343 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 344 },
345 },
346 [ C(DTLB) ] = {
347 [ C(OP_READ) ] = {
348 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
349 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
350 },
351 [ C(OP_WRITE) ] = {
352 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
353 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
354 },
355 [ C(OP_PREFETCH) ] = {
356 [ C(RESULT_ACCESS) ] = 0x0,
357 [ C(RESULT_MISS) ] = 0x0,
358 },
359 },
360 [ C(ITLB) ] = {
361 [ C(OP_READ) ] = {
362 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
363 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
364 },
365 [ C(OP_WRITE) ] = {
366 [ C(RESULT_ACCESS) ] = -1,
367 [ C(RESULT_MISS) ] = -1,
368 },
369 [ C(OP_PREFETCH) ] = {
370 [ C(RESULT_ACCESS) ] = -1,
371 [ C(RESULT_MISS) ] = -1,
372 },
373 },
374 [ C(BPU ) ] = {
375 [ C(OP_READ) ] = {
376 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
377 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
378 },
379 [ C(OP_WRITE) ] = {
380 [ C(RESULT_ACCESS) ] = -1,
381 [ C(RESULT_MISS) ] = -1,
382 },
383 [ C(OP_PREFETCH) ] = {
384 [ C(RESULT_ACCESS) ] = -1,
385 [ C(RESULT_MISS) ] = -1,
386 },
387 },
89d6c0b5
PZ		 388 [ C(NODE) ] = {
389 [ C(OP_READ) ] = {
74e6543f
YZ		 390 [ C(RESULT_ACCESS) ] = 0x01b7,
391 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 392 },
393 [ C(OP_WRITE) ] = {
74e6543f
YZ		 394 [ C(RESULT_ACCESS) ] = 0x01b7,
395 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 396 },
397 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 398 [ C(RESULT_ACCESS) ] = 0x01b7,
399 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 400 },
401 },
402
b06b3d49
LM		 403};
404
caaa8be3 405static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 406 [PERF_COUNT_HW_CACHE_MAX]
407 [PERF_COUNT_HW_CACHE_OP_MAX]
408 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
409{
410 [ C(L1D) ] = {
411 [ C(OP_READ) ] = {
412 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
413 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
414 },
415 [ C(OP_WRITE) ] = {
416 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
417 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
418 },
419 [ C(OP_PREFETCH) ] = {
420 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
421 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
422 },
423 },
424 [ C(L1I ) ] = {
425 [ C(OP_READ) ] = {
426 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
427 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
428 },
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = -1,
431 [ C(RESULT_MISS) ] = -1,
432 },
433 [ C(OP_PREFETCH) ] = {
434 [ C(RESULT_ACCESS) ] = 0x0,
435 [ C(RESULT_MISS) ] = 0x0,
436 },
437 },
438 [ C(LL ) ] = {
439 [ C(OP_READ) ] = {
63b6a675 440 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 441 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 442 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
443 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 444 },
e994d7d2
AK		 445 /*
446 * Use RFO, not WRITEBACK, because a write miss would typically occur
447 * on RFO.
448 */
f22f54f4 449 [ C(OP_WRITE) ] = {
63b6a675
PZ		 450 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
451 [ C(RESULT_ACCESS) ] = 0x01b7,
452 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 453 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 454 },
455 [ C(OP_PREFETCH) ] = {
63b6a675 456 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 457 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 458 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
459 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 460 },
461 },
462 [ C(DTLB) ] = {
463 [ C(OP_READ) ] = {
464 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
465 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
466 },
467 [ C(OP_WRITE) ] = {
468 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
469 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
470 },
471 [ C(OP_PREFETCH) ] = {
472 [ C(RESULT_ACCESS) ] = 0x0,
473 [ C(RESULT_MISS) ] = 0x0,
474 },
475 },
476 [ C(ITLB) ] = {
477 [ C(OP_READ) ] = {
478 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
479 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = -1,
483 [ C(RESULT_MISS) ] = -1,
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = -1,
487 [ C(RESULT_MISS) ] = -1,
488 },
489 },
490 [ C(BPU ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
493 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = -1,
501 [ C(RESULT_MISS) ] = -1,
502 },
503 },
89d6c0b5
PZ		 504 [ C(NODE) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x01b7,
507 [ C(RESULT_MISS) ] = 0x01b7,
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = 0x01b7,
511 [ C(RESULT_MISS) ] = 0x01b7,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = 0x01b7,
515 [ C(RESULT_MISS) ] = 0x01b7,
516 },
517 },
f22f54f4
PZ		 518};
519
e994d7d2 520/*
63b6a675
PZ		 521 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
522 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 523 */
524
63b6a675
PZ		 525#define NHM_DMND_DATA_RD (1 << 0)
526#define NHM_DMND_RFO (1 << 1)
527#define NHM_DMND_IFETCH (1 << 2)
528#define NHM_DMND_WB (1 << 3)
529#define NHM_PF_DATA_RD (1 << 4)
530#define NHM_PF_DATA_RFO (1 << 5)
531#define NHM_PF_IFETCH (1 << 6)
532#define NHM_OFFCORE_OTHER (1 << 7)
533#define NHM_UNCORE_HIT (1 << 8)
534#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
535#define NHM_OTHER_CORE_HITM (1 << 10)
536 /* reserved */
537#define NHM_REMOTE_CACHE_FWD (1 << 12)
538#define NHM_REMOTE_DRAM (1 << 13)
539#define NHM_LOCAL_DRAM (1 << 14)
540#define NHM_NON_DRAM (1 << 15)
541
87e24f4b
PZ		 542#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
543#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 544
545#define NHM_DMND_READ (NHM_DMND_DATA_RD)
546#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
547#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
548
549#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 550#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 551#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 552
553static __initconst const u64 nehalem_hw_cache_extra_regs
554 [PERF_COUNT_HW_CACHE_MAX]
555 [PERF_COUNT_HW_CACHE_OP_MAX]
556 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
557{
558 [ C(LL ) ] = {
559 [ C(OP_READ) ] = {
63b6a675
PZ		 560 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
561 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 562 },
563 [ C(OP_WRITE) ] = {
63b6a675
PZ		 564 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
565 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 566 },
567 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 568 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
569 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 570 },
89d6c0b5
PZ		 571 },
572 [ C(NODE) ] = {
573 [ C(OP_READ) ] = {
87e24f4b
PZ		 574 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
575 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 576 },
577 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 578 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
579 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 580 },
581 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 582 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
583 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 584 },
585 },
e994d7d2
AK		 586};
587
caaa8be3 588static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 589 [PERF_COUNT_HW_CACHE_MAX]
590 [PERF_COUNT_HW_CACHE_OP_MAX]
591 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
592{
593 [ C(L1D) ] = {
594 [ C(OP_READ) ] = {
f4929bd3
PZ		 595 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
596 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 597 },
598 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 599 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
600 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 601 },
602 [ C(OP_PREFETCH) ] = {
603 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
604 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
605 },
606 },
607 [ C(L1I ) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
610 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = 0x0,
618 [ C(RESULT_MISS) ] = 0x0,
619 },
620 },
621 [ C(LL ) ] = {
622 [ C(OP_READ) ] = {
e994d7d2
AK		 623 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
624 [ C(RESULT_ACCESS) ] = 0x01b7,
625 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
626 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 627 },
e994d7d2
AK		 628 /*
629 * Use RFO, not WRITEBACK, because a write miss would typically occur
630 * on RFO.
631 */
f22f54f4 632 [ C(OP_WRITE) ] = {
e994d7d2
AK		 633 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
634 [ C(RESULT_ACCESS) ] = 0x01b7,
635 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
636 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 637 },
638 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 639 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
640 [ C(RESULT_ACCESS) ] = 0x01b7,
641 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
642 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 643 },
644 },
645 [ C(DTLB) ] = {
646 [ C(OP_READ) ] = {
647 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
648 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
649 },
650 [ C(OP_WRITE) ] = {
651 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
652 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
653 },
654 [ C(OP_PREFETCH) ] = {
655 [ C(RESULT_ACCESS) ] = 0x0,
656 [ C(RESULT_MISS) ] = 0x0,
657 },
658 },
659 [ C(ITLB) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
662 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
663 },
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = -1,
666 [ C(RESULT_MISS) ] = -1,
667 },
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = -1,
670 [ C(RESULT_MISS) ] = -1,
671 },
672 },
673 [ C(BPU ) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
676 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
677 },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = -1,
680 [ C(RESULT_MISS) ] = -1,
681 },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 },
89d6c0b5
PZ		 687 [ C(NODE) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0x01b7,
690 [ C(RESULT_MISS) ] = 0x01b7,
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = 0x01b7,
694 [ C(RESULT_MISS) ] = 0x01b7,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = 0x01b7,
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 },
f22f54f4
PZ		 701};
702
caaa8be3 703static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 704 [PERF_COUNT_HW_CACHE_MAX]
705 [PERF_COUNT_HW_CACHE_OP_MAX]
706 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
707{
708 [ C(L1D) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
711 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
715 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
719 [ C(RESULT_MISS) ] = 0,
720 },
721 },
722 [ C(L1I ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
725 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0,
733 [ C(RESULT_MISS) ] = 0,
734 },
735 },
736 [ C(LL ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
739 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
743 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0,
747 [ C(RESULT_MISS) ] = 0,
748 },
749 },
750 [ C(DTLB) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
753 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
757 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0,
761 [ C(RESULT_MISS) ] = 0,
762 },
763 },
764 [ C(ITLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
767 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = -1,
771 [ C(RESULT_MISS) ] = -1,
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 },
778 [ C(BPU ) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
781 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792};
793
caaa8be3 794static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 795 [PERF_COUNT_HW_CACHE_MAX]
796 [PERF_COUNT_HW_CACHE_OP_MAX]
797 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
798{
799 [ C(L1D) ] = {
800 [ C(OP_READ) ] = {
801 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
802 [ C(RESULT_MISS) ] = 0,
803 },
804 [ C(OP_WRITE) ] = {
805 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
806 [ C(RESULT_MISS) ] = 0,
807 },
808 [ C(OP_PREFETCH) ] = {
809 [ C(RESULT_ACCESS) ] = 0x0,
810 [ C(RESULT_MISS) ] = 0,
811 },
812 },
813 [ C(L1I ) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
816 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
817 },
818 [ C(OP_WRITE) ] = {
819 [ C(RESULT_ACCESS) ] = -1,
820 [ C(RESULT_MISS) ] = -1,
821 },
822 [ C(OP_PREFETCH) ] = {
823 [ C(RESULT_ACCESS) ] = 0,
824 [ C(RESULT_MISS) ] = 0,
825 },
826 },
827 [ C(LL ) ] = {
828 [ C(OP_READ) ] = {
829 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
830 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
831 },
832 [ C(OP_WRITE) ] = {
833 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
834 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
835 },
836 [ C(OP_PREFETCH) ] = {
837 [ C(RESULT_ACCESS) ] = 0,
838 [ C(RESULT_MISS) ] = 0,
839 },
840 },
841 [ C(DTLB) ] = {
842 [ C(OP_READ) ] = {
843 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
844 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
845 },
846 [ C(OP_WRITE) ] = {
847 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
848 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
849 },
850 [ C(OP_PREFETCH) ] = {
851 [ C(RESULT_ACCESS) ] = 0,
852 [ C(RESULT_MISS) ] = 0,
853 },
854 },
855 [ C(ITLB) ] = {
856 [ C(OP_READ) ] = {
857 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
858 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
859 },
860 [ C(OP_WRITE) ] = {
861 [ C(RESULT_ACCESS) ] = -1,
862 [ C(RESULT_MISS) ] = -1,
863 },
864 [ C(OP_PREFETCH) ] = {
865 [ C(RESULT_ACCESS) ] = -1,
866 [ C(RESULT_MISS) ] = -1,
867 },
868 },
869 [ C(BPU ) ] = {
870 [ C(OP_READ) ] = {
871 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
872 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
873 },
874 [ C(OP_WRITE) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 [ C(OP_PREFETCH) ] = {
879 [ C(RESULT_ACCESS) ] = -1,
880 [ C(RESULT_MISS) ] = -1,
881 },
882 },
883};
884
60ce0fbd
SE		 885static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
886{
887 /* user explicitly requested branch sampling */
888 if (has_branch_stack(event))
889 return true;
890
891 /* implicit branch sampling to correct PEBS skid */
3044318f
AK		 892 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
893 x86_pmu.intel_cap.pebs_format < 2)
60ce0fbd
SE		 894 return true;
895
896 return false;
897}
898
f22f54f4
PZ		 899static void intel_pmu_disable_all(void)
900{
901 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
902
903 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
904
15c7ad51 905 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 906 intel_pmu_disable_bts();
ca037701
PZ		 907
908 intel_pmu_pebs_disable_all();
caff2bef 909 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 910}
911
11164cd4 912static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 913{
914 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
915
d329527e
PZ		 916 intel_pmu_pebs_enable_all();
917 intel_pmu_lbr_enable_all();
144d31e6
GN		 918 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
919 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 920
15c7ad51 921 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 922 struct perf_event *event =
15c7ad51 923 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 924
925 if (WARN_ON_ONCE(!event))
926 return;
927
928 intel_pmu_enable_bts(event->hw.config);
929 }
930}
931
11164cd4
PZ		 932/*
933 * Workaround for:
934 * Intel Errata AAK100 (model 26)
935 * Intel Errata AAP53 (model 30)
40b91cd1 936 * Intel Errata BD53 (model 44)
11164cd4 937 *
351af072
ZY		 938 * The official story:
939 * These chips need to be 'reset' when adding counters by programming the
940 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
941 * in sequence on the same PMC or on different PMCs.
942 *
943 * In practise it appears some of these events do in fact count, and
944 * we need to programm all 4 events.
11164cd4 945 */
351af072 946static void intel_pmu_nhm_workaround(void)
11164cd4 947{
351af072
ZY		 948 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
949 static const unsigned long nhm_magic[4] = {
950 0x4300B5,
951 0x4300D2,
952 0x4300B1,
953 0x4300B1
954 };
955 struct perf_event *event;
956 int i;
11164cd4 957
351af072
ZY		 958 /*
959 * The Errata requires below steps:
960 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
961 * 2) Configure 4 PERFEVTSELx with the magic events and clear
962 * the corresponding PMCx;
963 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
964 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
965 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
966 */
11164cd4 967
351af072
ZY		 968 /*
969 * The real steps we choose are a little different from above.
970 * A) To reduce MSR operations, we don't run step 1) as they
971 * are already cleared before this function is called;
972 * B) Call x86_perf_event_update to save PMCx before configuring
973 * PERFEVTSELx with magic number;
974 * C) With step 5), we do clear only when the PERFEVTSELx is
975 * not used currently.
976 * D) Call x86_perf_event_set_period to restore PMCx;
977 */
11164cd4 978
351af072
ZY		 979 /* We always operate 4 pairs of PERF Counters */
980 for (i = 0; i < 4; i++) {
981 event = cpuc->events[i];
982 if (event)
983 x86_perf_event_update(event);
984 }
11164cd4 985
351af072
ZY		 986 for (i = 0; i < 4; i++) {
987 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
988 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
989 }
990
991 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
992 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 993
351af072
ZY		 994 for (i = 0; i < 4; i++) {
995 event = cpuc->events[i];
996
997 if (event) {
998 x86_perf_event_set_period(event);
31fa58af 999 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1000 ARCH_PERFMON_EVENTSEL_ENABLE);
1001 } else
1002 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1003 }
351af072
ZY		 1004}
1005
1006static void intel_pmu_nhm_enable_all(int added)
1007{
1008 if (added)
1009 intel_pmu_nhm_workaround();
11164cd4
PZ		 1010 intel_pmu_enable_all(added);
1011}
1012
f22f54f4
PZ		 1013static inline u64 intel_pmu_get_status(void)
1014{
1015 u64 status;
1016
1017 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1018
1019 return status;
1020}
1021
1022static inline void intel_pmu_ack_status(u64 ack)
1023{
1024 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1025}
1026
ca037701 1027static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1028{
15c7ad51 1029 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1030 u64 ctrl_val, mask;
1031
1032 mask = 0xfULL << (idx * 4);
1033
1034 rdmsrl(hwc->config_base, ctrl_val);
1035 ctrl_val &= ~mask;
7645a24c 1036 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1037}
1038
ca037701 1039static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1040{
aff3d91a 1041 struct hw_perf_event *hwc = &event->hw;
144d31e6 1042 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1043
15c7ad51 1044 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1045 intel_pmu_disable_bts();
1046 intel_pmu_drain_bts_buffer();
1047 return;
1048 }
1049
144d31e6
GN		 1050 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1051 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1052
60ce0fbd
SE		 1053 /*
1054 * must disable before any actual event
1055 * because any event may be combined with LBR
1056 */
1057 if (intel_pmu_needs_lbr_smpl(event))
1058 intel_pmu_lbr_disable(event);
1059
f22f54f4 1060 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1061 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1062 return;
1063 }
1064
aff3d91a 1065 x86_pmu_disable_event(event);
ca037701 1066
ab608344 1067 if (unlikely(event->attr.precise_ip))
ef21f683 1068 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1069}
1070
ca037701 1071static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1072{
15c7ad51 1073 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1074 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1075
1076 /*
1077 * Enable IRQ generation (0x8),
1078 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1079 * if requested:
1080 */
1081 bits = 0x8ULL;
1082 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1083 bits |= 0x2;
1084 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1085 bits |= 0x1;
1086
1087 /*
1088 * ANY bit is supported in v3 and up
1089 */
1090 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1091 bits |= 0x4;
1092
1093 bits <<= (idx * 4);
1094 mask = 0xfULL << (idx * 4);
1095
1096 rdmsrl(hwc->config_base, ctrl_val);
1097 ctrl_val &= ~mask;
1098 ctrl_val |= bits;
7645a24c 1099 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1100}
1101
aff3d91a 1102static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1103{
aff3d91a 1104 struct hw_perf_event *hwc = &event->hw;
144d31e6 1105 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1106
15c7ad51 1107 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1108 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1109 return;
1110
1111 intel_pmu_enable_bts(hwc->config);
1112 return;
1113 }
60ce0fbd
SE		 1114 /*
1115 * must enabled before any actual event
1116 * because any event may be combined with LBR
1117 */
1118 if (intel_pmu_needs_lbr_smpl(event))
1119 intel_pmu_lbr_enable(event);
f22f54f4 1120
144d31e6
GN		 1121 if (event->attr.exclude_host)
1122 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1123 if (event->attr.exclude_guest)
1124 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1125
f22f54f4 1126 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1127 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1128 return;
1129 }
1130
ab608344 1131 if (unlikely(event->attr.precise_ip))
ef21f683 1132 intel_pmu_pebs_enable(event);
ca037701 1133
31fa58af 1134 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1135}
1136
1137/*
1138 * Save and restart an expired event. Called by NMI contexts,
1139 * so it has to be careful about preempting normal event ops:
1140 */
de0428a7 1141int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1142{
cc2ad4ba
PZ		 1143 x86_perf_event_update(event);
1144 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1145}
1146
1147static void intel_pmu_reset(void)
1148{
0a3aee0d 1149 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1150 unsigned long flags;
1151 int idx;
1152
948b1bb8 1153 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1154 return;
1155
1156 local_irq_save(flags);
1157
c767a54b 1158 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1159
948b1bb8 1160 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1161 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1162 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1163 }
948b1bb8 1164 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1165 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1166
f22f54f4
PZ		 1167 if (ds)
1168 ds->bts_index = ds->bts_buffer_base;
1169
1170 local_irq_restore(flags);
1171}
1172
1173/*
1174 * This handler is triggered by the local APIC, so the APIC IRQ handling
1175 * rules apply:
1176 */
1177static int intel_pmu_handle_irq(struct pt_regs *regs)
1178{
1179 struct perf_sample_data data;
1180 struct cpu_hw_events *cpuc;
1181 int bit, loops;
2e556b5b 1182 u64 status;
b0b2072d 1183 int handled;
f22f54f4 1184
f22f54f4
PZ		 1185 cpuc = &__get_cpu_var(cpu_hw_events);
1186
2bce5dac 1187 /*
72db5596
AK		 1188 * No known reason to not always do late ACK,
1189 * but just in case do it opt-in.
2bce5dac 1190 */
72db5596
AK		 1191 if (!x86_pmu.late_ack)
1192 apic_write(APIC_LVTPC, APIC_DM_NMI);
3fb2b8dd 1193 intel_pmu_disable_all();
b0b2072d 1194 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1195 status = intel_pmu_get_status();
1196 if (!status) {
11164cd4 1197 intel_pmu_enable_all(0);
b0b2072d 1198 return handled;
f22f54f4
PZ		 1199 }
1200
1201 loops = 0;
1202again:
2e556b5b 1203 intel_pmu_ack_status(status);
f22f54f4 1204 if (++loops > 100) {
ae0def05
DH		 1205 static bool warned = false;
1206 if (!warned) {
1207 WARN(1, "perfevents: irq loop stuck!\n");
1208 perf_event_print_debug();
1209 warned = true;
1210 }
f22f54f4 1211 intel_pmu_reset();
3fb2b8dd 1212 goto done;
f22f54f4
PZ		 1213 }
1214
1215 inc_irq_stat(apic_perf_irqs);
ca037701 1216
caff2bef
PZ		 1217 intel_pmu_lbr_read();
1218
ca037701
PZ		 1219 /*
1220 * PEBS overflow sets bit 62 in the global status register
1221 */
de725dec
PZ		 1222 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1223 handled++;
ca037701 1224 x86_pmu.drain_pebs(regs);
de725dec 1225 }
ca037701 1226
984b3f57 1227 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1228 struct perf_event *event = cpuc->events[bit];
1229
de725dec
PZ		 1230 handled++;
1231
f22f54f4
PZ		 1232 if (!test_bit(bit, cpuc->active_mask))
1233 continue;
1234
1235 if (!intel_pmu_save_and_restart(event))
1236 continue;
1237
fd0d000b 1238 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1239
60ce0fbd
SE		 1240 if (has_branch_stack(event))
1241 data.br_stack = &cpuc->lbr_stack;
1242
a8b0ca17 1243 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1244 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1245 }
1246
f22f54f4
PZ		 1247 /*
1248 * Repeat if there is more work to be done:
1249 */
1250 status = intel_pmu_get_status();
1251 if (status)
1252 goto again;
1253
3fb2b8dd 1254done:
11164cd4 1255 intel_pmu_enable_all(0);
72db5596
AK		 1256 /*
1257 * Only unmask the NMI after the overflow counters
1258 * have been reset. This avoids spurious NMIs on
1259 * Haswell CPUs.
1260 */
1261 if (x86_pmu.late_ack)
1262 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1263 return handled;
f22f54f4
PZ		 1264}
1265
f22f54f4 1266static struct event_constraint *
ca037701 1267intel_bts_constraints(struct perf_event *event)
f22f54f4 1268{
ca037701
PZ		 1269 struct hw_perf_event *hwc = &event->hw;
1270 unsigned int hw_event, bts_event;
f22f54f4 1271
18a073a3
PZ		 1272 if (event->attr.freq)
1273 return NULL;
1274
ca037701
PZ		 1275 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1276 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1277
ca037701 1278 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1279 return &bts_constraint;
ca037701 1280
f22f54f4
PZ		 1281 return NULL;
1282}
1283
5a425294 1284static int intel_alt_er(int idx)
b79e8941
PZ		 1285{
1286 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1287 return idx;
b79e8941 1288
5a425294
PZ		 1289 if (idx == EXTRA_REG_RSP_0)
1290 return EXTRA_REG_RSP_1;
1291
1292 if (idx == EXTRA_REG_RSP_1)
1293 return EXTRA_REG_RSP_0;
1294
1295 return idx;
1296}
1297
1298static void intel_fixup_er(struct perf_event *event, int idx)
1299{
1300 event->hw.extra_reg.idx = idx;
1301
1302 if (idx == EXTRA_REG_RSP_0) {
b79e8941
PZ		 1303 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1304 event->hw.config |= 0x01b7;
b79e8941 1305 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1306 } else if (idx == EXTRA_REG_RSP_1) {
1307 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1308 event->hw.config |= 0x01bb;
1309 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1310 }
b79e8941
PZ		 1311}
1312
efc9f05d
SE		 1313/*
1314 * manage allocation of shared extra msr for certain events
1315 *
1316 * sharing can be:
1317 * per-cpu: to be shared between the various events on a single PMU
1318 * per-core: per-cpu + shared by HT threads
1319 */
a7e3ed1e 1320static struct event_constraint *
efc9f05d 1321__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1322 struct perf_event *event,
1323 struct hw_perf_event_extra *reg)
a7e3ed1e 1324{
efc9f05d 1325 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1326 struct er_account *era;
cd8a38d3 1327 unsigned long flags;
5a425294 1328 int idx = reg->idx;
a7e3ed1e 1329
5a425294
PZ		 1330 /*
1331 * reg->alloc can be set due to existing state, so for fake cpuc we
1332 * need to ignore this, otherwise we might fail to allocate proper fake
1333 * state for this extra reg constraint. Also see the comment below.
1334 */
1335 if (reg->alloc && !cpuc->is_fake)
b36817e8 1336 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1337
b79e8941 1338again:
5a425294 1339 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1340 /*
1341 * we use spin_lock_irqsave() to avoid lockdep issues when
1342 * passing a fake cpuc
1343 */
1344 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1345
1346 if (!atomic_read(&era->ref) || era->config == reg->config) {
1347
5a425294
PZ		 1348 /*
1349 * If its a fake cpuc -- as per validate_{group,event}() we
1350 * shouldn't touch event state and we can avoid doing so
1351 * since both will only call get_event_constraints() once
1352 * on each event, this avoids the need for reg->alloc.
1353 *
1354 * Not doing the ER fixup will only result in era->reg being
1355 * wrong, but since we won't actually try and program hardware
1356 * this isn't a problem either.
1357 */
1358 if (!cpuc->is_fake) {
1359 if (idx != reg->idx)
1360 intel_fixup_er(event, idx);
1361
1362 /*
1363 * x86_schedule_events() can call get_event_constraints()
1364 * multiple times on events in the case of incremental
1365 * scheduling(). reg->alloc ensures we only do the ER
1366 * allocation once.
1367 */
1368 reg->alloc = 1;
1369 }
1370
efc9f05d
SE		 1371 /* lock in msr value */
1372 era->config = reg->config;
1373 era->reg = reg->reg;
1374
1375 /* one more user */
1376 atomic_inc(&era->ref);
1377
a7e3ed1e 1378 /*
b36817e8
SE		 1379 * need to call x86_get_event_constraint()
1380 * to check if associated event has constraints
a7e3ed1e 1381 */
b36817e8 1382 c = NULL;
5a425294
PZ		 1383 } else {
1384 idx = intel_alt_er(idx);
1385 if (idx != reg->idx) {
1386 raw_spin_unlock_irqrestore(&era->lock, flags);
1387 goto again;
1388 }
a7e3ed1e 1389 }
cd8a38d3 1390 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1391
efc9f05d
SE		 1392 return c;
1393}
1394
1395static void
1396__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1397 struct hw_perf_event_extra *reg)
1398{
1399 struct er_account *era;
1400
1401 /*
5a425294
PZ		 1402 * Only put constraint if extra reg was actually allocated. Also takes
1403 * care of event which do not use an extra shared reg.
1404 *
1405 * Also, if this is a fake cpuc we shouldn't touch any event state
1406 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1407 * either since it'll be thrown out.
efc9f05d 1408 */
5a425294 1409 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1410 return;
1411
1412 era = &cpuc->shared_regs->regs[reg->idx];
1413
1414 /* one fewer user */
1415 atomic_dec(&era->ref);
1416
1417 /* allocate again next time */
1418 reg->alloc = 0;
1419}
1420
1421static struct event_constraint *
1422intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1423 struct perf_event *event)
1424{
b36817e8
SE		 1425 struct event_constraint *c = NULL, *d;
1426 struct hw_perf_event_extra *xreg, *breg;
1427
1428 xreg = &event->hw.extra_reg;
1429 if (xreg->idx != EXTRA_REG_NONE) {
1430 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1431 if (c == &emptyconstraint)
1432 return c;
1433 }
1434 breg = &event->hw.branch_reg;
1435 if (breg->idx != EXTRA_REG_NONE) {
1436 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1437 if (d == &emptyconstraint) {
1438 __intel_shared_reg_put_constraints(cpuc, xreg);
1439 c = d;
1440 }
1441 }
efc9f05d 1442 return c;
a7e3ed1e
AK		 1443}
1444
de0428a7
KW		 1445struct event_constraint *
1446x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1447{
1448 struct event_constraint *c;
1449
1450 if (x86_pmu.event_constraints) {
1451 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 1452 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 1453 event->hw.flags |= c->flags;
de0428a7 1454 return c;
9fac2cf3 1455 }
de0428a7
KW		 1456 }
1457 }
1458
1459 return &unconstrained;
1460}
1461
f22f54f4
PZ		 1462static struct event_constraint *
1463intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1464{
1465 struct event_constraint *c;
1466
ca037701
PZ		 1467 c = intel_bts_constraints(event);
1468 if (c)
1469 return c;
1470
1471 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1472 if (c)
1473 return c;
1474
efc9f05d 1475 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1476 if (c)
1477 return c;
1478
f22f54f4
PZ		 1479 return x86_get_event_constraints(cpuc, event);
1480}
1481
efc9f05d
SE		 1482static void
1483intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1484 struct perf_event *event)
1485{
efc9f05d 1486 struct hw_perf_event_extra *reg;
a7e3ed1e 1487
efc9f05d
SE		 1488 reg = &event->hw.extra_reg;
1489 if (reg->idx != EXTRA_REG_NONE)
1490 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1491
1492 reg = &event->hw.branch_reg;
1493 if (reg->idx != EXTRA_REG_NONE)
1494 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1495}
a7e3ed1e 1496
efc9f05d
SE		 1497static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1498 struct perf_event *event)
1499{
1500 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1501}
1502
0780c927 1503static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1504{
0780c927 1505 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1506 /*
1507 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1508 * (0x003c) so that we can use it with PEBS.
1509 *
1510 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1511 * PEBS capable. However we can use INST_RETIRED.ANY_P
1512 * (0x00c0), which is a PEBS capable event, to get the same
1513 * count.
1514 *
1515 * INST_RETIRED.ANY_P counts the number of cycles that retires
1516 * CNTMASK instructions. By setting CNTMASK to a value (16)
1517 * larger than the maximum number of instructions that can be
1518 * retired per cycle (4) and then inverting the condition, we
1519 * count all cycles that retire 16 or less instructions, which
1520 * is every cycle.
1521 *
1522 * Thereby we gain a PEBS capable cycle counter.
1523 */
f9b4eeb8
PZ		 1524 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1525
0780c927
PZ		 1526 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1527 event->hw.config = alt_config;
1528 }
1529}
1530
1531static void intel_pebs_aliases_snb(struct perf_event *event)
1532{
1533 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1534 /*
1535 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1536 * (0x003c) so that we can use it with PEBS.
1537 *
1538 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1539 * PEBS capable. However we can use UOPS_RETIRED.ALL
1540 * (0x01c2), which is a PEBS capable event, to get the same
1541 * count.
1542 *
1543 * UOPS_RETIRED.ALL counts the number of cycles that retires
1544 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1545 * larger than the maximum number of micro-ops that can be
1546 * retired per cycle (4) and then inverting the condition, we
1547 * count all cycles that retire 16 or less micro-ops, which
1548 * is every cycle.
1549 *
1550 * Thereby we gain a PEBS capable cycle counter.
1551 */
1552 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1553
1554 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1555 event->hw.config = alt_config;
1556 }
0780c927
PZ		 1557}
1558
1559static int intel_pmu_hw_config(struct perf_event *event)
1560{
1561 int ret = x86_pmu_hw_config(event);
1562
1563 if (ret)
1564 return ret;
1565
1566 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1567 x86_pmu.pebs_aliases(event);
7639dae0 1568
60ce0fbd
SE		 1569 if (intel_pmu_needs_lbr_smpl(event)) {
1570 ret = intel_pmu_setup_lbr_filter(event);
1571 if (ret)
1572 return ret;
1573 }
1574
b4cdc5c2
PZ		 1575 if (event->attr.type != PERF_TYPE_RAW)
1576 return 0;
1577
1578 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1579 return 0;
1580
1581 if (x86_pmu.version < 3)
1582 return -EINVAL;
1583
1584 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1585 return -EACCES;
1586
1587 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1588
1589 return 0;
1590}
1591
144d31e6
GN		 1592struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1593{
1594 if (x86_pmu.guest_get_msrs)
1595 return x86_pmu.guest_get_msrs(nr);
1596 *nr = 0;
1597 return NULL;
1598}
1599EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1600
1601static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1602{
1603 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1604 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1605
1606 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1607 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1608 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1609 /*
1610 * If PMU counter has PEBS enabled it is not enough to disable counter
1611 * on a guest entry since PEBS memory write can overshoot guest entry
1612 * and corrupt guest memory. Disabling PEBS solves the problem.
1613 */
1614 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1615 arr[1].host = cpuc->pebs_enabled;
1616 arr[1].guest = 0;
144d31e6 1617
26a4f3c0 1618 *nr = 2;
144d31e6
GN		 1619 return arr;
1620}
1621
1622static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1623{
1624 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1625 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1626 int idx;
1627
1628 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1629 struct perf_event *event = cpuc->events[idx];
1630
1631 arr[idx].msr = x86_pmu_config_addr(idx);
1632 arr[idx].host = arr[idx].guest = 0;
1633
1634 if (!test_bit(idx, cpuc->active_mask))
1635 continue;
1636
1637 arr[idx].host = arr[idx].guest =
1638 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1639
1640 if (event->attr.exclude_host)
1641 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1642 else if (event->attr.exclude_guest)
1643 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1644 }
1645
1646 *nr = x86_pmu.num_counters;
1647 return arr;
1648}
1649
1650static void core_pmu_enable_event(struct perf_event *event)
1651{
1652 if (!event->attr.exclude_host)
1653 x86_pmu_enable_event(event);
1654}
1655
1656static void core_pmu_enable_all(int added)
1657{
1658 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1659 int idx;
1660
1661 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1662 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1663
1664 if (!test_bit(idx, cpuc->active_mask) ||
1665 cpuc->events[idx]->attr.exclude_host)
1666 continue;
1667
1668 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1669 }
1670}
1671
3a632cb2
AK		 1672static int hsw_hw_config(struct perf_event *event)
1673{
1674 int ret = intel_pmu_hw_config(event);
1675
1676 if (ret)
1677 return ret;
1678 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1679 return 0;
1680 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1681
1682 /*
1683 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1684 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1685 * this combination.
1686 */
1687 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1688 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1689 event->attr.precise_ip > 0))
1690 return -EOPNOTSUPP;
1691
1692 return 0;
1693}
1694
1695static struct event_constraint counter2_constraint =
1696 EVENT_CONSTRAINT(0, 0x4, 0);
1697
1698static struct event_constraint *
1699hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1700{
1701 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1702
1703 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1704 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1705 if (c->idxmsk64 & (1U << 2))
1706 return &counter2_constraint;
1707 return &emptyconstraint;
1708 }
1709
1710 return c;
1711}
1712
641cc938
JO		 1713PMU_FORMAT_ATTR(event, "config:0-7" );
1714PMU_FORMAT_ATTR(umask, "config:8-15" );
1715PMU_FORMAT_ATTR(edge, "config:18" );
1716PMU_FORMAT_ATTR(pc, "config:19" );
1717PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1718PMU_FORMAT_ATTR(inv, "config:23" );
1719PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 1720PMU_FORMAT_ATTR(in_tx, "config:32");
1721PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 1722
1723static struct attribute *intel_arch_formats_attr[] = {
1724 &format_attr_event.attr,
1725 &format_attr_umask.attr,
1726 &format_attr_edge.attr,
1727 &format_attr_pc.attr,
1728 &format_attr_inv.attr,
1729 &format_attr_cmask.attr,
1730 NULL,
1731};
1732
0bf79d44
JO		 1733ssize_t intel_event_sysfs_show(char *page, u64 config)
1734{
1735 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1736
1737 return x86_event_sysfs_show(page, config, event);
1738}
1739
caaa8be3 1740static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1741 .name = "core",
1742 .handle_irq = x86_pmu_handle_irq,
1743 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1744 .enable_all = core_pmu_enable_all,
1745 .enable = core_pmu_enable_event,
f22f54f4 1746 .disable = x86_pmu_disable_event,
b4cdc5c2 1747 .hw_config = x86_pmu_hw_config,
a072738e 1748 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1749 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1750 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1751 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1752 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1753 .apic = 1,
1754 /*
1755 * Intel PMCs cannot be accessed sanely above 32 bit width,
1756 * so we install an artificial 1<<31 period regardless of
1757 * the generic event period:
1758 */
1759 .max_period = (1ULL << 31) - 1,
1760 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1761 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1762 .event_constraints = intel_core_event_constraints,
144d31e6 1763 .guest_get_msrs = core_guest_get_msrs,
641cc938 1764 .format_attrs = intel_arch_formats_attr,
0bf79d44 1765 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 1766};
1767
de0428a7 1768struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1769{
1770 struct intel_shared_regs *regs;
1771 int i;
1772
1773 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1774 GFP_KERNEL, cpu_to_node(cpu));
1775 if (regs) {
1776 /*
1777 * initialize the locks to keep lockdep happy
1778 */
1779 for (i = 0; i < EXTRA_REG_MAX; i++)
1780 raw_spin_lock_init(&regs->regs[i].lock);
1781
1782 regs->core_id = -1;
1783 }
1784 return regs;
1785}
1786
a7e3ed1e
AK		 1787static int intel_pmu_cpu_prepare(int cpu)
1788{
1789 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1790
b36817e8 1791 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 1792 return NOTIFY_OK;
1793
efc9f05d
SE		 1794 cpuc->shared_regs = allocate_shared_regs(cpu);
1795 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1796 return NOTIFY_BAD;
1797
a7e3ed1e
AK		 1798 return NOTIFY_OK;
1799}
1800
74846d35
PZ		 1801static void intel_pmu_cpu_starting(int cpu)
1802{
a7e3ed1e
AK		 1803 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1804 int core_id = topology_core_id(cpu);
1805 int i;
1806
69092624
LM		 1807 init_debug_store_on_cpu(cpu);
1808 /*
1809 * Deal with CPUs that don't clear their LBRs on power-up.
1810 */
1811 intel_pmu_lbr_reset();
1812
b36817e8
SE		 1813 cpuc->lbr_sel = NULL;
1814
1815 if (!cpuc->shared_regs)
69092624
LM		 1816 return;
1817
b36817e8
SE		 1818 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1819 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1820 struct intel_shared_regs *pc;
a7e3ed1e 1821
b36817e8
SE		 1822 pc = per_cpu(cpu_hw_events, i).shared_regs;
1823 if (pc && pc->core_id == core_id) {
1824 cpuc->kfree_on_online = cpuc->shared_regs;
1825 cpuc->shared_regs = pc;
1826 break;
1827 }
a7e3ed1e 1828 }
b36817e8
SE		 1829 cpuc->shared_regs->core_id = core_id;
1830 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 1831 }
1832
b36817e8
SE		 1833 if (x86_pmu.lbr_sel_map)
1834 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 1835}
1836
1837static void intel_pmu_cpu_dying(int cpu)
1838{
a7e3ed1e 1839 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1840 struct intel_shared_regs *pc;
a7e3ed1e 1841
efc9f05d 1842 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1843 if (pc) {
1844 if (pc->core_id == -1 || --pc->refcnt == 0)
1845 kfree(pc);
efc9f05d 1846 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1847 }
1848
74846d35
PZ		 1849 fini_debug_store_on_cpu(cpu);
1850}
1851
d010b332
SE		 1852static void intel_pmu_flush_branch_stack(void)
1853{
1854 /*
1855 * Intel LBR does not tag entries with the
1856 * PID of the current task, then we need to
1857 * flush it on ctxsw
1858 * For now, we simply reset it
1859 */
1860 if (x86_pmu.lbr_nr)
1861 intel_pmu_lbr_reset();
1862}
1863
641cc938
JO		 1864PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1865
a63fcab4
SE		 1866PMU_FORMAT_ATTR(ldlat, "config1:0-15");
1867
641cc938
JO		 1868static struct attribute *intel_arch3_formats_attr[] = {
1869 &format_attr_event.attr,
1870 &format_attr_umask.attr,
1871 &format_attr_edge.attr,
1872 &format_attr_pc.attr,
1873 &format_attr_any.attr,
1874 &format_attr_inv.attr,
1875 &format_attr_cmask.attr,
3a632cb2
AK		 1876 &format_attr_in_tx.attr,
1877 &format_attr_in_tx_cp.attr,
641cc938
JO		 1878
1879 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 1880 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 1881 NULL,
1882};
1883
caaa8be3 1884static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1885 .name = "Intel",
1886 .handle_irq = intel_pmu_handle_irq,
1887 .disable_all = intel_pmu_disable_all,
1888 .enable_all = intel_pmu_enable_all,
1889 .enable = intel_pmu_enable_event,
1890 .disable = intel_pmu_disable_event,
b4cdc5c2 1891 .hw_config = intel_pmu_hw_config,
a072738e 1892 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1893 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1894 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1895 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1896 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1897 .apic = 1,
1898 /*
1899 * Intel PMCs cannot be accessed sanely above 32 bit width,
1900 * so we install an artificial 1<<31 period regardless of
1901 * the generic event period:
1902 */
1903 .max_period = (1ULL << 31) - 1,
3f6da390 1904 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1905 .put_event_constraints = intel_put_event_constraints,
0780c927 1906 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 1907
641cc938 1908 .format_attrs = intel_arch3_formats_attr,
0bf79d44 1909 .events_sysfs_show = intel_event_sysfs_show,
641cc938 1910
a7e3ed1e 1911 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1912 .cpu_starting = intel_pmu_cpu_starting,
1913 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 1914 .guest_get_msrs = intel_guest_get_msrs,
d010b332 1915 .flush_branch_stack = intel_pmu_flush_branch_stack,
f22f54f4
PZ		 1916};
1917
c1d6f42f 1918static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 1919{
1920 /*
1921 * PEBS is unreliable due to:
1922 *
1923 * AJ67 - PEBS may experience CPL leaks
1924 * AJ68 - PEBS PMI may be delayed by one event
1925 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1926 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1927 *
1928 * AJ67 could be worked around by restricting the OS/USR flags.
1929 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1930 *
1931 * AJ106 could possibly be worked around by not allowing LBR
1932 * usage from PEBS, including the fixup.
1933 * AJ68 could possibly be worked around by always programming
ec75a716 1934 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1935 *
1936 * But taken together it might just make sense to not enable PEBS on
1937 * these chips.
1938 */
c767a54b 1939 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 1940 x86_pmu.pebs = 0;
1941 x86_pmu.pebs_constraints = NULL;
1942}
1943
c93dc84c
PZ		 1944static int intel_snb_pebs_broken(int cpu)
1945{
1946 u32 rev = UINT_MAX; /* default to broken for unknown models */
1947
1948 switch (cpu_data(cpu).x86_model) {
1949 case 42: /* SNB */
1950 rev = 0x28;
1951 break;
1952
1953 case 45: /* SNB-EP */
1954 switch (cpu_data(cpu).x86_mask) {
1955 case 6: rev = 0x618; break;
1956 case 7: rev = 0x70c; break;
1957 }
1958 }
1959
1960 return (cpu_data(cpu).microcode < rev);
1961}
1962
1963static void intel_snb_check_microcode(void)
1964{
1965 int pebs_broken = 0;
1966 int cpu;
1967
1968 get_online_cpus();
1969 for_each_online_cpu(cpu) {
1970 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1971 break;
1972 }
1973 put_online_cpus();
1974
1975 if (pebs_broken == x86_pmu.pebs_broken)
1976 return;
1977
1978 /*
1979 * Serialized by the microcode lock..
1980 */
1981 if (x86_pmu.pebs_broken) {
1982 pr_info("PEBS enabled due to microcode update\n");
1983 x86_pmu.pebs_broken = 0;
1984 } else {
1985 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1986 x86_pmu.pebs_broken = 1;
1987 }
1988}
1989
c1d6f42f 1990static __init void intel_sandybridge_quirk(void)
6a600a8b 1991{
c93dc84c
PZ		 1992 x86_pmu.check_microcode = intel_snb_check_microcode;
1993 intel_snb_check_microcode();
6a600a8b
PZ		 1994}
1995
c1d6f42f
PZ		 1996static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1997 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1998 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1999 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2000 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2001 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2002 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2003 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2004};
2005
c1d6f42f
PZ		 2006static __init void intel_arch_events_quirk(void)
2007{
2008 int bit;
2009
2010 /* disable event that reported as not presend by cpuid */
2011 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2012 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2013 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2014 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2015 }
2016}
2017
2018static __init void intel_nehalem_quirk(void)
2019{
2020 union cpuid10_ebx ebx;
2021
2022 ebx.full = x86_pmu.events_maskl;
2023 if (ebx.split.no_branch_misses_retired) {
2024 /*
2025 * Erratum AAJ80 detected, we work it around by using
2026 * the BR_MISP_EXEC.ANY event. This will over-count
2027 * branch-misses, but it's still much better than the
2028 * architectural event which is often completely bogus:
2029 */
2030 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2031 ebx.split.no_branch_misses_retired = 0;
2032 x86_pmu.events_maskl = ebx.full;
c767a54b 2033 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2034 }
2035}
2036
f9134f36
AK		 2037EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2038EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
2039
2040static struct attribute *hsw_events_attrs[] = {
2041 EVENT_PTR(mem_ld_hsw),
2042 EVENT_PTR(mem_st_hsw),
2043 NULL
2044};
2045
de0428a7 2046__init int intel_pmu_init(void)
f22f54f4
PZ		 2047{
2048 union cpuid10_edx edx;
2049 union cpuid10_eax eax;
ffb871bc 2050 union cpuid10_ebx ebx;
a1eac7ac 2051 struct event_constraint *c;
f22f54f4 2052 unsigned int unused;
f22f54f4
PZ		 2053 int version;
2054
2055 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2056 switch (boot_cpu_data.x86) {
2057 case 0x6:
2058 return p6_pmu_init();
e717bf4e
VW		 2059 case 0xb:
2060 return knc_pmu_init();
a072738e
CG		 2061 case 0xf:
2062 return p4_pmu_init();
2063 }
f22f54f4 2064 return -ENODEV;
f22f54f4
PZ		 2065 }
2066
2067 /*
2068 * Check whether the Architectural PerfMon supports
2069 * Branch Misses Retired hw_event or not.
2070 */
ffb871bc
GN		 2071 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2072 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 2073 return -ENODEV;
2074
2075 version = eax.split.version_id;
2076 if (version < 2)
2077 x86_pmu = core_pmu;
2078 else
2079 x86_pmu = intel_pmu;
2080
2081 x86_pmu.version = version;
948b1bb8
RR		 2082 x86_pmu.num_counters = eax.split.num_counters;
2083 x86_pmu.cntval_bits = eax.split.bit_width;
2084 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 2085
c1d6f42f
PZ		 2086 x86_pmu.events_maskl = ebx.full;
2087 x86_pmu.events_mask_len = eax.split.mask_length;
2088
70ab7003
AK		 2089 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2090
f22f54f4
PZ		 2091 /*
2092 * Quirk: v2 perfmon does not report fixed-purpose events, so
2093 * assume at least 3 events:
2094 */
2095 if (version > 1)
948b1bb8 2096 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2097
8db909a7
PZ		 2098 /*
2099 * v2 and above have a perf capabilities MSR
2100 */
2101 if (version > 1) {
2102 u64 capabilities;
2103
2104 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2105 x86_pmu.intel_cap.capabilities = capabilities;
2106 }
2107
ca037701
PZ		 2108 intel_ds_init();
2109
c1d6f42f
PZ		 2110 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2111
f22f54f4
PZ		 2112 /*
2113 * Install the hw-cache-events table:
2114 */
2115 switch (boot_cpu_data.x86_model) {
2116 case 14: /* 65 nm core solo/duo, "Yonah" */
2117 pr_cont("Core events, ");
2118 break;
2119
2120 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 2121 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 2122 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2123 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2124 case 29: /* six-core 45 nm xeon "Dunnington" */
2125 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2126 sizeof(hw_cache_event_ids));
2127
caff2bef
PZ		 2128 intel_pmu_lbr_init_core();
2129
f22f54f4 2130 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 2131 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 2132 pr_cont("Core2 events, ");
2133 break;
2134
2135 case 26: /* 45 nm nehalem, "Bloomfield" */
2136 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 2137 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 2138 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2139 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2140 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2141 sizeof(hw_cache_extra_regs));
f22f54f4 2142
caff2bef
PZ		 2143 intel_pmu_lbr_init_nhm();
2144
f22f54f4 2145 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 2146 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 2147 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 2148 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 2149
f20093ee
SE		 2150 x86_pmu.cpu_events = nhm_events_attrs;
2151
91fc4cc0 2152 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2153 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2154 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2155 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2156 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2157 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2158
c1d6f42f 2159 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2160
11164cd4 2161 pr_cont("Nehalem events, ");
f22f54f4 2162 break;
caff2bef 2163
b622d644 2164 case 28: /* Atom */
0927b482
SL		 2165 case 38: /* Lincroft */
2166 case 39: /* Penwell */
2167 case 53: /* Cloverview */
2168 case 54: /* Cedarview */
f22f54f4
PZ		 2169 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2170 sizeof(hw_cache_event_ids));
2171
caff2bef
PZ		 2172 intel_pmu_lbr_init_atom();
2173
f22f54f4 2174 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2175 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2176 pr_cont("Atom events, ");
2177 break;
2178
2179 case 37: /* 32 nm nehalem, "Clarkdale" */
2180 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 2181 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 2182 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2183 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2184 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2185 sizeof(hw_cache_extra_regs));
f22f54f4 2186
caff2bef
PZ		 2187 intel_pmu_lbr_init_nhm();
2188
f22f54f4 2189 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2190 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2191 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2192 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2193 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039 2194
f20093ee
SE		 2195 x86_pmu.cpu_events = nhm_events_attrs;
2196
30112039 2197 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2198 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2199 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2200 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2201 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2202 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2203
f22f54f4
PZ		 2204 pr_cont("Westmere events, ");
2205 break;
b622d644 2206
b06b3d49 2207 case 42: /* SandyBridge */
a34668f6 2208 case 45: /* SandyBridge, "Romely-EP" */
47a8863d 2209 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2210 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2211 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2212 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2213 sizeof(hw_cache_extra_regs));
b06b3d49 2214
c5cc2cd9 2215 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2216
2217 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2218 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2219 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2220 if (boot_cpu_data.x86_model == 45)
2221 x86_pmu.extra_regs = intel_snbep_extra_regs;
2222 else
2223 x86_pmu.extra_regs = intel_snb_extra_regs;
ee89cbc2 2224 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2225 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2226 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23 2227
f20093ee
SE		 2228 x86_pmu.cpu_events = snb_events_attrs;
2229
e04d1b23 2230 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2231 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2232 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2233 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2234 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2235 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2236
b06b3d49
LM		 2237 pr_cont("SandyBridge events, ");
2238 break;
20a36e39 2239 case 58: /* IvyBridge */
923d8697 2240 case 62: /* IvyBridge EP */
20a36e39
SE		 2241 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2242 sizeof(hw_cache_event_ids));
2243 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2244 sizeof(hw_cache_extra_regs));
2245
2246 intel_pmu_lbr_init_snb();
2247
69943182 2248 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 2249 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2250 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2251 if (boot_cpu_data.x86_model == 62)
2252 x86_pmu.extra_regs = intel_snbep_extra_regs;
2253 else
2254 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39
SE		 2255 /* all extra regs are per-cpu when HT is on */
2256 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2257 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2258
f20093ee
SE		 2259 x86_pmu.cpu_events = snb_events_attrs;
2260
20a36e39
SE		 2261 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2262 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2263 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2264
2265 pr_cont("IvyBridge events, ");
2266 break;
2267
b06b3d49 2268
3a632cb2
AK		 2269 case 60: /* Haswell Client */
2270 case 70:
2271 case 71:
2272 case 63:
72db5596 2273 x86_pmu.late_ack = true;
3a632cb2
AK		 2274 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2275 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2276
2277 intel_pmu_lbr_init_snb();
2278
2279 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 2280 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3a632cb2 2281 x86_pmu.extra_regs = intel_snb_extra_regs;
3044318f 2282 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2
AK		 2283 /* all extra regs are per-cpu when HT is on */
2284 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2285 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2286
2287 x86_pmu.hw_config = hsw_hw_config;
2288 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 2289 x86_pmu.cpu_events = hsw_events_attrs;
3a632cb2
AK		 2290 pr_cont("Haswell events, ");
2291 break;
2292
f22f54f4 2293 default:
0af3ac1f
AK		 2294 switch (x86_pmu.version) {
2295 case 1:
2296 x86_pmu.event_constraints = intel_v1_event_constraints;
2297 pr_cont("generic architected perfmon v1, ");
2298 break;
2299 default:
2300 /*
2301 * default constraints for v2 and up
2302 */
2303 x86_pmu.event_constraints = intel_gen_event_constraints;
2304 pr_cont("generic architected perfmon, ");
2305 break;
2306 }
f22f54f4 2307 }
ffb871bc 2308
a1eac7ac
RR		 2309 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2310 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2311 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2312 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2313 }
2314 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2315
2316 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2317 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2318 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2319 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2320 }
2321
2322 x86_pmu.intel_ctrl |=
2323 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2324
2325 if (x86_pmu.event_constraints) {
2326 /*
2327 * event on fixed counter2 (REF_CYCLES) only works on this
2328 * counter, so do not extend mask to generic counters
2329 */
2330 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 2331 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 2332 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2333 continue;
2334 }
2335
2336 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2337 c->weight += x86_pmu.num_counters;
2338 }
2339 }
2340
069e0c3c
AK		 2341 /* Support full width counters using alternative MSR range */
2342 if (x86_pmu.intel_cap.full_width_write) {
2343 x86_pmu.max_period = x86_pmu.cntval_mask;
2344 x86_pmu.perfctr = MSR_IA32_PMC0;
2345 pr_cont("full-width counters, ");
2346 }
2347
f22f54f4
PZ		 2348 return 0;
2349}
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