[linux.git] / arch / arm / mm / proc-arm922.S

/*
 *  linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
 *
 *  Copyright (C) 1999,2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  Copyright (C) 2001 Altera Corporation
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm922.
 *
 *  CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/procinfo.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	4

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintainence instructions.  (I think this should
 * be 32768).
 */
#define CACHE_DLIMIT	8192


	.text
/*
 * cpu_arm922_proc_init()
 */
ENTRY(cpu_arm922_proc_init)
	mov	pc, lr

/*
 * cpu_arm922_proc_fin()
 */
ENTRY(cpu_arm922_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	msr	cpsr_c, ip
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bl	arm922_flush_kern_cache_all
#else
	bl	v4wt_flush_kern_cache_all
#endif
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_arm922_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm922_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm922_do_idle()
 */
	.align	5
ENTRY(cpu_arm922_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr


#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm922_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm922_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 8 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 7 to 0
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm922_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm922_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm922_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_page(void *page)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- page aligned address
 */
ENTRY(arm922_flush_kern_dcache_page)
	add	r1, r0, #PAGE_SZ
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm922_dma_inv_range)
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
ENTRY(arm922_dma_clean_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm922_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

ENTRY(arm922_cache_fns)
	.long	arm922_flush_kern_cache_all
	.long	arm922_flush_user_cache_all
	.long	arm922_flush_user_cache_range
	.long	arm922_coherent_kern_range
	.long	arm922_coherent_user_range
	.long	arm922_flush_kern_dcache_page
	.long	arm922_dma_inv_range
	.long	arm922_dma_clean_range
	.long	arm922_dma_flush_range

#endif


ENTRY(cpu_arm922_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm922_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm922_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
@ && Re-written to use Index Ops.
@ && Uses registers r1, r3 and ip

	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 7 to 0
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr

/*
 * cpu_arm922_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm922_set_pte)
#ifdef CONFIG_MMU
	str	r1, [r0], #-2048		@ linux version

	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY

	bic	r2, r1, #PTE_SMALL_AP_MASK
	bic	r2, r2, #PTE_TYPE_MASK
	orr	r2, r2, #PTE_TYPE_SMALL

	tst	r1, #L_PTE_USER			@ User?
	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW

	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW

	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
	movne	r2, #0

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	eor	r3, r2, #0x0a			@ C & small page?
	tst	r3, #0x0b
	biceq	r2, r2, #4
#endif
	str	r2, [r0]			@ hardware version
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif /* CONFIG_MMU */
	mov	pc, lr

	__INIT

	.type	__arm922_setup, #function
__arm922_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif
	adr	r5, arm922_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
	mov	pc, lr
	.size	__arm922_setup, . - __arm922_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * ..11 0001 ..11 0101
	 * 
	 */
	.type	arm922_crval, #object
arm922_crval:
	crval	clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm922_processor_functions, #object
arm922_processor_functions:
	.word	v4t_early_abort
	.word	cpu_arm922_proc_init
	.word	cpu_arm922_proc_fin
	.word	cpu_arm922_reset
	.word   cpu_arm922_do_idle
	.word	cpu_arm922_dcache_clean_area
	.word	cpu_arm922_switch_mm
	.word	cpu_arm922_set_pte
	.size	arm922_processor_functions, . - arm922_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv4t"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v4"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm922_name, #object
cpu_arm922_name:
	.asciz	"ARM922T"
	.size	cpu_arm922_name, . - cpu_arm922_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm922_proc_info,#object
__arm922_proc_info:
	.long	0x41009220
	.long	0xff00fff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm922_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm922_name
	.long	arm922_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	.long	arm922_cache_fns
#else
	.long	v4wt_cache_fns
#endif
	.size	__arm922_proc_info, . - __arm922_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
	3	*
	4	* Copyright (C) 1999,2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	6	* Copyright (C) 2001 Altera Corporation
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*
	24	* These are the low level assembler for performing cache and TLB
	25	* functions on the arm922.
	26	*
	27	* CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
	28	*/
	29	#include <linux/linkage.h>
1da177e4 LT	30	#include <linux/init.h>
1da177e4 LT	31	#include <asm/assembler.h>
74945c86	32	#include <asm/pgtable-hwdef.h>
1da177e4 LT	33	#include <asm/pgtable.h>
1da177e4 LT	34	#include <asm/procinfo.h>
1da177e4 LT	35	#include <asm/page.h>
	36	#include <asm/ptrace.h>
	37	#include "proc-macros.S"
	38
	39	/*
	40	* The size of one data cache line.
	41	*/
	42	#define CACHE_DLINESIZE 32
	43
	44	/*
	45	* The number of data cache segments.
	46	*/
	47	#define CACHE_DSEGMENTS 4
	48
	49	/*
	50	* The number of lines in a cache segment.
	51	*/
	52	#define CACHE_DENTRIES 64
	53
	54	/*
	55	* This is the size at which it becomes more efficient to
	56	* clean the whole cache, rather than using the individual
	57	* cache line maintainence instructions. (I think this should
	58	* be 32768).
	59	*/
	60	#define CACHE_DLIMIT 8192
	61
	62
	63	.text
	64	/*
	65	* cpu_arm922_proc_init()
	66	*/
	67	ENTRY(cpu_arm922_proc_init)
	68	mov pc, lr
	69
	70	/*
	71	* cpu_arm922_proc_fin()
	72	*/
	73	ENTRY(cpu_arm922_proc_fin)
	74	stmfd sp!, {lr}
	75	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	76	msr cpsr_c, ip
	77	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	78	bl arm922_flush_kern_cache_all
	79	#else
	80	bl v4wt_flush_kern_cache_all
	81	#endif
	82	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	83	bic r0, r0, #0x1000 @ ...i............
	84	bic r0, r0, #0x000e @ ............wca.
	85	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	86	ldmfd sp!, {pc}
	87
	88	/*
	89	* cpu_arm922_reset(loc)
	90	*
	91	* Perform a soft reset of the system. Put the CPU into the
	92	* same state as it would be if it had been reset, and branch
	93	* to what would be the reset vector.
	94	*
	95	* loc: location to jump to for soft reset
	96	*/
	97	.align 5
	98	ENTRY(cpu_arm922_reset)
99	mov ip, #0
100	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	102	#ifdef CONFIG_MMU
1da177e4	103	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	104	#endif
1da177e4 LT	105	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	106	bic ip, ip, #0x000f @ ............wcam
	107	bic ip, ip, #0x1100 @ ...i...s........
	108	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	109	mov pc, r0
	110
	111	/*
	112	* cpu_arm922_do_idle()
	113	*/
	114	.align 5
	115	ENTRY(cpu_arm922_do_idle)
	116	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	117	mov pc, lr
	118
	119
	120	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	121
	122	/*
	123	* flush_user_cache_all()
	124	*
	125	* Clean and invalidate all cache entries in a particular
	126	* address space.
	127	*/
	128	ENTRY(arm922_flush_user_cache_all)
	129	/* FALLTHROUGH */
	130
	131	/*
	132	* flush_kern_cache_all()
	133	*
	134	* Clean and invalidate the entire cache.
	135	*/
	136	ENTRY(arm922_flush_kern_cache_all)
	137	mov r2, #VM_EXEC
	138	mov ip, #0
	139	__flush_whole_cache:
	140	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
	141	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	142	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	143	subs r3, r3, #1 << 26
	144	bcs 2b @ entries 63 to 0
	145	subs r1, r1, #1 << 5
	146	bcs 1b @ segments 7 to 0
	147	tst r2, #VM_EXEC
	148	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	149	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	150	mov pc, lr
	151
	152	/*
	153	* flush_user_cache_range(start, end, flags)
	154	*
	155	* Clean and invalidate a range of cache entries in the
	156	* specified address range.
	157	*
	158	* - start - start address (inclusive)
	159	* - end - end address (exclusive)
	160	* - flags - vm_flags describing address space
	161	*/
	162	ENTRY(arm922_flush_user_cache_range)
	163	mov ip, #0
	164	sub r3, r1, r0 @ calculate total size
	165	cmp r3, #CACHE_DLIMIT
	166	bhs __flush_whole_cache
	167
	168	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
169	tst r2, #VM_EXEC
170	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
171	add r0, r0, #CACHE_DLINESIZE
172	cmp r0, r1
173	blo 1b
174	tst r2, #VM_EXEC
175	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
176	mov pc, lr
177
178	/*
179	* coherent_kern_range(start, end)
180	*
181	* Ensure coherency between the Icache and the Dcache in the
182	* region described by start, end. If you have non-snooping
183	* Harvard caches, you need to implement this function.
184	*
185	* - start - virtual start address
186	* - end - virtual end address
187	*/
188	ENTRY(arm922_coherent_kern_range)
189	/* FALLTHROUGH */
190
191	/*
192	* coherent_user_range(start, end)
193	*
194	* Ensure coherency between the Icache and the Dcache in the
195	* region described by start, end. If you have non-snooping
196	* Harvard caches, you need to implement this function.
197	*
198	* - start - virtual start address
199	* - end - virtual end address
200	*/
201	ENTRY(arm922_coherent_user_range)
202	bic r0, r0, #CACHE_DLINESIZE - 1
203	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
204	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
205	add r0, r0, #CACHE_DLINESIZE
206	cmp r0, r1
207	blo 1b
208	mcr p15, 0, r0, c7, c10, 4 @ drain WB
209	mov pc, lr
210
211	/*
212	* flush_kern_dcache_page(void *page)
213	*
214	* Ensure no D cache aliasing occurs, either with itself or
215	* the I cache
216	*
217	* - addr - page aligned address
218	*/
219	ENTRY(arm922_flush_kern_dcache_page)
220	add r1, r0, #PAGE_SZ
221	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
222	add r0, r0, #CACHE_DLINESIZE
223	cmp r0, r1
224	blo 1b
225	mov r0, #0
226	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
227	mcr p15, 0, r0, c7, c10, 4 @ drain WB
228	mov pc, lr
229
230	/*
231	* dma_inv_range(start, end)
232	*
233	* Invalidate (discard) the specified virtual address range.
234	* May not write back any entries. If 'start' or 'end'
235	* are not cache line aligned, those lines must be written
236	* back.
237	*
238	* - start - virtual start address
239	* - end - virtual end address
240	*
241	* (same as v4wb)
242	*/
243	ENTRY(arm922_dma_inv_range)
244	tst r0, #CACHE_DLINESIZE - 1
245	bic r0, r0, #CACHE_DLINESIZE - 1
246	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
247	tst r1, #CACHE_DLINESIZE - 1
248	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
249	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
250	add r0, r0, #CACHE_DLINESIZE
251	cmp r0, r1
252	blo 1b
253	mcr p15, 0, r0, c7, c10, 4 @ drain WB
254	mov pc, lr
255
256	/*
257	* dma_clean_range(start, end)
258	*
259	* Clean the specified virtual address range.
260	*
261	* - start - virtual start address
262	* - end - virtual end address
263	*
264	* (same as v4wb)
265	*/
266	ENTRY(arm922_dma_clean_range)
267	bic r0, r0, #CACHE_DLINESIZE - 1
268	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
269	add r0, r0, #CACHE_DLINESIZE
270	cmp r0, r1
271	blo 1b
272	mcr p15, 0, r0, c7, c10, 4 @ drain WB
273	mov pc, lr
274
275	/*
276	* dma_flush_range(start, end)
277	*
278	* Clean and invalidate the specified virtual address range.
279	*
280	* - start - virtual start address
281	* - end - virtual end address
282	*/
283	ENTRY(arm922_dma_flush_range)
284	bic r0, r0, #CACHE_DLINESIZE - 1
285	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
286	add r0, r0, #CACHE_DLINESIZE
287	cmp r0, r1
288	blo 1b
289	mcr p15, 0, r0, c7, c10, 4 @ drain WB
290	mov pc, lr
291
292	ENTRY(arm922_cache_fns)
293	.long arm922_flush_kern_cache_all
294	.long arm922_flush_user_cache_all
295	.long arm922_flush_user_cache_range
296	.long arm922_coherent_kern_range
297	.long arm922_coherent_user_range
298	.long arm922_flush_kern_dcache_page
299	.long arm922_dma_inv_range
300	.long arm922_dma_clean_range
301	.long arm922_dma_flush_range
302
303	#endif
304
305
306	ENTRY(cpu_arm922_dcache_clean_area)
307	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
308	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
309	add r0, r0, #CACHE_DLINESIZE
310	subs r1, r1, #CACHE_DLINESIZE
311	bhi 1b
312	#endif
313	mov pc, lr
314
315	/* =============================== PageTable ============================== */
316
317	/*
318	* cpu_arm922_switch_mm(pgd)
319	*
320	* Set the translation base pointer to be as described by pgd.
321	*
322	* pgd: new page tables
323	*/
324	.align 5
325	ENTRY(cpu_arm922_switch_mm)
d090ddda	326	#ifdef CONFIG_MMU
1da177e4 LT	327	mov ip, #0
	328	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	329	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	330	#else
	331	@ && 'Clean & Invalidate whole DCache'
	332	@ && Re-written to use Index Ops.
	333	@ && Uses registers r1, r3 and ip
	334
	335	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
	336	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	337	2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
	338	subs r3, r3, #1 << 26
	339	bcs 2b @ entries 63 to 0
	340	subs r1, r1, #1 << 5
	341	bcs 1b @ segments 7 to 0
	342	#endif
	343	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	344	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	345	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	346	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	347	#endif
1da177e4 LT	348	mov pc, lr
	349
	350	/*
	351	* cpu_arm922_set_pte(ptep, pte)
	352	*
	353	* Set a PTE and flush it out
	354	*/
	355	.align 5
	356	ENTRY(cpu_arm922_set_pte)
d090ddda	357	#ifdef CONFIG_MMU
1da177e4 LT	358	str r1, [r0], #-2048 @ linux version
	359
	360	eor r1, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_WRITE \| L_PTE_DIRTY
	361
	362	bic r2, r1, #PTE_SMALL_AP_MASK
	363	bic r2, r2, #PTE_TYPE_MASK
	364	orr r2, r2, #PTE_TYPE_SMALL
	365
	366	tst r1, #L_PTE_USER @ User?
	367	orrne r2, r2, #PTE_SMALL_AP_URO_SRW
	368
	369	tst r1, #L_PTE_WRITE \| L_PTE_DIRTY @ Write and Dirty?
	370	orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
	371
	372	tst r1, #L_PTE_PRESENT \| L_PTE_YOUNG @ Present and Young?
	373	movne r2, #0
	374
	375	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	376	eor r3, r2, #0x0a @ C & small page?
	377	tst r3, #0x0b
	378	biceq r2, r2, #4
	379	#endif
	380	str r2, [r0] @ hardware version
	381	mov r0, r0
	382	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	383	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	384	#endif /* CONFIG_MMU */
1da177e4 LT	385	mov pc, lr
	386
	387	__INIT
	388
	389	.type __arm922_setup, #function
	390	__arm922_setup:
	391	mov r0, #0
	392	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	393	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	394	#ifdef CONFIG_MMU
1da177e4	395	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	396	#endif
22b19086 RK	397	adr r5, arm922_crval
22b19086 RK	398	ldmia r5, {r5, r6}
1da177e4	399	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	400	bic r0, r0, r5
22b19086	401	orr r0, r0, r6
1da177e4 LT	402	mov pc, lr
	403	.size __arm922_setup, . - __arm922_setup
	404
	405	/*
	406	* R
	407	* .RVI ZFRS BLDP WCAM
	408	* ..11 0001 ..11 0101
	409	*
	410	*/
22b19086 RK	411	.type arm922_crval, #object
	412	arm922_crval:
	413	crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
1da177e4 LT	414
	415	__INITDATA
	416
	417	/*
	418	* Purpose : Function pointers used to access above functions - all calls
	419	* come through these
	420	*/
	421	.type arm922_processor_functions, #object
	422	arm922_processor_functions:
	423	.word v4t_early_abort
	424	.word cpu_arm922_proc_init
	425	.word cpu_arm922_proc_fin
	426	.word cpu_arm922_reset
	427	.word cpu_arm922_do_idle
	428	.word cpu_arm922_dcache_clean_area
	429	.word cpu_arm922_switch_mm
	430	.word cpu_arm922_set_pte
	431	.size arm922_processor_functions, . - arm922_processor_functions
	432
	433	.section ".rodata"
	434
	435	.type cpu_arch_name, #object
	436	cpu_arch_name:
	437	.asciz "armv4t"
	438	.size cpu_arch_name, . - cpu_arch_name
	439
	440	.type cpu_elf_name, #object
	441	cpu_elf_name:
	442	.asciz "v4"
	443	.size cpu_elf_name, . - cpu_elf_name
	444
	445	.type cpu_arm922_name, #object
	446	cpu_arm922_name:
264edb35	447	.asciz "ARM922T"
1da177e4 LT	448	.size cpu_arm922_name, . - cpu_arm922_name
	449
	450	.align
	451
02b7dd12	452	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	453
	454	.type __arm922_proc_info,#object
	455	__arm922_proc_info:
	456	.long 0x41009220
	457	.long 0xff00fff0
	458	.long PMD_TYPE_SECT \| \
	459	PMD_SECT_BUFFERABLE \| \
	460	PMD_SECT_CACHEABLE \| \
	461	PMD_BIT4 \| \
	462	PMD_SECT_AP_WRITE \| \
	463	PMD_SECT_AP_READ
8799ee9f RK	464	.long PMD_TYPE_SECT \| \
	465	PMD_BIT4 \| \
	466	PMD_SECT_AP_WRITE \| \
	467	PMD_SECT_AP_READ
1da177e4 LT	468	b __arm922_setup
	469	.long cpu_arch_name
	470	.long cpu_elf_name
	471	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	472	.long cpu_arm922_name
	473	.long arm922_processor_functions
	474	.long v4wbi_tlb_fns
	475	.long v4wb_user_fns
	476	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	477	.long arm922_cache_fns
	478	#else
	479	.long v4wt_cache_fns
	480	#endif
	481	.size __arm922_proc_info, . - __arm922_proc_info