[linux.git] / drivers / watchdog / iTCO_wdt.c

/*
 *	intel TCO Watchdog Driver
 *
 *	(c) Copyright 2006-2011 Wim Van Sebroeck <[email protected]>.
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
 *	provide warranty for any of this software. This material is
 *	provided "AS-IS" and at no charge.
 *
 *	The TCO watchdog is implemented in the following I/O controller hubs:
 *	(See the intel documentation on http://developer.intel.com.)
 *	document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
 *	document number 290687-002, 298242-027: 82801BA (ICH2)
 *	document number 290733-003, 290739-013: 82801CA (ICH3-S)
 *	document number 290716-001, 290718-007: 82801CAM (ICH3-M)
 *	document number 290744-001, 290745-025: 82801DB (ICH4)
 *	document number 252337-001, 252663-008: 82801DBM (ICH4-M)
 *	document number 273599-001, 273645-002: 82801E (C-ICH)
 *	document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
 *	document number 300641-004, 300884-013: 6300ESB
 *	document number 301473-002, 301474-026: 82801F (ICH6)
 *	document number 313082-001, 313075-006: 631xESB, 632xESB
 *	document number 307013-003, 307014-024: 82801G (ICH7)
 *	document number 322896-001, 322897-001: NM10
 *	document number 313056-003, 313057-017: 82801H (ICH8)
 *	document number 316972-004, 316973-012: 82801I (ICH9)
 *	document number 319973-002, 319974-002: 82801J (ICH10)
 *	document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
 *	document number 320066-003, 320257-008: EP80597 (IICH)
 *	document number 324645-001, 324646-001: Cougar Point (CPT)
 *	document number TBD                   : Patsburg (PBG)
 *	document number TBD                   : DH89xxCC
 *	document number TBD                   : Panther Point
 *	document number TBD                   : Lynx Point
 */

/*
 *	Includes, defines, variables, module parameters, ...
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

/* Module and version information */
#define DRV_NAME	"iTCO_wdt"
#define DRV_VERSION	"1.10"

/* Includes */
#include <linux/module.h>		/* For module specific items */
#include <linux/moduleparam.h>		/* For new moduleparam's */
#include <linux/types.h>		/* For standard types (like size_t) */
#include <linux/errno.h>		/* For the -ENODEV/... values */
#include <linux/kernel.h>		/* For printk/panic/... */
#include <linux/miscdevice.h>		/* For MODULE_ALIAS_MISCDEV
							(WATCHDOG_MINOR) */
#include <linux/watchdog.h>		/* For the watchdog specific items */
#include <linux/init.h>			/* For __init/__exit/... */
#include <linux/fs.h>			/* For file operations */
#include <linux/platform_device.h>	/* For platform_driver framework */
#include <linux/pci.h>			/* For pci functions */
#include <linux/ioport.h>		/* For io-port access */
#include <linux/spinlock.h>		/* For spin_lock/spin_unlock/... */
#include <linux/uaccess.h>		/* For copy_to_user/put_user/... */
#include <linux/io.h>			/* For inb/outb/... */
#include <linux/mfd/core.h>
#include <linux/mfd/lpc_ich.h>

#include "iTCO_vendor.h"

/* Address definitions for the TCO */
/* TCO base address */
#define TCOBASE		(iTCO_wdt_private.tco_res->start)
/* SMI Control and Enable Register */
#define SMI_EN		(iTCO_wdt_private.smi_res->start)

#define TCO_RLD		(TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
#define TCOv1_TMR	(TCOBASE + 0x01) /* TCOv1 Timer Initial Value	*/
#define TCO_DAT_IN	(TCOBASE + 0x02) /* TCO Data In Register	*/
#define TCO_DAT_OUT	(TCOBASE + 0x03) /* TCO Data Out Register	*/
#define TCO1_STS	(TCOBASE + 0x04) /* TCO1 Status Register	*/
#define TCO2_STS	(TCOBASE + 0x06) /* TCO2 Status Register	*/
#define TCO1_CNT	(TCOBASE + 0x08) /* TCO1 Control Register	*/
#define TCO2_CNT	(TCOBASE + 0x0a) /* TCO2 Control Register	*/
#define TCOv2_TMR	(TCOBASE + 0x12) /* TCOv2 Timer Initial Value	*/

/* internal variables */
static struct {		/* this is private data for the iTCO_wdt device */
	/* TCO version/generation */
	unsigned int iTCO_version;
	struct resource *tco_res;
	struct resource *smi_res;
	struct resource *gcs_res;
	/* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
	unsigned long __iomem *gcs;
	/* the lock for io operations */
	spinlock_t io_lock;
	struct platform_device *dev;
	/* the PCI-device */
	struct pci_dev *pdev;
} iTCO_wdt_private;

/* module parameters */
#define WATCHDOG_TIMEOUT 30	/* 30 sec default heartbeat */
static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
	"5..76 (TCO v1) or 3..614 (TCO v2), default="
				__MODULE_STRING(WATCHDOG_TIMEOUT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static int turn_SMI_watchdog_clear_off = 1;
module_param(turn_SMI_watchdog_clear_off, int, 0);
MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
	"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");

/*
 * Some TCO specific functions
 */

static inline unsigned int seconds_to_ticks(int seconds)
{
	/* the internal timer is stored as ticks which decrement
	 * every 0.6 seconds */
	return (seconds * 10) / 6;
}

static void iTCO_wdt_set_NO_REBOOT_bit(void)
{
	u32 val32;

	/* Set the NO_REBOOT bit: this disables reboots */
	if (iTCO_wdt_private.iTCO_version == 2) {
		val32 = readl(iTCO_wdt_private.gcs);
		val32 |= 0x00000020;
		writel(val32, iTCO_wdt_private.gcs);
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
		val32 |= 0x00000002;
		pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
	}
}

static int iTCO_wdt_unset_NO_REBOOT_bit(void)
{
	int ret = 0;
	u32 val32;

	/* Unset the NO_REBOOT bit: this enables reboots */
	if (iTCO_wdt_private.iTCO_version == 2) {
		val32 = readl(iTCO_wdt_private.gcs);
		val32 &= 0xffffffdf;
		writel(val32, iTCO_wdt_private.gcs);

		val32 = readl(iTCO_wdt_private.gcs);
		if (val32 & 0x00000020)
			ret = -EIO;
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
		val32 &= 0xfffffffd;
		pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);

		pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
		if (val32 & 0x00000002)
			ret = -EIO;
	}

	return ret; /* returns: 0 = OK, -EIO = Error */
}

static int iTCO_wdt_start(struct watchdog_device *wd_dev)
{
	unsigned int val;

	spin_lock(&iTCO_wdt_private.io_lock);

	iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);

	/* disable chipset's NO_REBOOT bit */
	if (iTCO_wdt_unset_NO_REBOOT_bit()) {
		spin_unlock(&iTCO_wdt_private.io_lock);
		pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
		return -EIO;
	}

	/* Force the timer to its reload value by writing to the TCO_RLD
	   register */
	if (iTCO_wdt_private.iTCO_version == 2)
		outw(0x01, TCO_RLD);
	else if (iTCO_wdt_private.iTCO_version == 1)
		outb(0x01, TCO_RLD);

	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
	val = inw(TCO1_CNT);
	val &= 0xf7ff;
	outw(val, TCO1_CNT);
	val = inw(TCO1_CNT);
	spin_unlock(&iTCO_wdt_private.io_lock);

	if (val & 0x0800)
		return -1;
	return 0;
}

static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
{
	unsigned int val;

	spin_lock(&iTCO_wdt_private.io_lock);

	iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);

	/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
	val = inw(TCO1_CNT);
	val |= 0x0800;
	outw(val, TCO1_CNT);
	val = inw(TCO1_CNT);

	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	iTCO_wdt_set_NO_REBOOT_bit();

	spin_unlock(&iTCO_wdt_private.io_lock);

	if ((val & 0x0800) == 0)
		return -1;
	return 0;
}

static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
{
	spin_lock(&iTCO_wdt_private.io_lock);

	iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);

	/* Reload the timer by writing to the TCO Timer Counter register */
	if (iTCO_wdt_private.iTCO_version == 2)
		outw(0x01, TCO_RLD);
	else if (iTCO_wdt_private.iTCO_version == 1) {
		/* Reset the timeout status bit so that the timer
		 * needs to count down twice again before rebooting */
		outw(0x0008, TCO1_STS);	/* write 1 to clear bit */

		outb(0x01, TCO_RLD);
	}

	spin_unlock(&iTCO_wdt_private.io_lock);
	return 0;
}

static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
{
	unsigned int val16;
	unsigned char val8;
	unsigned int tmrval;

	tmrval = seconds_to_ticks(t);

	/* For TCO v1 the timer counts down twice before rebooting */
	if (iTCO_wdt_private.iTCO_version == 1)
		tmrval /= 2;

	/* from the specs: */
	/* "Values of 0h-3h are ignored and should not be attempted" */
	if (tmrval < 0x04)
		return -EINVAL;
	if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
	    ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
		return -EINVAL;

	iTCO_vendor_pre_set_heartbeat(tmrval);

	/* Write new heartbeat to watchdog */
	if (iTCO_wdt_private.iTCO_version == 2) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val16 = inw(TCOv2_TMR);
		val16 &= 0xfc00;
		val16 |= tmrval;
		outw(val16, TCOv2_TMR);
		val16 = inw(TCOv2_TMR);
		spin_unlock(&iTCO_wdt_private.io_lock);

		if ((val16 & 0x3ff) != tmrval)
			return -EINVAL;
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val8 = inb(TCOv1_TMR);
		val8 &= 0xc0;
		val8 |= (tmrval & 0xff);
		outb(val8, TCOv1_TMR);
		val8 = inb(TCOv1_TMR);
		spin_unlock(&iTCO_wdt_private.io_lock);

		if ((val8 & 0x3f) != tmrval)
			return -EINVAL;
	}

	wd_dev->timeout = t;
	return 0;
}

static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
{
	unsigned int val16;
	unsigned char val8;
	unsigned int time_left = 0;

	/* read the TCO Timer */
	if (iTCO_wdt_private.iTCO_version == 2) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val16 = inw(TCO_RLD);
		val16 &= 0x3ff;
		spin_unlock(&iTCO_wdt_private.io_lock);

		time_left = (val16 * 6) / 10;
	} else if (iTCO_wdt_private.iTCO_version == 1) {
		spin_lock(&iTCO_wdt_private.io_lock);
		val8 = inb(TCO_RLD);
		val8 &= 0x3f;
		if (!(inw(TCO1_STS) & 0x0008))
			val8 += (inb(TCOv1_TMR) & 0x3f);
		spin_unlock(&iTCO_wdt_private.io_lock);

		time_left = (val8 * 6) / 10;
	}
	return time_left;
}

/*
 *	Kernel Interfaces
 */

static const struct watchdog_info ident = {
	.options =		WDIOF_SETTIMEOUT |
				WDIOF_KEEPALIVEPING |
				WDIOF_MAGICCLOSE,
	.firmware_version =	0,
	.identity =		DRV_NAME,
};

static const struct watchdog_ops iTCO_wdt_ops = {
	.owner =		THIS_MODULE,
	.start =		iTCO_wdt_start,
	.stop = 		iTCO_wdt_stop,
	.ping = 		iTCO_wdt_ping,
	.set_timeout =		iTCO_wdt_set_timeout,
	.get_timeleft =		iTCO_wdt_get_timeleft,
};

static struct watchdog_device iTCO_wdt_watchdog_dev = {
	.info =		&ident,
	.ops = 		&iTCO_wdt_ops,
};

/*
 *	Init & exit routines
 */

static void __devexit iTCO_wdt_cleanup(void)
{
	/* Stop the timer before we leave */
	if (!nowayout)
		iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);

	/* Deregister */
	watchdog_unregister_device(&iTCO_wdt_watchdog_dev);

	/* release resources */
	release_region(iTCO_wdt_private.tco_res->start,
			resource_size(iTCO_wdt_private.tco_res));
	release_region(iTCO_wdt_private.smi_res->start,
			resource_size(iTCO_wdt_private.smi_res));
	if (iTCO_wdt_private.iTCO_version == 2) {
		iounmap(iTCO_wdt_private.gcs);
		release_mem_region(iTCO_wdt_private.gcs_res->start,
				resource_size(iTCO_wdt_private.gcs_res));
	}

	iTCO_wdt_private.tco_res = NULL;
	iTCO_wdt_private.smi_res = NULL;
	iTCO_wdt_private.gcs_res = NULL;
	iTCO_wdt_private.gcs = NULL;
}

static int __devinit iTCO_wdt_probe(struct platform_device *dev)
{
	int ret = -ENODEV;
	unsigned long val32;
	struct lpc_ich_info *ich_info = dev->dev.platform_data;

	if (!ich_info)
		goto out;

	spin_lock_init(&iTCO_wdt_private.io_lock);

	iTCO_wdt_private.tco_res =
		platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
	if (!iTCO_wdt_private.tco_res)
		goto out;

	iTCO_wdt_private.smi_res =
		platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
	if (!iTCO_wdt_private.smi_res)
		goto out;

	iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
	iTCO_wdt_private.dev = dev;
	iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);

	/*
	 * Get the Memory-Mapped GCS register, we need it for the
	 * NO_REBOOT flag (TCO v2).
	 */
	if (iTCO_wdt_private.iTCO_version == 2) {
		iTCO_wdt_private.gcs_res = platform_get_resource(dev,
							IORESOURCE_MEM,
							ICH_RES_MEM_GCS);

		if (!iTCO_wdt_private.gcs_res)
			goto out;

		if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
			resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
			ret = -EBUSY;
			goto out;
		}
		iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
			resource_size(iTCO_wdt_private.gcs_res));
		if (!iTCO_wdt_private.gcs) {
			ret = -EIO;
			goto unreg_gcs;
		}
	}

	/* Check chipset's NO_REBOOT bit */
	if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
		pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
		ret = -ENODEV;	/* Cannot reset NO_REBOOT bit */
		goto unmap_gcs;
	}

	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	iTCO_wdt_set_NO_REBOOT_bit();

	/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
	if (!request_region(iTCO_wdt_private.smi_res->start,
			resource_size(iTCO_wdt_private.smi_res), dev->name)) {
		pr_err("I/O address 0x%04llx already in use, device disabled\n",
		       (u64)SMI_EN);
		ret = -EBUSY;
		goto unmap_gcs;
	}
	if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
		/*
		 * Bit 13: TCO_EN -> 0
		 * Disables TCO logic generating an SMI#
		 */
		val32 = inl(SMI_EN);
		val32 &= 0xffffdfff;	/* Turn off SMI clearing watchdog */
		outl(val32, SMI_EN);
	}

	if (!request_region(iTCO_wdt_private.tco_res->start,
			resource_size(iTCO_wdt_private.tco_res), dev->name)) {
		pr_err("I/O address 0x%04llx already in use, device disabled\n",
		       (u64)TCOBASE);
		ret = -EBUSY;
		goto unreg_smi;
	}

	pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
		ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);

	/* Clear out the (probably old) status */
	outw(0x0008, TCO1_STS);	/* Clear the Time Out Status bit */
	outw(0x0002, TCO2_STS);	/* Clear SECOND_TO_STS bit */
	outw(0x0004, TCO2_STS);	/* Clear BOOT_STS bit */

	iTCO_wdt_watchdog_dev.bootstatus = 0;
	iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
	watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
	iTCO_wdt_watchdog_dev.parent = dev->dev.parent;

	/* Make sure the watchdog is not running */
	iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);

	/* Check that the heartbeat value is within it's range;
	   if not reset to the default */
	if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
		iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
		pr_info("timeout value out of range, using %d\n",
			WATCHDOG_TIMEOUT);
	}

	ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
	if (ret != 0) {
		pr_err("cannot register watchdog device (err=%d)\n", ret);
		goto unreg_tco;
	}

	pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
		heartbeat, nowayout);

	return 0;

unreg_tco:
	release_region(iTCO_wdt_private.tco_res->start,
			resource_size(iTCO_wdt_private.tco_res));
unreg_smi:
	release_region(iTCO_wdt_private.smi_res->start,
			resource_size(iTCO_wdt_private.smi_res));
unmap_gcs:
	if (iTCO_wdt_private.iTCO_version == 2)
		iounmap(iTCO_wdt_private.gcs);
unreg_gcs:
	if (iTCO_wdt_private.iTCO_version == 2)
		release_mem_region(iTCO_wdt_private.gcs_res->start,
				resource_size(iTCO_wdt_private.gcs_res));
out:
	iTCO_wdt_private.tco_res = NULL;
	iTCO_wdt_private.smi_res = NULL;
	iTCO_wdt_private.gcs_res = NULL;
	iTCO_wdt_private.gcs = NULL;

	return ret;
}

static int __devexit iTCO_wdt_remove(struct platform_device *dev)
{
	if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
		iTCO_wdt_cleanup();

	return 0;
}

static void iTCO_wdt_shutdown(struct platform_device *dev)
{
	iTCO_wdt_stop(NULL);
}

static struct platform_driver iTCO_wdt_driver = {
	.probe          = iTCO_wdt_probe,
	.remove         = __devexit_p(iTCO_wdt_remove),
	.shutdown       = iTCO_wdt_shutdown,
	.driver         = {
		.owner  = THIS_MODULE,
		.name   = DRV_NAME,
	},
};

static int __init iTCO_wdt_init_module(void)
{
	int err;

	pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);

	err = platform_driver_register(&iTCO_wdt_driver);
	if (err)
		return err;

	return 0;
}

static void __exit iTCO_wdt_cleanup_module(void)
{
	platform_driver_unregister(&iTCO_wdt_driver);
	pr_info("Watchdog Module Unloaded\n");
}

module_init(iTCO_wdt_init_module);
module_exit(iTCO_wdt_cleanup_module);

MODULE_AUTHOR("Wim Van Sebroeck <[email protected]>");
MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
9e0ea345	1	/*
cb711a19	2	* intel TCO Watchdog Driver
9e0ea345	3	*
deb9197b	4	* (c) Copyright 2006-2011 Wim Van Sebroeck <[email protected]>.
9e0ea345 WVS	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*
	11	* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
	12	* provide warranty for any of this software. This material is
	13	* provided "AS-IS" and at no charge.
	14	*
	15	* The TCO watchdog is implemented in the following I/O controller hubs:
	16	* (See the intel documentation on http://developer.intel.com.)
cb711a19 WVS	17	* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
	18	* document number 290687-002, 298242-027: 82801BA (ICH2)
	19	* document number 290733-003, 290739-013: 82801CA (ICH3-S)
	20	* document number 290716-001, 290718-007: 82801CAM (ICH3-M)
	21	* document number 290744-001, 290745-025: 82801DB (ICH4)
	22	* document number 252337-001, 252663-008: 82801DBM (ICH4-M)
	23	* document number 273599-001, 273645-002: 82801E (C-ICH)
	24	* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
	25	* document number 300641-004, 300884-013: 6300ESB
	26	* document number 301473-002, 301474-026: 82801F (ICH6)
	27	* document number 313082-001, 313075-006: 631xESB, 632xESB
	28	* document number 307013-003, 307014-024: 82801G (ICH7)
d38bd479	29	* document number 322896-001, 322897-001: NM10
cb711a19 WVS	30	* document number 313056-003, 313057-017: 82801H (ICH8)
	31	* document number 316972-004, 316973-012: 82801I (ICH9)
	32	* document number 319973-002, 319974-002: 82801J (ICH10)
3c9d8ecc	33	* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
4946f835	34	* document number 320066-003, 320257-008: EP80597 (IICH)
203f8d89	35	* document number 324645-001, 324646-001: Cougar Point (CPT)
c54fb811	36	* document number TBD : Patsburg (PBG)
203f8d89	37	* document number TBD : DH89xxCC
aa1f4652	38	* document number TBD : Panther Point
84e83c28	39	* document number TBD : Lynx Point
9e0ea345 WVS	40	*/
	41
	42	/*
	43	* Includes, defines, variables, module parameters, ...
	44	*/
	45
27c766aa JP	46	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	47
9e0ea345	48	/* Module and version information */
7944d3a5	49	#define DRV_NAME "iTCO_wdt"
bff23431	50	#define DRV_VERSION "1.10"
9e0ea345 WVS	51
9e0ea345 WVS	52	/* Includes */
3836cc0f WVS	53	#include <linux/module.h> /* For module specific items */
	54	#include <linux/moduleparam.h> /* For new moduleparam's */
	55	#include <linux/types.h> /* For standard types (like size_t) */
	56	#include <linux/errno.h> /* For the -ENODEV/... values */
	57	#include <linux/kernel.h> /* For printk/panic/... */
0e6fa3fb AC	58	#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
0e6fa3fb AC	59	(WATCHDOG_MINOR) */
3836cc0f	60	#include <linux/watchdog.h> /* For the watchdog specific items */
3836cc0f WVS	61	#include <linux/init.h> /* For __init/__exit/... */
	62	#include <linux/fs.h> /* For file operations */
	63	#include <linux/platform_device.h> /* For platform_driver framework */
	64	#include <linux/pci.h> /* For pci functions */
	65	#include <linux/ioport.h> /* For io-port access */
	66	#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
0e6fa3fb AC	67	#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
0e6fa3fb AC	68	#include <linux/io.h> /* For inb/outb/... */
887c8ec7 AS	69	#include <linux/mfd/core.h>
887c8ec7 AS	70	#include <linux/mfd/lpc_ich.h>
3836cc0f	71
0e6fa3fb	72	#include "iTCO_vendor.h"
9e0ea345	73
9e0ea345	74	/* Address definitions for the TCO */
0e6fa3fb	75	/* TCO base address */
887c8ec7	76	#define TCOBASE (iTCO_wdt_private.tco_res->start)
0e6fa3fb	77	/* SMI Control and Enable Register */
887c8ec7	78	#define SMI_EN (iTCO_wdt_private.smi_res->start)
9e0ea345	79
0a7e6582 WVS	80	#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
	81	#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
	82	#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
	83	#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
	84	#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
	85	#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
	86	#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
	87	#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
	88	#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
9e0ea345 WVS	89
9e0ea345 WVS	90	/* internal variables */
0e6fa3fb AC	91	static struct { /* this is private data for the iTCO_wdt device */
	92	/* TCO version/generation */
	93	unsigned int iTCO_version;
887c8ec7 AS	94	struct resource *tco_res;
	95	struct resource *smi_res;
	96	struct resource *gcs_res;
0e6fa3fb AC	97	/* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
	98	unsigned long __iomem *gcs;
	99	/* the lock for io operations */
	100	spinlock_t io_lock;
887c8ec7	101	struct platform_device *dev;
0e6fa3fb AC	102	/* the PCI-device */
0e6fa3fb AC	103	struct pci_dev *pdev;
9e0ea345 WVS	104	} iTCO_wdt_private;
	105
	106	/* module parameters */
bff23431 WVS	107	#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
bff23431 WVS	108	static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
9e0ea345	109	module_param(heartbeat, int, 0);
7e6811da PB	110	MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
7e6811da PB	111	"5..76 (TCO v1) or 3..614 (TCO v2), default="
bff23431	112	__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
9e0ea345	113
86a1e189 WVS	114	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	115	module_param(nowayout, bool, 0);
0e6fa3fb AC	116	MODULE_PARM_DESC(nowayout,
	117	"Watchdog cannot be stopped once started (default="
	118	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
e033351d	119
0d098587	120	static int turn_SMI_watchdog_clear_off = 1;
deb9197b WVS	121	module_param(turn_SMI_watchdog_clear_off, int, 0);
deb9197b WVS	122	MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
0d098587	123	"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
deb9197b	124
9e0ea345 WVS	125	/*
	126	* Some TCO specific functions
	127	*/
	128
	129	static inline unsigned int seconds_to_ticks(int seconds)
	130	{
	131	/* the internal timer is stored as ticks which decrement
	132	* every 0.6 seconds */
	133	return (seconds * 10) / 6;
	134	}
	135
	136	static void iTCO_wdt_set_NO_REBOOT_bit(void)
	137	{
	138	u32 val32;
	139
	140	/* Set the NO_REBOOT bit: this disables reboots */
	141	if (iTCO_wdt_private.iTCO_version == 2) {
	142	val32 = readl(iTCO_wdt_private.gcs);
	143	val32 \|= 0x00000020;
	144	writel(val32, iTCO_wdt_private.gcs);
	145	} else if (iTCO_wdt_private.iTCO_version == 1) {
	146	pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
	147	val32 \|= 0x00000002;
	148	pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
	149	}
	150	}
	151
	152	static int iTCO_wdt_unset_NO_REBOOT_bit(void)
	153	{
	154	int ret = 0;
	155	u32 val32;
	156
	157	/* Unset the NO_REBOOT bit: this enables reboots */
	158	if (iTCO_wdt_private.iTCO_version == 2) {
	159	val32 = readl(iTCO_wdt_private.gcs);
	160	val32 &= 0xffffffdf;
	161	writel(val32, iTCO_wdt_private.gcs);
	162
	163	val32 = readl(iTCO_wdt_private.gcs);
	164	if (val32 & 0x00000020)
	165	ret = -EIO;
	166	} else if (iTCO_wdt_private.iTCO_version == 1) {
	167	pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
	168	val32 &= 0xfffffffd;
	169	pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
	170
	171	pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
	172	if (val32 & 0x00000002)
	173	ret = -EIO;
	174	}
	175
	176	return ret; /* returns: 0 = OK, -EIO = Error */
	177	}
	178
bff23431	179	static int iTCO_wdt_start(struct watchdog_device *wd_dev)
9e0ea345 WVS	180	{
	181	unsigned int val;
	182
	183	spin_lock(&iTCO_wdt_private.io_lock);
	184
bff23431	185	iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
e033351d	186
9e0ea345 WVS	187	/* disable chipset's NO_REBOOT bit */
9e0ea345 WVS	188	if (iTCO_wdt_unset_NO_REBOOT_bit()) {
2ba7d7b3	189	spin_unlock(&iTCO_wdt_private.io_lock);
27c766aa	190	pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
9e0ea345 WVS	191	return -EIO;
	192	}
	193
7cd5b08b WVS	194	/* Force the timer to its reload value by writing to the TCO_RLD
	195	register */
	196	if (iTCO_wdt_private.iTCO_version == 2)
	197	outw(0x01, TCO_RLD);
	198	else if (iTCO_wdt_private.iTCO_version == 1)
	199	outb(0x01, TCO_RLD);
	200
9e0ea345 WVS	201	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
	202	val = inw(TCO1_CNT);
	203	val &= 0xf7ff;
	204	outw(val, TCO1_CNT);
	205	val = inw(TCO1_CNT);
	206	spin_unlock(&iTCO_wdt_private.io_lock);
	207
	208	if (val & 0x0800)
	209	return -1;
	210	return 0;
	211	}
	212
bff23431	213	static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
9e0ea345 WVS	214	{
	215	unsigned int val;
	216
	217	spin_lock(&iTCO_wdt_private.io_lock);
	218
887c8ec7	219	iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
e033351d	220
9e0ea345 WVS	221	/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
	222	val = inw(TCO1_CNT);
	223	val \|= 0x0800;
	224	outw(val, TCO1_CNT);
	225	val = inw(TCO1_CNT);
	226
	227	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	228	iTCO_wdt_set_NO_REBOOT_bit();
	229
	230	spin_unlock(&iTCO_wdt_private.io_lock);
	231
	232	if ((val & 0x0800) == 0)
	233	return -1;
	234	return 0;
	235	}
	236
bff23431	237	static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
9e0ea345 WVS	238	{
	239	spin_lock(&iTCO_wdt_private.io_lock);
	240
bff23431	241	iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
e033351d	242
9e0ea345	243	/* Reload the timer by writing to the TCO Timer Counter register */
0e6fa3fb	244	if (iTCO_wdt_private.iTCO_version == 2)
9e0ea345	245	outw(0x01, TCO_RLD);
7e6811da PB	246	else if (iTCO_wdt_private.iTCO_version == 1) {
	247	/* Reset the timeout status bit so that the timer
	248	* needs to count down twice again before rebooting */
	249	outw(0x0008, TCO1_STS); /* write 1 to clear bit */
	250
9e0ea345	251	outb(0x01, TCO_RLD);
7e6811da	252	}
9e0ea345 WVS	253
	254	spin_unlock(&iTCO_wdt_private.io_lock);
	255	return 0;
	256	}
	257
bff23431	258	static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
9e0ea345 WVS	259	{
	260	unsigned int val16;
	261	unsigned char val8;
	262	unsigned int tmrval;
	263
	264	tmrval = seconds_to_ticks(t);
7e6811da PB	265
	266	/* For TCO v1 the timer counts down twice before rebooting */
	267	if (iTCO_wdt_private.iTCO_version == 1)
	268	tmrval /= 2;
	269
9e0ea345 WVS	270	/* from the specs: */
	271	/* "Values of 0h-3h are ignored and should not be attempted" */
	272	if (tmrval < 0x04)
	273	return -EINVAL;
	274	if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) \|\|
	275	((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
	276	return -EINVAL;
	277
e033351d WVS	278	iTCO_vendor_pre_set_heartbeat(tmrval);
e033351d WVS	279
9e0ea345 WVS	280	/* Write new heartbeat to watchdog */
	281	if (iTCO_wdt_private.iTCO_version == 2) {
	282	spin_lock(&iTCO_wdt_private.io_lock);
	283	val16 = inw(TCOv2_TMR);
	284	val16 &= 0xfc00;
	285	val16 \|= tmrval;
	286	outw(val16, TCOv2_TMR);
	287	val16 = inw(TCOv2_TMR);
	288	spin_unlock(&iTCO_wdt_private.io_lock);
	289
	290	if ((val16 & 0x3ff) != tmrval)
	291	return -EINVAL;
	292	} else if (iTCO_wdt_private.iTCO_version == 1) {
	293	spin_lock(&iTCO_wdt_private.io_lock);
	294	val8 = inb(TCOv1_TMR);
	295	val8 &= 0xc0;
	296	val8 \|= (tmrval & 0xff);
	297	outb(val8, TCOv1_TMR);
	298	val8 = inb(TCOv1_TMR);
	299	spin_unlock(&iTCO_wdt_private.io_lock);
	300
	301	if ((val8 & 0x3f) != tmrval)
	302	return -EINVAL;
	303	}
	304
bff23431	305	wd_dev->timeout = t;
9e0ea345 WVS	306	return 0;
	307	}
	308
bff23431	309	static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
9e0ea345 WVS	310	{
	311	unsigned int val16;
	312	unsigned char val8;
bff23431	313	unsigned int time_left = 0;
9e0ea345 WVS	314
	315	/* read the TCO Timer */
	316	if (iTCO_wdt_private.iTCO_version == 2) {
	317	spin_lock(&iTCO_wdt_private.io_lock);
	318	val16 = inw(TCO_RLD);
	319	val16 &= 0x3ff;
	320	spin_unlock(&iTCO_wdt_private.io_lock);
	321
bff23431	322	time_left = (val16 * 6) / 10;
9e0ea345 WVS	323	} else if (iTCO_wdt_private.iTCO_version == 1) {
	324	spin_lock(&iTCO_wdt_private.io_lock);
	325	val8 = inb(TCO_RLD);
	326	val8 &= 0x3f;
7e6811da PB	327	if (!(inw(TCO1_STS) & 0x0008))
7e6811da PB	328	val8 += (inb(TCOv1_TMR) & 0x3f);
9e0ea345 WVS	329	spin_unlock(&iTCO_wdt_private.io_lock);
9e0ea345 WVS	330
bff23431	331	time_left = (val8 * 6) / 10;
9e0ea345	332	}
bff23431	333	return time_left;
9e0ea345 WVS	334	}
9e0ea345 WVS	335
9e0ea345 WVS	336	/*
	337	* Kernel Interfaces
	338	*/
	339
bff23431 WVS	340	static const struct watchdog_info ident = {
	341	.options = WDIOF_SETTIMEOUT \|
	342	WDIOF_KEEPALIVEPING \|
	343	WDIOF_MAGICCLOSE,
	344	.firmware_version = 0,
	345	.identity = DRV_NAME,
	346	};
	347
	348	static const struct watchdog_ops iTCO_wdt_ops = {
0e6fa3fb	349	.owner = THIS_MODULE,
bff23431 WVS	350	.start = iTCO_wdt_start,
	351	.stop = iTCO_wdt_stop,
	352	.ping = iTCO_wdt_ping,
	353	.set_timeout = iTCO_wdt_set_timeout,
	354	.get_timeleft = iTCO_wdt_get_timeleft,
9e0ea345 WVS	355	};
9e0ea345 WVS	356
bff23431 WVS	357	static struct watchdog_device iTCO_wdt_watchdog_dev = {
	358	.info = &ident,
	359	.ops = &iTCO_wdt_ops,
9e0ea345 WVS	360	};
9e0ea345 WVS	361
9e0ea345 WVS	362	/*
	363	* Init & exit routines
	364	*/
	365
887c8ec7 AS	366	static void __devexit iTCO_wdt_cleanup(void)
	367	{
	368	/* Stop the timer before we leave */
	369	if (!nowayout)
bff23431	370	iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
887c8ec7 AS	371
887c8ec7 AS	372	/* Deregister */
bff23431	373	watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
887c8ec7 AS	374
	375	/* release resources */
	376	release_region(iTCO_wdt_private.tco_res->start,
	377	resource_size(iTCO_wdt_private.tco_res));
	378	release_region(iTCO_wdt_private.smi_res->start,
	379	resource_size(iTCO_wdt_private.smi_res));
	380	if (iTCO_wdt_private.iTCO_version == 2) {
	381	iounmap(iTCO_wdt_private.gcs);
	382	release_mem_region(iTCO_wdt_private.gcs_res->start,
	383	resource_size(iTCO_wdt_private.gcs_res));
	384	}
	385
	386	iTCO_wdt_private.tco_res = NULL;
	387	iTCO_wdt_private.smi_res = NULL;
	388	iTCO_wdt_private.gcs_res = NULL;
	389	iTCO_wdt_private.gcs = NULL;
	390	}
	391
	392	static int __devinit iTCO_wdt_probe(struct platform_device *dev)
9e0ea345	393	{
887c8ec7	394	int ret = -ENODEV;
12d60e28	395	unsigned long val32;
887c8ec7 AS	396	struct lpc_ich_info *ich_info = dev->dev.platform_data;
	397
	398	if (!ich_info)
	399	goto out;
	400
	401	spin_lock_init(&iTCO_wdt_private.io_lock);
	402
	403	iTCO_wdt_private.tco_res =
	404	platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
	405	if (!iTCO_wdt_private.tco_res)
	406	goto out;
	407
	408	iTCO_wdt_private.smi_res =
	409	platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
	410	if (!iTCO_wdt_private.smi_res)
	411	goto out;
	412
	413	iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
	414	iTCO_wdt_private.dev = dev;
	415	iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
9e0ea345 WVS	416
9e0ea345 WVS	417	/*
887c8ec7 AS	418	* Get the Memory-Mapped GCS register, we need it for the
887c8ec7 AS	419	* NO_REBOOT flag (TCO v2).
9e0ea345	420	*/
9e0ea345	421	if (iTCO_wdt_private.iTCO_version == 2) {
887c8ec7 AS	422	iTCO_wdt_private.gcs_res = platform_get_resource(dev,
	423	IORESOURCE_MEM,
	424	ICH_RES_MEM_GCS);
	425
	426	if (!iTCO_wdt_private.gcs_res)
	427	goto out;
	428
	429	if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
	430	resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
	431	ret = -EBUSY;
de8cd9a3 DL	432	goto out;
de8cd9a3 DL	433	}
887c8ec7 AS	434	iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
	435	resource_size(iTCO_wdt_private.gcs_res));
	436	if (!iTCO_wdt_private.gcs) {
	437	ret = -EIO;
	438	goto unreg_gcs;
	439	}
9e0ea345 WVS	440	}
	441
	442	/* Check chipset's NO_REBOOT bit */
e033351d	443	if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
27c766aa	444	pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
9e0ea345	445	ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
887c8ec7	446	goto unmap_gcs;
9e0ea345 WVS	447	}
	448
	449	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
	450	iTCO_wdt_set_NO_REBOOT_bit();
	451
7cd5b08b	452	/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
887c8ec7 AS	453	if (!request_region(iTCO_wdt_private.smi_res->start,
	454	resource_size(iTCO_wdt_private.smi_res), dev->name)) {
	455	pr_err("I/O address 0x%04llx already in use, device disabled\n",
4b98b32a	456	(u64)SMI_EN);
887c8ec7 AS	457	ret = -EBUSY;
887c8ec7 AS	458	goto unmap_gcs;
9e0ea345	459	}
0d098587	460	if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
887c8ec7 AS	461	/*
	462	* Bit 13: TCO_EN -> 0
	463	* Disables TCO logic generating an SMI#
	464	*/
deb9197b WVS	465	val32 = inl(SMI_EN);
	466	val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
	467	outl(val32, SMI_EN);
	468	}
9e0ea345	469
887c8ec7 AS	470	if (!request_region(iTCO_wdt_private.tco_res->start,
	471	resource_size(iTCO_wdt_private.tco_res), dev->name)) {
	472	pr_err("I/O address 0x%04llx already in use, device disabled\n",
4b98b32a	473	(u64)TCOBASE);
887c8ec7 AS	474	ret = -EBUSY;
887c8ec7 AS	475	goto unreg_smi;
9e0ea345 WVS	476	}
9e0ea345 WVS	477
887c8ec7	478	pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
4b98b32a	479	ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);
9e0ea345 WVS	480
9e0ea345 WVS	481	/* Clear out the (probably old) status */
7e6811da PB	482	outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
	483	outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
	484	outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
9e0ea345	485
bff23431 WVS	486	iTCO_wdt_watchdog_dev.bootstatus = 0;
	487	iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
	488	watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
	489	iTCO_wdt_watchdog_dev.parent = dev->dev.parent;
	490
9e0ea345	491	/* Make sure the watchdog is not running */
bff23431	492	iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
9e0ea345	493
0e6fa3fb AC	494	/* Check that the heartbeat value is within it's range;
0e6fa3fb AC	495	if not reset to the default */
bff23431 WVS	496	if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
	497	iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
	498	pr_info("timeout value out of range, using %d\n",
	499	WATCHDOG_TIMEOUT);
9e0ea345 WVS	500	}
9e0ea345 WVS	501
bff23431	502	ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
9e0ea345	503	if (ret != 0) {
bff23431	504	pr_err("cannot register watchdog device (err=%d)\n", ret);
887c8ec7	505	goto unreg_tco;
9e0ea345 WVS	506	}
9e0ea345 WVS	507
27c766aa JP	508	pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
27c766aa JP	509	heartbeat, nowayout);
9e0ea345 WVS	510
	511	return 0;
	512
887c8ec7 AS	513	unreg_tco:
	514	release_region(iTCO_wdt_private.tco_res->start,
	515	resource_size(iTCO_wdt_private.tco_res));
	516	unreg_smi:
	517	release_region(iTCO_wdt_private.smi_res->start,
	518	resource_size(iTCO_wdt_private.smi_res));
	519	unmap_gcs:
9e0ea345 WVS	520	if (iTCO_wdt_private.iTCO_version == 2)
9e0ea345 WVS	521	iounmap(iTCO_wdt_private.gcs);
887c8ec7	522	unreg_gcs:
9e0ea345	523	if (iTCO_wdt_private.iTCO_version == 2)
887c8ec7 AS	524	release_mem_region(iTCO_wdt_private.gcs_res->start,
	525	resource_size(iTCO_wdt_private.gcs_res));
	526	out:
	527	iTCO_wdt_private.tco_res = NULL;
	528	iTCO_wdt_private.smi_res = NULL;
	529	iTCO_wdt_private.gcs_res = NULL;
	530	iTCO_wdt_private.gcs = NULL;
9e0ea345	531
ec26985b	532	return ret;
9e0ea345 WVS	533	}
9e0ea345 WVS	534
08113e39	535	static int __devexit iTCO_wdt_remove(struct platform_device *dev)
9e0ea345	536	{
887c8ec7	537	if (iTCO_wdt_private.tco_res \|\| iTCO_wdt_private.smi_res)
9e0ea345 WVS	538	iTCO_wdt_cleanup();
9e0ea345 WVS	539
3836cc0f WVS	540	return 0;
	541	}
	542
	543	static void iTCO_wdt_shutdown(struct platform_device *dev)
	544	{
bff23431	545	iTCO_wdt_stop(NULL);
3836cc0f WVS	546	}
3836cc0f WVS	547
3836cc0f WVS	548	static struct platform_driver iTCO_wdt_driver = {
3836cc0f WVS	549	.probe = iTCO_wdt_probe,
08113e39	550	.remove = __devexit_p(iTCO_wdt_remove),
3836cc0f	551	.shutdown = iTCO_wdt_shutdown,
3836cc0f WVS	552	.driver = {
	553	.owner = THIS_MODULE,
	554	.name = DRV_NAME,
	555	},
	556	};
	557
	558	static int __init iTCO_wdt_init_module(void)
	559	{
	560	int err;
	561
27c766aa	562	pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
3836cc0f WVS	563
	564	err = platform_driver_register(&iTCO_wdt_driver);
	565	if (err)
	566	return err;
	567
3836cc0f	568	return 0;
3836cc0f WVS	569	}
	570
	571	static void __exit iTCO_wdt_cleanup_module(void)
	572	{
3836cc0f	573	platform_driver_unregister(&iTCO_wdt_driver);
27c766aa	574	pr_info("Watchdog Module Unloaded\n");
9e0ea345 WVS	575	}
	576
	577	module_init(iTCO_wdt_init_module);
	578	module_exit(iTCO_wdt_cleanup_module);
	579
	580	MODULE_AUTHOR("Wim Van Sebroeck <[email protected]>");
	581	MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
3836cc0f	582	MODULE_VERSION(DRV_VERSION);
9e0ea345 WVS	583	MODULE_LICENSE("GPL");
9e0ea345 WVS	584	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
e5de32e3	585	MODULE_ALIAS("platform:" DRV_NAME);