[linux.git] / drivers / spi / spi-s3c24xx.c

/*
 * Copyright (c) 2006 Ben Dooks
 * Copyright 2006-2009 Simtec Electronics
 *	Ben Dooks <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/slab.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/spi/s3c24xx.h>
#include <linux/module.h>

#include <plat/regs-spi.h>

#include <plat/fiq.h>
#include <asm/fiq.h>

#include "spi-s3c24xx-fiq.h"

/**
 * s3c24xx_spi_devstate - per device data
 * @hz: Last frequency calculated for @sppre field.
 * @mode: Last mode setting for the @spcon field.
 * @spcon: Value to write to the SPCON register.
 * @sppre: Value to write to the SPPRE register.
 */
struct s3c24xx_spi_devstate {
	unsigned int	hz;
	unsigned int	mode;
	u8		spcon;
	u8		sppre;
};

enum spi_fiq_mode {
	FIQ_MODE_NONE	= 0,
	FIQ_MODE_TX	= 1,
	FIQ_MODE_RX	= 2,
	FIQ_MODE_TXRX	= 3,
};

struct s3c24xx_spi {
	/* bitbang has to be first */
	struct spi_bitbang	 bitbang;
	struct completion	 done;

	void __iomem		*regs;
	int			 irq;
	int			 len;
	int			 count;

	struct fiq_handler	 fiq_handler;
	enum spi_fiq_mode	 fiq_mode;
	unsigned char		 fiq_inuse;
	unsigned char		 fiq_claimed;

	void			(*set_cs)(struct s3c2410_spi_info *spi,
					  int cs, int pol);

	/* data buffers */
	const unsigned char	*tx;
	unsigned char		*rx;

	struct clk		*clk;
	struct resource		*ioarea;
	struct spi_master	*master;
	struct spi_device	*curdev;
	struct device		*dev;
	struct s3c2410_spi_info *pdata;
};


#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)

static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
{
	return spi_master_get_devdata(sdev->master);
}

static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
{
	gpio_set_value(spi->pin_cs, pol);
}

static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
{
	struct s3c24xx_spi_devstate *cs = spi->controller_state;
	struct s3c24xx_spi *hw = to_hw(spi);
	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;

	/* change the chipselect state and the state of the spi engine clock */

	switch (value) {
	case BITBANG_CS_INACTIVE:
		hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
		writeb(cs->spcon, hw->regs + S3C2410_SPCON);
		break;

	case BITBANG_CS_ACTIVE:
		writeb(cs->spcon | S3C2410_SPCON_ENSCK,
		       hw->regs + S3C2410_SPCON);
		hw->set_cs(hw->pdata, spi->chip_select, cspol);
		break;
	}
}

static int s3c24xx_spi_update_state(struct spi_device *spi,
				    struct spi_transfer *t)
{
	struct s3c24xx_spi *hw = to_hw(spi);
	struct s3c24xx_spi_devstate *cs = spi->controller_state;
	unsigned int bpw;
	unsigned int hz;
	unsigned int div;
	unsigned long clk;

	bpw = t ? t->bits_per_word : spi->bits_per_word;
	hz  = t ? t->speed_hz : spi->max_speed_hz;

	if (!bpw)
		bpw = 8;

	if (!hz)
		hz = spi->max_speed_hz;

	if (bpw != 8) {
		dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
		return -EINVAL;
	}

	if (spi->mode != cs->mode) {
		u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;

		if (spi->mode & SPI_CPHA)
			spcon |= S3C2410_SPCON_CPHA_FMTB;

		if (spi->mode & SPI_CPOL)
			spcon |= S3C2410_SPCON_CPOL_HIGH;

		cs->mode = spi->mode;
		cs->spcon = spcon;
	}

	if (cs->hz != hz) {
		clk = clk_get_rate(hw->clk);
		div = DIV_ROUND_UP(clk, hz * 2) - 1;

		if (div > 255)
			div = 255;

		dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
			div, hz, clk / (2 * (div + 1)));

		cs->hz = hz;
		cs->sppre = div;
	}

	return 0;
}

static int s3c24xx_spi_setupxfer(struct spi_device *spi,
				 struct spi_transfer *t)
{
	struct s3c24xx_spi_devstate *cs = spi->controller_state;
	struct s3c24xx_spi *hw = to_hw(spi);
	int ret;

	ret = s3c24xx_spi_update_state(spi, t);
	if (!ret)
		writeb(cs->sppre, hw->regs + S3C2410_SPPRE);

	return ret;
}

static int s3c24xx_spi_setup(struct spi_device *spi)
{
	struct s3c24xx_spi_devstate *cs = spi->controller_state;
	struct s3c24xx_spi *hw = to_hw(spi);
	int ret;

	/* allocate settings on the first call */
	if (!cs) {
		cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
		if (!cs) {
			dev_err(&spi->dev, "no memory for controller state\n");
			return -ENOMEM;
		}

		cs->spcon = SPCON_DEFAULT;
		cs->hz = -1;
		spi->controller_state = cs;
	}

	/* initialise the state from the device */
	ret = s3c24xx_spi_update_state(spi, NULL);
	if (ret)
		return ret;

	spin_lock(&hw->bitbang.lock);
	if (!hw->bitbang.busy) {
		hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
		/* need to ndelay for 0.5 clocktick ? */
	}
	spin_unlock(&hw->bitbang.lock);

	return 0;
}

static void s3c24xx_spi_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
{
	return hw->tx ? hw->tx[count] : 0;
}

#ifdef CONFIG_SPI_S3C24XX_FIQ
/* Support for FIQ based pseudo-DMA to improve the transfer speed.
 *
 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
 * used by the FIQ core to move data between main memory and the peripheral
 * block. Since this is code running on the processor, there is no problem
 * with cache coherency of the buffers, so we can use any buffer we like.
 */

/**
 * struct spi_fiq_code - FIQ code and header
 * @length: The length of the code fragment, excluding this header.
 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
 * @data: The code itself to install as a FIQ handler.
 */
struct spi_fiq_code {
	u32	length;
	u32	ack_offset;
	u8	data[0];
};

extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
extern struct spi_fiq_code s3c24xx_spi_fiq_rx;

/**
 * ack_bit - turn IRQ into IRQ acknowledgement bit
 * @irq: The interrupt number
 *
 * Returns the bit to write to the interrupt acknowledge register.
 */
static inline u32 ack_bit(unsigned int irq)
{
	return 1 << (irq - IRQ_EINT0);
}

/**
 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
 * @hw: The hardware state.
 *
 * Claim the FIQ handler (only one can be active at any one time) and
 * then setup the correct transfer code for this transfer.
 *
 * This call updates all the necessary state information if successful,
 * so the caller does not need to do anything more than start the transfer
 * as normal, since the IRQ will have been re-routed to the FIQ handler.
*/
void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
{
	struct pt_regs regs;
	enum spi_fiq_mode mode;
	struct spi_fiq_code *code;
	int ret;

	if (!hw->fiq_claimed) {
		/* try and claim fiq if we haven't got it, and if not
		 * then return and simply use another transfer method */

		ret = claim_fiq(&hw->fiq_handler);
		if (ret)
			return;
	}

	if (hw->tx && !hw->rx)
		mode = FIQ_MODE_TX;
	else if (hw->rx && !hw->tx)
		mode = FIQ_MODE_RX;
	else
		mode = FIQ_MODE_TXRX;

	regs.uregs[fiq_rspi] = (long)hw->regs;
	regs.uregs[fiq_rrx]  = (long)hw->rx;
	regs.uregs[fiq_rtx]  = (long)hw->tx + 1;
	regs.uregs[fiq_rcount] = hw->len - 1;
	regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;

	set_fiq_regs(&regs);

	if (hw->fiq_mode != mode) {
		u32 *ack_ptr;

		hw->fiq_mode = mode;

		switch (mode) {
		case FIQ_MODE_TX:
			code = &s3c24xx_spi_fiq_tx;
			break;
		case FIQ_MODE_RX:
			code = &s3c24xx_spi_fiq_rx;
			break;
		case FIQ_MODE_TXRX:
			code = &s3c24xx_spi_fiq_txrx;
			break;
		default:
			code = NULL;
		}

		BUG_ON(!code);

		ack_ptr = (u32 *)&code->data[code->ack_offset];
		*ack_ptr = ack_bit(hw->irq);

		set_fiq_handler(&code->data, code->length);
	}

	s3c24xx_set_fiq(hw->irq, true);

	hw->fiq_mode = mode;
	hw->fiq_inuse = 1;
}

/**
 * s3c24xx_spi_fiqop - FIQ core code callback
 * @pw: Data registered with the handler
 * @release: Whether this is a release or a return.
 *
 * Called by the FIQ code when another module wants to use the FIQ, so
 * return whether we are currently using this or not and then update our
 * internal state.
 */
static int s3c24xx_spi_fiqop(void *pw, int release)
{
	struct s3c24xx_spi *hw = pw;
	int ret = 0;

	if (release) {
		if (hw->fiq_inuse)
			ret = -EBUSY;

		/* note, we do not need to unroute the FIQ, as the FIQ
		 * vector code de-routes it to signal the end of transfer */

		hw->fiq_mode = FIQ_MODE_NONE;
		hw->fiq_claimed = 0;
	} else {
		hw->fiq_claimed = 1;
	}

	return ret;
}

/**
 * s3c24xx_spi_initfiq - setup the information for the FIQ core
 * @hw: The hardware state.
 *
 * Setup the fiq_handler block to pass to the FIQ core.
 */
static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
{
	hw->fiq_handler.dev_id = hw;
	hw->fiq_handler.name = dev_name(hw->dev);
	hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
}

/**
 * s3c24xx_spi_usefiq - return if we should be using FIQ.
 * @hw: The hardware state.
 *
 * Return true if the platform data specifies whether this channel is
 * allowed to use the FIQ.
 */
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
{
	return hw->pdata->use_fiq;
}

/**
 * s3c24xx_spi_usingfiq - return if channel is using FIQ
 * @spi: The hardware state.
 *
 * Return whether the channel is currently using the FIQ (separate from
 * whether the FIQ is claimed).
 */
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
{
	return spi->fiq_inuse;
}
#else

static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }

#endif /* CONFIG_SPI_S3C24XX_FIQ */

static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	struct s3c24xx_spi *hw = to_hw(spi);

	hw->tx = t->tx_buf;
	hw->rx = t->rx_buf;
	hw->len = t->len;
	hw->count = 0;

	init_completion(&hw->done);

	hw->fiq_inuse = 0;
	if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
		s3c24xx_spi_tryfiq(hw);

	/* send the first byte */
	writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);

	wait_for_completion(&hw->done);
	return hw->count;
}

static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
{
	struct s3c24xx_spi *hw = dev;
	unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
	unsigned int count = hw->count;

	if (spsta & S3C2410_SPSTA_DCOL) {
		dev_dbg(hw->dev, "data-collision\n");
		complete(&hw->done);
		goto irq_done;
	}

	if (!(spsta & S3C2410_SPSTA_READY)) {
		dev_dbg(hw->dev, "spi not ready for tx?\n");
		complete(&hw->done);
		goto irq_done;
	}

	if (!s3c24xx_spi_usingfiq(hw)) {
		hw->count++;

		if (hw->rx)
			hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);

		count++;

		if (count < hw->len)
			writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
		else
			complete(&hw->done);
	} else {
		hw->count = hw->len;
		hw->fiq_inuse = 0;

		if (hw->rx)
			hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);

		complete(&hw->done);
	}

 irq_done:
	return IRQ_HANDLED;
}

static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
{
	/* for the moment, permanently enable the clock */

	clk_enable(hw->clk);

	/* program defaults into the registers */

	writeb(0xff, hw->regs + S3C2410_SPPRE);
	writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
	writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);

	if (hw->pdata) {
		if (hw->set_cs == s3c24xx_spi_gpiocs)
			gpio_direction_output(hw->pdata->pin_cs, 1);

		if (hw->pdata->gpio_setup)
			hw->pdata->gpio_setup(hw->pdata, 1);
	}
}

static int __devinit s3c24xx_spi_probe(struct platform_device *pdev)
{
	struct s3c2410_spi_info *pdata;
	struct s3c24xx_spi *hw;
	struct spi_master *master;
	struct resource *res;
	int err = 0;

	master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
	if (master == NULL) {
		dev_err(&pdev->dev, "No memory for spi_master\n");
		err = -ENOMEM;
		goto err_nomem;
	}

	hw = spi_master_get_devdata(master);
	memset(hw, 0, sizeof(struct s3c24xx_spi));

	hw->master = spi_master_get(master);
	hw->pdata = pdata = pdev->dev.platform_data;
	hw->dev = &pdev->dev;

	if (pdata == NULL) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		err = -ENOENT;
		goto err_no_pdata;
	}

	platform_set_drvdata(pdev, hw);
	init_completion(&hw->done);

	/* initialise fiq handler */

	s3c24xx_spi_initfiq(hw);

	/* setup the master state. */

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;

	master->num_chipselect = hw->pdata->num_cs;
	master->bus_num = pdata->bus_num;

	/* setup the state for the bitbang driver */

	hw->bitbang.master         = hw->master;
	hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
	hw->bitbang.chipselect     = s3c24xx_spi_chipsel;
	hw->bitbang.txrx_bufs      = s3c24xx_spi_txrx;

	hw->master->setup  = s3c24xx_spi_setup;
	hw->master->cleanup = s3c24xx_spi_cleanup;

	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);

	/* find and map our resources */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
		err = -ENOENT;
		goto err_no_iores;
	}

	hw->ioarea = request_mem_region(res->start, resource_size(res),
					pdev->name);

	if (hw->ioarea == NULL) {
		dev_err(&pdev->dev, "Cannot reserve region\n");
		err = -ENXIO;
		goto err_no_iores;
	}

	hw->regs = ioremap(res->start, resource_size(res));
	if (hw->regs == NULL) {
		dev_err(&pdev->dev, "Cannot map IO\n");
		err = -ENXIO;
		goto err_no_iomap;
	}

	hw->irq = platform_get_irq(pdev, 0);
	if (hw->irq < 0) {
		dev_err(&pdev->dev, "No IRQ specified\n");
		err = -ENOENT;
		goto err_no_irq;
	}

	err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
	if (err) {
		dev_err(&pdev->dev, "Cannot claim IRQ\n");
		goto err_no_irq;
	}

	hw->clk = clk_get(&pdev->dev, "spi");
	if (IS_ERR(hw->clk)) {
		dev_err(&pdev->dev, "No clock for device\n");
		err = PTR_ERR(hw->clk);
		goto err_no_clk;
	}

	/* setup any gpio we can */

	if (!pdata->set_cs) {
		if (pdata->pin_cs < 0) {
			dev_err(&pdev->dev, "No chipselect pin\n");
			goto err_register;
		}

		err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
		if (err) {
			dev_err(&pdev->dev, "Failed to get gpio for cs\n");
			goto err_register;
		}

		hw->set_cs = s3c24xx_spi_gpiocs;
		gpio_direction_output(pdata->pin_cs, 1);
	} else
		hw->set_cs = pdata->set_cs;

	s3c24xx_spi_initialsetup(hw);

	/* register our spi controller */

	err = spi_bitbang_start(&hw->bitbang);
	if (err) {
		dev_err(&pdev->dev, "Failed to register SPI master\n");
		goto err_register;
	}

	return 0;

 err_register:
	if (hw->set_cs == s3c24xx_spi_gpiocs)
		gpio_free(pdata->pin_cs);

	clk_disable(hw->clk);
	clk_put(hw->clk);

 err_no_clk:
	free_irq(hw->irq, hw);

 err_no_irq:
	iounmap(hw->regs);

 err_no_iomap:
	release_resource(hw->ioarea);
	kfree(hw->ioarea);

 err_no_iores:
 err_no_pdata:
	spi_master_put(hw->master);

 err_nomem:
	return err;
}

static int __devexit s3c24xx_spi_remove(struct platform_device *dev)
{
	struct s3c24xx_spi *hw = platform_get_drvdata(dev);

	platform_set_drvdata(dev, NULL);

	spi_bitbang_stop(&hw->bitbang);

	clk_disable(hw->clk);
	clk_put(hw->clk);

	free_irq(hw->irq, hw);
	iounmap(hw->regs);

	if (hw->set_cs == s3c24xx_spi_gpiocs)
		gpio_free(hw->pdata->pin_cs);

	release_resource(hw->ioarea);
	kfree(hw->ioarea);

	spi_master_put(hw->master);
	return 0;
}


#ifdef CONFIG_PM

static int s3c24xx_spi_suspend(struct device *dev)
{
	struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));

	if (hw->pdata && hw->pdata->gpio_setup)
		hw->pdata->gpio_setup(hw->pdata, 0);

	clk_disable(hw->clk);
	return 0;
}

static int s3c24xx_spi_resume(struct device *dev)
{
	struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));

	s3c24xx_spi_initialsetup(hw);
	return 0;
}

static const struct dev_pm_ops s3c24xx_spi_pmops = {
	.suspend	= s3c24xx_spi_suspend,
	.resume		= s3c24xx_spi_resume,
};

#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
#else
#define S3C24XX_SPI_PMOPS NULL
#endif /* CONFIG_PM */

MODULE_ALIAS("platform:s3c2410-spi");
static struct platform_driver s3c24xx_spi_driver = {
	.probe		= s3c24xx_spi_probe,
	.remove		= __devexit_p(s3c24xx_spi_remove),
	.driver		= {
		.name	= "s3c2410-spi",
		.owner	= THIS_MODULE,
		.pm	= S3C24XX_SPI_PMOPS,
	},
};
module_platform_driver(s3c24xx_spi_driver);

MODULE_DESCRIPTION("S3C24XX SPI Driver");
MODULE_AUTHOR("Ben Dooks, <[email protected]>");
MODULE_LICENSE("GPL");
Commit	Line	Data
ca632f55	1	/*
7fba5340	2	* Copyright (c) 2006 Ben Dooks
bec0806c	3	* Copyright 2006-2009 Simtec Electronics
7fba5340 BD	4	* Ben Dooks <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
7fba5340 BD	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/workqueue.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/delay.h>
	17	#include <linux/errno.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
	20	#include <linux/platform_device.h>
ee9c1fbf	21	#include <linux/gpio.h>
1a0c220f	22	#include <linux/io.h>
5a0e3ad6	23	#include <linux/slab.h>
7fba5340 BD	24
	25	#include <linux/spi/spi.h>
	26	#include <linux/spi/spi_bitbang.h>
f35ef7ca	27	#include <linux/spi/s3c24xx.h>
d7614de4	28	#include <linux/module.h>
7fba5340	29
13622708	30	#include <plat/regs-spi.h>
7fba5340	31
bec0806c BD	32	#include <plat/fiq.h>
	33	#include <asm/fiq.h>
	34
ca632f55	35	#include "spi-s3c24xx-fiq.h"
bec0806c	36
570327d9 BD	37	/**
	38	* s3c24xx_spi_devstate - per device data
	39	* @hz: Last frequency calculated for @sppre field.
	40	* @mode: Last mode setting for the @spcon field.
	41	* @spcon: Value to write to the SPCON register.
	42	* @sppre: Value to write to the SPPRE register.
	43	*/
	44	struct s3c24xx_spi_devstate {
	45	unsigned int hz;
	46	unsigned int mode;
	47	u8 spcon;
	48	u8 sppre;
	49	};
	50
bec0806c BD	51	enum spi_fiq_mode {
	52	FIQ_MODE_NONE = 0,
	53	FIQ_MODE_TX = 1,
	54	FIQ_MODE_RX = 2,
	55	FIQ_MODE_TXRX = 3,
	56	};
	57
7fba5340 BD	58	struct s3c24xx_spi {
	59	/* bitbang has to be first */
	60	struct spi_bitbang bitbang;
	61	struct completion done;
	62
	63	void __iomem *regs;
	64	int irq;
	65	int len;
	66	int count;
	67
bec0806c BD	68	struct fiq_handler fiq_handler;
	69	enum spi_fiq_mode fiq_mode;
	70	unsigned char fiq_inuse;
	71	unsigned char fiq_claimed;
	72
6c912a3d	73	void (set_cs)(struct s3c2410_spi_info spi,
8736b927 BD	74	int cs, int pol);
8736b927 BD	75
7fba5340 BD	76	/* data buffers */
	77	const unsigned char *tx;
	78	unsigned char *rx;
	79
	80	struct clk *clk;
	81	struct resource *ioarea;
	82	struct spi_master *master;
	83	struct spi_device *curdev;
	84	struct device *dev;
	85	struct s3c2410_spi_info *pdata;
	86	};
	87
bec0806c	88
7fba5340 BD	89	#define SPCON_DEFAULT (S3C2410_SPCON_MSTR \| S3C2410_SPCON_SMOD_INT)
	90	#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
	91
	92	static inline struct s3c24xx_spi to_hw(struct spi_device sdev)
	93	{
	94	return spi_master_get_devdata(sdev->master);
	95	}
	96
8736b927 BD	97	static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
8736b927 BD	98	{
ee9c1fbf	99	gpio_set_value(spi->pin_cs, pol);
8736b927 BD	100	}
8736b927 BD	101
7fba5340 BD	102	static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
7fba5340 BD	103	{
570327d9	104	struct s3c24xx_spi_devstate *cs = spi->controller_state;
7fba5340 BD	105	struct s3c24xx_spi *hw = to_hw(spi);
7fba5340 BD	106	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
570327d9 BD	107
570327d9 BD	108	/* change the chipselect state and the state of the spi engine clock */
7fba5340 BD	109
	110	switch (value) {
	111	case BITBANG_CS_INACTIVE:
3d2c5b41	112	hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
570327d9	113	writeb(cs->spcon, hw->regs + S3C2410_SPCON);
7fba5340 BD	114	break;
	115
	116	case BITBANG_CS_ACTIVE:
570327d9 BD	117	writeb(cs->spcon \| S3C2410_SPCON_ENSCK,
570327d9 BD	118	hw->regs + S3C2410_SPCON);
3d2c5b41	119	hw->set_cs(hw->pdata, spi->chip_select, cspol);
7fba5340	120	break;
7fba5340 BD	121	}
	122	}
	123
570327d9 BD	124	static int s3c24xx_spi_update_state(struct spi_device *spi,
570327d9 BD	125	struct spi_transfer *t)
7fba5340 BD	126	{
7fba5340 BD	127	struct s3c24xx_spi *hw = to_hw(spi);
570327d9	128	struct s3c24xx_spi_devstate *cs = spi->controller_state;
7fba5340 BD	129	unsigned int bpw;
	130	unsigned int hz;
	131	unsigned int div;
b8978784	132	unsigned long clk;
7fba5340 BD	133
	134	bpw = t ? t->bits_per_word : spi->bits_per_word;
	135	hz = t ? t->speed_hz : spi->max_speed_hz;
	136
19152975 BD	137	if (!bpw)
	138	bpw = 8;
	139
	140	if (!hz)
	141	hz = spi->max_speed_hz;
	142
7fba5340 BD	143	if (bpw != 8) {
	144	dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
	145	return -EINVAL;
	146	}
	147
570327d9	148	if (spi->mode != cs->mode) {
bec0806c	149	u8 spcon = SPCON_DEFAULT \| S3C2410_SPCON_ENSCK;
570327d9 BD	150
	151	if (spi->mode & SPI_CPHA)
	152	spcon \|= S3C2410_SPCON_CPHA_FMTB;
7fba5340	153
570327d9 BD	154	if (spi->mode & SPI_CPOL)
570327d9 BD	155	spcon \|= S3C2410_SPCON_CPOL_HIGH;
7fba5340	156
570327d9 BD	157	cs->mode = spi->mode;
	158	cs->spcon = spcon;
	159	}
b8978784	160
570327d9 BD	161	if (cs->hz != hz) {
	162	clk = clk_get_rate(hw->clk);
	163	div = DIV_ROUND_UP(clk, hz * 2) - 1;
b8978784	164
570327d9 BD	165	if (div > 255)
570327d9 BD	166	div = 255;
7fba5340	167
570327d9 BD	168	dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
	169	div, hz, clk / (2 * (div + 1)));
	170
	171	cs->hz = hz;
	172	cs->sppre = div;
7fba5340	173	}
7fba5340 BD	174
	175	return 0;
	176	}
	177
570327d9 BD	178	static int s3c24xx_spi_setupxfer(struct spi_device *spi,
	179	struct spi_transfer *t)
	180	{
	181	struct s3c24xx_spi_devstate *cs = spi->controller_state;
	182	struct s3c24xx_spi *hw = to_hw(spi);
	183	int ret;
	184
	185	ret = s3c24xx_spi_update_state(spi, t);
	186	if (!ret)
	187	writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
	188
	189	return ret;
	190	}
	191
7fba5340 BD	192	static int s3c24xx_spi_setup(struct spi_device *spi)
7fba5340 BD	193	{
570327d9 BD	194	struct s3c24xx_spi_devstate *cs = spi->controller_state;
570327d9 BD	195	struct s3c24xx_spi *hw = to_hw(spi);
7fba5340 BD	196	int ret;
7fba5340 BD	197
570327d9 BD	198	/* allocate settings on the first call */
	199	if (!cs) {
	200	cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
	201	if (!cs) {
	202	dev_err(&spi->dev, "no memory for controller state\n");
	203	return -ENOMEM;
	204	}
	205
	206	cs->spcon = SPCON_DEFAULT;
	207	cs->hz = -1;
	208	spi->controller_state = cs;
	209	}
	210
	211	/* initialise the state from the device */
	212	ret = s3c24xx_spi_update_state(spi, NULL);
	213	if (ret)
7fba5340	214	return ret;
570327d9 BD	215
	216	spin_lock(&hw->bitbang.lock);
	217	if (!hw->bitbang.busy) {
	218	hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
	219	/* need to ndelay for 0.5 clocktick ? */
7fba5340	220	}
570327d9	221	spin_unlock(&hw->bitbang.lock);
7fba5340	222
7fba5340 BD	223	return 0;
	224	}
	225
570327d9 BD	226	static void s3c24xx_spi_cleanup(struct spi_device *spi)
	227	{
	228	kfree(spi->controller_state);
	229	}
	230
7fba5340 BD	231	static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
7fba5340 BD	232	{
4b1badf5	233	return hw->tx ? hw->tx[count] : 0;
7fba5340 BD	234	}
7fba5340 BD	235
bec0806c BD	236	#ifdef CONFIG_SPI_S3C24XX_FIQ
	237	/* Support for FIQ based pseudo-DMA to improve the transfer speed.
	238	*
	239	* This code uses the assembly helper in spi_s3c24xx_spi.S which is
	240	* used by the FIQ core to move data between main memory and the peripheral
	241	* block. Since this is code running on the processor, there is no problem
	242	* with cache coherency of the buffers, so we can use any buffer we like.
	243	*/
	244
	245	/**
	246	* struct spi_fiq_code - FIQ code and header
	247	* @length: The length of the code fragment, excluding this header.
	248	* @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
	249	* @data: The code itself to install as a FIQ handler.
	250	*/
	251	struct spi_fiq_code {
	252	u32 length;
	253	u32 ack_offset;
	254	u8 data[0];
	255	};
	256
	257	extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
	258	extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
	259	extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
	260
	261	/**
	262	* ack_bit - turn IRQ into IRQ acknowledgement bit
	263	* @irq: The interrupt number
	264	*
	265	* Returns the bit to write to the interrupt acknowledge register.
	266	*/
	267	static inline u32 ack_bit(unsigned int irq)
	268	{
	269	return 1 << (irq - IRQ_EINT0);
	270	}
	271
	272	/**
	273	* s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
	274	* @hw: The hardware state.
	275	*
	276	* Claim the FIQ handler (only one can be active at any one time) and
	277	* then setup the correct transfer code for this transfer.
	278	*
3ad2f3fb	279	* This call updates all the necessary state information if successful,
bec0806c BD	280	* so the caller does not need to do anything more than start the transfer
	281	* as normal, since the IRQ will have been re-routed to the FIQ handler.
	282	*/
	283	void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
	284	{
	285	struct pt_regs regs;
	286	enum spi_fiq_mode mode;
	287	struct spi_fiq_code *code;
	288	int ret;
	289
	290	if (!hw->fiq_claimed) {
	291	/* try and claim fiq if we haven't got it, and if not
	292	* then return and simply use another transfer method */
	293
	294	ret = claim_fiq(&hw->fiq_handler);
	295	if (ret)
	296	return;
	297	}
	298
	299	if (hw->tx && !hw->rx)
	300	mode = FIQ_MODE_TX;
	301	else if (hw->rx && !hw->tx)
	302	mode = FIQ_MODE_RX;
	303	else
	304	mode = FIQ_MODE_TXRX;
	305
	306	regs.uregs[fiq_rspi] = (long)hw->regs;
	307	regs.uregs[fiq_rrx] = (long)hw->rx;
	308	regs.uregs[fiq_rtx] = (long)hw->tx + 1;
	309	regs.uregs[fiq_rcount] = hw->len - 1;
	310	regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
	311
	312	set_fiq_regs(&regs);
	313
	314	if (hw->fiq_mode != mode) {
	315	u32 *ack_ptr;
	316
	317	hw->fiq_mode = mode;
	318
	319	switch (mode) {
	320	case FIQ_MODE_TX:
	321	code = &s3c24xx_spi_fiq_tx;
	322	break;
	323	case FIQ_MODE_RX:
	324	code = &s3c24xx_spi_fiq_rx;
	325	break;
	326	case FIQ_MODE_TXRX:
	327	code = &s3c24xx_spi_fiq_txrx;
	328	break;
	329	default:
	330	code = NULL;
	331	}
	332
	333	BUG_ON(!code);
	334
	335	ack_ptr = (u32 *)&code->data[code->ack_offset];
	336	*ack_ptr = ack_bit(hw->irq);
	337
	338	set_fiq_handler(&code->data, code->length);
	339	}
	340
	341	s3c24xx_set_fiq(hw->irq, true);
	342
	343	hw->fiq_mode = mode;
344	hw->fiq_inuse = 1;
345	}
346
347	/**
348	* s3c24xx_spi_fiqop - FIQ core code callback
349	* @pw: Data registered with the handler
350	* @release: Whether this is a release or a return.
351	*
352	* Called by the FIQ code when another module wants to use the FIQ, so
353	* return whether we are currently using this or not and then update our
354	* internal state.
355	*/
356	static int s3c24xx_spi_fiqop(void *pw, int release)
357	{
358	struct s3c24xx_spi *hw = pw;
359	int ret = 0;
360
361	if (release) {
362	if (hw->fiq_inuse)
363	ret = -EBUSY;
364
365	/* note, we do not need to unroute the FIQ, as the FIQ
366	* vector code de-routes it to signal the end of transfer */
367
368	hw->fiq_mode = FIQ_MODE_NONE;
369	hw->fiq_claimed = 0;
370	} else {
371	hw->fiq_claimed = 1;
372	}
373
374	return ret;
375	}
376
377	/**
378	* s3c24xx_spi_initfiq - setup the information for the FIQ core
379	* @hw: The hardware state.
380	*
381	* Setup the fiq_handler block to pass to the FIQ core.
382	*/
383	static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
384	{
385	hw->fiq_handler.dev_id = hw;
386	hw->fiq_handler.name = dev_name(hw->dev);
387	hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
388	}
389
390	/**
391	* s3c24xx_spi_usefiq - return if we should be using FIQ.
392	* @hw: The hardware state.
393	*
394	* Return true if the platform data specifies whether this channel is
395	* allowed to use the FIQ.
396	*/
397	static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
398	{
399	return hw->pdata->use_fiq;
400	}
401
402	/**
403	* s3c24xx_spi_usingfiq - return if channel is using FIQ
404	* @spi: The hardware state.
405	*
406	* Return whether the channel is currently using the FIQ (separate from
407	* whether the FIQ is claimed).
408	*/
409	static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
410	{
411	return spi->fiq_inuse;
412	}
413	#else
414
415	static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
416	static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
417	static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
418	static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
419
420	#endif /* CONFIG_SPI_S3C24XX_FIQ */
421
7fba5340 BD	422	static int s3c24xx_spi_txrx(struct spi_device spi, struct spi_transfer t)
	423	{
	424	struct s3c24xx_spi *hw = to_hw(spi);
	425
7fba5340 BD	426	hw->tx = t->tx_buf;
	427	hw->rx = t->rx_buf;
	428	hw->len = t->len;
	429	hw->count = 0;
	430
4bb5eba0 BD	431	init_completion(&hw->done);
4bb5eba0 BD	432
bec0806c BD	433	hw->fiq_inuse = 0;
	434	if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
	435	s3c24xx_spi_tryfiq(hw);
	436
7fba5340 BD	437	/* send the first byte */
7fba5340 BD	438	writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
4bb5eba0	439
7fba5340	440	wait_for_completion(&hw->done);
7fba5340 BD	441	return hw->count;
	442	}
	443
7d12e780	444	static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
7fba5340 BD	445	{
	446	struct s3c24xx_spi *hw = dev;
	447	unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
	448	unsigned int count = hw->count;
	449
	450	if (spsta & S3C2410_SPSTA_DCOL) {
	451	dev_dbg(hw->dev, "data-collision\n");
	452	complete(&hw->done);
	453	goto irq_done;
	454	}
	455
	456	if (!(spsta & S3C2410_SPSTA_READY)) {
	457	dev_dbg(hw->dev, "spi not ready for tx?\n");
	458	complete(&hw->done);
	459	goto irq_done;
	460	}
	461
bec0806c BD	462	if (!s3c24xx_spi_usingfiq(hw)) {
bec0806c BD	463	hw->count++;
7fba5340	464
bec0806c BD	465	if (hw->rx)
bec0806c BD	466	hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
7fba5340	467
bec0806c BD	468	count++;
	469
	470	if (count < hw->len)
	471	writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
	472	else
	473	complete(&hw->done);
	474	} else {
	475	hw->count = hw->len;
	476	hw->fiq_inuse = 0;
	477
	478	if (hw->rx)
	479	hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
7fba5340	480
7fba5340	481	complete(&hw->done);
bec0806c	482	}
7fba5340 BD	483
	484	irq_done:
	485	return IRQ_HANDLED;
	486	}
	487
5aa6cf30 BD	488	static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
	489	{
	490	/* for the moment, permanently enable the clock */
	491
	492	clk_enable(hw->clk);
	493
	494	/* program defaults into the registers */
	495
	496	writeb(0xff, hw->regs + S3C2410_SPPRE);
	497	writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
	498	writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
cf46b973	499
ee9c1fbf BD	500	if (hw->pdata) {
	501	if (hw->set_cs == s3c24xx_spi_gpiocs)
	502	gpio_direction_output(hw->pdata->pin_cs, 1);
	503
	504	if (hw->pdata->gpio_setup)
	505	hw->pdata->gpio_setup(hw->pdata, 1);
	506	}
5aa6cf30 BD	507	}
5aa6cf30 BD	508
940ab889	509	static int __devinit s3c24xx_spi_probe(struct platform_device *pdev)
7fba5340	510	{
50f426b5	511	struct s3c2410_spi_info *pdata;
7fba5340 BD	512	struct s3c24xx_spi *hw;
7fba5340 BD	513	struct spi_master *master;
7fba5340 BD	514	struct resource *res;
7fba5340 BD	515	int err = 0;
7fba5340 BD	516
	517	master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
	518	if (master == NULL) {
	519	dev_err(&pdev->dev, "No memory for spi_master\n");
	520	err = -ENOMEM;
	521	goto err_nomem;
	522	}
	523
	524	hw = spi_master_get_devdata(master);
	525	memset(hw, 0, sizeof(struct s3c24xx_spi));
	526
	527	hw->master = spi_master_get(master);
50f426b5	528	hw->pdata = pdata = pdev->dev.platform_data;
7fba5340 BD	529	hw->dev = &pdev->dev;
7fba5340 BD	530
50f426b5	531	if (pdata == NULL) {
7fba5340 BD	532	dev_err(&pdev->dev, "No platform data supplied\n");
	533	err = -ENOENT;
	534	goto err_no_pdata;
	535	}
	536
	537	platform_set_drvdata(pdev, hw);
	538	init_completion(&hw->done);
	539
bec0806c BD	540	/* initialise fiq handler */
	541
	542	s3c24xx_spi_initfiq(hw);
	543
d1e77806 BD	544	/* setup the master state. */
d1e77806 BD	545
e7db06b5 DB	546	/* the spi->mode bits understood by this driver: */
	547	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
	548
d1e77806	549	master->num_chipselect = hw->pdata->num_cs;
cb1d0a7a	550	master->bus_num = pdata->bus_num;
d1e77806	551
7fba5340 BD	552	/* setup the state for the bitbang driver */
	553
	554	hw->bitbang.master = hw->master;
	555	hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
	556	hw->bitbang.chipselect = s3c24xx_spi_chipsel;
	557	hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
570327d9 BD	558
	559	hw->master->setup = s3c24xx_spi_setup;
	560	hw->master->cleanup = s3c24xx_spi_cleanup;
7fba5340 BD	561
	562	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
	563
	564	/* find and map our resources */
	565
	566	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	567	if (res == NULL) {
	568	dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
	569	err = -ENOENT;
	570	goto err_no_iores;
	571	}
	572
b5e3afb5	573	hw->ioarea = request_mem_region(res->start, resource_size(res),
7fba5340 BD	574	pdev->name);
	575
	576	if (hw->ioarea == NULL) {
	577	dev_err(&pdev->dev, "Cannot reserve region\n");
	578	err = -ENXIO;
	579	goto err_no_iores;
	580	}
	581
b5e3afb5	582	hw->regs = ioremap(res->start, resource_size(res));
7fba5340 BD	583	if (hw->regs == NULL) {
	584	dev_err(&pdev->dev, "Cannot map IO\n");
	585	err = -ENXIO;
	586	goto err_no_iomap;
	587	}
	588
	589	hw->irq = platform_get_irq(pdev, 0);
	590	if (hw->irq < 0) {
	591	dev_err(&pdev->dev, "No IRQ specified\n");
	592	err = -ENOENT;
	593	goto err_no_irq;
	594	}
	595
	596	err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
	597	if (err) {
	598	dev_err(&pdev->dev, "Cannot claim IRQ\n");
	599	goto err_no_irq;
	600	}
	601
	602	hw->clk = clk_get(&pdev->dev, "spi");
	603	if (IS_ERR(hw->clk)) {
	604	dev_err(&pdev->dev, "No clock for device\n");
	605	err = PTR_ERR(hw->clk);
	606	goto err_no_clk;
	607	}
	608
7fba5340 BD	609	/* setup any gpio we can */
7fba5340 BD	610
50f426b5	611	if (!pdata->set_cs) {
ee9c1fbf BD	612	if (pdata->pin_cs < 0) {
	613	dev_err(&pdev->dev, "No chipselect pin\n");
	614	goto err_register;
	615	}
8736b927	616
ee9c1fbf BD	617	err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
	618	if (err) {
	619	dev_err(&pdev->dev, "Failed to get gpio for cs\n");
	620	goto err_register;
	621	}
	622
	623	hw->set_cs = s3c24xx_spi_gpiocs;
	624	gpio_direction_output(pdata->pin_cs, 1);
8736b927	625	} else
50f426b5	626	hw->set_cs = pdata->set_cs;
7fba5340	627
ee9c1fbf BD	628	s3c24xx_spi_initialsetup(hw);
ee9c1fbf BD	629
7fba5340 BD	630	/* register our spi controller */
	631
	632	err = spi_bitbang_start(&hw->bitbang);
	633	if (err) {
	634	dev_err(&pdev->dev, "Failed to register SPI master\n");
	635	goto err_register;
	636	}
	637
7fba5340 BD	638	return 0;
	639
	640	err_register:
ee9c1fbf BD	641	if (hw->set_cs == s3c24xx_spi_gpiocs)
	642	gpio_free(pdata->pin_cs);
	643
7fba5340 BD	644	clk_disable(hw->clk);
	645	clk_put(hw->clk);
	646
	647	err_no_clk:
	648	free_irq(hw->irq, hw);
	649
	650	err_no_irq:
	651	iounmap(hw->regs);
	652
	653	err_no_iomap:
	654	release_resource(hw->ioarea);
	655	kfree(hw->ioarea);
	656
	657	err_no_iores:
	658	err_no_pdata:
a419aef8	659	spi_master_put(hw->master);
7fba5340 BD	660
	661	err_nomem:
	662	return err;
	663	}
	664
940ab889	665	static int __devexit s3c24xx_spi_remove(struct platform_device *dev)
7fba5340 BD	666	{
	667	struct s3c24xx_spi *hw = platform_get_drvdata(dev);
	668
	669	platform_set_drvdata(dev, NULL);
	670
c6e7b8cb	671	spi_bitbang_stop(&hw->bitbang);
7fba5340 BD	672
	673	clk_disable(hw->clk);
	674	clk_put(hw->clk);
	675
	676	free_irq(hw->irq, hw);
	677	iounmap(hw->regs);
	678
ee9c1fbf BD	679	if (hw->set_cs == s3c24xx_spi_gpiocs)
	680	gpio_free(hw->pdata->pin_cs);
	681
7fba5340 BD	682	release_resource(hw->ioarea);
	683	kfree(hw->ioarea);
	684
	685	spi_master_put(hw->master);
	686	return 0;
	687	}
	688
	689
	690	#ifdef CONFIG_PM
	691
6d613207	692	static int s3c24xx_spi_suspend(struct device *dev)
7fba5340	693	{
6d613207	694	struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
7fba5340	695
cf46b973 BD	696	if (hw->pdata && hw->pdata->gpio_setup)
	697	hw->pdata->gpio_setup(hw->pdata, 0);
	698
7fba5340 BD	699	clk_disable(hw->clk);
	700	return 0;
	701	}
	702
6d613207	703	static int s3c24xx_spi_resume(struct device *dev)
7fba5340	704	{
6d613207	705	struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
7fba5340	706
5aa6cf30	707	s3c24xx_spi_initialsetup(hw);
7fba5340 BD	708	return 0;
	709	}
	710
47145210	711	static const struct dev_pm_ops s3c24xx_spi_pmops = {
6d613207 BD	712	.suspend = s3c24xx_spi_suspend,
	713	.resume = s3c24xx_spi_resume,
	714	};
	715
	716	#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
7fba5340	717	#else
6d613207 BD	718	#define S3C24XX_SPI_PMOPS NULL
6d613207 BD	719	#endif /* CONFIG_PM */
7fba5340	720
7e38c3c4	721	MODULE_ALIAS("platform:s3c2410-spi");
42cde430	722	static struct platform_driver s3c24xx_spi_driver = {
940ab889 GL	723	.probe = s3c24xx_spi_probe,
940ab889 GL	724	.remove = __devexit_p(s3c24xx_spi_remove),
7fba5340 BD	725	.driver = {
	726	.name = "s3c2410-spi",
	727	.owner = THIS_MODULE,
6d613207	728	.pm = S3C24XX_SPI_PMOPS,
7fba5340 BD	729	},
7fba5340 BD	730	};
940ab889	731	module_platform_driver(s3c24xx_spi_driver);
7fba5340 BD	732
	733	MODULE_DESCRIPTION("S3C24XX SPI Driver");
	734	MODULE_AUTHOR("Ben Dooks, <[email protected]>");
	735	MODULE_LICENSE("GPL");