]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef __PPC_PCI_H |
2 | #define __PPC_PCI_H | |
3 | #ifdef __KERNEL__ | |
4 | ||
5 | #include <linux/types.h> | |
6 | #include <linux/slab.h> | |
7 | #include <linux/string.h> | |
8 | #include <linux/mm.h> | |
9 | #include <asm/scatterlist.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/pci-bridge.h> | |
12 | #include <asm-generic/pci-dma-compat.h> | |
13 | ||
14 | struct pci_dev; | |
15 | ||
16 | /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ | |
17 | #define IOBASE_BRIDGE_NUMBER 0 | |
18 | #define IOBASE_MEMORY 1 | |
19 | #define IOBASE_IO 2 | |
20 | #define IOBASE_ISA_IO 3 | |
21 | #define IOBASE_ISA_MEM 4 | |
22 | ||
23 | /* | |
24 | * Set this to 1 if you want the kernel to re-assign all PCI | |
25 | * bus numbers | |
26 | */ | |
399fe2bd | 27 | extern int pci_assign_all_buses; |
1da177e4 | 28 | |
399fe2bd | 29 | #define pcibios_assign_all_busses() (pci_assign_all_buses) |
1da177e4 LT |
30 | #define pcibios_scan_all_fns(a, b) 0 |
31 | ||
32 | #define PCIBIOS_MIN_IO 0x1000 | |
33 | #define PCIBIOS_MIN_MEM 0x10000000 | |
34 | ||
35 | extern inline void pcibios_set_master(struct pci_dev *dev) | |
36 | { | |
37 | /* No special bus mastering setup handling */ | |
38 | } | |
39 | ||
c9c3e457 | 40 | extern inline void pcibios_penalize_isa_irq(int irq, int active) |
1da177e4 LT |
41 | { |
42 | /* We don't do dynamic PCI IRQ allocation */ | |
43 | } | |
44 | ||
45 | extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res); | |
46 | ||
47 | /* | |
48 | * The PCI bus bridge can translate addresses issued by the processor(s) | |
49 | * into a different address on the PCI bus. On 32-bit cpus, we assume | |
50 | * this mapping is 1-1, but on 64-bit systems it often isn't. | |
51 | * | |
52 | * Obsolete ! Drivers should now use pci_resource_to_bus | |
53 | */ | |
54 | extern unsigned long phys_to_bus(unsigned long pa); | |
55 | extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr); | |
56 | extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr); | |
57 | ||
58 | /* The PCI address space does equal the physical memory | |
59 | * address space. The networking and block device layers use | |
60 | * this boolean for bounce buffer decisions. | |
61 | */ | |
62 | #define PCI_DMA_BUS_IS_PHYS (1) | |
63 | ||
64 | /* pci_unmap_{page,single} is a nop so... */ | |
65 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) | |
66 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) | |
67 | #define pci_unmap_addr(PTR, ADDR_NAME) (0) | |
68 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
69 | #define pci_unmap_len(PTR, LEN_NAME) (0) | |
70 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
71 | ||
bb4a61b6 | 72 | #ifdef CONFIG_PCI |
e24c2d96 DM |
73 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
74 | enum pci_dma_burst_strategy *strat, | |
75 | unsigned long *strategy_parameter) | |
76 | { | |
77 | *strat = PCI_DMA_BURST_INFINITY; | |
78 | *strategy_parameter = ~0UL; | |
79 | } | |
bb4a61b6 | 80 | #endif |
e24c2d96 | 81 | |
1da177e4 LT |
82 | /* |
83 | * At present there are very few 32-bit PPC machines that can have | |
84 | * memory above the 4GB point, and we don't support that. | |
85 | */ | |
86 | #define pci_dac_dma_supported(pci_dev, mask) (0) | |
87 | ||
88 | /* Return the index of the PCI controller for device PDEV. */ | |
89 | #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index | |
90 | ||
91 | /* Set the name of the bus as it appears in /proc/bus/pci */ | |
92 | static inline int pci_proc_domain(struct pci_bus *bus) | |
93 | { | |
94 | return 0; | |
95 | } | |
96 | ||
97 | /* Map a range of PCI memory or I/O space for a device into user space */ | |
98 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, | |
99 | enum pci_mmap_state mmap_state, int write_combine); | |
100 | ||
101 | /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ | |
102 | #define HAVE_PCI_MMAP 1 | |
103 | ||
104 | extern void | |
105 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
106 | struct resource *res); | |
107 | ||
43c34735 DB |
108 | extern void |
109 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
110 | struct pci_bus_region *region); | |
111 | ||
085ae41f DM |
112 | static inline struct resource * |
113 | pcibios_select_root(struct pci_dev *pdev, struct resource *res) | |
114 | { | |
115 | struct resource *root = NULL; | |
116 | ||
117 | if (res->flags & IORESOURCE_IO) | |
118 | root = &ioport_resource; | |
119 | if (res->flags & IORESOURCE_MEM) | |
120 | root = &iomem_resource; | |
121 | ||
122 | return root; | |
123 | } | |
124 | ||
1da177e4 LT |
125 | extern void pcibios_add_platform_entries(struct pci_dev *dev); |
126 | ||
127 | struct file; | |
128 | extern pgprot_t pci_phys_mem_access_prot(struct file *file, | |
8b150478 | 129 | unsigned long pfn, |
1da177e4 LT |
130 | unsigned long size, |
131 | pgprot_t prot); | |
132 | ||
2311b1f2 ME |
133 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER |
134 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
135 | const struct resource *rsrc, | |
e31dd6e4 | 136 | resource_size_t *start, resource_size_t *end); |
2311b1f2 ME |
137 | |
138 | ||
1da177e4 LT |
139 | #endif /* __KERNEL__ */ |
140 | ||
141 | #endif /* __PPC_PCI_H */ |