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1da177e4 LT |
1 | #ifndef HAYESESP_H |
2 | #define HAYESESP_H | |
3 | ||
4 | struct hayes_esp_config { | |
5 | short flow_on; | |
6 | short flow_off; | |
7 | short rx_trigger; | |
8 | short tx_trigger; | |
9 | short pio_threshold; | |
10 | unsigned char rx_timeout; | |
11 | char dma_channel; | |
12 | }; | |
13 | ||
14 | #ifdef __KERNEL__ | |
15 | ||
16 | #define ESP_DMA_CHANNEL 0 | |
17 | #define ESP_RX_TRIGGER 768 | |
18 | #define ESP_TX_TRIGGER 768 | |
19 | #define ESP_FLOW_OFF 1016 | |
20 | #define ESP_FLOW_ON 944 | |
21 | #define ESP_RX_TMOUT 128 | |
22 | #define ESP_PIO_THRESHOLD 32 | |
23 | ||
24 | #define ESP_IN_MAJOR 57 /* major dev # for dial in */ | |
25 | #define ESP_OUT_MAJOR 58 /* major dev # for dial out */ | |
26 | #define ESPC_SCALE 3 | |
27 | #define UART_ESI_BASE 0x00 | |
28 | #define UART_ESI_SID 0x01 | |
29 | #define UART_ESI_RX 0x02 | |
30 | #define UART_ESI_TX 0x02 | |
31 | #define UART_ESI_CMD1 0x04 | |
32 | #define UART_ESI_CMD2 0x05 | |
33 | #define UART_ESI_STAT1 0x04 | |
34 | #define UART_ESI_STAT2 0x05 | |
35 | #define UART_ESI_RWS 0x07 | |
36 | ||
37 | #define UART_IER_DMA_TMOUT 0x80 | |
38 | #define UART_IER_DMA_TC 0x08 | |
39 | ||
40 | #define ESI_SET_IRQ 0x04 | |
41 | #define ESI_SET_DMA_TMOUT 0x05 | |
42 | #define ESI_SET_SRV_MASK 0x06 | |
43 | #define ESI_SET_ERR_MASK 0x07 | |
44 | #define ESI_SET_FLOW_CNTL 0x08 | |
45 | #define ESI_SET_FLOW_CHARS 0x09 | |
46 | #define ESI_SET_FLOW_LVL 0x0a | |
47 | #define ESI_SET_TRIGGER 0x0b | |
48 | #define ESI_SET_RX_TIMEOUT 0x0c | |
49 | #define ESI_SET_FLOW_TMOUT 0x0d | |
50 | #define ESI_WRITE_UART 0x0e | |
51 | #define ESI_READ_UART 0x0f | |
52 | #define ESI_SET_MODE 0x10 | |
53 | #define ESI_GET_ERR_STAT 0x12 | |
54 | #define ESI_GET_UART_STAT 0x13 | |
55 | #define ESI_GET_RX_AVAIL 0x14 | |
56 | #define ESI_GET_TX_AVAIL 0x15 | |
57 | #define ESI_START_DMA_RX 0x16 | |
58 | #define ESI_START_DMA_TX 0x17 | |
59 | #define ESI_ISSUE_BREAK 0x1a | |
60 | #define ESI_FLUSH_RX 0x1b | |
61 | #define ESI_FLUSH_TX 0x1c | |
62 | #define ESI_SET_BAUD 0x1d | |
63 | #define ESI_SET_ENH_IRQ 0x1f | |
64 | #define ESI_SET_REINTR 0x20 | |
65 | #define ESI_SET_PRESCALAR 0x23 | |
66 | #define ESI_NO_COMMAND 0xff | |
67 | ||
68 | #define ESP_STAT_RX_TIMEOUT 0x01 | |
69 | #define ESP_STAT_DMA_RX 0x02 | |
70 | #define ESP_STAT_DMA_TX 0x04 | |
71 | #define ESP_STAT_NEVER_DMA 0x08 | |
72 | #define ESP_STAT_USE_PIO 0x10 | |
73 | ||
1da177e4 LT |
74 | #define ESP_MAGIC 0x53ee |
75 | #define ESP_XMIT_SIZE 4096 | |
76 | ||
77 | struct esp_struct { | |
78 | int magic; | |
4982d6b3 | 79 | struct tty_port port; |
1da177e4 | 80 | spinlock_t lock; |
4982d6b3 | 81 | int io_port; |
1da177e4 | 82 | int irq; |
1da177e4 LT |
83 | int read_status_mask; |
84 | int ignore_status_mask; | |
85 | int timeout; | |
86 | int stat_flags; | |
87 | int custom_divisor; | |
88 | int close_delay; | |
89 | unsigned short closing_wait; | |
90 | unsigned short closing_wait2; | |
91 | int IER; /* Interrupt Enable Register */ | |
92 | int MCR; /* Modem control register */ | |
1da177e4 LT |
93 | unsigned long last_active; |
94 | int line; | |
1da177e4 LT |
95 | unsigned char *xmit_buf; |
96 | int xmit_head; | |
97 | int xmit_tail; | |
98 | int xmit_cnt; | |
1da177e4 LT |
99 | wait_queue_head_t delta_msr_wait; |
100 | wait_queue_head_t break_wait; | |
101 | struct async_icount icount; /* kernel counters for the 4 input interrupts */ | |
102 | struct hayes_esp_config config; /* port configuration */ | |
103 | struct esp_struct *next_port; /* For the linked list */ | |
104 | }; | |
105 | ||
106 | struct esp_pio_buffer { | |
107 | unsigned char data[1024]; | |
108 | struct esp_pio_buffer *next; | |
109 | }; | |
110 | ||
111 | #endif /* __KERNEL__ */ | |
112 | ||
113 | ||
114 | #endif /* ESP_H */ | |
115 |