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da9091ee | 1 | /* |
ccd32e22 | 2 | * Copyright (C) 2004 Red Hat |
0e9b4e53 | 3 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
da9091ee AC |
4 | * |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | * Based in part on the ITE vendor provided SCSI driver. | |
7 | * | |
f38344b0 BZ |
8 | * Documentation: |
9 | * Datasheet is freely available, some other documents under NDA. | |
da9091ee AC |
10 | * |
11 | * The ITE8212 isn't exactly a standard IDE controller. It has two | |
12 | * modes. In pass through mode then it is an IDE controller. In its smart | |
13 | * mode its actually quite a capable hardware raid controller disguised | |
14 | * as an IDE controller. Smart mode only understands DMA read/write and | |
15 | * identify, none of the fancier commands apply. The IT8211 is identical | |
16 | * in other respects but lacks the raid mode. | |
17 | * | |
18 | * Errata: | |
19 | * o Rev 0x10 also requires master/slave hold the same DMA timings and | |
20 | * cannot do ATAPI MWDMA. | |
21 | * o The identify data for raid volumes lacks CHS info (technically ok) | |
22 | * but also fails to set the LBA28 and other bits. We fix these in | |
23 | * the IDE probe quirk code. | |
24 | * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode | |
25 | * raid then the controller firmware dies | |
26 | * o Smart mode without RAID doesn't clear all the necessary identify | |
27 | * bits to reduce the command set to the one used | |
28 | * | |
29 | * This has a few impacts on the driver | |
30 | * - In pass through mode we do all the work you would expect | |
31 | * - In smart mode the clocking set up is done by the controller generally | |
32 | * but we must watch the other limits and filter. | |
33 | * - There are a few extra vendor commands that actually talk to the | |
34 | * controller but only work PIO with no IRQ. | |
35 | * | |
36 | * Vendor areas of the identify block in smart mode are used for the | |
37 | * timing and policy set up. Each HDD in raid mode also has a serial | |
38 | * block on the disk. The hardware extra commands are get/set chip status, | |
39 | * rebuild, get rebuild status. | |
40 | * | |
41 | * In Linux the driver supports pass through mode as if the device was | |
42 | * just another IDE controller. If the smart mode is running then | |
43 | * volumes are managed by the controller firmware and each IDE "disk" | |
44 | * is a raid volume. Even more cute - the controller can do automated | |
45 | * hotplug and rebuild. | |
46 | * | |
47 | * The pass through controller itself is a little demented. It has a | |
48 | * flaw that it has a single set of PIO/MWDMA timings per channel so | |
49 | * non UDMA devices restrict each others performance. It also has a | |
50 | * single clock source per channel so mixed UDMA100/133 performance | |
51 | * isn't perfect and we have to pick a clock. Thankfully none of this | |
52 | * matters in smart mode. ATAPI DMA is not currently supported. | |
53 | * | |
54 | * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. | |
55 | * | |
56 | * TODO | |
57 | * - ATAPI UDMA is ok but not MWDMA it seems | |
58 | * - RAID configuration ioctls | |
59 | * - Move to libata once it grows up | |
60 | */ | |
61 | ||
da9091ee AC |
62 | #include <linux/types.h> |
63 | #include <linux/module.h> | |
5a0e3ad6 | 64 | #include <linux/slab.h> |
da9091ee | 65 | #include <linux/pci.h> |
da9091ee AC |
66 | #include <linux/ide.h> |
67 | #include <linux/init.h> | |
68 | ||
ced3ec8a BZ |
69 | #define DRV_NAME "it821x" |
70 | ||
b94b898f BP |
71 | #define QUIRK_VORTEX86 1 |
72 | ||
da9091ee AC |
73 | struct it821x_dev |
74 | { | |
75 | unsigned int smart:1, /* Are we in smart raid mode */ | |
76 | timing10:1; /* Rev 0x10 */ | |
77 | u8 clock_mode; /* 0, ATA_50 or ATA_66 */ | |
78 | u8 want[2][2]; /* Mode/Pri log for master slave */ | |
79 | /* We need these for switching the clock when DMA goes on/off | |
80 | The high byte is the 66Mhz timing */ | |
81 | u16 pio[2]; /* Cached PIO values */ | |
82 | u16 mwdma[2]; /* Cached MWDMA values */ | |
83 | u16 udma[2]; /* Cached UDMA values (per drive) */ | |
b94b898f | 84 | u16 quirks; |
da9091ee AC |
85 | }; |
86 | ||
87 | #define ATA_66 0 | |
88 | #define ATA_50 1 | |
89 | #define ATA_ANY 2 | |
90 | ||
91 | #define UDMA_OFF 0 | |
92 | #define MWDMA_OFF 0 | |
93 | ||
94 | /* | |
95 | * We allow users to force the card into non raid mode without | |
3a4fa0a2 | 96 | * flashing the alternative BIOS. This is also necessary right now |
da9091ee AC |
97 | * for embedded platforms that cannot run a PC BIOS but are using this |
98 | * device. | |
99 | */ | |
100 | ||
101 | static int it8212_noraid; | |
102 | ||
103 | /** | |
104 | * it821x_program - program the PIO/MWDMA registers | |
105 | * @drive: drive to tune | |
0e9b4e53 | 106 | * @timing: timing info |
da9091ee AC |
107 | * |
108 | * Program the PIO/MWDMA timing for this channel according to the | |
109 | * current clock. | |
110 | */ | |
111 | ||
112 | static void it821x_program(ide_drive_t *drive, u16 timing) | |
113 | { | |
36501650 BZ |
114 | ide_hwif_t *hwif = drive->hwif; |
115 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
116 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
117 | int channel = hwif->channel; | |
118 | u8 conf; | |
119 | ||
120 | /* Program PIO/MWDMA timing bits */ | |
121 | if(itdev->clock_mode == ATA_66) | |
122 | conf = timing >> 8; | |
123 | else | |
124 | conf = timing & 0xFF; | |
36501650 BZ |
125 | |
126 | pci_write_config_byte(dev, 0x54 + 4 * channel, conf); | |
da9091ee AC |
127 | } |
128 | ||
129 | /** | |
130 | * it821x_program_udma - program the UDMA registers | |
131 | * @drive: drive to tune | |
0e9b4e53 | 132 | * @timing: timing info |
da9091ee AC |
133 | * |
134 | * Program the UDMA timing for this drive according to the | |
135 | * current clock. | |
136 | */ | |
137 | ||
138 | static void it821x_program_udma(ide_drive_t *drive, u16 timing) | |
139 | { | |
36501650 BZ |
140 | ide_hwif_t *hwif = drive->hwif; |
141 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
142 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
143 | int channel = hwif->channel; | |
123995b9 | 144 | u8 unit = drive->dn & 1, conf; |
da9091ee AC |
145 | |
146 | /* Program UDMA timing bits */ | |
147 | if(itdev->clock_mode == ATA_66) | |
148 | conf = timing >> 8; | |
149 | else | |
150 | conf = timing & 0xFF; | |
36501650 BZ |
151 | |
152 | if (itdev->timing10 == 0) | |
153 | pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf); | |
da9091ee | 154 | else { |
36501650 BZ |
155 | pci_write_config_byte(dev, 0x56 + 4 * channel, conf); |
156 | pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf); | |
da9091ee AC |
157 | } |
158 | } | |
159 | ||
da9091ee AC |
160 | /** |
161 | * it821x_clock_strategy | |
0e9b4e53 | 162 | * @drive: drive to set up |
da9091ee AC |
163 | * |
164 | * Select between the 50 and 66Mhz base clocks to get the best | |
165 | * results for this interface. | |
166 | */ | |
167 | ||
168 | static void it821x_clock_strategy(ide_drive_t *drive) | |
169 | { | |
170 | ide_hwif_t *hwif = drive->hwif; | |
36501650 | 171 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee | 172 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
07af5a5b | 173 | ide_drive_t *pair = ide_get_pair_dev(drive); |
123995b9 BZ |
174 | int clock, altclock, sel = 0; |
175 | u8 unit = drive->dn & 1, v; | |
da9091ee | 176 | |
da9091ee AC |
177 | if(itdev->want[0][0] > itdev->want[1][0]) { |
178 | clock = itdev->want[0][1]; | |
179 | altclock = itdev->want[1][1]; | |
180 | } else { | |
181 | clock = itdev->want[1][1]; | |
182 | altclock = itdev->want[0][1]; | |
183 | } | |
184 | ||
0e9b4e53 BZ |
185 | /* |
186 | * if both clocks can be used for the mode with the higher priority | |
187 | * use the clock needed by the mode with the lower priority | |
188 | */ | |
189 | if (clock == ATA_ANY) | |
da9091ee AC |
190 | clock = altclock; |
191 | ||
192 | /* Nobody cares - keep the same clock */ | |
193 | if(clock == ATA_ANY) | |
194 | return; | |
195 | /* No change */ | |
196 | if(clock == itdev->clock_mode) | |
197 | return; | |
198 | ||
199 | /* Load this into the controller ? */ | |
200 | if(clock == ATA_66) | |
201 | itdev->clock_mode = ATA_66; | |
202 | else { | |
203 | itdev->clock_mode = ATA_50; | |
204 | sel = 1; | |
205 | } | |
36501650 BZ |
206 | |
207 | pci_read_config_byte(dev, 0x50, &v); | |
da9091ee AC |
208 | v &= ~(1 << (1 + hwif->channel)); |
209 | v |= sel << (1 + hwif->channel); | |
36501650 | 210 | pci_write_config_byte(dev, 0x50, v); |
da9091ee AC |
211 | |
212 | /* | |
213 | * Reprogram the UDMA/PIO of the pair drive for the switch | |
214 | * MWDMA will be dealt with by the dma switcher | |
215 | */ | |
216 | if(pair && itdev->udma[1-unit] != UDMA_OFF) { | |
217 | it821x_program_udma(pair, itdev->udma[1-unit]); | |
218 | it821x_program(pair, itdev->pio[1-unit]); | |
219 | } | |
220 | /* | |
221 | * Reprogram the UDMA/PIO of our drive for the switch. | |
222 | * MWDMA will be dealt with by the dma switcher | |
223 | */ | |
224 | if(itdev->udma[unit] != UDMA_OFF) { | |
225 | it821x_program_udma(drive, itdev->udma[unit]); | |
226 | it821x_program(drive, itdev->pio[unit]); | |
227 | } | |
228 | } | |
229 | ||
da9091ee | 230 | /** |
88b2b32b | 231 | * it821x_set_pio_mode - set host controller for PIO mode |
e085b3ca | 232 | * @hwif: port |
88b2b32b | 233 | * @drive: drive |
da9091ee | 234 | * |
88b2b32b BZ |
235 | * Tune the host to the desired PIO mode taking into the consideration |
236 | * the maximum PIO mode supported by the other device on the cable. | |
da9091ee AC |
237 | */ |
238 | ||
e085b3ca | 239 | static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
da9091ee | 240 | { |
da9091ee | 241 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
07af5a5b | 242 | ide_drive_t *pair = ide_get_pair_dev(drive); |
e085b3ca | 243 | const u8 pio = drive->pio_mode - XFER_PIO_0; |
123995b9 | 244 | u8 unit = drive->dn & 1, set_pio = pio; |
da9091ee AC |
245 | |
246 | /* Spec says 89 ref driver uses 88 */ | |
88b2b32b | 247 | static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; |
da9091ee AC |
248 | static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; |
249 | ||
0e9b4e53 BZ |
250 | /* |
251 | * Compute the best PIO mode we can for a given device. We must | |
252 | * pick a speed that does not cause problems with the other device | |
253 | * on the cable. | |
254 | */ | |
255 | if (pair) { | |
f657911d | 256 | u8 pair_pio = pair->pio_mode - XFER_PIO_0; |
0e9b4e53 BZ |
257 | /* trim PIO to the slowest of the master/slave */ |
258 | if (pair_pio < set_pio) | |
259 | set_pio = pair_pio; | |
260 | } | |
261 | ||
da9091ee | 262 | /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
0e9b4e53 | 263 | itdev->want[unit][1] = pio_want[set_pio]; |
da9091ee | 264 | itdev->want[unit][0] = 1; /* PIO is lowest priority */ |
88b2b32b | 265 | itdev->pio[unit] = pio_timings[set_pio]; |
da9091ee AC |
266 | it821x_clock_strategy(drive); |
267 | it821x_program(drive, itdev->pio[unit]); | |
268 | } | |
269 | ||
270 | /** | |
271 | * it821x_tune_mwdma - tune a channel for MWDMA | |
272 | * @drive: drive to set up | |
273 | * @mode_wanted: the target operating mode | |
274 | * | |
275 | * Load the timing settings for this device mode into the | |
276 | * controller when doing MWDMA in pass through mode. The caller | |
277 | * must manage the whole lack of per device MWDMA/PIO timings and | |
278 | * the shared MWDMA/PIO timing register. | |
279 | */ | |
280 | ||
9892ec54 | 281 | static void it821x_tune_mwdma(ide_drive_t *drive, u8 mode_wanted) |
da9091ee | 282 | { |
36501650 BZ |
283 | ide_hwif_t *hwif = drive->hwif; |
284 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee | 285 | struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); |
123995b9 | 286 | u8 unit = drive->dn & 1, channel = hwif->channel, conf; |
da9091ee AC |
287 | |
288 | static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; | |
289 | static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; | |
290 | ||
291 | itdev->want[unit][1] = mwdma_want[mode_wanted]; | |
292 | itdev->want[unit][0] = 2; /* MWDMA is low priority */ | |
293 | itdev->mwdma[unit] = dma[mode_wanted]; | |
294 | itdev->udma[unit] = UDMA_OFF; | |
295 | ||
296 | /* UDMA bits off - Revision 0x10 do them in pairs */ | |
36501650 BZ |
297 | pci_read_config_byte(dev, 0x50, &conf); |
298 | if (itdev->timing10) | |
da9091ee AC |
299 | conf |= channel ? 0x60: 0x18; |
300 | else | |
301 | conf |= 1 << (3 + 2 * channel + unit); | |
36501650 | 302 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
303 | |
304 | it821x_clock_strategy(drive); | |
305 | /* FIXME: do we need to program this ? */ | |
306 | /* it821x_program(drive, itdev->mwdma[unit]); */ | |
307 | } | |
308 | ||
309 | /** | |
310 | * it821x_tune_udma - tune a channel for UDMA | |
311 | * @drive: drive to set up | |
312 | * @mode_wanted: the target operating mode | |
313 | * | |
314 | * Load the timing settings for this device mode into the | |
315 | * controller when doing UDMA modes in pass through. | |
316 | */ | |
317 | ||
9892ec54 | 318 | static void it821x_tune_udma(ide_drive_t *drive, u8 mode_wanted) |
da9091ee | 319 | { |
36501650 BZ |
320 | ide_hwif_t *hwif = drive->hwif; |
321 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee | 322 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
123995b9 | 323 | u8 unit = drive->dn & 1, channel = hwif->channel, conf; |
da9091ee AC |
324 | |
325 | static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; | |
326 | static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; | |
327 | ||
328 | itdev->want[unit][1] = udma_want[mode_wanted]; | |
329 | itdev->want[unit][0] = 3; /* UDMA is high priority */ | |
330 | itdev->mwdma[unit] = MWDMA_OFF; | |
331 | itdev->udma[unit] = udma[mode_wanted]; | |
332 | if(mode_wanted >= 5) | |
333 | itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ | |
334 | ||
335 | /* UDMA on. Again revision 0x10 must do the pair */ | |
36501650 BZ |
336 | pci_read_config_byte(dev, 0x50, &conf); |
337 | if (itdev->timing10) | |
da9091ee AC |
338 | conf &= channel ? 0x9F: 0xE7; |
339 | else | |
340 | conf &= ~ (1 << (3 + 2 * channel + unit)); | |
36501650 | 341 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
342 | |
343 | it821x_clock_strategy(drive); | |
344 | it821x_program_udma(drive, itdev->udma[unit]); | |
345 | ||
346 | } | |
347 | ||
da9091ee AC |
348 | /** |
349 | * it821x_dma_read - DMA hook | |
350 | * @drive: drive for DMA | |
351 | * | |
352 | * The IT821x has a single timing register for MWDMA and for PIO | |
353 | * operations. As we flip back and forth we have to reload the | |
354 | * clock. In addition the rev 0x10 device only works if the same | |
355 | * timing value is loaded into the master and slave UDMA clock | |
356 | * so we must also reload that. | |
357 | * | |
358 | * FIXME: we could figure out in advance if we need to do reloads | |
359 | */ | |
360 | ||
361 | static void it821x_dma_start(ide_drive_t *drive) | |
362 | { | |
363 | ide_hwif_t *hwif = drive->hwif; | |
364 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
123995b9 BZ |
365 | u8 unit = drive->dn & 1; |
366 | ||
da9091ee AC |
367 | if(itdev->mwdma[unit] != MWDMA_OFF) |
368 | it821x_program(drive, itdev->mwdma[unit]); | |
369 | else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) | |
370 | it821x_program_udma(drive, itdev->udma[unit]); | |
371 | ide_dma_start(drive); | |
372 | } | |
373 | ||
374 | /** | |
375 | * it821x_dma_write - DMA hook | |
376 | * @drive: drive for DMA stop | |
377 | * | |
378 | * The IT821x has a single timing register for MWDMA and for PIO | |
379 | * operations. As we flip back and forth we have to reload the | |
380 | * clock. | |
381 | */ | |
382 | ||
383 | static int it821x_dma_end(ide_drive_t *drive) | |
384 | { | |
385 | ide_hwif_t *hwif = drive->hwif; | |
da9091ee | 386 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
653bcf52 | 387 | int ret = ide_dma_end(drive); |
123995b9 BZ |
388 | u8 unit = drive->dn & 1; |
389 | ||
da9091ee AC |
390 | if(itdev->mwdma[unit] != MWDMA_OFF) |
391 | it821x_program(drive, itdev->pio[unit]); | |
392 | return ret; | |
393 | } | |
394 | ||
da9091ee | 395 | /** |
88b2b32b | 396 | * it821x_set_dma_mode - set host controller for DMA mode |
8776168c | 397 | * @hwif: port |
88b2b32b | 398 | * @drive: drive |
da9091ee | 399 | * |
88b2b32b | 400 | * Tune the ITE chipset for the desired DMA mode. |
da9091ee AC |
401 | */ |
402 | ||
8776168c | 403 | static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
da9091ee | 404 | { |
8776168c BZ |
405 | const u8 speed = drive->dma_mode; |
406 | ||
88b2b32b BZ |
407 | /* |
408 | * MWDMA tuning is really hard because our MWDMA and PIO | |
409 | * timings are kept in the same place. We can switch in the | |
410 | * host dma on/off callbacks. | |
411 | */ | |
412 | if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6) | |
413 | it821x_tune_udma(drive, speed - XFER_UDMA_0); | |
414 | else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) | |
415 | it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0); | |
da9091ee AC |
416 | } |
417 | ||
da9091ee | 418 | /** |
ac95beed | 419 | * it821x_cable_detect - cable detection |
da9091ee AC |
420 | * @hwif: interface to check |
421 | * | |
422 | * Check for the presence of an ATA66 capable cable on the | |
423 | * interface. Problematic as it seems some cards don't have | |
424 | * the needed logic onboard. | |
425 | */ | |
426 | ||
f454cbe8 | 427 | static u8 it821x_cable_detect(ide_hwif_t *hwif) |
da9091ee AC |
428 | { |
429 | /* The reference driver also only does disk side */ | |
49521f97 | 430 | return ATA_CBL_PATA80; |
da9091ee AC |
431 | } |
432 | ||
433 | /** | |
f01393e4 BZ |
434 | * it821x_quirkproc - post init callback |
435 | * @drive: drive | |
da9091ee | 436 | * |
f01393e4 | 437 | * This callback is run after the drive has been probed but |
da9091ee AC |
438 | * before anything gets attached. It allows drivers to do any |
439 | * final tuning that is needed, or fixups to work around bugs. | |
440 | */ | |
441 | ||
36de9948 | 442 | static void it821x_quirkproc(ide_drive_t *drive) |
da9091ee | 443 | { |
f01393e4 | 444 | struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif); |
4dde4492 | 445 | u16 *id = drive->id; |
da9091ee | 446 | |
f01393e4 | 447 | if (!itdev->smart) { |
da9091ee AC |
448 | /* |
449 | * If we are in pass through mode then not much | |
450 | * needs to be done, but we do bother to clear the | |
451 | * IRQ mask as we may well be in PIO (eg rev 0x10) | |
452 | * for now and we know unmasking is safe on this chipset. | |
453 | */ | |
97100fc8 | 454 | drive->dev_flags |= IDE_DFLAG_UNMASK; |
f01393e4 | 455 | } else { |
da9091ee AC |
456 | /* |
457 | * Perform fixups on smart mode. We need to "lose" some | |
458 | * capabilities the firmware lacks but does not filter, and | |
459 | * also patch up some capability bits that it forgets to set | |
460 | * in RAID mode. | |
461 | */ | |
462 | ||
da9091ee | 463 | /* Check for RAID v native */ |
4dde4492 BZ |
464 | if (strstr((char *)&id[ATA_ID_PROD], |
465 | "Integrated Technology Express")) { | |
da9091ee AC |
466 | /* In raid mode the ident block is slightly buggy |
467 | We need to set the bits so that the IDE layer knows | |
468 | LBA28. LBA48 and DMA ar valid */ | |
48fb2688 | 469 | id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */ |
4dde4492 BZ |
470 | id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */ |
471 | id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */ | |
da9091ee AC |
472 | /* Reporting logic */ |
473 | printk(KERN_INFO "%s: IT8212 %sRAID %d volume", | |
4dde4492 BZ |
474 | drive->name, id[147] ? "Bootable " : "", |
475 | id[ATA_ID_CSFO]); | |
476 | if (id[ATA_ID_CSFO] != 1) | |
477 | printk(KERN_CONT "(%dK stripe)", id[146]); | |
478 | printk(KERN_CONT ".\n"); | |
da9091ee AC |
479 | } else { |
480 | /* Non RAID volume. Fixups to stop the core code | |
481 | doing unsupported things */ | |
4dde4492 BZ |
482 | id[ATA_ID_FIELD_VALID] &= 3; |
483 | id[ATA_ID_QUEUE_DEPTH] = 0; | |
484 | id[ATA_ID_COMMAND_SET_1] = 0; | |
485 | id[ATA_ID_COMMAND_SET_2] &= 0xC400; | |
486 | id[ATA_ID_CFSSE] &= 0xC000; | |
487 | id[ATA_ID_CFS_ENABLE_1] = 0; | |
488 | id[ATA_ID_CFS_ENABLE_2] &= 0xC400; | |
489 | id[ATA_ID_CSF_DEFAULT] &= 0xC000; | |
490 | id[127] = 0; | |
491 | id[ATA_ID_DLF] = 0; | |
492 | id[ATA_ID_CSFO] = 0; | |
493 | id[ATA_ID_CFA_POWER] = 0; | |
da9091ee AC |
494 | printk(KERN_INFO "%s: Performing identify fixups.\n", |
495 | drive->name); | |
496 | } | |
0380dad4 BZ |
497 | |
498 | /* | |
499 | * Set MWDMA0 mode as enabled/support - just to tell | |
500 | * IDE core that DMA is supported (it821x hardware | |
501 | * takes care of DMA mode programming). | |
502 | */ | |
48fb2688 | 503 | if (ata_id_has_dma(id)) { |
4dde4492 | 504 | id[ATA_ID_MWDMA_MODES] |= 0x0101; |
0380dad4 BZ |
505 | drive->current_speed = XFER_MW_DMA_0; |
506 | } | |
da9091ee AC |
507 | } |
508 | ||
509 | } | |
510 | ||
b5a608fb | 511 | static const struct ide_dma_ops it821x_pass_through_dma_ops = { |
84e0f3f6 DG |
512 | .dma_host_set = ide_dma_host_set, |
513 | .dma_setup = ide_dma_setup, | |
5e37bdc0 BZ |
514 | .dma_start = it821x_dma_start, |
515 | .dma_end = it821x_dma_end, | |
84e0f3f6 | 516 | .dma_test_irq = ide_dma_test_irq, |
84e0f3f6 | 517 | .dma_lost_irq = ide_dma_lost_irq, |
35c9b4da | 518 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b5315 | 519 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
520 | }; |
521 | ||
da9091ee AC |
522 | /** |
523 | * init_hwif_it821x - set up hwif structs | |
524 | * @hwif: interface to set up | |
525 | * | |
526 | * We do the basic set up of the interface structure. The IT8212 | |
527 | * requires several custom handlers so we override the default | |
528 | * ide DMA handlers appropriately | |
529 | */ | |
530 | ||
fe31edc8 | 531 | static void init_hwif_it821x(ide_hwif_t *hwif) |
da9091ee | 532 | { |
36501650 | 533 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1d76d9dc BZ |
534 | struct ide_host *host = pci_get_drvdata(dev); |
535 | struct it821x_dev *itdevs = host->host_priv; | |
536 | struct it821x_dev *idev = itdevs + hwif->channel; | |
da9091ee AC |
537 | u8 conf; |
538 | ||
da9091ee AC |
539 | ide_set_hwifdata(hwif, idev); |
540 | ||
36501650 | 541 | pci_read_config_byte(dev, 0x50, &conf); |
33c1002e | 542 | if (conf & 1) { |
da9091ee | 543 | idev->smart = 1; |
33c1002e | 544 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
da9091ee AC |
545 | /* Long I/O's although allowed in LBA48 space cause the |
546 | onboard firmware to enter the twighlight zone */ | |
547 | hwif->rqsize = 256; | |
548 | } | |
549 | ||
550 | /* Pull the current clocks from 0x50 also */ | |
551 | if (conf & (1 << (1 + hwif->channel))) | |
552 | idev->clock_mode = ATA_50; | |
553 | else | |
554 | idev->clock_mode = ATA_66; | |
555 | ||
556 | idev->want[0][1] = ATA_ANY; | |
557 | idev->want[1][1] = ATA_ANY; | |
558 | ||
559 | /* | |
560 | * Not in the docs but according to the reference driver | |
3a4fa0a2 | 561 | * this is necessary. |
da9091ee AC |
562 | */ |
563 | ||
4a246269 | 564 | if (dev->revision == 0x10) { |
da9091ee | 565 | idev->timing10 = 1; |
33c1002e BZ |
566 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
567 | if (idev->smart == 0) | |
ced3ec8a | 568 | printk(KERN_WARNING DRV_NAME " %s: revision 0x10, " |
28cfd8af | 569 | "workarounds activated\n", pci_name(dev)); |
da9091ee AC |
570 | } |
571 | ||
88b2b32b | 572 | if (idev->smart == 0) { |
88b2b32b | 573 | /* MWDMA/PIO clock switching for pass through mode */ |
5e37bdc0 | 574 | hwif->dma_ops = &it821x_pass_through_dma_ops; |
88b2b32b BZ |
575 | } else |
576 | hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; | |
da9091ee | 577 | |
9ff6f72f BZ |
578 | if (hwif->dma_base == 0) |
579 | return; | |
da9091ee | 580 | |
5f8b6c34 BZ |
581 | hwif->ultra_mask = ATA_UDMA6; |
582 | hwif->mwdma_mask = ATA_MWDMA2; | |
b94b898f BP |
583 | |
584 | /* Vortex86SX quirk: prevent Ultra-DMA mode to fix BadCRC issue */ | |
585 | if (idev->quirks & QUIRK_VORTEX86) { | |
586 | if (dev->revision == 0x11) | |
587 | hwif->ultra_mask = 0; | |
588 | } | |
da9091ee AC |
589 | } |
590 | ||
feb22b7f | 591 | static void it8212_disable_raid(struct pci_dev *dev) |
da9091ee AC |
592 | { |
593 | /* Reset local CPU, and set BIOS not ready */ | |
594 | pci_write_config_byte(dev, 0x5E, 0x01); | |
595 | ||
596 | /* Set to bypass mode, and reset PCI bus */ | |
597 | pci_write_config_byte(dev, 0x50, 0x00); | |
598 | pci_write_config_word(dev, PCI_COMMAND, | |
599 | PCI_COMMAND_PARITY | PCI_COMMAND_IO | | |
600 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
601 | pci_write_config_word(dev, 0x40, 0xA0F3); | |
602 | ||
603 | pci_write_config_dword(dev,0x4C, 0x02040204); | |
604 | pci_write_config_byte(dev, 0x42, 0x36); | |
0c866b51 | 605 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); |
da9091ee AC |
606 | } |
607 | ||
2ed0ef54 | 608 | static int init_chipset_it821x(struct pci_dev *dev) |
da9091ee AC |
609 | { |
610 | u8 conf; | |
611 | static char *mode[2] = { "pass through", "smart" }; | |
612 | ||
613 | /* Force the card into bypass mode if so requested */ | |
614 | if (it8212_noraid) { | |
ced3ec8a | 615 | printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n", |
28cfd8af | 616 | pci_name(dev)); |
da9091ee AC |
617 | it8212_disable_raid(dev); |
618 | } | |
619 | pci_read_config_byte(dev, 0x50, &conf); | |
ced3ec8a | 620 | printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n", |
28cfd8af | 621 | pci_name(dev), mode[conf & 1]); |
da9091ee AC |
622 | return 0; |
623 | } | |
624 | ||
ac95beed BZ |
625 | static const struct ide_port_ops it821x_port_ops = { |
626 | /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */ | |
627 | .set_pio_mode = it821x_set_pio_mode, | |
628 | .set_dma_mode = it821x_set_dma_mode, | |
629 | .quirkproc = it821x_quirkproc, | |
630 | .cable_detect = it821x_cable_detect, | |
631 | }; | |
da9091ee | 632 | |
fe31edc8 | 633 | static const struct ide_port_info it821x_chipset = { |
ced3ec8a | 634 | .name = DRV_NAME, |
04ba6e73 BZ |
635 | .init_chipset = init_chipset_it821x, |
636 | .init_hwif = init_hwif_it821x, | |
637 | .port_ops = &it821x_port_ops, | |
638 | .pio_mask = ATA_PIO4, | |
da9091ee AC |
639 | }; |
640 | ||
641 | /** | |
642 | * it821x_init_one - pci layer discovery entry | |
643 | * @dev: PCI device | |
644 | * @id: ident table entry | |
645 | * | |
646 | * Called by the PCI code when it finds an ITE821x controller. | |
647 | * We then use the IDE PCI generic helper to do most of the work. | |
648 | */ | |
649 | ||
fe31edc8 | 650 | static int it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
da9091ee | 651 | { |
1d76d9dc BZ |
652 | struct it821x_dev *itdevs; |
653 | int rc; | |
eb7a07e8 | 654 | |
6396bb22 | 655 | itdevs = kcalloc(2, sizeof(*itdevs), GFP_KERNEL); |
1d76d9dc | 656 | if (itdevs == NULL) { |
ced3ec8a | 657 | printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev)); |
1d76d9dc | 658 | return -ENOMEM; |
eb7a07e8 BZ |
659 | } |
660 | ||
b94b898f BP |
661 | itdevs->quirks = id->driver_data; |
662 | ||
04ba6e73 | 663 | rc = ide_pci_init_one(dev, &it821x_chipset, itdevs); |
1d76d9dc BZ |
664 | if (rc) |
665 | kfree(itdevs); | |
eb7a07e8 | 666 | |
1d76d9dc | 667 | return rc; |
da9091ee AC |
668 | } |
669 | ||
fe31edc8 | 670 | static void it821x_remove(struct pci_dev *dev) |
87d8b613 BZ |
671 | { |
672 | struct ide_host *host = pci_get_drvdata(dev); | |
673 | struct it821x_dev *itdevs = host->host_priv; | |
674 | ||
675 | ide_pci_remove(dev); | |
676 | kfree(itdevs); | |
677 | } | |
678 | ||
9cbcc5e3 BZ |
679 | static const struct pci_device_id it821x_pci_tbl[] = { |
680 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 }, | |
681 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 }, | |
b94b898f | 682 | { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), QUIRK_VORTEX86 }, |
da9091ee AC |
683 | { 0, }, |
684 | }; | |
685 | ||
686 | MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); | |
687 | ||
a9ab09e2 | 688 | static struct pci_driver it821x_pci_driver = { |
da9091ee AC |
689 | .name = "ITE821x IDE", |
690 | .id_table = it821x_pci_tbl, | |
691 | .probe = it821x_init_one, | |
fe31edc8 | 692 | .remove = it821x_remove, |
feb22b7f BZ |
693 | .suspend = ide_pci_suspend, |
694 | .resume = ide_pci_resume, | |
da9091ee AC |
695 | }; |
696 | ||
697 | static int __init it821x_ide_init(void) | |
698 | { | |
a9ab09e2 | 699 | return ide_pci_register_driver(&it821x_pci_driver); |
da9091ee AC |
700 | } |
701 | ||
87d8b613 BZ |
702 | static void __exit it821x_ide_exit(void) |
703 | { | |
a9ab09e2 | 704 | pci_unregister_driver(&it821x_pci_driver); |
87d8b613 BZ |
705 | } |
706 | ||
da9091ee | 707 | module_init(it821x_ide_init); |
87d8b613 | 708 | module_exit(it821x_ide_exit); |
da9091ee AC |
709 | |
710 | module_param_named(noraid, it8212_noraid, int, S_IRUGO); | |
da195665 | 711 | MODULE_PARM_DESC(noraid, "Force card into bypass mode"); |
da9091ee AC |
712 | |
713 | MODULE_AUTHOR("Alan Cox"); | |
714 | MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); | |
715 | MODULE_LICENSE("GPL"); |