[linux.git] / drivers / ata / pata_sl82c105.c

/*
 * pata_sl82c105.c 	- SL82C105 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <[email protected]>
 *
 * Based in part on linux/drivers/ide/pci/sl82c105.c
 * 		SL82C105/Winbond 553 IDE driver
 *
 * and in part on the documentation and errata sheet
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sl82c105"
#define DRV_VERSION "0.2.3"

enum {
	/*
	 * SL82C105 PCI config register 0x40 bits.
	 */
	CTRL_IDE_IRQB	=	(1 << 30),
	CTRL_IDE_IRQA   =	(1 << 28),
	CTRL_LEGIRQ     =	(1 << 11),
	CTRL_P1F16      =	(1 << 5),
	CTRL_P1EN       =	(1 << 4),
	CTRL_P0F16      =	(1 << 1),
	CTRL_P0EN       =	(1 << 0)
};

/**
 *	sl82c105_pre_reset		-	probe begin
 *	@ap: ATA port
 *
 *	Set up cable type and use generic probe init
 */

static int sl82c105_pre_reset(struct ata_port *ap)
{
	static const struct pci_bits sl82c105_enable_bits[] = {
		{ 0x40, 1, 0x01, 0x01 },
		{ 0x40, 1, 0x10, 0x10 }
	};
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
		return -ENOENT;
	ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}


static void sl82c105_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, sl82c105_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}


/**
 *	sl82c105_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static u16 pio_timing[5] = {
		0x50D, 0x407, 0x304, 0x242, 0x240
	};
	u16 dummy;
	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);

	pci_write_config_word(pdev, timing, pio_timing[pio]);
	/* Can we lose this oddity of the old driver */
	pci_read_config_word(pdev, timing, &dummy);
}

/**
 *	sl82c105_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	sl82c105_configure_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static u16 dma_timing[3] = {
		0x707, 0x201, 0x200
	};
	u16 dummy;
	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
	int dma = adev->dma_mode - XFER_MW_DMA_0;

	pci_write_config_word(pdev, timing, dma_timing[dma]);
	/* Can we lose this oddity of the old driver */
	pci_read_config_word(pdev, timing, &dummy);
}

/**
 *	sl82c105_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup. This replaces the PIO timings
 *	for the device in question. Set appropriate PIO timings not DMA
 *	timings at this point.
 */

static void sl82c105_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	switch(adev->dma_mode) {
		case XFER_MW_DMA_0:
			sl82c105_configure_piomode(ap, adev, 1);
			break;
		case XFER_MW_DMA_1:
			sl82c105_configure_piomode(ap, adev, 3);
			break;
		case XFER_MW_DMA_2:
			sl82c105_configure_piomode(ap, adev, 3);
			break;
		default:
			BUG();
	}
}

/**
 *	sl82c105_reset_engine	-	Reset the DMA engine
 *	@ap: ATA interface
 *
 *	The sl82c105 has some serious problems with the DMA engine
 *	when transfers don't run as expected or ATAPI is used. The
 *	recommended fix is to reset the engine each use using a chip
 *	test register.
 */

static void sl82c105_reset_engine(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 val;

	pci_read_config_word(pdev, 0x7E, &val);
	pci_write_config_word(pdev, 0x7E, val | 4);
	pci_write_config_word(pdev, 0x7E, val & ~4);
}

/**
 *	sl82c105_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	Reset the DMA engine each use as recommended by the errata
 *	document.
 *
 *	FIXME: if we switch clock at BMDMA start/end we might get better
 *	PIO performance on DMA capable devices.
 */

static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	sl82c105_reset_engine(ap);

	/* Set the clocks for DMA */
	sl82c105_configure_dmamode(ap, qc->dev);
	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	sl82c105_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	Reset the DMA engine each use as recommended by the errata
 *	document.
 *
 *	This function is also called to turn off DMA when a timeout occurs
 *	during DMA operation. In both cases we need to reset the engine,
 *	so no actual eng_timeout handler is required.
 *
 *	We assume bmdma_stop is always called if bmdma_start as called. If
 *	not then we may need to wrap qc_issue.
 */

static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	ata_bmdma_stop(qc);
	sl82c105_reset_engine(ap);

	/* This will redo the initial setup of the DMA device to matching
	   PIO timings */
	sl82c105_set_dmamode(ap, qc->dev);
}

static struct scsi_host_template sl82c105_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations sl82c105_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= sl82c105_set_piomode,
	.set_dmamode	= sl82c105_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.error_handler	= sl82c105_error_handler,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= sl82c105_bmdma_start,
	.bmdma_stop	= sl82c105_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};

/**
 *	sl82c105_bridge_revision	-	find bridge version
 *	@pdev: PCI device for the ATA function
 *
 *	Locates the PCI bridge associated with the ATA function and
 *	providing it is a Winbond 553 reports the revision. If it cannot
 *	find a revision or the right device it returns -1
 */

static int sl82c105_bridge_revision(struct pci_dev *pdev)
{
	struct pci_dev *bridge;
	u8 rev;

	/*
	 * The bridge should be part of the same device, but function 0.
	 */
	bridge = pci_get_slot(pdev->bus,
			       PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
	if (!bridge)
		return -1;

	/*
	 * Make sure it is a Winbond 553 and is an ISA bridge.
	 */
	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	    	pci_dev_put(bridge);
		return -1;
	}
	/*
	 * We need to find function 0's revision, not function 1
	 */
	pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);

	pci_dev_put(bridge);
	return rev;
}


static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static struct ata_port_info info_dma = {
		.sht = &sl82c105_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &sl82c105_port_ops
	};
	static struct ata_port_info info_early = {
		.sht = &sl82c105_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.port_ops = &sl82c105_port_ops
	};
	static struct ata_port_info *port_info[2] = { &info_early, &info_early };
	u32 val;
	int rev;

	rev = sl82c105_bridge_revision(dev);

	if (rev == -1)
		dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
	else if (rev <= 5)
		dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
	else {
		port_info[0] = &info_dma;
		port_info[1] = &info_dma;
	}

	pci_read_config_dword(dev, 0x40, &val);
	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
	pci_write_config_dword(dev, 0x40, val);


	return ata_pci_init_one(dev, port_info, 1); /* For now */
}

static const struct pci_device_id sl82c105[] = {
	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },

	{ },
};

static struct pci_driver sl82c105_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sl82c105,
	.probe 		= sl82c105_init_one,
	.remove		= ata_pci_remove_one
};

static int __init sl82c105_init(void)
{
	return pci_register_driver(&sl82c105_pci_driver);
}

static void __exit sl82c105_exit(void)
{
	pci_unregister_driver(&sl82c105_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Sl82c105");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sl82c105);
MODULE_VERSION(DRV_VERSION);

module_init(sl82c105_init);
module_exit(sl82c105_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sl82c105.c - SL82C105 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <[email protected]>
	5	*
	6	* Based in part on linux/drivers/ide/pci/sl82c105.c
	7	* SL82C105/Winbond 553 IDE driver
	8	*
	9	* and in part on the documentation and errata sheet
	10	*/
85cd7251	11
669a5db4 JG	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/pci.h>
	15	#include <linux/init.h>
	16	#include <linux/blkdev.h>
	17	#include <linux/delay.h>
	18	#include <scsi/scsi_host.h>
	19	#include <linux/libata.h>
	20
	21	#define DRV_NAME "pata_sl82c105"
c961922b	22	#define DRV_VERSION "0.2.3"
669a5db4 JG	23
	24	enum {
	25	/*
	26	* SL82C105 PCI config register 0x40 bits.
	27	*/
	28	CTRL_IDE_IRQB = (1 << 30),
	29	CTRL_IDE_IRQA = (1 << 28),
	30	CTRL_LEGIRQ = (1 << 11),
	31	CTRL_P1F16 = (1 << 5),
	32	CTRL_P1EN = (1 << 4),
	33	CTRL_P0F16 = (1 << 1),
	34	CTRL_P0EN = (1 << 0)
	35	};
	36
	37	/**
	38	* sl82c105_pre_reset - probe begin
	39	* @ap: ATA port
	40	*
	41	* Set up cable type and use generic probe init
	42	*/
85cd7251	43
669a5db4 JG	44	static int sl82c105_pre_reset(struct ata_port *ap)
	45	{
	46	static const struct pci_bits sl82c105_enable_bits[] = {
	47	{ 0x40, 1, 0x01, 0x01 },
	48	{ 0x40, 1, 0x10, 0x10 }
	49	};
	50	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	51
c961922b AC	52	if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
c961922b AC	53	return -ENOENT;
669a5db4 JG	54	ap->cbl = ATA_CBL_PATA40;
	55	return ata_std_prereset(ap);
	56	}
	57
	58
	59	static void sl82c105_error_handler(struct ata_port *ap)
	60	{
	61	ata_bmdma_drive_eh(ap, sl82c105_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	62	}
	63
	64
	65	/**
	66	* sl82c105_configure_piomode - set chip PIO timing
	67	* @ap: ATA interface
	68	* @adev: ATA device
	69	* @pio: PIO mode
	70	*
	71	* Called to do the PIO mode setup. Our timing registers are shared
	72	* so a configure_dmamode call will undo any work we do here and vice
	73	* versa
	74	*/
85cd7251	75
669a5db4 JG	76	static void sl82c105_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
	77	{
	78	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	79	static u16 pio_timing[5] = {
	80	0x50D, 0x407, 0x304, 0x242, 0x240
	81	};
	82	u16 dummy;
	83	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
85cd7251	84
669a5db4 JG	85	pci_write_config_word(pdev, timing, pio_timing[pio]);
	86	/* Can we lose this oddity of the old driver */
	87	pci_read_config_word(pdev, timing, &dummy);
	88	}
	89
	90	/**
	91	* sl82c105_set_piomode - set initial PIO mode data
	92	* @ap: ATA interface
	93	* @adev: ATA device
	94	*
	95	* Called to do the PIO mode setup. Our timing registers are shared
	96	* but we want to set the PIO timing by default.
	97	*/
85cd7251	98
669a5db4 JG	99	static void sl82c105_set_piomode(struct ata_port ap, struct ata_device adev)
	100	{
	101	sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
	102	}
	103
	104	/**
	105	* sl82c105_configure_dmamode - set DMA mode in chip
	106	* @ap: ATA interface
	107	* @adev: ATA device
	108	*
	109	* Load DMA cycle times into the chip ready for a DMA transfer
	110	* to occur.
	111	*/
85cd7251	112
669a5db4 JG	113	static void sl82c105_configure_dmamode(struct ata_port ap, struct ata_device adev)
	114	{
	115	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	116	static u16 dma_timing[3] = {
	117	0x707, 0x201, 0x200
	118	};
	119	u16 dummy;
	120	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
	121	int dma = adev->dma_mode - XFER_MW_DMA_0;
85cd7251	122
669a5db4 JG	123	pci_write_config_word(pdev, timing, dma_timing[dma]);
	124	/* Can we lose this oddity of the old driver */
	125	pci_read_config_word(pdev, timing, &dummy);
	126	}
	127
	128	/**
	129	* sl82c105_set_dmamode - set initial DMA mode data
	130	* @ap: ATA interface
	131	* @adev: ATA device
	132	*
	133	* Called to do the DMA mode setup. This replaces the PIO timings
	134	* for the device in question. Set appropriate PIO timings not DMA
	135	* timings at this point.
	136	*/
85cd7251	137
669a5db4 JG	138	static void sl82c105_set_dmamode(struct ata_port ap, struct ata_device adev)
	139	{
	140	switch(adev->dma_mode) {
	141	case XFER_MW_DMA_0:
	142	sl82c105_configure_piomode(ap, adev, 1);
	143	break;
	144	case XFER_MW_DMA_1:
	145	sl82c105_configure_piomode(ap, adev, 3);
	146	break;
	147	case XFER_MW_DMA_2:
	148	sl82c105_configure_piomode(ap, adev, 3);
	149	break;
	150	default:
	151	BUG();
85cd7251	152	}
669a5db4 JG	153	}
	154
	155	/**
	156	* sl82c105_reset_engine - Reset the DMA engine
	157	* @ap: ATA interface
	158	*
	159	* The sl82c105 has some serious problems with the DMA engine
85cd7251	160	* when transfers don't run as expected or ATAPI is used. The
669a5db4 JG	161	* recommended fix is to reset the engine each use using a chip
	162	* test register.
	163	*/
85cd7251	164
669a5db4 JG	165	static void sl82c105_reset_engine(struct ata_port *ap)
	166	{
	167	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	168	u16 val;
85cd7251	169
669a5db4 JG	170	pci_read_config_word(pdev, 0x7E, &val);
	171	pci_write_config_word(pdev, 0x7E, val \| 4);
	172	pci_write_config_word(pdev, 0x7E, val & ~4);
	173	}
	174
	175	/**
	176	* sl82c105_bmdma_start - DMA engine begin
	177	* @qc: ATA command
	178	*
	179	* Reset the DMA engine each use as recommended by the errata
85cd7251	180	* document.
669a5db4 JG	181	*
	182	* FIXME: if we switch clock at BMDMA start/end we might get better
	183	* PIO performance on DMA capable devices.
	184	*/
85cd7251	185
669a5db4 JG	186	static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
	187	{
	188	struct ata_port *ap = qc->ap;
	189
	190	sl82c105_reset_engine(ap);
85cd7251	191
669a5db4 JG	192	/* Set the clocks for DMA */
669a5db4 JG	193	sl82c105_configure_dmamode(ap, qc->dev);
85cd7251	194	/* Activate DMA */
669a5db4 JG	195	ata_bmdma_start(qc);
	196	}
	197
	198	/**
	199	* sl82c105_bmdma_end - DMA engine stop
	200	* @qc: ATA command
	201	*
	202	* Reset the DMA engine each use as recommended by the errata
	203	* document.
	204	*
	205	* This function is also called to turn off DMA when a timeout occurs
	206	* during DMA operation. In both cases we need to reset the engine,
	207	* so no actual eng_timeout handler is required.
	208	*
	209	* We assume bmdma_stop is always called if bmdma_start as called. If
	210	* not then we may need to wrap qc_issue.
	211	*/
85cd7251	212
669a5db4 JG	213	static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
	214	{
	215	struct ata_port *ap = qc->ap;
	216
	217	ata_bmdma_stop(qc);
	218	sl82c105_reset_engine(ap);
85cd7251	219
669a5db4 JG	220	/* This will redo the initial setup of the DMA device to matching
	221	PIO timings */
	222	sl82c105_set_dmamode(ap, qc->dev);
	223	}
	224
	225	static struct scsi_host_template sl82c105_sht = {
	226	.module = THIS_MODULE,
	227	.name = DRV_NAME,
	228	.ioctl = ata_scsi_ioctl,
	229	.queuecommand = ata_scsi_queuecmd,
	230	.can_queue = ATA_DEF_QUEUE,
	231	.this_id = ATA_SHT_THIS_ID,
	232	.sg_tablesize = LIBATA_MAX_PRD,
	233	.max_sectors = ATA_MAX_SECTORS,
	234	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	235	.emulated = ATA_SHT_EMULATED,
	236	.use_clustering = ATA_SHT_USE_CLUSTERING,
	237	.proc_name = DRV_NAME,
	238	.dma_boundary = ATA_DMA_BOUNDARY,
	239	.slave_configure = ata_scsi_slave_config,
	240	.bios_param = ata_std_bios_param,
	241	};
	242
	243	static struct ata_port_operations sl82c105_port_ops = {
	244	.port_disable = ata_port_disable,
	245	.set_piomode = sl82c105_set_piomode,
	246	.set_dmamode = sl82c105_set_dmamode,
	247	.mode_filter = ata_pci_default_filter,
	248
	249	.tf_load = ata_tf_load,
	250	.tf_read = ata_tf_read,
	251	.check_status = ata_check_status,
	252	.exec_command = ata_exec_command,
	253	.dev_select = ata_std_dev_select,
	254
	255	.error_handler = sl82c105_error_handler,
	256
	257	.bmdma_setup = ata_bmdma_setup,
	258	.bmdma_start = sl82c105_bmdma_start,
	259	.bmdma_stop = sl82c105_bmdma_stop,
	260	.bmdma_status = ata_bmdma_status,
	261
	262	.qc_prep = ata_qc_prep,
	263	.qc_issue = ata_qc_issue_prot,
bda30288	264
669a5db4 JG	265	.data_xfer = ata_pio_data_xfer,
	266
	267	.irq_handler = ata_interrupt,
	268	.irq_clear = ata_bmdma_irq_clear,
85cd7251	269
669a5db4 JG	270	.port_start = ata_port_start,
	271	.port_stop = ata_port_stop,
	272	.host_stop = ata_host_stop
85cd7251	273	};
669a5db4 JG	274
	275	/**
	276	* sl82c105_bridge_revision - find bridge version
	277	* @pdev: PCI device for the ATA function
	278	*
	279	* Locates the PCI bridge associated with the ATA function and
	280	* providing it is a Winbond 553 reports the revision. If it cannot
	281	* find a revision or the right device it returns -1
	282	*/
85cd7251	283
669a5db4 JG	284	static int sl82c105_bridge_revision(struct pci_dev *pdev)
	285	{
	286	struct pci_dev *bridge;
	287	u8 rev;
	288
	289	/*
	290	* The bridge should be part of the same device, but function 0.
	291	*/
	292	bridge = pci_get_slot(pdev->bus,
	293	PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
	294	if (!bridge)
	295	return -1;
	296
	297	/*
	298	* Make sure it is a Winbond 553 and is an ISA bridge.
	299	*/
	300	if (bridge->vendor != PCI_VENDOR_ID_WINBOND \|\|
	301	bridge->device != PCI_DEVICE_ID_WINBOND_83C553 \|\|
	302	bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	303	pci_dev_put(bridge);
	304	return -1;
	305	}
	306	/*
	307	* We need to find function 0's revision, not function 1
	308	*/
	309	pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
	310
	311	pci_dev_put(bridge);
	312	return rev;
	313	}
	314
85cd7251	315
669a5db4 JG	316	static int sl82c105_init_one(struct pci_dev dev, const struct pci_device_id id)
	317	{
	318	static struct ata_port_info info_dma = {
	319	.sht = &sl82c105_sht,
	320	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	321	.pio_mask = 0x1f,
	322	.mwdma_mask = 0x07,
	323	.port_ops = &sl82c105_port_ops
	324	};
	325	static struct ata_port_info info_early = {
	326	.sht = &sl82c105_sht,
	327	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	328	.pio_mask = 0x1f,
	329	.port_ops = &sl82c105_port_ops
	330	};
	331	static struct ata_port_info *port_info[2] = { &info_early, &info_early };
	332	u32 val;
	333	int rev;
	334
	335	rev = sl82c105_bridge_revision(dev);
85cd7251	336
669a5db4 JG	337	if (rev == -1)
	338	dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
	339	else if (rev <= 5)
	340	dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
	341	else {
	342	port_info[0] = &info_dma;
	343	port_info[1] = &info_dma;
	344	}
85cd7251	345
669a5db4 JG	346	pci_read_config_dword(dev, 0x40, &val);
	347	val \|= CTRL_P0EN \| CTRL_P0F16 \| CTRL_P1F16;
	348	pci_write_config_dword(dev, 0x40, val);
	349
	350
	351	return ata_pci_init_one(dev, port_info, 1); /* For now */
	352	}
	353
2d2744fc JG	354	static const struct pci_device_id sl82c105[] = {
	355	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
	356
	357	{ },
669a5db4 JG	358	};
	359
	360	static struct pci_driver sl82c105_pci_driver = {
	361	.name = DRV_NAME,
	362	.id_table = sl82c105,
	363	.probe = sl82c105_init_one,
	364	.remove = ata_pci_remove_one
	365	};
	366
	367	static int __init sl82c105_init(void)
	368	{
	369	return pci_register_driver(&sl82c105_pci_driver);
	370	}
	371
669a5db4 JG	372	static void __exit sl82c105_exit(void)
	373	{
	374	pci_unregister_driver(&sl82c105_pci_driver);
	375	}
	376
669a5db4 JG	377	MODULE_AUTHOR("Alan Cox");
	378	MODULE_DESCRIPTION("low-level driver for Sl82c105");
	379	MODULE_LICENSE("GPL");
	380	MODULE_DEVICE_TABLE(pci, sl82c105);
	381	MODULE_VERSION(DRV_VERSION);
	382
	383	module_init(sl82c105_init);
	384	module_exit(sl82c105_exit);