[linux.git] / drivers / gpio / gpio-generic.c

/*
 * Generic driver for memory-mapped GPIO controllers.
 *
 * Copyright 2008 MontaVista Software, Inc.
 * Copyright 2008,2010 Anton Vorontsov <[email protected]>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
 * ...``                                                         ```````..
 * ..The simplest form of a GPIO controller that the driver supports is``
 *  `.just a single "data" register, where GPIO state can be read and/or `
 *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
 *        `````````
                                    ___
_/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
__________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
                                                 `....trivial..'~`.```.```
 *                                                    ```````
 *  .```````~~~~`..`.``.``.
 * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
 * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
 *  . register the device with -be`. .with a pair of set/clear-bit registers ,
 *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
 *     ``.`.``...```                  ```.. output pins are also supported.`
 *                        ^^             `````.`````````.,``~``~``~~``````
 *                                                   .                  ^^
 *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
 * .. The expectation is that in at least some cases .    ,-~~~-,
 *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
 *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
 *  ..````````......```````````                             \o_
 *                                                           |
 *                              ^^                          / \
 *
 *           ...`````~~`.....``.`..........``````.`.``.```........``.
 *            `  8, 16, 32 and 64 bits registers are supported, and``.
 *            . the number of GPIOs is determined by the width of   ~
 *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
 *               `.......````.```
 */

#include <linux/init.h>
#include <linux/err.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/basic_mmio_gpio.h>

static void bgpio_write8(void __iomem *reg, unsigned long data)
{
	writeb(data, reg);
}

static unsigned long bgpio_read8(void __iomem *reg)
{
	return readb(reg);
}

static void bgpio_write16(void __iomem *reg, unsigned long data)
{
	writew(data, reg);
}

static unsigned long bgpio_read16(void __iomem *reg)
{
	return readw(reg);
}

static void bgpio_write32(void __iomem *reg, unsigned long data)
{
	writel(data, reg);
}

static unsigned long bgpio_read32(void __iomem *reg)
{
	return readl(reg);
}

#if BITS_PER_LONG >= 64
static void bgpio_write64(void __iomem *reg, unsigned long data)
{
	writeq(data, reg);
}

static unsigned long bgpio_read64(void __iomem *reg)
{
	return readq(reg);
}
#endif /* BITS_PER_LONG >= 64 */

static void bgpio_write16be(void __iomem *reg, unsigned long data)
{
	iowrite16be(data, reg);
}

static unsigned long bgpio_read16be(void __iomem *reg)
{
	return ioread16be(reg);
}

static void bgpio_write32be(void __iomem *reg, unsigned long data)
{
	iowrite32be(data, reg);
}

static unsigned long bgpio_read32be(void __iomem *reg)
{
	return ioread32be(reg);
}

static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
{
	return 1 << pin;
}

static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
				       unsigned int pin)
{
	return 1 << (bgc->bits - 1 - pin);
}

static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
}

static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	if (val)
		bgc->data |= mask;
	else
		bgc->data &= ~mask;

	bgc->write_reg(bgc->reg_dat, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
				 int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);

	if (val)
		bgc->write_reg(bgc->reg_set, mask);
	else
		bgc->write_reg(bgc->reg_clr, mask);
}

static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	if (val)
		bgc->data |= mask;
	else
		bgc->data &= ~mask;

	bgc->write_reg(bgc->reg_set, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	return 0;
}

static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
				int val)
{
	gc->set(gc, gpio, val);

	return 0;
}

static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	gc->set(gc, gpio, val);

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir |= bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir |= bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	gc->set(gc, gpio, val);

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_setup_accessors(struct device *dev,
				 struct bgpio_chip *bgc,
				 bool bit_be,
				 bool byte_be)
{

	switch (bgc->bits) {
	case 8:
		bgc->read_reg	= bgpio_read8;
		bgc->write_reg	= bgpio_write8;
		break;
	case 16:
		if (byte_be) {
			bgc->read_reg	= bgpio_read16be;
			bgc->write_reg	= bgpio_write16be;
		} else {
			bgc->read_reg	= bgpio_read16;
			bgc->write_reg	= bgpio_write16;
		}
		break;
	case 32:
		if (byte_be) {
			bgc->read_reg	= bgpio_read32be;
			bgc->write_reg	= bgpio_write32be;
		} else {
			bgc->read_reg	= bgpio_read32;
			bgc->write_reg	= bgpio_write32;
		}
		break;
#if BITS_PER_LONG >= 64
	case 64:
		if (byte_be) {
			dev_err(dev,
				"64 bit big endian byte order unsupported\n");
			return -EINVAL;
		} else {
			bgc->read_reg	= bgpio_read64;
			bgc->write_reg	= bgpio_write64;
		}
		break;
#endif /* BITS_PER_LONG >= 64 */
	default:
		dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
		return -EINVAL;
	}

	bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;

	return 0;
}

/*
 * Create the device and allocate the resources.  For setting GPIO's there are
 * three supported configurations:
 *
 *	- single input/output register resource (named "dat").
 *	- set/clear pair (named "set" and "clr").
 *	- single output register resource and single input resource ("set" and
 *	dat").
 *
 * For the single output register, this drives a 1 by setting a bit and a zero
 * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
 * in the set register and clears it by setting a bit in the clear register.
 * The configuration is detected by which resources are present.
 *
 * For setting the GPIO direction, there are three supported configurations:
 *
 *	- simple bidirection GPIO that requires no configuration.
 *	- an output direction register (named "dirout") where a 1 bit
 *	indicates the GPIO is an output.
 *	- an input direction register (named "dirin") where a 1 bit indicates
 *	the GPIO is an input.
 */
static int bgpio_setup_io(struct bgpio_chip *bgc,
			  void __iomem *dat,
			  void __iomem *set,
			  void __iomem *clr)
{

	bgc->reg_dat = dat;
	if (!bgc->reg_dat)
		return -EINVAL;

	if (set && clr) {
		bgc->reg_set = set;
		bgc->reg_clr = clr;
		bgc->gc.set = bgpio_set_with_clear;
	} else if (set && !clr) {
		bgc->reg_set = set;
		bgc->gc.set = bgpio_set_set;
	} else {
		bgc->gc.set = bgpio_set;
	}

	bgc->gc.get = bgpio_get;

	return 0;
}

static int bgpio_setup_direction(struct bgpio_chip *bgc,
				 void __iomem *dirout,
				 void __iomem *dirin)
{
	if (dirout && dirin) {
		return -EINVAL;
	} else if (dirout) {
		bgc->reg_dir = dirout;
		bgc->gc.direction_output = bgpio_dir_out;
		bgc->gc.direction_input = bgpio_dir_in;
	} else if (dirin) {
		bgc->reg_dir = dirin;
		bgc->gc.direction_output = bgpio_dir_out_inv;
		bgc->gc.direction_input = bgpio_dir_in_inv;
	} else {
		bgc->gc.direction_output = bgpio_simple_dir_out;
		bgc->gc.direction_input = bgpio_simple_dir_in;
	}

	return 0;
}

static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
{
	if (gpio_pin < chip->ngpio)
		return 0;

	return -EINVAL;
}

int bgpio_remove(struct bgpio_chip *bgc)
{
	gpiochip_remove(&bgc->gc);
	return 0;
}
EXPORT_SYMBOL_GPL(bgpio_remove);

int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags)
{
	int ret;

	if (!is_power_of_2(sz))
		return -EINVAL;

	bgc->bits = sz * 8;
	if (bgc->bits > BITS_PER_LONG)
		return -EINVAL;

	spin_lock_init(&bgc->lock);
	bgc->gc.dev = dev;
	bgc->gc.label = dev_name(dev);
	bgc->gc.base = -1;
	bgc->gc.ngpio = bgc->bits;
	bgc->gc.request = bgpio_request;

	ret = bgpio_setup_io(bgc, dat, set, clr);
	if (ret)
		return ret;

	ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
				    flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	if (ret)
		return ret;

	ret = bgpio_setup_direction(bgc, dirout, dirin);
	if (ret)
		return ret;

	bgc->data = bgc->read_reg(bgc->reg_dat);
	if (bgc->gc.set == bgpio_set_set &&
			!(flags & BGPIOF_UNREADABLE_REG_SET))
		bgc->data = bgc->read_reg(bgc->reg_set);
	if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
		bgc->dir = bgc->read_reg(bgc->reg_dir);

	return ret;
}
EXPORT_SYMBOL_GPL(bgpio_init);

#ifdef CONFIG_GPIO_GENERIC_PLATFORM

static void __iomem *bgpio_map(struct platform_device *pdev,
			       const char *name,
			       resource_size_t sane_sz,
			       int *err)
{
	struct device *dev = &pdev->dev;
	struct resource *r;
	resource_size_t start;
	resource_size_t sz;
	void __iomem *ret;

	*err = 0;

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	if (!r)
		return NULL;

	sz = resource_size(r);
	if (sz != sane_sz) {
		*err = -EINVAL;
		return NULL;
	}

	start = r->start;
	if (!devm_request_mem_region(dev, start, sz, r->name)) {
		*err = -EBUSY;
		return NULL;
	}

	ret = devm_ioremap(dev, start, sz);
	if (!ret) {
		*err = -ENOMEM;
		return NULL;
	}

	return ret;
}

static int bgpio_pdev_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *r;
	void __iomem *dat;
	void __iomem *set;
	void __iomem *clr;
	void __iomem *dirout;
	void __iomem *dirin;
	unsigned long sz;
	unsigned long flags = pdev->id_entry->driver_data;
	int err;
	struct bgpio_chip *bgc;
	struct bgpio_pdata *pdata = dev_get_platdata(dev);

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
	if (!r)
		return -EINVAL;

	sz = resource_size(r);

	dat = bgpio_map(pdev, "dat", sz, &err);
	if (!dat)
		return err ? err : -EINVAL;

	set = bgpio_map(pdev, "set", sz, &err);
	if (err)
		return err;

	clr = bgpio_map(pdev, "clr", sz, &err);
	if (err)
		return err;

	dirout = bgpio_map(pdev, "dirout", sz, &err);
	if (err)
		return err;

	dirin = bgpio_map(pdev, "dirin", sz, &err);
	if (err)
		return err;

	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
	if (!bgc)
		return -ENOMEM;

	err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
	if (err)
		return err;

	if (pdata) {
		if (pdata->label)
			bgc->gc.label = pdata->label;
		bgc->gc.base = pdata->base;
		if (pdata->ngpio > 0)
			bgc->gc.ngpio = pdata->ngpio;
	}

	platform_set_drvdata(pdev, bgc);

	return gpiochip_add(&bgc->gc);
}

static int bgpio_pdev_remove(struct platform_device *pdev)
{
	struct bgpio_chip *bgc = platform_get_drvdata(pdev);

	return bgpio_remove(bgc);
}

static const struct platform_device_id bgpio_id_table[] = {
	{
		.name		= "basic-mmio-gpio",
		.driver_data	= 0,
	}, {
		.name		= "basic-mmio-gpio-be",
		.driver_data	= BGPIOF_BIG_ENDIAN,
	},
	{ }
};
MODULE_DEVICE_TABLE(platform, bgpio_id_table);

static struct platform_driver bgpio_driver = {
	.driver = {
		.name = "basic-mmio-gpio",
	},
	.id_table = bgpio_id_table,
	.probe = bgpio_pdev_probe,
	.remove = bgpio_pdev_remove,
};

module_platform_driver(bgpio_driver);

#endif /* CONFIG_GPIO_GENERIC_PLATFORM */

MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
MODULE_AUTHOR("Anton Vorontsov <[email protected]>");
MODULE_LICENSE("GPL");
Commit	Line	Data
aeec56e3	1	/*
c103de24	2	* Generic driver for memory-mapped GPIO controllers.
aeec56e3 AV	3	*
	4	* Copyright 2008 MontaVista Software, Inc.
	5	* Copyright 2008,2010 Anton Vorontsov <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	* ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
	13	* ...`` ```````..
	14	* ..The simplest form of a GPIO controller that the driver supports is``
	15	* `.just a single "data" register, where GPIO state can be read and/or `
	16	* `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
	17	* `````````
	18	___
	19	_/~~\|___/~\| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
	20	__________\|~$@~~~ %~ /ooooo*o\ .. Implementing such a GPIO .
	21	o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
	22	`....trivial..'~`.```.```
	23	* ```````
	24	* .```````~~~~`..`.``.``.
	25	* . The driver supports `... ,..```.`~~~```````````````....````.``,,
	26	* . big-endian notation, just`. .. A bit more sophisticated controllers ,
	27	* . register the device with -be`. .with a pair of set/clear-bit registers ,
	28	* `.. suffix. ```~~`````....`.` . affecting the data register and the .`
	29	* ``.`.``...``` ```.. output pins are also supported.`
	30	* ^^ `````.`````````.,``~``~``~~``````
	31	* . ^^
	32	* ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
	33	* .. The expectation is that in at least some cases . ,-~~~-,
	34	* .this will be used with roll-your-own ASIC/FPGA .` \ /
	35	* .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
	36	* ..````````......``````````` \o_
	37	* \|
	38	* ^^ / \
	39	*
	40	* ...`````~~`.....``.`..........``````.`.``.```........``.
	41	* ` 8, 16, 32 and 64 bits registers are supported, and``.
	42	* . the number of GPIOs is determined by the width of ~
	43	* .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
	44	* `.......````.```
	45	*/
	46
	47	#include <linux/init.h>
280df6b3	48	#include <linux/err.h>
aeec56e3 AV	49	#include <linux/bug.h>
	50	#include <linux/kernel.h>
	51	#include <linux/module.h>
	52	#include <linux/spinlock.h>
	53	#include <linux/compiler.h>
	54	#include <linux/types.h>
	55	#include <linux/errno.h>
	56	#include <linux/log2.h>
	57	#include <linux/ioport.h>
	58	#include <linux/io.h>
	59	#include <linux/gpio.h>
	60	#include <linux/slab.h>
	61	#include <linux/platform_device.h>
	62	#include <linux/mod_devicetable.h>
	63	#include <linux/basic_mmio_gpio.h>
	64
8467afec	65	static void bgpio_write8(void __iomem *reg, unsigned long data)
aeec56e3	66	{
fd996235	67	writeb(data, reg);
aeec56e3 AV	68	}
aeec56e3 AV	69
8467afec	70	static unsigned long bgpio_read8(void __iomem *reg)
aeec56e3	71	{
fd996235	72	return readb(reg);
8467afec JI	73	}
	74
	75	static void bgpio_write16(void __iomem *reg, unsigned long data)
	76	{
fd996235	77	writew(data, reg);
8467afec JI	78	}
	79
	80	static unsigned long bgpio_read16(void __iomem *reg)
	81	{
fd996235	82	return readw(reg);
8467afec JI	83	}
	84
	85	static void bgpio_write32(void __iomem *reg, unsigned long data)
	86	{
fd996235	87	writel(data, reg);
8467afec JI	88	}
	89
	90	static unsigned long bgpio_read32(void __iomem *reg)
	91	{
fd996235	92	return readl(reg);
8467afec JI	93	}
8467afec JI	94
aeec56e3	95	#if BITS_PER_LONG >= 64
8467afec JI	96	static void bgpio_write64(void __iomem *reg, unsigned long data)
8467afec JI	97	{
fd996235	98	writeq(data, reg);
8467afec JI	99	}
	100
	101	static unsigned long bgpio_read64(void __iomem *reg)
	102	{
fd996235	103	return readq(reg);
aeec56e3	104	}
8467afec	105	#endif /* BITS_PER_LONG >= 64 */
aeec56e3	106
2b78f1e1 AL	107	static void bgpio_write16be(void __iomem *reg, unsigned long data)
	108	{
	109	iowrite16be(data, reg);
	110	}
	111
	112	static unsigned long bgpio_read16be(void __iomem *reg)
	113	{
	114	return ioread16be(reg);
	115	}
	116
	117	static void bgpio_write32be(void __iomem *reg, unsigned long data)
	118	{
	119	iowrite32be(data, reg);
	120	}
	121
	122	static unsigned long bgpio_read32be(void __iomem *reg)
	123	{
	124	return ioread32be(reg);
	125	}
	126
aeec56e3 AV	127	static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
aeec56e3 AV	128	{
8467afec JI	129	return 1 << pin;
	130	}
	131
	132	static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
	133	unsigned int pin)
	134	{
	135	return 1 << (bgc->bits - 1 - pin);
aeec56e3 AV	136	}
	137
	138	static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
	139	{
	140	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	141
25b35da7	142	return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
aeec56e3 AV	143	}
	144
	145	static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	146	{
	147	struct bgpio_chip *bgc = to_bgpio_chip(gc);
8467afec	148	unsigned long mask = bgc->pin2mask(bgc, gpio);
aeec56e3 AV	149	unsigned long flags;
aeec56e3 AV	150
aeec56e3 AV	151	spin_lock_irqsave(&bgc->lock, flags);
	152
	153	if (val)
	154	bgc->data \|= mask;
	155	else
	156	bgc->data &= ~mask;
	157
8467afec	158	bgc->write_reg(bgc->reg_dat, bgc->data);
aeec56e3 AV	159
	160	spin_unlock_irqrestore(&bgc->lock, flags);
	161	}
	162
e027d6f9 JI	163	static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
	164	int val)
	165	{
	166	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	167	unsigned long mask = bgc->pin2mask(bgc, gpio);
	168
	169	if (val)
	170	bgc->write_reg(bgc->reg_set, mask);
	171	else
	172	bgc->write_reg(bgc->reg_clr, mask);
	173	}
	174
dd86a0cc JI	175	static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
	176	{
	177	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	178	unsigned long mask = bgc->pin2mask(bgc, gpio);
	179	unsigned long flags;
	180
	181	spin_lock_irqsave(&bgc->lock, flags);
	182
	183	if (val)
	184	bgc->data \|= mask;
	185	else
	186	bgc->data &= ~mask;
	187
	188	bgc->write_reg(bgc->reg_set, bgc->data);
	189
	190	spin_unlock_irqrestore(&bgc->lock, flags);
	191	}
	192
31029116 JI	193	static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
	194	{
	195	return 0;
	196	}
	197
	198	static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
	199	int val)
	200	{
	201	gc->set(gc, gpio, val);
	202
	203	return 0;
	204	}
	205
aeec56e3 AV	206	static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
aeec56e3 AV	207	{
31029116 JI	208	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	209	unsigned long flags;
	210
	211	spin_lock_irqsave(&bgc->lock, flags);
	212
	213	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	214	bgc->write_reg(bgc->reg_dir, bgc->dir);
	215
	216	spin_unlock_irqrestore(&bgc->lock, flags);
	217
aeec56e3 AV	218	return 0;
	219	}
	220
	221	static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	222	{
31029116 JI	223	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	224	unsigned long flags;
	225
	226	gc->set(gc, gpio, val);
	227
	228	spin_lock_irqsave(&bgc->lock, flags);
	229
	230	bgc->dir \|= bgc->pin2mask(bgc, gpio);
	231	bgc->write_reg(bgc->reg_dir, bgc->dir);
	232
	233	spin_unlock_irqrestore(&bgc->lock, flags);
	234
	235	return 0;
	236	}
	237
	238	static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
	239	{
	240	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	241	unsigned long flags;
	242
	243	spin_lock_irqsave(&bgc->lock, flags);
	244
	245	bgc->dir \|= bgc->pin2mask(bgc, gpio);
	246	bgc->write_reg(bgc->reg_dir, bgc->dir);
	247
	248	spin_unlock_irqrestore(&bgc->lock, flags);
	249
	250	return 0;
	251	}
	252
	253	static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
	254	{
	255	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	256	unsigned long flags;
	257
e027d6f9 JI	258	gc->set(gc, gpio, val);
e027d6f9 JI	259
31029116 JI	260	spin_lock_irqsave(&bgc->lock, flags);
	261
	262	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	263	bgc->write_reg(bgc->reg_dir, bgc->dir);
	264
	265	spin_unlock_irqrestore(&bgc->lock, flags);
	266
aeec56e3 AV	267	return 0;
	268	}
	269
280df6b3 JI	270	static int bgpio_setup_accessors(struct device *dev,
280df6b3 JI	271	struct bgpio_chip *bgc,
2b78f1e1 AL	272	bool bit_be,
2b78f1e1 AL	273	bool byte_be)
aeec56e3	274	{
8467afec JI	275
	276	switch (bgc->bits) {
	277	case 8:
	278	bgc->read_reg = bgpio_read8;
	279	bgc->write_reg = bgpio_write8;
	280	break;
	281	case 16:
2b78f1e1 AL	282	if (byte_be) {
	283	bgc->read_reg = bgpio_read16be;
	284	bgc->write_reg = bgpio_write16be;
	285	} else {
	286	bgc->read_reg = bgpio_read16;
	287	bgc->write_reg = bgpio_write16;
	288	}
8467afec JI	289	break;
8467afec JI	290	case 32:
2b78f1e1 AL	291	if (byte_be) {
	292	bgc->read_reg = bgpio_read32be;
	293	bgc->write_reg = bgpio_write32be;
	294	} else {
	295	bgc->read_reg = bgpio_read32;
	296	bgc->write_reg = bgpio_write32;
	297	}
8467afec JI	298	break;
	299	#if BITS_PER_LONG >= 64
	300	case 64:
2b78f1e1 AL	301	if (byte_be) {
	302	dev_err(dev,
	303	"64 bit big endian byte order unsupported\n");
	304	return -EINVAL;
	305	} else {
	306	bgc->read_reg = bgpio_read64;
	307	bgc->write_reg = bgpio_write64;
	308	}
8467afec JI	309	break;
	310	#endif /* BITS_PER_LONG >= 64 */
	311	default:
280df6b3	312	dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
8467afec JI	313	return -EINVAL;
	314	}
	315
2b78f1e1	316	bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
8467afec JI	317
	318	return 0;
	319	}
	320
e027d6f9 JI	321	/*
e027d6f9 JI	322	* Create the device and allocate the resources. For setting GPIO's there are
dd86a0cc	323	* three supported configurations:
e027d6f9	324	*
dd86a0cc	325	* - single input/output register resource (named "dat").
e027d6f9	326	* - set/clear pair (named "set" and "clr").
dd86a0cc JI	327	* - single output register resource and single input resource ("set" and
dd86a0cc JI	328	* dat").
e027d6f9 JI	329	*
	330	* For the single output register, this drives a 1 by setting a bit and a zero
	331	* by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
	332	* in the set register and clears it by setting a bit in the clear register.
	333	* The configuration is detected by which resources are present.
31029116 JI	334	*
	335	* For setting the GPIO direction, there are three supported configurations:
	336	*
	337	* - simple bidirection GPIO that requires no configuration.
	338	* - an output direction register (named "dirout") where a 1 bit
	339	* indicates the GPIO is an output.
	340	* - an input direction register (named "dirin") where a 1 bit indicates
	341	* the GPIO is an input.
e027d6f9	342	*/
280df6b3 JI	343	static int bgpio_setup_io(struct bgpio_chip *bgc,
	344	void __iomem *dat,
	345	void __iomem *set,
	346	void __iomem *clr)
8467afec	347	{
aeec56e3	348
280df6b3	349	bgc->reg_dat = dat;
aeec56e3	350	if (!bgc->reg_dat)
280df6b3	351	return -EINVAL;
e027d6f9	352
280df6b3 JI	353	if (set && clr) {
	354	bgc->reg_set = set;
	355	bgc->reg_clr = clr;
e027d6f9	356	bgc->gc.set = bgpio_set_with_clear;
280df6b3 JI	357	} else if (set && !clr) {
280df6b3 JI	358	bgc->reg_set = set;
dd86a0cc	359	bgc->gc.set = bgpio_set_set;
e027d6f9 JI	360	} else {
e027d6f9 JI	361	bgc->gc.set = bgpio_set;
aeec56e3 AV	362	}
aeec56e3 AV	363
dd86a0cc JI	364	bgc->gc.get = bgpio_get;
dd86a0cc JI	365
e027d6f9 JI	366	return 0;
	367	}
	368
280df6b3 JI	369	static int bgpio_setup_direction(struct bgpio_chip *bgc,
	370	void __iomem *dirout,
	371	void __iomem *dirin)
31029116	372	{
280df6b3	373	if (dirout && dirin) {
31029116	374	return -EINVAL;
280df6b3 JI	375	} else if (dirout) {
280df6b3 JI	376	bgc->reg_dir = dirout;
31029116 JI	377	bgc->gc.direction_output = bgpio_dir_out;
31029116 JI	378	bgc->gc.direction_input = bgpio_dir_in;
280df6b3 JI	379	} else if (dirin) {
280df6b3 JI	380	bgc->reg_dir = dirin;
31029116 JI	381	bgc->gc.direction_output = bgpio_dir_out_inv;
	382	bgc->gc.direction_input = bgpio_dir_in_inv;
	383	} else {
	384	bgc->gc.direction_output = bgpio_simple_dir_out;
	385	bgc->gc.direction_input = bgpio_simple_dir_in;
	386	}
	387
	388	return 0;
	389	}
	390
7b42e3db AF	391	static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
	392	{
	393	if (gpio_pin < chip->ngpio)
	394	return 0;
	395
	396	return -EINVAL;
	397	}
	398
4f5b0480	399	int bgpio_remove(struct bgpio_chip *bgc)
280df6b3	400	{
9f5132ae	401	gpiochip_remove(&bgc->gc);
9f5132ae	402	return 0;
280df6b3 JI	403	}
	404	EXPORT_SYMBOL_GPL(bgpio_remove);
	405
4f5b0480 RK	406	int bgpio_init(struct bgpio_chip bgc, struct device dev,
	407	unsigned long sz, void __iomem dat, void __iomem set,
	408	void __iomem clr, void __iomem dirout, void __iomem *dirin,
3e11f7b8	409	unsigned long flags)
e027d6f9	410	{
e027d6f9	411	int ret;
e027d6f9	412
280df6b3 JI	413	if (!is_power_of_2(sz))
280df6b3 JI	414	return -EINVAL;
e027d6f9	415
280df6b3 JI	416	bgc->bits = sz * 8;
	417	if (bgc->bits > BITS_PER_LONG)
	418	return -EINVAL;
	419
	420	spin_lock_init(&bgc->lock);
	421	bgc->gc.dev = dev;
	422	bgc->gc.label = dev_name(dev);
	423	bgc->gc.base = -1;
	424	bgc->gc.ngpio = bgc->bits;
7b42e3db	425	bgc->gc.request = bgpio_request;
280df6b3 JI	426
280df6b3 JI	427	ret = bgpio_setup_io(bgc, dat, set, clr);
e027d6f9 JI	428	if (ret)
e027d6f9 JI	429	return ret;
aeec56e3	430
2b78f1e1 AL	431	ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
2b78f1e1 AL	432	flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
8467afec JI	433	if (ret)
8467afec JI	434	return ret;
aeec56e3	435
280df6b3	436	ret = bgpio_setup_direction(bgc, dirout, dirin);
31029116 JI	437	if (ret)
	438	return ret;
	439
8467afec	440	bgc->data = bgc->read_reg(bgc->reg_dat);
3e11f7b8 SG	441	if (bgc->gc.set == bgpio_set_set &&
	442	!(flags & BGPIOF_UNREADABLE_REG_SET))
	443	bgc->data = bgc->read_reg(bgc->reg_set);
	444	if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
	445	bgc->dir = bgc->read_reg(bgc->reg_dir);
924e7a9f	446
280df6b3 JI	447	return ret;
	448	}
	449	EXPORT_SYMBOL_GPL(bgpio_init);
aeec56e3	450
c103de24	451	#ifdef CONFIG_GPIO_GENERIC_PLATFORM
aeec56e3	452
280df6b3 JI	453	static void __iomem bgpio_map(struct platform_device pdev,
	454	const char *name,
	455	resource_size_t sane_sz,
	456	int *err)
	457	{
	458	struct device *dev = &pdev->dev;
	459	struct resource *r;
	460	resource_size_t start;
	461	resource_size_t sz;
	462	void __iomem *ret;
	463
	464	*err = 0;
	465
	466	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	467	if (!r)
	468	return NULL;
	469
	470	sz = resource_size(r);
	471	if (sz != sane_sz) {
	472	*err = -EINVAL;
	473	return NULL;
	474	}
	475
	476	start = r->start;
	477	if (!devm_request_mem_region(dev, start, sz, r->name)) {
	478	*err = -EBUSY;
	479	return NULL;
	480	}
	481
	482	ret = devm_ioremap(dev, start, sz);
	483	if (!ret) {
	484	*err = -ENOMEM;
	485	return NULL;
	486	}
aeec56e3 AV	487
	488	return ret;
	489	}
	490
3836309d	491	static int bgpio_pdev_probe(struct platform_device *pdev)
280df6b3 JI	492	{
	493	struct device *dev = &pdev->dev;
	494	struct resource *r;
	495	void __iomem *dat;
	496	void __iomem *set;
	497	void __iomem *clr;
	498	void __iomem *dirout;
	499	void __iomem *dirin;
	500	unsigned long sz;
19338530	501	unsigned long flags = pdev->id_entry->driver_data;
280df6b3 JI	502	int err;
	503	struct bgpio_chip *bgc;
	504	struct bgpio_pdata *pdata = dev_get_platdata(dev);
	505
	506	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
	507	if (!r)
	508	return -EINVAL;
	509
	510	sz = resource_size(r);
	511
	512	dat = bgpio_map(pdev, "dat", sz, &err);
	513	if (!dat)
	514	return err ? err : -EINVAL;
	515
	516	set = bgpio_map(pdev, "set", sz, &err);
	517	if (err)
	518	return err;
	519
	520	clr = bgpio_map(pdev, "clr", sz, &err);
	521	if (err)
	522	return err;
	523
	524	dirout = bgpio_map(pdev, "dirout", sz, &err);
	525	if (err)
	526	return err;
	527
	528	dirin = bgpio_map(pdev, "dirin", sz, &err);
	529	if (err)
	530	return err;
	531
280df6b3 JI	532	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
	533	if (!bgc)
	534	return -ENOMEM;
	535
3e11f7b8	536	err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
280df6b3 JI	537	if (err)
	538	return err;
	539
	540	if (pdata) {
781f6d71 PM	541	if (pdata->label)
781f6d71 PM	542	bgc->gc.label = pdata->label;
280df6b3 JI	543	bgc->gc.base = pdata->base;
	544	if (pdata->ngpio > 0)
	545	bgc->gc.ngpio = pdata->ngpio;
	546	}
	547
	548	platform_set_drvdata(pdev, bgc);
	549
	550	return gpiochip_add(&bgc->gc);
	551	}
	552
206210ce	553	static int bgpio_pdev_remove(struct platform_device *pdev)
aeec56e3	554	{
4ddb8ae2	555	struct bgpio_chip *bgc = platform_get_drvdata(pdev);
aeec56e3	556
280df6b3	557	return bgpio_remove(bgc);
aeec56e3 AV	558	}
	559
	560	static const struct platform_device_id bgpio_id_table[] = {
19338530 AS	561	{
	562	.name = "basic-mmio-gpio",
	563	.driver_data = 0,
	564	}, {
	565	.name = "basic-mmio-gpio-be",
	566	.driver_data = BGPIOF_BIG_ENDIAN,
	567	},
	568	{ }
aeec56e3 AV	569	};
	570	MODULE_DEVICE_TABLE(platform, bgpio_id_table);
	571
	572	static struct platform_driver bgpio_driver = {
	573	.driver = {
	574	.name = "basic-mmio-gpio",
	575	},
	576	.id_table = bgpio_id_table,
280df6b3	577	.probe = bgpio_pdev_probe,
8283c4ff	578	.remove = bgpio_pdev_remove,
aeec56e3 AV	579	};
aeec56e3 AV	580
6f61415e	581	module_platform_driver(bgpio_driver);
280df6b3	582
c103de24	583	#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
aeec56e3 AV	584
	585	MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
	586	MODULE_AUTHOR("Anton Vorontsov <[email protected]>");
	587	MODULE_LICENSE("GPL");