[linux.git] / drivers / net / spider_net.h

/*
 * Network device driver for Cell Processor-Based Blade and Celleb platform
 *
 * (C) Copyright IBM Corp. 2005
 * (C) Copyright 2006 TOSHIBA CORPORATION
 *
 * Authors : Utz Bacher <[email protected]>
 *           Jens Osterkamp <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _SPIDER_NET_H
#define _SPIDER_NET_H

#define VERSION "2.0 B"

#include "sungem_phy.h"

extern int spider_net_stop(struct net_device *netdev);
extern int spider_net_open(struct net_device *netdev);

extern const struct ethtool_ops spider_net_ethtool_ops;

extern char spider_net_driver_name[];

#define SPIDER_NET_MAX_FRAME			2312
#define SPIDER_NET_MAX_MTU			2294
#define SPIDER_NET_MIN_MTU			64

#define SPIDER_NET_RXBUF_ALIGN			128

#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT	256
#define SPIDER_NET_RX_DESCRIPTORS_MIN		16
#define SPIDER_NET_RX_DESCRIPTORS_MAX		512

#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT	256
#define SPIDER_NET_TX_DESCRIPTORS_MIN		16
#define SPIDER_NET_TX_DESCRIPTORS_MAX		512

#define SPIDER_NET_TX_TIMER			(HZ/5)
#define SPIDER_NET_ANEG_TIMER			(HZ)
#define SPIDER_NET_ANEG_TIMEOUT			2

#define SPIDER_NET_RX_CSUM_DEFAULT		1

#define SPIDER_NET_WATCHDOG_TIMEOUT		50*HZ
#define SPIDER_NET_NAPI_WEIGHT			64

#define SPIDER_NET_FIRMWARE_SEQS	6
#define SPIDER_NET_FIRMWARE_SEQWORDS	1024
#define SPIDER_NET_FIRMWARE_LEN		(SPIDER_NET_FIRMWARE_SEQS * \
					 SPIDER_NET_FIRMWARE_SEQWORDS * \
					 sizeof(u32))
#define SPIDER_NET_FIRMWARE_NAME	"spider_fw.bin"

/** spider_net SMMIO registers */
#define SPIDER_NET_GHIINT0STS		0x00000000
#define SPIDER_NET_GHIINT1STS		0x00000004
#define SPIDER_NET_GHIINT2STS		0x00000008
#define SPIDER_NET_GHIINT0MSK		0x00000010
#define SPIDER_NET_GHIINT1MSK		0x00000014
#define SPIDER_NET_GHIINT2MSK		0x00000018

#define SPIDER_NET_GRESUMINTNUM		0x00000020
#define SPIDER_NET_GREINTNUM		0x00000024

#define SPIDER_NET_GFFRMNUM		0x00000028
#define SPIDER_NET_GFAFRMNUM		0x0000002c
#define SPIDER_NET_GFBFRMNUM		0x00000030
#define SPIDER_NET_GFCFRMNUM		0x00000034
#define SPIDER_NET_GFDFRMNUM		0x00000038

/* clear them (don't use it) */
#define SPIDER_NET_GFREECNNUM		0x0000003c
#define SPIDER_NET_GONETIMENUM		0x00000040

#define SPIDER_NET_GTOUTFRMNUM		0x00000044

#define SPIDER_NET_GTXMDSET		0x00000050
#define SPIDER_NET_GPCCTRL		0x00000054
#define SPIDER_NET_GRXMDSET		0x00000058
#define SPIDER_NET_GIPSECINIT		0x0000005c
#define SPIDER_NET_GFTRESTRT		0x00000060
#define SPIDER_NET_GRXDMAEN		0x00000064
#define SPIDER_NET_GMRWOLCTRL		0x00000068
#define SPIDER_NET_GPCWOPCMD		0x0000006c
#define SPIDER_NET_GPCROPCMD		0x00000070
#define SPIDER_NET_GTTFRMCNT		0x00000078
#define SPIDER_NET_GTESTMD		0x0000007c

#define SPIDER_NET_GSINIT		0x00000080
#define SPIDER_NET_GSnPRGADR		0x00000084
#define SPIDER_NET_GSnPRGDAT		0x00000088

#define SPIDER_NET_GMACOPEMD		0x00000100
#define SPIDER_NET_GMACLENLMT		0x00000108
#define SPIDER_NET_GMACST		0x00000110
#define SPIDER_NET_GMACINTEN		0x00000118
#define SPIDER_NET_GMACPHYCTRL		0x00000120

#define SPIDER_NET_GMACAPAUSE		0x00000154
#define SPIDER_NET_GMACTXPAUSE		0x00000164

#define SPIDER_NET_GMACMODE		0x000001b0
#define SPIDER_NET_GMACBSTLMT		0x000001b4

#define SPIDER_NET_GMACUNIMACU		0x000001c0
#define SPIDER_NET_GMACUNIMACL		0x000001c8

#define SPIDER_NET_GMRMHFILnR		0x00000400
#define SPIDER_NET_MULTICAST_HASHES	256

#define SPIDER_NET_GMRUAFILnR		0x00000500
#define SPIDER_NET_GMRUA0FIL15R		0x00000578

#define SPIDER_NET_GTTQMSK		0x00000934

/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
 * 0x00000b.. for DMA controller B, etc. */
#define SPIDER_NET_GDADCHA		0x00000a00
#define SPIDER_NET_GDADMACCNTR		0x00000a04
#define SPIDER_NET_GDACTDPA		0x00000a08
#define SPIDER_NET_GDACTDCNT		0x00000a0c
#define SPIDER_NET_GDACDBADDR		0x00000a20
#define SPIDER_NET_GDACDBSIZE		0x00000a24
#define SPIDER_NET_GDACNEXTDA		0x00000a28
#define SPIDER_NET_GDACCOMST		0x00000a2c
#define SPIDER_NET_GDAWBCOMST		0x00000a30
#define SPIDER_NET_GDAWBRSIZE		0x00000a34
#define SPIDER_NET_GDAWBVSIZE		0x00000a38
#define SPIDER_NET_GDAWBTRST		0x00000a3c
#define SPIDER_NET_GDAWBTRERR		0x00000a40

/* TX DMA controller registers */
#define SPIDER_NET_GDTDCHA		0x00000e00
#define SPIDER_NET_GDTDMACCNTR		0x00000e04
#define SPIDER_NET_GDTCDPA		0x00000e08
#define SPIDER_NET_GDTDMASEL		0x00000e14

#define SPIDER_NET_ECMODE		0x00000f00
/* clock and reset control register */
#define SPIDER_NET_CKRCTRL		0x00000ff0

/** SCONFIG registers */
#define SPIDER_NET_SCONFIG_IOACTE	0x00002810

/** interrupt mask registers */
#define SPIDER_NET_INT0_MASK_VALUE	0x3f7fe2c7
#define SPIDER_NET_INT1_MASK_VALUE	0xffff7ff7
/* no MAC aborts -> auto retransmission */
#define SPIDER_NET_INT2_MASK_VALUE	0xffef7ff1

/* we rely on flagged descriptor interrupts */
#define SPIDER_NET_FRAMENUM_VALUE	0x00000000
/* set this first, then the FRAMENUM_VALUE */
#define SPIDER_NET_GFXFRAMES_VALUE	0x00000000

#define SPIDER_NET_STOP_SEQ_VALUE	0x00000000
#define SPIDER_NET_RUN_SEQ_VALUE	0x0000007e

#define SPIDER_NET_PHY_CTRL_VALUE	0x00040040
/* #define SPIDER_NET_PHY_CTRL_VALUE	0x01070080*/
#define SPIDER_NET_RXMODE_VALUE		0x00000011
/* auto retransmission in case of MAC aborts */
#define SPIDER_NET_TXMODE_VALUE		0x00010000
#define SPIDER_NET_RESTART_VALUE	0x00000000
#define SPIDER_NET_WOL_VALUE		0x00001111
#if 0
#define SPIDER_NET_WOL_VALUE		0x00000000
#endif
#define SPIDER_NET_IPSECINIT_VALUE	0x6f716f71

/* pause frames: automatic, no upper retransmission count */
/* outside loopback mode: ETOMOD signal dont matter, not connected */
/* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */
#define SPIDER_NET_OPMODE_VALUE		0x00000067
/*#define SPIDER_NET_OPMODE_VALUE		0x001b0062*/
#define SPIDER_NET_LENLMT_VALUE		0x00000908

#define SPIDER_NET_MACAPAUSE_VALUE	0x00000800 /* about 1 ms */
#define SPIDER_NET_TXPAUSE_VALUE	0x00000000

#define SPIDER_NET_MACMODE_VALUE	0x00000001
#define SPIDER_NET_BURSTLMT_VALUE	0x00000200 /* about 16 us */

/* DMAC control register GDMACCNTR
 *
 * 1(0)				enable r/tx dma
 *  0000000				fixed to 0
 *
 *         000000			fixed to 0
 *               0(1)			en/disable descr writeback on force end
 *                0(1)			force end
 *
 *                 000000		fixed to 0
 *                       00		burst alignment: 128 bytes
 *                       11		burst alignment: 1024 bytes
 *
 *                         00000	fixed to 0
 *                              0	descr writeback size 32 bytes
 *                               0(1)	descr chain end interrupt enable
 *                                0(1)	descr status writeback enable */

/* to set RX_DMA_EN */
#define SPIDER_NET_DMA_RX_VALUE		0x80000000
#define SPIDER_NET_DMA_RX_FEND_VALUE	0x00030003
/* to set TX_DMA_EN */
#define SPIDER_NET_TX_DMA_EN           0x80000000
#define SPIDER_NET_GDTBSTA             0x00000300
#define SPIDER_NET_GDTDCEIDIS          0x00000002
#define SPIDER_NET_DMA_TX_VALUE        SPIDER_NET_TX_DMA_EN | \
                                       SPIDER_NET_GDTBSTA

#define SPIDER_NET_DMA_TX_FEND_VALUE	0x00030003

/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
#define SPIDER_NET_UA_DESCR_VALUE	0x00080000
#define SPIDER_NET_PROMISC_VALUE	0x00080000
#define SPIDER_NET_NONPROMISC_VALUE	0x00000000

#define SPIDER_NET_DMASEL_VALUE		0x00000001

#define SPIDER_NET_ECMODE_VALUE		0x00000000

#define SPIDER_NET_CKRCTRL_RUN_VALUE	0x1fff010f
#define SPIDER_NET_CKRCTRL_STOP_VALUE	0x0000010f

#define SPIDER_NET_SBIMSTATE_VALUE	0x00000000
#define SPIDER_NET_SBTMSTATE_VALUE	0x00000000

/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
 * with 1 << SPIDER_NET_... */
enum spider_net_int0_status {
	SPIDER_NET_GPHYINT = 0,
	SPIDER_NET_GMAC2INT,
	SPIDER_NET_GMAC1INT,
	SPIDER_NET_GIPSINT,
	SPIDER_NET_GFIFOINT,
	SPIDER_NET_GDMACINT,
	SPIDER_NET_GSYSINT,
	SPIDER_NET_GPWOPCMPINT,
	SPIDER_NET_GPROPCMPINT,
	SPIDER_NET_GPWFFINT,
	SPIDER_NET_GRMDADRINT,
	SPIDER_NET_GRMARPINT,
	SPIDER_NET_GRMMPINT,
	SPIDER_NET_GDTDEN0INT,
	SPIDER_NET_GDDDEN0INT,
	SPIDER_NET_GDCDEN0INT,
	SPIDER_NET_GDBDEN0INT,
	SPIDER_NET_GDADEN0INT,
	SPIDER_NET_GDTFDCINT,
	SPIDER_NET_GDDFDCINT,
	SPIDER_NET_GDCFDCINT,
	SPIDER_NET_GDBFDCINT,
	SPIDER_NET_GDAFDCINT,
	SPIDER_NET_GTTEDINT,
	SPIDER_NET_GDTDCEINT,
	SPIDER_NET_GRFDNMINT,
	SPIDER_NET_GRFCNMINT,
	SPIDER_NET_GRFBNMINT,
	SPIDER_NET_GRFANMINT,
	SPIDER_NET_GRFNMINT,
	SPIDER_NET_G1TMCNTINT,
	SPIDER_NET_GFREECNTINT
};
/* GHIINT1STS bits */
enum spider_net_int1_status {
	SPIDER_NET_GTMFLLINT = 0,
	SPIDER_NET_GRMFLLINT,
	SPIDER_NET_GTMSHTINT,
	SPIDER_NET_GDTINVDINT,
	SPIDER_NET_GRFDFLLINT,
	SPIDER_NET_GDDDCEINT,
	SPIDER_NET_GDDINVDINT,
	SPIDER_NET_GRFCFLLINT,
	SPIDER_NET_GDCDCEINT,
	SPIDER_NET_GDCINVDINT,
	SPIDER_NET_GRFBFLLINT,
	SPIDER_NET_GDBDCEINT,
	SPIDER_NET_GDBINVDINT,
	SPIDER_NET_GRFAFLLINT,
	SPIDER_NET_GDADCEINT,
	SPIDER_NET_GDAINVDINT,
	SPIDER_NET_GDTRSERINT,
	SPIDER_NET_GDDRSERINT,
	SPIDER_NET_GDCRSERINT,
	SPIDER_NET_GDBRSERINT,
	SPIDER_NET_GDARSERINT,
	SPIDER_NET_GDSERINT,
	SPIDER_NET_GDTPTERINT,
	SPIDER_NET_GDDPTERINT,
	SPIDER_NET_GDCPTERINT,
	SPIDER_NET_GDBPTERINT,
	SPIDER_NET_GDAPTERINT
};
/* GHIINT2STS bits */
enum spider_net_int2_status {
	SPIDER_NET_GPROPERINT = 0,
	SPIDER_NET_GMCTCRSNGINT,
	SPIDER_NET_GMCTLCOLINT,
	SPIDER_NET_GMCTTMOTINT,
	SPIDER_NET_GMCRCAERINT,
	SPIDER_NET_GMCRCALERINT,
	SPIDER_NET_GMCRALNERINT,
	SPIDER_NET_GMCROVRINT,
	SPIDER_NET_GMCRRNTINT,
	SPIDER_NET_GMCRRXERINT,
	SPIDER_NET_GTITCSERINT,
	SPIDER_NET_GTIFMTERINT,
	SPIDER_NET_GTIPKTRVKINT,
	SPIDER_NET_GTISPINGINT,
	SPIDER_NET_GTISADNGINT,
	SPIDER_NET_GTISPDNGINT,
	SPIDER_NET_GRIFMTERINT,
	SPIDER_NET_GRIPKTRVKINT,
	SPIDER_NET_GRISPINGINT,
	SPIDER_NET_GRISADNGINT,
	SPIDER_NET_GRISPDNGINT
};

#define SPIDER_NET_TXINT	( (1 << SPIDER_NET_GDTFDCINT) | \
                             (1 << SPIDER_NET_GDTDCEINT) )

/* We rely on flagged descriptor interrupts */
#define SPIDER_NET_RXINT	( (1 << SPIDER_NET_GDAFDCINT) )

#define SPIDER_NET_LINKINT	( 1 << SPIDER_NET_GMAC2INT )

#define SPIDER_NET_ERRINT	( 0xffffffff & \
				  (~SPIDER_NET_TXINT) & \
				  (~SPIDER_NET_RXINT) & \
				  (~SPIDER_NET_LINKINT) )

#define SPIDER_NET_GPREXEC			0x80000000
#define SPIDER_NET_GPRDAT_MASK			0x0000ffff

#define SPIDER_NET_DMAC_NOINTR_COMPLETE		0x00800000
#define SPIDER_NET_DMAC_NOCS			0x00040000
#define SPIDER_NET_DMAC_TCP			0x00020000
#define SPIDER_NET_DMAC_UDP			0x00030000
#define SPIDER_NET_TXDCEST			0x08000000

#define SPIDER_NET_DESCR_IND_PROC_MASK		0xF0000000
#define SPIDER_NET_DESCR_COMPLETE		0x00000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_RESPONSE_ERROR		0x10000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_PROTECTION_ERROR	0x20000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_FRAME_END		0x40000000 /* used in rx */
#define SPIDER_NET_DESCR_FORCE_END		0x50000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_CARDOWNED		0xA0000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_NOT_IN_USE		0xF0000000
#define SPIDER_NET_DESCR_TXDESFLG		0x00800000

/* Descriptor, as defined by the hardware */
struct spider_net_hw_descr {
	u32 buf_addr;
	u32 buf_size;
	u32 next_descr_addr;
	u32 dmac_cmd_status;
	u32 result_size;
	u32 valid_size;	/* all zeroes for tx */
	u32 data_status;
	u32 data_error;	/* all zeroes for tx */
} __attribute__((aligned(32)));

struct spider_net_descr {
	struct spider_net_hw_descr *hwdescr;
	struct sk_buff *skb;
	u32 bus_addr;
	struct spider_net_descr *next;
	struct spider_net_descr *prev;
};

struct spider_net_descr_chain {
	spinlock_t lock;
	struct spider_net_descr *head;
	struct spider_net_descr *tail;
	struct spider_net_descr *ring;
	int num_desc;
	struct spider_net_hw_descr *hwring;
	dma_addr_t dma_addr;
};

/* descriptor data_status bits */
#define SPIDER_NET_RX_IPCHK		29
#define SPIDER_NET_RX_TCPCHK		28
#define SPIDER_NET_VLAN_PACKET		21
#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
					  (1 << SPIDER_NET_RX_TCPCHK) )

/* descriptor data_error bits */
#define SPIDER_NET_RX_IPCHKERR		27
#define SPIDER_NET_RX_RXTCPCHKERR	28

#define SPIDER_NET_DATA_ERR_CKSUM_MASK	(1 << SPIDER_NET_RX_IPCHKERR)

/* the cases we don't pass the packet to the stack.
 * 701b8000 would be correct, but every packets gets that flag */
#define SPIDER_NET_DESTROY_RX_FLAGS	0x700b8000

/* this will be bigger some time */
struct spider_net_options {
	int rx_csum; /* for rx: if 0 ip_summed=NONE,
			if 1 and hw has verified, ip_summed=UNNECESSARY */
};

#define SPIDER_NET_DEFAULT_MSG		( NETIF_MSG_DRV | \
					  NETIF_MSG_PROBE | \
					  NETIF_MSG_LINK | \
					  NETIF_MSG_TIMER | \
					  NETIF_MSG_IFDOWN | \
					  NETIF_MSG_IFUP | \
					  NETIF_MSG_RX_ERR | \
					  NETIF_MSG_TX_ERR | \
					  NETIF_MSG_TX_QUEUED | \
					  NETIF_MSG_INTR | \
					  NETIF_MSG_TX_DONE | \
					  NETIF_MSG_RX_STATUS | \
					  NETIF_MSG_PKTDATA | \
					  NETIF_MSG_HW | \
					  NETIF_MSG_WOL )

struct spider_net_extra_stats {
	unsigned long rx_desc_error;
	unsigned long tx_timeouts;
	unsigned long alloc_rx_skb_error;
	unsigned long rx_iommu_map_error;
	unsigned long tx_iommu_map_error;
	unsigned long rx_desc_unk_state;
};

struct spider_net_card {
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct mii_phy phy;

	int medium;

	void __iomem *regs;

	struct spider_net_descr_chain tx_chain;
	struct spider_net_descr_chain rx_chain;
	struct spider_net_descr *low_watermark;

	int aneg_count;
	struct timer_list aneg_timer;
	struct timer_list tx_timer;
	struct work_struct tx_timeout_task;
	atomic_t tx_timeout_task_counter;
	wait_queue_head_t waitq;
	int num_rx_ints;

	/* for ethtool */
	int msg_enable;
	struct net_device_stats netdev_stats;
	struct spider_net_extra_stats spider_stats;
	struct spider_net_options options;

	/* Must be last item in struct */
	struct spider_net_descr darray[0];
};

#define pr_err(fmt,arg...) \
	printk(KERN_ERR fmt ,##arg)

#endif
Commit	Line	Data
aaec0fab	1	/*
3342cf0e	2	* Network device driver for Cell Processor-Based Blade and Celleb platform
aaec0fab JO	3	*
aaec0fab JO	4	* (C) Copyright IBM Corp. 2005
3342cf0e	5	* (C) Copyright 2006 TOSHIBA CORPORATION
aaec0fab JO	6	*
	7	* Authors : Utz Bacher <[email protected]>
	8	* Jens Osterkamp <[email protected]>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2, or (at your option)
	13	* any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24
	25	#ifndef _SPIDER_NET_H
	26	#define _SPIDER_NET_H
	27
4c4bd5a9	28	#define VERSION "2.0 B"
90f10841	29
aaec0fab JO	30	#include "sungem_phy.h"
	31
	32	extern int spider_net_stop(struct net_device *netdev);
	33	extern int spider_net_open(struct net_device *netdev);
	34
7282d491	35	extern const struct ethtool_ops spider_net_ethtool_ops;
aaec0fab JO	36
	37	extern char spider_net_driver_name[];
	38
11f1a52b AB	39	#define SPIDER_NET_MAX_FRAME 2312
11f1a52b AB	40	#define SPIDER_NET_MAX_MTU 2294
aaec0fab JO	41	#define SPIDER_NET_MIN_MTU 64
	42
	43	#define SPIDER_NET_RXBUF_ALIGN 128
	44
11f1a52b	45	#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256
aaec0fab	46	#define SPIDER_NET_RX_DESCRIPTORS_MIN 16
11f1a52b	47	#define SPIDER_NET_RX_DESCRIPTORS_MAX 512
aaec0fab	48
11f1a52b	49	#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256
aaec0fab	50	#define SPIDER_NET_TX_DESCRIPTORS_MIN 16
11f1a52b AB	51	#define SPIDER_NET_TX_DESCRIPTORS_MAX 512
11f1a52b AB	52
204e5fa1	53	#define SPIDER_NET_TX_TIMER (HZ/5)
abdb66b5 KI	54	#define SPIDER_NET_ANEG_TIMER (HZ)
abdb66b5 KI	55	#define SPIDER_NET_ANEG_TIMEOUT 2
aaec0fab JO	56
	57	#define SPIDER_NET_RX_CSUM_DEFAULT 1
	58
11f1a52b AB	59	#define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ
11f1a52b AB	60	#define SPIDER_NET_NAPI_WEIGHT 64
aaec0fab	61
11f1a52b AB	62	#define SPIDER_NET_FIRMWARE_SEQS 6
	63	#define SPIDER_NET_FIRMWARE_SEQWORDS 1024
	64	#define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \
	65	SPIDER_NET_FIRMWARE_SEQWORDS * \
	66	sizeof(u32))
aaec0fab JO	67	#define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"
	68
	69	/** spider_net SMMIO registers */
	70	#define SPIDER_NET_GHIINT0STS 0x00000000
	71	#define SPIDER_NET_GHIINT1STS 0x00000004
	72	#define SPIDER_NET_GHIINT2STS 0x00000008
	73	#define SPIDER_NET_GHIINT0MSK 0x00000010
	74	#define SPIDER_NET_GHIINT1MSK 0x00000014
	75	#define SPIDER_NET_GHIINT2MSK 0x00000018
	76
	77	#define SPIDER_NET_GRESUMINTNUM 0x00000020
	78	#define SPIDER_NET_GREINTNUM 0x00000024
	79
	80	#define SPIDER_NET_GFFRMNUM 0x00000028
	81	#define SPIDER_NET_GFAFRMNUM 0x0000002c
	82	#define SPIDER_NET_GFBFRMNUM 0x00000030
	83	#define SPIDER_NET_GFCFRMNUM 0x00000034
	84	#define SPIDER_NET_GFDFRMNUM 0x00000038
	85
	86	/* clear them (don't use it) */
	87	#define SPIDER_NET_GFREECNNUM 0x0000003c
	88	#define SPIDER_NET_GONETIMENUM 0x00000040
	89
	90	#define SPIDER_NET_GTOUTFRMNUM 0x00000044
	91
	92	#define SPIDER_NET_GTXMDSET 0x00000050
	93	#define SPIDER_NET_GPCCTRL 0x00000054
	94	#define SPIDER_NET_GRXMDSET 0x00000058
	95	#define SPIDER_NET_GIPSECINIT 0x0000005c
	96	#define SPIDER_NET_GFTRESTRT 0x00000060
	97	#define SPIDER_NET_GRXDMAEN 0x00000064
	98	#define SPIDER_NET_GMRWOLCTRL 0x00000068
	99	#define SPIDER_NET_GPCWOPCMD 0x0000006c
	100	#define SPIDER_NET_GPCROPCMD 0x00000070
	101	#define SPIDER_NET_GTTFRMCNT 0x00000078
	102	#define SPIDER_NET_GTESTMD 0x0000007c
	103
	104	#define SPIDER_NET_GSINIT 0x00000080
	105	#define SPIDER_NET_GSnPRGADR 0x00000084
	106	#define SPIDER_NET_GSnPRGDAT 0x00000088
	107
	108	#define SPIDER_NET_GMACOPEMD 0x00000100
	109	#define SPIDER_NET_GMACLENLMT 0x00000108
abdb66b5	110	#define SPIDER_NET_GMACST 0x00000110
aaec0fab JO	111	#define SPIDER_NET_GMACINTEN 0x00000118
	112	#define SPIDER_NET_GMACPHYCTRL 0x00000120
	113
	114	#define SPIDER_NET_GMACAPAUSE 0x00000154
	115	#define SPIDER_NET_GMACTXPAUSE 0x00000164
	116
	117	#define SPIDER_NET_GMACMODE 0x000001b0
	118	#define SPIDER_NET_GMACBSTLMT 0x000001b4
	119
	120	#define SPIDER_NET_GMACUNIMACU 0x000001c0
	121	#define SPIDER_NET_GMACUNIMACL 0x000001c8
	122
	123	#define SPIDER_NET_GMRMHFILnR 0x00000400
	124	#define SPIDER_NET_MULTICAST_HASHES 256
	125
	126	#define SPIDER_NET_GMRUAFILnR 0x00000500
	127	#define SPIDER_NET_GMRUA0FIL15R 0x00000578
	128
b636d17a JO	129	#define SPIDER_NET_GTTQMSK 0x00000934
b636d17a JO	130
aaec0fab JO	131	/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
	132	* 0x00000b.. for DMA controller B, etc. */
	133	#define SPIDER_NET_GDADCHA 0x00000a00
	134	#define SPIDER_NET_GDADMACCNTR 0x00000a04
	135	#define SPIDER_NET_GDACTDPA 0x00000a08
	136	#define SPIDER_NET_GDACTDCNT 0x00000a0c
	137	#define SPIDER_NET_GDACDBADDR 0x00000a20
	138	#define SPIDER_NET_GDACDBSIZE 0x00000a24
	139	#define SPIDER_NET_GDACNEXTDA 0x00000a28
	140	#define SPIDER_NET_GDACCOMST 0x00000a2c
	141	#define SPIDER_NET_GDAWBCOMST 0x00000a30
	142	#define SPIDER_NET_GDAWBRSIZE 0x00000a34
	143	#define SPIDER_NET_GDAWBVSIZE 0x00000a38
	144	#define SPIDER_NET_GDAWBTRST 0x00000a3c
	145	#define SPIDER_NET_GDAWBTRERR 0x00000a40
	146
	147	/* TX DMA controller registers */
	148	#define SPIDER_NET_GDTDCHA 0x00000e00
	149	#define SPIDER_NET_GDTDMACCNTR 0x00000e04
	150	#define SPIDER_NET_GDTCDPA 0x00000e08
	151	#define SPIDER_NET_GDTDMASEL 0x00000e14
	152
	153	#define SPIDER_NET_ECMODE 0x00000f00
	154	/* clock and reset control register */
	155	#define SPIDER_NET_CKRCTRL 0x00000ff0
	156
	157	/** SCONFIG registers */
	158	#define SPIDER_NET_SCONFIG_IOACTE 0x00002810
	159
11f1a52b AB	160	/** interrupt mask registers */
	161	#define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7
	162	#define SPIDER_NET_INT1_MASK_VALUE 0xffff7ff7
aaec0fab	163	/* no MAC aborts -> auto retransmission */
11f1a52b	164	#define SPIDER_NET_INT2_MASK_VALUE 0xffef7ff1
aaec0fab	165
aaec0fab JO	166	/* we rely on flagged descriptor interrupts */
	167	#define SPIDER_NET_FRAMENUM_VALUE 0x00000000
	168	/* set this first, then the FRAMENUM_VALUE */
	169	#define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
	170
	171	#define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
	172	#define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
	173
	174	#define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
	175	/* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
	176	#define SPIDER_NET_RXMODE_VALUE 0x00000011
	177	/* auto retransmission in case of MAC aborts */
	178	#define SPIDER_NET_TXMODE_VALUE 0x00010000
	179	#define SPIDER_NET_RESTART_VALUE 0x00000000
	180	#define SPIDER_NET_WOL_VALUE 0x00001111
	181	#if 0
	182	#define SPIDER_NET_WOL_VALUE 0x00000000
	183	#endif
11f1a52b	184	#define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71
aaec0fab JO	185
	186	/* pause frames: automatic, no upper retransmission count */
	187	/* outside loopback mode: ETOMOD signal dont matter, not connected */
3342cf0e KI	188	/* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */
3342cf0e KI	189	#define SPIDER_NET_OPMODE_VALUE 0x00000067
aaec0fab JO	190	/#define SPIDER_NET_OPMODE_VALUE 0x001b0062/
	191	#define SPIDER_NET_LENLMT_VALUE 0x00000908
	192
	193	#define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
	194	#define SPIDER_NET_TXPAUSE_VALUE 0x00000000
	195
	196	#define SPIDER_NET_MACMODE_VALUE 0x00000001
	197	#define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
	198
ded8028a LV	199	/* DMAC control register GDMACCNTR
	200	*
	201	* 1(0) enable r/tx dma
aaec0fab JO	202	* 0000000 fixed to 0
	203	*
	204	* 000000 fixed to 0
	205	* 0(1) en/disable descr writeback on force end
	206	* 0(1) force end
	207	*
	208	* 000000 fixed to 0
	209	* 00 burst alignment: 128 bytes
ded8028a	210	* 11 burst alignment: 1024 bytes
aaec0fab JO	211	*
	212	* 00000 fixed to 0
	213	* 0 descr writeback size 32 bytes
	214	* 0(1) descr chain end interrupt enable
	215	* 0(1) descr status writeback enable */
	216
	217	/* to set RX_DMA_EN */
	218	#define SPIDER_NET_DMA_RX_VALUE 0x80000000
	219	#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
	220	/* to set TX_DMA_EN */
ded8028a LV	221	#define SPIDER_NET_TX_DMA_EN 0x80000000
	222	#define SPIDER_NET_GDTBSTA 0x00000300
	223	#define SPIDER_NET_GDTDCEIDIS 0x00000002
	224	#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN \| \
7bd54c86	225	SPIDER_NET_GDTBSTA
ded8028a	226
aaec0fab JO	227	#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
	228
	229	/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
	230	#define SPIDER_NET_UA_DESCR_VALUE 0x00080000
	231	#define SPIDER_NET_PROMISC_VALUE 0x00080000
	232	#define SPIDER_NET_NONPROMISC_VALUE 0x00000000
	233
	234	#define SPIDER_NET_DMASEL_VALUE 0x00000001
	235
	236	#define SPIDER_NET_ECMODE_VALUE 0x00000000
	237
	238	#define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
	239	#define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
	240
	241	#define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
	242	#define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
	243
	244	/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
	245	* with 1 << SPIDER_NET_... */
	246	enum spider_net_int0_status {
	247	SPIDER_NET_GPHYINT = 0,
	248	SPIDER_NET_GMAC2INT,
	249	SPIDER_NET_GMAC1INT,
	250	SPIDER_NET_GIPSINT,
	251	SPIDER_NET_GFIFOINT,
	252	SPIDER_NET_GDMACINT,
	253	SPIDER_NET_GSYSINT,
	254	SPIDER_NET_GPWOPCMPINT,
	255	SPIDER_NET_GPROPCMPINT,
	256	SPIDER_NET_GPWFFINT,
	257	SPIDER_NET_GRMDADRINT,
	258	SPIDER_NET_GRMARPINT,
	259	SPIDER_NET_GRMMPINT,
	260	SPIDER_NET_GDTDEN0INT,
	261	SPIDER_NET_GDDDEN0INT,
	262	SPIDER_NET_GDCDEN0INT,
	263	SPIDER_NET_GDBDEN0INT,
	264	SPIDER_NET_GDADEN0INT,
	265	SPIDER_NET_GDTFDCINT,
	266	SPIDER_NET_GDDFDCINT,
	267	SPIDER_NET_GDCFDCINT,
	268	SPIDER_NET_GDBFDCINT,
	269	SPIDER_NET_GDAFDCINT,
	270	SPIDER_NET_GTTEDINT,
	271	SPIDER_NET_GDTDCEINT,
	272	SPIDER_NET_GRFDNMINT,
	273	SPIDER_NET_GRFCNMINT,
	274	SPIDER_NET_GRFBNMINT,
	275	SPIDER_NET_GRFANMINT,
	276	SPIDER_NET_GRFNMINT,
	277	SPIDER_NET_G1TMCNTINT,
	278	SPIDER_NET_GFREECNTINT
	279	};
	280	/* GHIINT1STS bits */
	281	enum spider_net_int1_status {
	282	SPIDER_NET_GTMFLLINT = 0,
	283	SPIDER_NET_GRMFLLINT,
	284	SPIDER_NET_GTMSHTINT,
	285	SPIDER_NET_GDTINVDINT,
	286	SPIDER_NET_GRFDFLLINT,
	287	SPIDER_NET_GDDDCEINT,
	288	SPIDER_NET_GDDINVDINT,
	289	SPIDER_NET_GRFCFLLINT,
	290	SPIDER_NET_GDCDCEINT,
291	SPIDER_NET_GDCINVDINT,
292	SPIDER_NET_GRFBFLLINT,
293	SPIDER_NET_GDBDCEINT,
294	SPIDER_NET_GDBINVDINT,
295	SPIDER_NET_GRFAFLLINT,
296	SPIDER_NET_GDADCEINT,
297	SPIDER_NET_GDAINVDINT,
298	SPIDER_NET_GDTRSERINT,
299	SPIDER_NET_GDDRSERINT,
300	SPIDER_NET_GDCRSERINT,
301	SPIDER_NET_GDBRSERINT,
302	SPIDER_NET_GDARSERINT,
303	SPIDER_NET_GDSERINT,
304	SPIDER_NET_GDTPTERINT,
305	SPIDER_NET_GDDPTERINT,
306	SPIDER_NET_GDCPTERINT,
307	SPIDER_NET_GDBPTERINT,
308	SPIDER_NET_GDAPTERINT
309	};
310	/* GHIINT2STS bits */
311	enum spider_net_int2_status {
312	SPIDER_NET_GPROPERINT = 0,
313	SPIDER_NET_GMCTCRSNGINT,
314	SPIDER_NET_GMCTLCOLINT,
315	SPIDER_NET_GMCTTMOTINT,
316	SPIDER_NET_GMCRCAERINT,
317	SPIDER_NET_GMCRCALERINT,
318	SPIDER_NET_GMCRALNERINT,
319	SPIDER_NET_GMCROVRINT,
320	SPIDER_NET_GMCRRNTINT,
321	SPIDER_NET_GMCRRXERINT,
322	SPIDER_NET_GTITCSERINT,
323	SPIDER_NET_GTIFMTERINT,
324	SPIDER_NET_GTIPKTRVKINT,
325	SPIDER_NET_GTISPINGINT,
326	SPIDER_NET_GTISADNGINT,
327	SPIDER_NET_GTISPDNGINT,
328	SPIDER_NET_GRIFMTERINT,
329	SPIDER_NET_GRIPKTRVKINT,
330	SPIDER_NET_GRISPINGINT,
331	SPIDER_NET_GRISADNGINT,
332	SPIDER_NET_GRISPDNGINT
333	};
334
7bd54c86 LV	335	#define SPIDER_NET_TXINT ( (1 << SPIDER_NET_GDTFDCINT) \| \
7bd54c86 LV	336	(1 << SPIDER_NET_GDTDCEINT) )
aaec0fab	337
43932d93 LV	338	/* We rely on flagged descriptor interrupts */
43932d93 LV	339	#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) )
aaec0fab	340
abdb66b5 KI	341	#define SPIDER_NET_LINKINT ( 1 << SPIDER_NET_GMAC2INT )
abdb66b5 KI	342
11f1a52b AB	343	#define SPIDER_NET_ERRINT ( 0xffffffff & \
11f1a52b AB	344	(~SPIDER_NET_TXINT) & \
abdb66b5 KI	345	(~SPIDER_NET_RXINT) & \
abdb66b5 KI	346	(~SPIDER_NET_LINKINT) )
11f1a52b	347
bdd01503 JO	348	#define SPIDER_NET_GPREXEC 0x80000000
bdd01503 JO	349	#define SPIDER_NET_GPRDAT_MASK 0x0000ffff
aaec0fab	350
bdd01503 JO	351	#define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000
	352	#define SPIDER_NET_DMAC_NOCS 0x00040000
	353	#define SPIDER_NET_DMAC_TCP 0x00020000
	354	#define SPIDER_NET_DMAC_UDP 0x00030000
	355	#define SPIDER_NET_TXDCEST 0x08000000
	356
	357	#define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000
	358	#define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */
	359	#define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */
	360	#define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */
	361	#define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */
	362	#define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */
	363	#define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */
	364	#define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000
204e5fa1	365	#define SPIDER_NET_DESCR_TXDESFLG 0x00800000
aaec0fab	366
4cb6f9e5 LV	367	/* Descriptor, as defined by the hardware */
4cb6f9e5 LV	368	struct spider_net_hw_descr {
8e0a613b	369	u32 buf_addr;
aaec0fab	370	u32 buf_size;
8e0a613b	371	u32 next_descr_addr;
aaec0fab JO	372	u32 dmac_cmd_status;
	373	u32 result_size;
	374	u32 valid_size; /* all zeroes for tx */
	375	u32 data_status;
	376	u32 data_error; /* all zeroes for tx */
4cb6f9e5	377	} __attribute__((aligned(32)));
aaec0fab	378
4cb6f9e5 LV	379	struct spider_net_descr {
4cb6f9e5 LV	380	struct spider_net_hw_descr *hwdescr;
aaec0fab	381	struct sk_buff *skb;
11f1a52b	382	u32 bus_addr;
aaec0fab JO	383	struct spider_net_descr *next;
aaec0fab JO	384	struct spider_net_descr *prev;
4cb6f9e5	385	};
aaec0fab JO	386
aaec0fab JO	387	struct spider_net_descr_chain {
bdd01503	388	spinlock_t lock;
aaec0fab JO	389	struct spider_net_descr *head;
aaec0fab JO	390	struct spider_net_descr *tail;
d4ed8f8d LV	391	struct spider_net_descr *ring;
d4ed8f8d LV	392	int num_desc;
4cb6f9e5	393	struct spider_net_hw_descr *hwring;
d4ed8f8d	394	dma_addr_t dma_addr;
aaec0fab JO	395	};
	396
	397	/* descriptor data_status bits */
11f1a52b AB	398	#define SPIDER_NET_RX_IPCHK 29
11f1a52b AB	399	#define SPIDER_NET_RX_TCPCHK 28
aaec0fab	400	#define SPIDER_NET_VLAN_PACKET 21
11f1a52b AB	401	#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) \| \
11f1a52b AB	402	(1 << SPIDER_NET_RX_TCPCHK) )
aaec0fab JO	403
aaec0fab JO	404	/* descriptor data_error bits */
11f1a52b AB	405	#define SPIDER_NET_RX_IPCHKERR 27
	406	#define SPIDER_NET_RX_RXTCPCHKERR 28
	407
	408	#define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)
aaec0fab	409
11f1a52b AB	410	/* the cases we don't pass the packet to the stack.
	411	* 701b8000 would be correct, but every packets gets that flag */
	412	#define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000
aaec0fab	413
aaec0fab JO	414	/* this will be bigger some time */
	415	struct spider_net_options {
	416	int rx_csum; /* for rx: if 0 ip_summed=NONE,
	417	if 1 and hw has verified, ip_summed=UNNECESSARY */
	418	};
	419
	420	#define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV \| \
	421	NETIF_MSG_PROBE \| \
	422	NETIF_MSG_LINK \| \
	423	NETIF_MSG_TIMER \| \
	424	NETIF_MSG_IFDOWN \| \
	425	NETIF_MSG_IFUP \| \
	426	NETIF_MSG_RX_ERR \| \
	427	NETIF_MSG_TX_ERR \| \
	428	NETIF_MSG_TX_QUEUED \| \
	429	NETIF_MSG_INTR \| \
	430	NETIF_MSG_TX_DONE \| \
	431	NETIF_MSG_RX_STATUS \| \
	432	NETIF_MSG_PKTDATA \| \
	433	NETIF_MSG_HW \| \
	434	NETIF_MSG_WOL )
	435
9b6b0b81 JL	436	struct spider_net_extra_stats {
	437	unsigned long rx_desc_error;
	438	unsigned long tx_timeouts;
	439	unsigned long alloc_rx_skb_error;
	440	unsigned long rx_iommu_map_error;
	441	unsigned long tx_iommu_map_error;
	442	unsigned long rx_desc_unk_state;
	443	};
	444
aaec0fab JO	445	struct spider_net_card {
	446	struct net_device *netdev;
	447	struct pci_dev *pdev;
	448	struct mii_phy phy;
	449
4b23a554 JO	450	int medium;
4b23a554 JO	451
aaec0fab JO	452	void __iomem *regs;
	453
	454	struct spider_net_descr_chain tx_chain;
	455	struct spider_net_descr_chain rx_chain;
204e5fa1	456	struct spider_net_descr *low_watermark;
aaec0fab	457
abdb66b5 KI	458	int aneg_count;
abdb66b5 KI	459	struct timer_list aneg_timer;
11f1a52b	460	struct timer_list tx_timer;
aaec0fab JO	461	struct work_struct tx_timeout_task;
	462	atomic_t tx_timeout_task_counter;
	463	wait_queue_head_t waitq;
4c4bd5a9	464	int num_rx_ints;
aaec0fab JO	465
	466	/* for ethtool */
	467	int msg_enable;
d4ed8f8d	468	struct net_device_stats netdev_stats;
9b6b0b81	469	struct spider_net_extra_stats spider_stats;
d4ed8f8d	470	struct spider_net_options options;
4cb6f9e5 LV	471
	472	/* Must be last item in struct */
	473	struct spider_net_descr darray[0];
aaec0fab JO	474	};
	475
	476	#define pr_err(fmt,arg...) \
	477	printk(KERN_ERR fmt ,##arg)
	478
	479	#endif