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md: remove handling of flush_pending in md_submit_flush_data
[linux.git] / drivers / char / rocket_int.h
CommitLineData
1da177e4
LT		 1/*
2 * rocket_int.h --- internal header file for rocket.c
3 *
4 * Written by Theodore Ts'o, Copyright 1997.
5 * Copyright 1997 Comtrol Corporation.
6 *
7 */
8
9/*
10 * Definition of the types in rcktpt_type
11 */
12#define ROCKET_TYPE_NORMAL 0
13#define ROCKET_TYPE_MODEM 1
14#define ROCKET_TYPE_MODEMII 2
15#define ROCKET_TYPE_MODEMIII 3
16#define ROCKET_TYPE_PC104 4
17
69f545ea
MK		 18#include <linux/mutex.h>
19
1da177e4
LT		 20#include <asm/io.h>
21#include <asm/byteorder.h>
22
23typedef unsigned char Byte_t;
24typedef unsigned int ByteIO_t;
25
26typedef unsigned int Word_t;
27typedef unsigned int WordIO_t;
28
1da177e4
LT		 29typedef unsigned int DWordIO_t;
30
31/*
32 * Note! Normally the Linux I/O macros already take care of
33 * byte-swapping the I/O instructions. However, all accesses using
34 * sOutDW aren't really 32-bit accesses, but should be handled in byte
35 * order. Hence the use of the cpu_to_le32() macro to byte-swap
36 * things to no-op the byte swapping done by the big-endian outl()
37 * instruction.
38 */
39
1da177e4
LT		 40static inline void sOutB(unsigned short port, unsigned char value)
41{
42#ifdef ROCKET_DEBUG_IO
68562b79 43 printk(KERN_DEBUG "sOutB(%x, %x)...\n", port, value);
1da177e4
LT		 44#endif
45 outb_p(value, port);
46}
47
48static inline void sOutW(unsigned short port, unsigned short value)
49{
50#ifdef ROCKET_DEBUG_IO
68562b79 51 printk(KERN_DEBUG "sOutW(%x, %x)...\n", port, value);
1da177e4
LT		 52#endif
53 outw_p(value, port);
54}
55
457fb605 56static inline void out32(unsigned short port, Byte_t *p)
1da177e4 57{
973ea70c 58 u32 value = get_unaligned_le32(p);
1da177e4 59#ifdef ROCKET_DEBUG_IO
457fb605 60 printk(KERN_DEBUG "out32(%x, %lx)...\n", port, value);
1da177e4 61#endif
457fb605 62 outl_p(value, port);
1da177e4
LT		 63}
64
65static inline unsigned char sInB(unsigned short port)
66{
67 return inb_p(port);
68}
69
70static inline unsigned short sInW(unsigned short port)
71{
72 return inw_p(port);
73}
74
1da177e4
LT		 75/* This is used to move arrays of bytes so byte swapping isn't appropriate. */
76#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
77#define sInStrW(port, addr, count) if (count) insw(port, addr, count)
78
79#define CTL_SIZE 8
80#define AIOP_CTL_SIZE 4
81#define CHAN_AIOP_SIZE 8
82#define MAX_PORTS_PER_AIOP 8
83#define MAX_AIOPS_PER_BOARD 4
84#define MAX_PORTS_PER_BOARD 32
85
86/* Bus type ID */
87#define isISA 0
88#define isPCI 1
89#define isMC 2
90
91/* Controller ID numbers */
92#define CTLID_NULL -1 /* no controller exists */
93#define CTLID_0001 0x0001 /* controller release 1 */
94
95/* AIOP ID numbers, identifies AIOP type implementing channel */
96#define AIOPID_NULL -1 /* no AIOP or channel exists */
97#define AIOPID_0001 0x0001 /* AIOP release 1 */
98
1da177e4
LT		 99/************************************************************************
100 Global Register Offsets - Direct Access - Fixed values
101************************************************************************/
102
103#define _CMD_REG 0x38 /* Command Register 8 Write */
104#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
105#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
106#define _UNUSED 0x3B /* Unused 8 */
107#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
108#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
109
110/************************************************************************
111 Channel Register Offsets for 1st channel in AIOP - Direct Access
112************************************************************************/
113#define _TD0 0x00 /* Transmit Data 16 Write */
114#define _RD0 0x00 /* Receive Data 16 Read */
115#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
116#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
117#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
118
119/************************************************************************
120 Tx Control Register Offsets - Indexed - External - Fixed
121************************************************************************/
122#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
123#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
124#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
125#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
126#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
127#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
128
129/************************************************************************
130Memory Controller Register Offsets - Indexed - External - Fixed
131************************************************************************/
132#define _RX_FIFO 0x000 /* Rx FIFO */
133#define _TX_FIFO 0x800 /* Tx FIFO */
134#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
135#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
136#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
137#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
138#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
139#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
140
141#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
142#define TXFIFO_SIZE 255 /* size of Tx FIFO */
143#define RXFIFO_SIZE 1023 /* size of Rx FIFO */
144
145/************************************************************************
146Tx Priority Buffer - Indexed - External - Fixed
147************************************************************************/
148#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
149#define TXP_SIZE 0x20 /* 32 bytes */
150
151/************************************************************************
152Channel Register Offsets - Indexed - Internal - Fixed
153************************************************************************/
154
155#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
156#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
157#define _BAUD 0xFF4 /* Baud Rate 16 Write */
158#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
159
160#define STMBREAK 0x08 /* BREAK */
161#define STMFRAME 0x04 /* framing error */
162#define STMRCVROVR 0x02 /* receiver over run error */
163#define STMPARITY 0x01 /* parity error */
164#define STMERROR (STMBREAK | STMFRAME | STMPARITY)
165#define STMBREAKH 0x800 /* BREAK */
166#define STMFRAMEH 0x400 /* framing error */
167#define STMRCVROVRH 0x200 /* receiver over run error */
168#define STMPARITYH 0x100 /* parity error */
169#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
170
171#define CTS_ACT 0x20 /* CTS input asserted */
172#define DSR_ACT 0x10 /* DSR input asserted */
173#define CD_ACT 0x08 /* CD input asserted */
174#define TXFIFOMT 0x04 /* Tx FIFO is empty */
175#define TXSHRMT 0x02 /* Tx shift register is empty */
176#define RDA 0x01 /* Rx data available */
177#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
178
179#define STATMODE 0x8000 /* status mode enable bit */
180#define RXFOVERFL 0x2000 /* receive FIFO overflow */
181#define RX2MATCH 0x1000 /* receive compare byte 2 match */
182#define RX1MATCH 0x0800 /* receive compare byte 1 match */
183#define RXBREAK 0x0400 /* received BREAK */
184#define RXFRAME 0x0200 /* received framing error */
185#define RXPARITY 0x0100 /* received parity error */
186#define STATERROR (RXBREAK | RXFRAME | RXPARITY)
187
188#define CTSFC_EN 0x80 /* CTS flow control enable bit */
189#define RTSTOG_EN 0x40 /* RTS toggle enable bit */
190#define TXINT_EN 0x10 /* transmit interrupt enable */
191#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
192#define PARITY_EN 0x04 /* enable parity (0 = no parity) */
193#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
194#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
195
196#define SETBREAK 0x10 /* send break condition (must clear) */
197#define LOCALLOOP 0x08 /* local loopback set for test */
198#define SET_DTR 0x04 /* assert DTR */
199#define SET_RTS 0x02 /* assert RTS */
200#define TX_ENABLE 0x01 /* enable transmitter */
201
202#define RTSFC_EN 0x40 /* RTS flow control enable */
203#define RXPROC_EN 0x20 /* receive processor enable */
204#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
205#define TRIG_1 0x08 /* trigger level 1 char */
206#define TRIG_1_2 0x10 /* trigger level 1/2 */
207#define TRIG_7_8 0x18 /* trigger level 7/8 */
208#define TRIG_MASK 0x18 /* trigger level mask */
209#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
210#define RXINT_EN 0x02 /* Rx interrupt enable */
211#define MCINT_EN 0x01 /* modem change interrupt enable */
212
213#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
214#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
215#define SRC_INT 0x08 /* special receive condition interrupt */
216#define DELTA_CD 0x04 /* CD change interrupt */
217#define DELTA_CTS 0x02 /* CTS change interrupt */
218#define DELTA_DSR 0x01 /* DSR change interrupt */
219
220#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
221#define IGN2_EN 0x08 /* ignore byte 2 enable */
222#define IGN1_EN 0x04 /* ignore byte 1 enable */
223#define COMP2_EN 0x02 /* compare byte 2 enable */
224#define COMP1_EN 0x01 /* compare byte 1 enable */
225
226#define RESET_ALL 0x80 /* reset AIOP (all channels) */
227#define TXOVERIDE 0x40 /* Transmit software off override */
228#define RESETUART 0x20 /* reset channel's UART */
229#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
230#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
231
232#define INTSTAT0 0x01 /* AIOP 0 interrupt status */
233#define INTSTAT1 0x02 /* AIOP 1 interrupt status */
234#define INTSTAT2 0x04 /* AIOP 2 interrupt status */
235#define INTSTAT3 0x08 /* AIOP 3 interrupt status */
236
237#define INTR_EN 0x08 /* allow interrupts to host */
238#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
239
240/**************************************************************************
241 MUDBAC remapped for PCI
242**************************************************************************/
243
244#define _CFG_INT_PCI 0x40
245#define _PCI_INT_FUNC 0x3A
246
247#define PCI_STROB 0x2000 /* bit 13 of int aiop register */
248#define INTR_EN_PCI 0x0010 /* allow interrupts to host */
249
250/*
251 * Definitions for Universal PCI board registers
252 */
253#define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */
254#define _PCI_9030_GPIO_CTRL 0x54
255#define PCI_INT_CTRL_AIOP 0x0001
256#define PCI_GPIO_CTRL_8PORT 0x4000
257#define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */
258
259#define CHAN3_EN 0x08 /* enable AIOP 3 */
260#define CHAN2_EN 0x04 /* enable AIOP 2 */
261#define CHAN1_EN 0x02 /* enable AIOP 1 */
262#define CHAN0_EN 0x01 /* enable AIOP 0 */
263#define FREQ_DIS 0x00
264#define FREQ_274HZ 0x60
265#define FREQ_137HZ 0x50
266#define FREQ_69HZ 0x40
267#define FREQ_34HZ 0x30
268#define FREQ_17HZ 0x20
269#define FREQ_9HZ 0x10
270#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
271
272#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
273
274#define RDATASIZE 72
275#define RREGDATASIZE 52
276
277/*
278 * AIOP interrupt bits for ISA/PCI boards and UPCI boards.
279 */
280#define AIOP_INTR_BIT_0 0x0001
281#define AIOP_INTR_BIT_1 0x0002
282#define AIOP_INTR_BIT_2 0x0004
283#define AIOP_INTR_BIT_3 0x0008
284
285#define AIOP_INTR_BITS ( \
286 AIOP_INTR_BIT_0 \
287 | AIOP_INTR_BIT_1 \
288 | AIOP_INTR_BIT_2 \
289 | AIOP_INTR_BIT_3)
290
291#define UPCI_AIOP_INTR_BIT_0 0x0004
292#define UPCI_AIOP_INTR_BIT_1 0x0020
293#define UPCI_AIOP_INTR_BIT_2 0x0100
294#define UPCI_AIOP_INTR_BIT_3 0x0800
295
296#define UPCI_AIOP_INTR_BITS ( \
297 UPCI_AIOP_INTR_BIT_0 \
298 | UPCI_AIOP_INTR_BIT_1 \
299 | UPCI_AIOP_INTR_BIT_2 \
300 | UPCI_AIOP_INTR_BIT_3)
301
302/* Controller level information structure */
303typedef struct {
304 int CtlID;
305 int CtlNum;
306 int BusType;
307 int boardType;
308 int isUPCI;
309 WordIO_t PCIIO;
310 WordIO_t PCIIO2;
311 ByteIO_t MBaseIO;
312 ByteIO_t MReg1IO;
313 ByteIO_t MReg2IO;
314 ByteIO_t MReg3IO;
315 Byte_t MReg2;
316 Byte_t MReg3;
317 int NumAiop;
318 int AltChanRingIndicator;
319 ByteIO_t UPCIRingInd;
320 WordIO_t AiopIO[AIOP_CTL_SIZE];
321 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
322 int AiopID[AIOP_CTL_SIZE];
323 int AiopNumChan[AIOP_CTL_SIZE];
324 Word_t *AiopIntrBits;
325} CONTROLLER_T;
326
327typedef CONTROLLER_T CONTROLLER_t;
328
329/* Channel level information structure */
330typedef struct {
331 CONTROLLER_T *CtlP;
332 int AiopNum;
333 int ChanID;
334 int ChanNum;
335 int rtsToggle;
336
337 ByteIO_t Cmd;
338 ByteIO_t IntChan;
339 ByteIO_t IntMask;
340 DWordIO_t IndexAddr;
341 WordIO_t IndexData;
342
343 WordIO_t TxRxData;
344 WordIO_t ChanStat;
345 WordIO_t TxRxCount;
346 ByteIO_t IntID;
347
348 Word_t TxFIFO;
349 Word_t TxFIFOPtrs;
350 Word_t RxFIFO;
351 Word_t RxFIFOPtrs;
352 Word_t TxPrioCnt;
353 Word_t TxPrioPtr;
354 Word_t TxPrioBuf;
355
356 Byte_t R[RREGDATASIZE];
357
358 Byte_t BaudDiv[4];
359 Byte_t TxControl[4];
360 Byte_t RxControl[4];
361 Byte_t TxEnables[4];
362 Byte_t TxCompare[4];
363 Byte_t TxReplace1[4];
364 Byte_t TxReplace2[4];
365} CHANNEL_T;
366
367typedef CHANNEL_T CHANNEL_t;
368typedef CHANNEL_T *CHANPTR_T;
369
370#define InterfaceModeRS232 0x00
371#define InterfaceModeRS422 0x08
372#define InterfaceModeRS485 0x10
373#define InterfaceModeRS232T 0x18
374
375/***************************************************************************
376Function: sClrBreak
377Purpose: Stop sending a transmit BREAK signal
378Call: sClrBreak(ChP)
379 CHANNEL_T *ChP; Ptr to channel structure
380*/
381#define sClrBreak(ChP) \
382do { \
383 (ChP)->TxControl[3] &= ~SETBREAK; \
457fb605 384 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 385} while (0)
386
387/***************************************************************************
388Function: sClrDTR
389Purpose: Clr the DTR output
390Call: sClrDTR(ChP)
391 CHANNEL_T *ChP; Ptr to channel structure
392*/
393#define sClrDTR(ChP) \
394do { \
395 (ChP)->TxControl[3] &= ~SET_DTR; \
457fb605 396 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 397} while (0)
398
399/***************************************************************************
400Function: sClrRTS
401Purpose: Clr the RTS output
402Call: sClrRTS(ChP)
403 CHANNEL_T *ChP; Ptr to channel structure
404*/
405#define sClrRTS(ChP) \
406do { \
407 if ((ChP)->rtsToggle) break; \
408 (ChP)->TxControl[3] &= ~SET_RTS; \
457fb605 409 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 410} while (0)
411
412/***************************************************************************
413Function: sClrTxXOFF
414Purpose: Clear any existing transmit software flow control off condition
415Call: sClrTxXOFF(ChP)
416 CHANNEL_T *ChP; Ptr to channel structure
417*/
418#define sClrTxXOFF(ChP) \
419do { \
420 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
421 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
422} while (0)
423
424/***************************************************************************
425Function: sCtlNumToCtlPtr
426Purpose: Convert a controller number to controller structure pointer
427Call: sCtlNumToCtlPtr(CtlNum)
428 int CtlNum; Controller number
429Return: CONTROLLER_T *: Ptr to controller structure
430*/
431#define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
432
433/***************************************************************************
434Function: sControllerEOI
435Purpose: Strobe the MUDBAC's End Of Interrupt bit.
436Call: sControllerEOI(CtlP)
437 CONTROLLER_T *CtlP; Ptr to controller structure
438*/
439#define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
440
441/***************************************************************************
442Function: sPCIControllerEOI
443Purpose: Strobe the PCI End Of Interrupt bit.
444 For the UPCI boards, toggle the AIOP interrupt enable bit
445 (this was taken from the Windows driver).
446Call: sPCIControllerEOI(CtlP)
447 CONTROLLER_T *CtlP; Ptr to controller structure
448*/
449#define sPCIControllerEOI(CTLP) \
450do { \
451 if ((CTLP)->isUPCI) { \
452 Word_t w = sInW((CTLP)->PCIIO); \
453 sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
454 sOutW((CTLP)->PCIIO, w); \
455 } \
456 else { \
457 sOutW((CTLP)->PCIIO, PCI_STROB); \
458 } \
459} while (0)
460
461/***************************************************************************
462Function: sDisAiop
463Purpose: Disable I/O access to an AIOP
464Call: sDisAiop(CltP)
465 CONTROLLER_T *CtlP; Ptr to controller structure
466 int AiopNum; Number of AIOP on controller
467*/
468#define sDisAiop(CTLP,AIOPNUM) \
469do { \
470 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
471 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
472} while (0)
473
474/***************************************************************************
475Function: sDisCTSFlowCtl
476Purpose: Disable output flow control using CTS
477Call: sDisCTSFlowCtl(ChP)
478 CHANNEL_T *ChP; Ptr to channel structure
479*/
480#define sDisCTSFlowCtl(ChP) \
481do { \
482 (ChP)->TxControl[2] &= ~CTSFC_EN; \
457fb605 483 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 484} while (0)
485
486/***************************************************************************
487Function: sDisIXANY
488Purpose: Disable IXANY Software Flow Control
489Call: sDisIXANY(ChP)
490 CHANNEL_T *ChP; Ptr to channel structure
491*/
492#define sDisIXANY(ChP) \
493do { \
494 (ChP)->R[0x0e] = 0x86; \
457fb605 495 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
1da177e4
LT		 496} while (0)
497
498/***************************************************************************
499Function: DisParity
500Purpose: Disable parity
501Call: sDisParity(ChP)
502 CHANNEL_T *ChP; Ptr to channel structure
503Comments: Function sSetParity() can be used in place of functions sEnParity(),
504 sDisParity(), sSetOddParity(), and sSetEvenParity().
505*/
506#define sDisParity(ChP) \
507do { \
508 (ChP)->TxControl[2] &= ~PARITY_EN; \
457fb605 509 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 510} while (0)
511
512/***************************************************************************
513Function: sDisRTSToggle
514Purpose: Disable RTS toggle
515Call: sDisRTSToggle(ChP)
516 CHANNEL_T *ChP; Ptr to channel structure
517*/
518#define sDisRTSToggle(ChP) \
519do { \
520 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
457fb605 521 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 522 (ChP)->rtsToggle = 0; \
523} while (0)
524
525/***************************************************************************
526Function: sDisRxFIFO
527Purpose: Disable Rx FIFO
528Call: sDisRxFIFO(ChP)
529 CHANNEL_T *ChP; Ptr to channel structure
530*/
531#define sDisRxFIFO(ChP) \
532do { \
533 (ChP)->R[0x32] = 0x0a; \
457fb605 534 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
1da177e4
LT		 535} while (0)
536
537/***************************************************************************
538Function: sDisRxStatusMode
539Purpose: Disable the Rx status mode
540Call: sDisRxStatusMode(ChP)
541 CHANNEL_T *ChP; Ptr to channel structure
542Comments: This takes the channel out of the receive status mode. All
543 subsequent reads of receive data using sReadRxWord() will return
544 two data bytes.
545*/
546#define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
547
548/***************************************************************************
549Function: sDisTransmit
550Purpose: Disable transmit
551Call: sDisTransmit(ChP)
552 CHANNEL_T *ChP; Ptr to channel structure
553 This disables movement of Tx data from the Tx FIFO into the 1 byte
554 Tx buffer. Therefore there could be up to a 2 byte latency
555 between the time sDisTransmit() is called and the transmit buffer
556 and transmit shift register going completely empty.
557*/
558#define sDisTransmit(ChP) \
559do { \
560 (ChP)->TxControl[3] &= ~TX_ENABLE; \
457fb605 561 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 562} while (0)
563
564/***************************************************************************
565Function: sDisTxSoftFlowCtl
566Purpose: Disable Tx Software Flow Control
567Call: sDisTxSoftFlowCtl(ChP)
568 CHANNEL_T *ChP; Ptr to channel structure
569*/
570#define sDisTxSoftFlowCtl(ChP) \
571do { \
572 (ChP)->R[0x06] = 0x8a; \
457fb605 573 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1da177e4
LT		 574} while (0)
575
576/***************************************************************************
577Function: sEnAiop
578Purpose: Enable I/O access to an AIOP
579Call: sEnAiop(CltP)
580 CONTROLLER_T *CtlP; Ptr to controller structure
581 int AiopNum; Number of AIOP on controller
582*/
583#define sEnAiop(CTLP,AIOPNUM) \
584do { \
585 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
586 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
587} while (0)
588
589/***************************************************************************
590Function: sEnCTSFlowCtl
591Purpose: Enable output flow control using CTS
592Call: sEnCTSFlowCtl(ChP)
593 CHANNEL_T *ChP; Ptr to channel structure
594*/
595#define sEnCTSFlowCtl(ChP) \
596do { \
597 (ChP)->TxControl[2] |= CTSFC_EN; \
457fb605 598 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 599} while (0)
600
601/***************************************************************************
602Function: sEnIXANY
603Purpose: Enable IXANY Software Flow Control
604Call: sEnIXANY(ChP)
605 CHANNEL_T *ChP; Ptr to channel structure
606*/
607#define sEnIXANY(ChP) \
608do { \
609 (ChP)->R[0x0e] = 0x21; \
457fb605 610 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
1da177e4
LT		 611} while (0)
612
613/***************************************************************************
614Function: EnParity
615Purpose: Enable parity
616Call: sEnParity(ChP)
617 CHANNEL_T *ChP; Ptr to channel structure
618Comments: Function sSetParity() can be used in place of functions sEnParity(),
619 sDisParity(), sSetOddParity(), and sSetEvenParity().
620
621Warnings: Before enabling parity odd or even parity should be chosen using
622 functions sSetOddParity() or sSetEvenParity().
623*/
624#define sEnParity(ChP) \
625do { \
626 (ChP)->TxControl[2] |= PARITY_EN; \
457fb605 627 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 628} while (0)
629
630/***************************************************************************
631Function: sEnRTSToggle
632Purpose: Enable RTS toggle
633Call: sEnRTSToggle(ChP)
634 CHANNEL_T *ChP; Ptr to channel structure
635Comments: This function will disable RTS flow control and clear the RTS
636 line to allow operation of RTS toggle.
637*/
638#define sEnRTSToggle(ChP) \
639do { \
640 (ChP)->RxControl[2] &= ~RTSFC_EN; \
457fb605 641 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1da177e4
LT		 642 (ChP)->TxControl[2] |= RTSTOG_EN; \
643 (ChP)->TxControl[3] &= ~SET_RTS; \
457fb605 644 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 645 (ChP)->rtsToggle = 1; \
646} while (0)
647
648/***************************************************************************
649Function: sEnRxFIFO
650Purpose: Enable Rx FIFO
651Call: sEnRxFIFO(ChP)
652 CHANNEL_T *ChP; Ptr to channel structure
653*/
654#define sEnRxFIFO(ChP) \
655do { \
656 (ChP)->R[0x32] = 0x08; \
457fb605 657 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
1da177e4
LT		 658} while (0)
659
660/***************************************************************************
661Function: sEnRxProcessor
662Purpose: Enable the receive processor
663Call: sEnRxProcessor(ChP)
664 CHANNEL_T *ChP; Ptr to channel structure
665Comments: This function is used to start the receive processor. When
666 the channel is in the reset state the receive processor is not
667 running. This is done to prevent the receive processor from
668 executing invalid microcode instructions prior to the
669 downloading of the microcode.
670
671Warnings: This function must be called after valid microcode has been
672 downloaded to the AIOP, and it must not be called before the
673 microcode has been downloaded.
674*/
675#define sEnRxProcessor(ChP) \
676do { \
677 (ChP)->RxControl[2] |= RXPROC_EN; \
457fb605 678 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1da177e4
LT		 679} while (0)
680
681/***************************************************************************
682Function: sEnRxStatusMode
683Purpose: Enable the Rx status mode
684Call: sEnRxStatusMode(ChP)
685 CHANNEL_T *ChP; Ptr to channel structure
686Comments: This places the channel in the receive status mode. All subsequent
687 reads of receive data using sReadRxWord() will return a data byte
688 in the low word and a status byte in the high word.
689
690*/
691#define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
692
693/***************************************************************************
694Function: sEnTransmit
695Purpose: Enable transmit
696Call: sEnTransmit(ChP)
697 CHANNEL_T *ChP; Ptr to channel structure
698*/
699#define sEnTransmit(ChP) \
700do { \
701 (ChP)->TxControl[3] |= TX_ENABLE; \
457fb605 702 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 703} while (0)
704
705/***************************************************************************
706Function: sEnTxSoftFlowCtl
707Purpose: Enable Tx Software Flow Control
708Call: sEnTxSoftFlowCtl(ChP)
709 CHANNEL_T *ChP; Ptr to channel structure
710*/
711#define sEnTxSoftFlowCtl(ChP) \
712do { \
713 (ChP)->R[0x06] = 0xc5; \
457fb605 714 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1da177e4
LT		 715} while (0)
716
717/***************************************************************************
718Function: sGetAiopIntStatus
719Purpose: Get the AIOP interrupt status
720Call: sGetAiopIntStatus(CtlP,AiopNum)
721 CONTROLLER_T *CtlP; Ptr to controller structure
722 int AiopNum; AIOP number
723Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
724 represent channels 0 through 7 respectively. If a
725 bit is set that channel is interrupting.
726*/
727#define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
728
729/***************************************************************************
730Function: sGetAiopNumChan
731Purpose: Get the number of channels supported by an AIOP
732Call: sGetAiopNumChan(CtlP,AiopNum)
733 CONTROLLER_T *CtlP; Ptr to controller structure
734 int AiopNum; AIOP number
735Return: int: The number of channels supported by the AIOP
736*/
737#define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
738
739/***************************************************************************
740Function: sGetChanIntID
741Purpose: Get a channel's interrupt identification byte
742Call: sGetChanIntID(ChP)
743 CHANNEL_T *ChP; Ptr to channel structure
744Return: Byte_t: The channel interrupt ID. Can be any
745 combination of the following flags:
746 RXF_TRIG: Rx FIFO trigger level interrupt
747 TXFIFO_MT: Tx FIFO empty interrupt
748 SRC_INT: Special receive condition interrupt
749 DELTA_CD: CD change interrupt
750 DELTA_CTS: CTS change interrupt
751 DELTA_DSR: DSR change interrupt
752*/
753#define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
754
755/***************************************************************************
756Function: sGetChanNum
757Purpose: Get the number of a channel within an AIOP
758Call: sGetChanNum(ChP)
759 CHANNEL_T *ChP; Ptr to channel structure
760Return: int: Channel number within AIOP, or NULLCHAN if channel does
761 not exist.
762*/
763#define sGetChanNum(ChP) (ChP)->ChanNum
764
765/***************************************************************************
766Function: sGetChanStatus
767Purpose: Get the channel status
768Call: sGetChanStatus(ChP)
769 CHANNEL_T *ChP; Ptr to channel structure
770Return: Word_t: The channel status. Can be any combination of
771 the following flags:
772 LOW BYTE FLAGS
773 CTS_ACT: CTS input asserted
774 DSR_ACT: DSR input asserted
775 CD_ACT: CD input asserted
776 TXFIFOMT: Tx FIFO is empty
777 TXSHRMT: Tx shift register is empty
778 RDA: Rx data available
779
780 HIGH BYTE FLAGS
781 STATMODE: status mode enable bit
782 RXFOVERFL: receive FIFO overflow
783 RX2MATCH: receive compare byte 2 match
784 RX1MATCH: receive compare byte 1 match
785 RXBREAK: received BREAK
786 RXFRAME: received framing error
787 RXPARITY: received parity error
788Warnings: This function will clear the high byte flags in the Channel
789 Status Register.
790*/
791#define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
792
793/***************************************************************************
794Function: sGetChanStatusLo
795Purpose: Get the low byte only of the channel status
796Call: sGetChanStatusLo(ChP)
797 CHANNEL_T *ChP; Ptr to channel structure
798Return: Byte_t: The channel status low byte. Can be any combination
799 of the following flags:
800 CTS_ACT: CTS input asserted
801 DSR_ACT: DSR input asserted
802 CD_ACT: CD input asserted
803 TXFIFOMT: Tx FIFO is empty
804 TXSHRMT: Tx shift register is empty
805 RDA: Rx data available
806*/
807#define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
808
809/**********************************************************************
810 * Get RI status of channel
811 * Defined as a function in rocket.c -aes
812 */
813#if 0
814#define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
815 (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
816 (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
817 (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
818 0))
819#endif
820
821/***************************************************************************
822Function: sGetControllerIntStatus
823Purpose: Get the controller interrupt status
824Call: sGetControllerIntStatus(CtlP)
825 CONTROLLER_T *CtlP; Ptr to controller structure
826Return: Byte_t: The controller interrupt status in the lower 4
827 bits. Bits 0 through 3 represent AIOP's 0
828 through 3 respectively. If a bit is set that
829 AIOP is interrupting. Bits 4 through 7 will
830 always be cleared.
831*/
832#define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
833
834/***************************************************************************
835Function: sPCIGetControllerIntStatus
836Purpose: Get the controller interrupt status
837Call: sPCIGetControllerIntStatus(CtlP)
838 CONTROLLER_T *CtlP; Ptr to controller structure
839Return: unsigned char: The controller interrupt status in the lower 4
840 bits and bit 4. Bits 0 through 3 represent AIOP's 0
841 through 3 respectively. Bit 4 is set if the int
842 was generated from periodic. If a bit is set the
843 AIOP is interrupting.
844*/
845#define sPCIGetControllerIntStatus(CTLP) \
846 ((CTLP)->isUPCI ? \
847 (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
848 ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))
849
850/***************************************************************************
851
852Function: sGetRxCnt
853Purpose: Get the number of data bytes in the Rx FIFO
854Call: sGetRxCnt(ChP)
855 CHANNEL_T *ChP; Ptr to channel structure
856Return: int: The number of data bytes in the Rx FIFO.
857Comments: Byte read of count register is required to obtain Rx count.
858
859*/
860#define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
861
862/***************************************************************************
863Function: sGetTxCnt
864Purpose: Get the number of data bytes in the Tx FIFO
865Call: sGetTxCnt(ChP)
866 CHANNEL_T *ChP; Ptr to channel structure
867Return: Byte_t: The number of data bytes in the Tx FIFO.
868Comments: Byte read of count register is required to obtain Tx count.
869
870*/
871#define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
872
873/*****************************************************************************
874Function: sGetTxRxDataIO
875Purpose: Get the I/O address of a channel's TxRx Data register
876Call: sGetTxRxDataIO(ChP)
877 CHANNEL_T *ChP; Ptr to channel structure
878Return: WordIO_t: I/O address of a channel's TxRx Data register
879*/
880#define sGetTxRxDataIO(ChP) (ChP)->TxRxData
881
882/***************************************************************************
883Function: sInitChanDefaults
884Purpose: Initialize a channel structure to it's default state.
885Call: sInitChanDefaults(ChP)
886 CHANNEL_T *ChP; Ptr to the channel structure
887Comments: This function must be called once for every channel structure
888 that exists before any other SSCI calls can be made.
889
890*/
891#define sInitChanDefaults(ChP) \
892do { \
893 (ChP)->CtlP = NULLCTLPTR; \
894 (ChP)->AiopNum = NULLAIOP; \
895 (ChP)->ChanID = AIOPID_NULL; \
896 (ChP)->ChanNum = NULLCHAN; \
897} while (0)
898
899/***************************************************************************
900Function: sResetAiopByNum
901Purpose: Reset the AIOP by number
902Call: sResetAiopByNum(CTLP,AIOPNUM)
903 CONTROLLER_T CTLP; Ptr to controller structure
904 AIOPNUM; AIOP index
905*/
906#define sResetAiopByNum(CTLP,AIOPNUM) \
907do { \
908 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
909 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
910} while (0)
911
912/***************************************************************************
913Function: sSendBreak
914Purpose: Send a transmit BREAK signal
915Call: sSendBreak(ChP)
916 CHANNEL_T *ChP; Ptr to channel structure
917*/
918#define sSendBreak(ChP) \
919do { \
920 (ChP)->TxControl[3] |= SETBREAK; \
457fb605 921 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 922} while (0)
923
924/***************************************************************************
925Function: sSetBaud
926Purpose: Set baud rate
927Call: sSetBaud(ChP,Divisor)
928 CHANNEL_T *ChP; Ptr to channel structure
929 Word_t Divisor; 16 bit baud rate divisor for channel
930*/
931#define sSetBaud(ChP,DIVISOR) \
932do { \
933 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
934 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
457fb605 935 out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
1da177e4
LT		 936} while (0)
937
938/***************************************************************************
939Function: sSetData7
940Purpose: Set data bits to 7
941Call: sSetData7(ChP)
942 CHANNEL_T *ChP; Ptr to channel structure
943*/
944#define sSetData7(ChP) \
945do { \
946 (ChP)->TxControl[2] &= ~DATA8BIT; \
457fb605 947 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 948} while (0)
949
950/***************************************************************************
951Function: sSetData8
952Purpose: Set data bits to 8
953Call: sSetData8(ChP)
954 CHANNEL_T *ChP; Ptr to channel structure
955*/
956#define sSetData8(ChP) \
957do { \
958 (ChP)->TxControl[2] |= DATA8BIT; \
457fb605 959 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 960} while (0)
961
962/***************************************************************************
963Function: sSetDTR
964Purpose: Set the DTR output
965Call: sSetDTR(ChP)
966 CHANNEL_T *ChP; Ptr to channel structure
967*/
968#define sSetDTR(ChP) \
969do { \
970 (ChP)->TxControl[3] |= SET_DTR; \
457fb605 971 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 972} while (0)
973
974/***************************************************************************
975Function: sSetEvenParity
976Purpose: Set even parity
977Call: sSetEvenParity(ChP)
978 CHANNEL_T *ChP; Ptr to channel structure
979Comments: Function sSetParity() can be used in place of functions sEnParity(),
980 sDisParity(), sSetOddParity(), and sSetEvenParity().
981
982Warnings: This function has no effect unless parity is enabled with function
983 sEnParity().
984*/
985#define sSetEvenParity(ChP) \
986do { \
987 (ChP)->TxControl[2] |= EVEN_PAR; \
457fb605 988 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 989} while (0)
990
991/***************************************************************************
992Function: sSetOddParity
993Purpose: Set odd parity
994Call: sSetOddParity(ChP)
995 CHANNEL_T *ChP; Ptr to channel structure
996Comments: Function sSetParity() can be used in place of functions sEnParity(),
997 sDisParity(), sSetOddParity(), and sSetEvenParity().
998
999Warnings: This function has no effect unless parity is enabled with function
1000 sEnParity().
1001*/
1002#define sSetOddParity(ChP) \
1003do { \
1004 (ChP)->TxControl[2] &= ~EVEN_PAR; \
457fb605 1005 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 1006} while (0)
1007
1008/***************************************************************************
1009Function: sSetRTS
1010Purpose: Set the RTS output
1011Call: sSetRTS(ChP)
1012 CHANNEL_T *ChP; Ptr to channel structure
1013*/
1014#define sSetRTS(ChP) \
1015do { \
1016 if ((ChP)->rtsToggle) break; \
1017 (ChP)->TxControl[3] |= SET_RTS; \
457fb605 1018 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 1019} while (0)
1020
1021/***************************************************************************
1022Function: sSetRxTrigger
1023Purpose: Set the Rx FIFO trigger level
1024Call: sSetRxProcessor(ChP,Level)
1025 CHANNEL_T *ChP; Ptr to channel structure
1026 Byte_t Level; Number of characters in Rx FIFO at which the
1027 interrupt will be generated. Can be any of the following flags:
1028
1029 TRIG_NO: no trigger
1030 TRIG_1: 1 character in FIFO
1031 TRIG_1_2: FIFO 1/2 full
1032 TRIG_7_8: FIFO 7/8 full
1033Comments: An interrupt will be generated when the trigger level is reached
1034 only if function sEnInterrupt() has been called with flag
1035 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
1036 register will be set whenever the trigger level is reached
1037 regardless of the setting of RXINT_EN.
1038
1039*/
1040#define sSetRxTrigger(ChP,LEVEL) \
1041do { \
1042 (ChP)->RxControl[2] &= ~TRIG_MASK; \
1043 (ChP)->RxControl[2] |= LEVEL; \
457fb605 1044 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1da177e4
LT		 1045} while (0)
1046
1047/***************************************************************************
1048Function: sSetStop1
1049Purpose: Set stop bits to 1
1050Call: sSetStop1(ChP)
1051 CHANNEL_T *ChP; Ptr to channel structure
1052*/
1053#define sSetStop1(ChP) \
1054do { \
1055 (ChP)->TxControl[2] &= ~STOP2; \
457fb605 1056 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 1057} while (0)
1058
1059/***************************************************************************
1060Function: sSetStop2
1061Purpose: Set stop bits to 2
1062Call: sSetStop2(ChP)
1063 CHANNEL_T *ChP; Ptr to channel structure
1064*/
1065#define sSetStop2(ChP) \
1066do { \
1067 (ChP)->TxControl[2] |= STOP2; \
457fb605 1068 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1da177e4
LT		 1069} while (0)
1070
1071/***************************************************************************
1072Function: sSetTxXOFFChar
1073Purpose: Set the Tx XOFF flow control character
1074Call: sSetTxXOFFChar(ChP,Ch)
1075 CHANNEL_T *ChP; Ptr to channel structure
1076 Byte_t Ch; The value to set the Tx XOFF character to
1077*/
1078#define sSetTxXOFFChar(ChP,CH) \
1079do { \
1080 (ChP)->R[0x07] = (CH); \
457fb605 1081 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1da177e4
LT		 1082} while (0)
1083
1084/***************************************************************************
1085Function: sSetTxXONChar
1086Purpose: Set the Tx XON flow control character
1087Call: sSetTxXONChar(ChP,Ch)
1088 CHANNEL_T *ChP; Ptr to channel structure
1089 Byte_t Ch; The value to set the Tx XON character to
1090*/
1091#define sSetTxXONChar(ChP,CH) \
1092do { \
1093 (ChP)->R[0x0b] = (CH); \
457fb605 1094 out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
1da177e4
LT		 1095} while (0)
1096
1097/***************************************************************************
1098Function: sStartRxProcessor
1099Purpose: Start a channel's receive processor
1100Call: sStartRxProcessor(ChP)
1101 CHANNEL_T *ChP; Ptr to channel structure
1102Comments: This function is used to start a Rx processor after it was
1103 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
1104 will restart both the Rx processor and software input flow control.
1105
1106*/
457fb605 1107#define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0])
1da177e4
LT		 1108
1109/***************************************************************************
1110Function: sWriteTxByte
1111Purpose: Write a transmit data byte to a channel.
1112 ByteIO_t io: Channel transmit register I/O address. This can
1113 be obtained with sGetTxRxDataIO().
1114 Byte_t Data; The transmit data byte.
1115Warnings: This function writes the data byte without checking to see if
1116 sMaxTxSize is exceeded in the Tx FIFO.
1117*/
1118#define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
1119
1da177e4
LT		 1120/*
1121 * Begin Linux specific definitions for the Rocketport driver
1122 *
1123 * This code is Copyright Theodore Ts'o, 1995-1997
1124 */
1125
1126struct r_port {
1127 int magic;
e60a1084 1128 struct tty_port port;
1da177e4 1129 int line;
e60a1084 1130 int flags; /* Don't yet match the ASY_ flags!! */
1da177e4
LT		 1131 unsigned int board:3;
1132 unsigned int aiop:2;
1133 unsigned int chan:3;
1134 CONTROLLER_t *ctlp;
1135 CHANNEL_t channel;
1da177e4
LT		 1136 int intmask;
1137 int xmit_fifo_room; /* room in xmit fifo */
1138 unsigned char *xmit_buf;
1139 int xmit_head;
1140 int xmit_tail;
1141 int xmit_cnt;
1da177e4
LT		 1142 int cd_status;
1143 int ignore_status_mask;
1144 int read_status_mask;
1145 int cps;
1146
e60a1084 1147 struct completion close_wait; /* Not yet matching the core */
1da177e4 1148 spinlock_t slock;
69f545ea 1149 struct mutex write_mtx;
1da177e4
LT		 1150};
1151
1152#define RPORT_MAGIC 0x525001
1153
1154#define NUM_BOARDS 8
1155#define MAX_RP_PORTS (32*NUM_BOARDS)
1156
1157/*
1158 * The size of the xmit buffer is 1 page, or 4096 bytes
1159 */
1160#define XMIT_BUF_SIZE 4096
1161
1162/* number of characters left in xmit buffer before we ask for more */
1163#define WAKEUP_CHARS 256
1164
1da177e4
LT		 1165/*
1166 * Assigned major numbers for the Comtrol Rocketport
1167 */
1168#define TTY_ROCKET_MAJOR 46
1169#define CUA_ROCKET_MAJOR 47
1170
1171#ifdef PCI_VENDOR_ID_RP
1172#undef PCI_VENDOR_ID_RP
1173#undef PCI_DEVICE_ID_RP8OCTA
1174#undef PCI_DEVICE_ID_RP8INTF
1175#undef PCI_DEVICE_ID_RP16INTF
1176#undef PCI_DEVICE_ID_RP32INTF
1177#undef PCI_DEVICE_ID_URP8OCTA
1178#undef PCI_DEVICE_ID_URP8INTF
1179#undef PCI_DEVICE_ID_URP16INTF
1180#undef PCI_DEVICE_ID_CRP16INTF
1181#undef PCI_DEVICE_ID_URP32INTF
1182#endif
1183
1184/* Comtrol PCI Vendor ID */
1185#define PCI_VENDOR_ID_RP 0x11fe
1186
1187/* Comtrol Device ID's */
1188#define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */
1189#define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */
1190#define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */
1191#define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */
1192#define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */
1193#define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */
1194#define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */
1195#define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
1196#define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */
1197#define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */
1198#define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */
1199#define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */
1200#define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */
1201#define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */
1202#define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */
1203
1204/* Universal PCI boards */
1205#define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */
1206#define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */
1207#define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */
1208#define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */
1209#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */
1210#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */
1211
1212/* Compact PCI device */
1213#define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */
1214
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