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[linux.git] / drivers / net / skge.c
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baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <[email protected]>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
747802ab 45#define DRV_VERSION "0.7"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 52#define RX_COPY_THRESHOLD 128
53#define RX_BUF_SIZE 1536
baef58b1
SH		 54#define PHY_RETRIES 1000
55#define ETH_JUMBO_MTU 9000
56#define TX_WATCHDOG (5 * HZ)
57#define NAPI_WEIGHT 64
58#define BLINK_HZ (HZ/4)
baef58b1
SH		 59
60MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61MODULE_AUTHOR("Stephen Hemminger <[email protected]>");
62MODULE_LICENSE("GPL");
63MODULE_VERSION(DRV_VERSION);
64
65static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69static int debug = -1; /* defaults above */
70module_param(debug, int, 0);
71MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
82 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
baef58b1
SH		 85 { 0 }
86};
87MODULE_DEVICE_TABLE(pci, skge_id_table);
88
89static int skge_up(struct net_device *dev);
90static int skge_down(struct net_device *dev);
91static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 92static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 94static void genesis_get_stats(struct skge_port *skge, u64 *data);
95static void yukon_get_stats(struct skge_port *skge, u64 *data);
96static void yukon_init(struct skge_hw *hw, int port);
97static void yukon_reset(struct skge_hw *hw, int port);
98static void genesis_mac_init(struct skge_hw *hw, int port);
99static void genesis_reset(struct skge_hw *hw, int port);
45bada65 100static void genesis_link_up(struct skge_port *skge);
baef58b1 101
7e676d91 102/* Avoid conditionals by using array */
baef58b1
SH		 103static const int txqaddr[] = { Q_XA1, Q_XA2 };
104static const int rxqaddr[] = { Q_R1, Q_R2 };
105static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 107static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1
SH		 108
109/* Don't need to look at whole 16K.
110 * last interesting register is descriptor poll timer.
111 */
112#define SKGE_REGS_LEN (29*128)
113
114static int skge_get_regs_len(struct net_device *dev)
115{
116 return SKGE_REGS_LEN;
117}
118
119/*
120 * Returns copy of control register region
121 * I/O region is divided into banks and certain regions are unreadable
122 */
123static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
124 void *p)
125{
126 const struct skge_port *skge = netdev_priv(dev);
127 unsigned long offs;
128 const void __iomem *io = skge->hw->regs;
129 static const unsigned long bankmap
130 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
131 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
132 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
133 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
134
135 regs->version = 1;
136 for (offs = 0; offs < regs->len; offs += 128) {
137 u32 len = min_t(u32, 128, regs->len - offs);
138
139 if (bankmap & (1<<(offs/128)))
140 memcpy_fromio(p + offs, io + offs, len);
141 else
142 memset(p + offs, 0, len);
143 }
144}
145
146/* Wake on Lan only supported on Yukon chps with rev 1 or above */
147static int wol_supported(const struct skge_hw *hw)
148{
149 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 150 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 151}
152
153static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
154{
155 struct skge_port *skge = netdev_priv(dev);
156
157 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
158 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
159}
160
161static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
162{
163 struct skge_port *skge = netdev_priv(dev);
164 struct skge_hw *hw = skge->hw;
165
95566065 166 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 167 return -EOPNOTSUPP;
168
169 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
170 return -EOPNOTSUPP;
171
172 skge->wol = wol->wolopts == WAKE_MAGIC;
173
174 if (skge->wol) {
175 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
176
177 skge_write16(hw, WOL_CTRL_STAT,
178 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
179 WOL_CTL_ENA_MAGIC_PKT_UNIT);
180 } else
181 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
182
183 return 0;
184}
185
31b619c5
SH		 186/* Determine supported/adverised modes based on hardware.
187 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
188 */
189static u32 skge_supported_modes(const struct skge_hw *hw)
190{
191 u32 supported;
192
193 if (iscopper(hw)) {
194 supported = SUPPORTED_10baseT_Half
195 | SUPPORTED_10baseT_Full
196 | SUPPORTED_100baseT_Half
197 | SUPPORTED_100baseT_Full
198 | SUPPORTED_1000baseT_Half
199 | SUPPORTED_1000baseT_Full
200 | SUPPORTED_Autoneg| SUPPORTED_TP;
201
202 if (hw->chip_id == CHIP_ID_GENESIS)
203 supported &= ~(SUPPORTED_10baseT_Half
204 | SUPPORTED_10baseT_Full
205 | SUPPORTED_100baseT_Half
206 | SUPPORTED_100baseT_Full);
207
208 else if (hw->chip_id == CHIP_ID_YUKON)
209 supported &= ~SUPPORTED_1000baseT_Half;
210 } else
211 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
212 | SUPPORTED_Autoneg;
213
214 return supported;
215}
baef58b1
SH		 216
217static int skge_get_settings(struct net_device *dev,
218 struct ethtool_cmd *ecmd)
219{
220 struct skge_port *skge = netdev_priv(dev);
221 struct skge_hw *hw = skge->hw;
222
223 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 224 ecmd->supported = skge_supported_modes(hw);
baef58b1
SH		 225
226 if (iscopper(hw)) {
baef58b1
SH		 227 ecmd->port = PORT_TP;
228 ecmd->phy_address = hw->phy_addr;
31b619c5 229 } else
baef58b1 230 ecmd->port = PORT_FIBRE;
baef58b1
SH		 231
232 ecmd->advertising = skge->advertising;
233 ecmd->autoneg = skge->autoneg;
234 ecmd->speed = skge->speed;
235 ecmd->duplex = skge->duplex;
236 return 0;
237}
238
baef58b1
SH		 239static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
240{
241 struct skge_port *skge = netdev_priv(dev);
242 const struct skge_hw *hw = skge->hw;
31b619c5 243 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 244
245 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 246 ecmd->advertising = supported;
247 skge->duplex = -1;
248 skge->speed = -1;
baef58b1 249 } else {
31b619c5
SH		 250 u32 setting;
251
252 switch(ecmd->speed) {
baef58b1 253 case SPEED_1000:
31b619c5
SH		 254 if (ecmd->duplex == DUPLEX_FULL)
255 setting = SUPPORTED_1000baseT_Full;
256 else if (ecmd->duplex == DUPLEX_HALF)
257 setting = SUPPORTED_1000baseT_Half;
258 else
259 return -EINVAL;
baef58b1
SH		 260 break;
261 case SPEED_100:
31b619c5
SH		 262 if (ecmd->duplex == DUPLEX_FULL)
263 setting = SUPPORTED_100baseT_Full;
264 else if (ecmd->duplex == DUPLEX_HALF)
265 setting = SUPPORTED_100baseT_Half;
266 else
267 return -EINVAL;
268 break;
269
baef58b1 270 case SPEED_10:
31b619c5
SH		 271 if (ecmd->duplex == DUPLEX_FULL)
272 setting = SUPPORTED_10baseT_Full;
273 else if (ecmd->duplex == DUPLEX_HALF)
274 setting = SUPPORTED_10baseT_Half;
275 else
baef58b1
SH		 276 return -EINVAL;
277 break;
278 default:
279 return -EINVAL;
280 }
31b619c5
SH		 281
282 if ((setting & supported) == 0)
283 return -EINVAL;
284
285 skge->speed = ecmd->speed;
286 skge->duplex = ecmd->duplex;
baef58b1
SH		 287 }
288
289 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 290 skge->advertising = ecmd->advertising;
291
292 if (netif_running(dev)) {
293 skge_down(dev);
294 skge_up(dev);
295 }
296 return (0);
297}
298
299static void skge_get_drvinfo(struct net_device *dev,
300 struct ethtool_drvinfo *info)
301{
302 struct skge_port *skge = netdev_priv(dev);
303
304 strcpy(info->driver, DRV_NAME);
305 strcpy(info->version, DRV_VERSION);
306 strcpy(info->fw_version, "N/A");
307 strcpy(info->bus_info, pci_name(skge->hw->pdev));
308}
309
310static const struct skge_stat {
311 char name[ETH_GSTRING_LEN];
312 u16 xmac_offset;
313 u16 gma_offset;
314} skge_stats[] = {
315 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
316 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
317
318 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
319 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
320 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
321 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
322 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
323 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
324 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
325 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
326
327 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
328 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
329 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
330 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
331 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
332 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
333
334 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
335 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
336 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
337 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
338 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
339};
340
341static int skge_get_stats_count(struct net_device *dev)
342{
343 return ARRAY_SIZE(skge_stats);
344}
345
346static void skge_get_ethtool_stats(struct net_device *dev,
347 struct ethtool_stats *stats, u64 *data)
348{
349 struct skge_port *skge = netdev_priv(dev);
350
351 if (skge->hw->chip_id == CHIP_ID_GENESIS)
352 genesis_get_stats(skge, data);
353 else
354 yukon_get_stats(skge, data);
355}
356
357/* Use hardware MIB variables for critical path statistics and
358 * transmit feedback not reported at interrupt.
359 * Other errors are accounted for in interrupt handler.
360 */
361static struct net_device_stats *skge_get_stats(struct net_device *dev)
362{
363 struct skge_port *skge = netdev_priv(dev);
364 u64 data[ARRAY_SIZE(skge_stats)];
365
366 if (skge->hw->chip_id == CHIP_ID_GENESIS)
367 genesis_get_stats(skge, data);
368 else
369 yukon_get_stats(skge, data);
370
371 skge->net_stats.tx_bytes = data[0];
372 skge->net_stats.rx_bytes = data[1];
373 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
374 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
375 skge->net_stats.multicast = data[5] + data[7];
376 skge->net_stats.collisions = data[10];
377 skge->net_stats.tx_aborted_errors = data[12];
378
379 return &skge->net_stats;
380}
381
382static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
383{
384 int i;
385
95566065 386 switch (stringset) {
baef58b1
SH		 387 case ETH_SS_STATS:
388 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
389 memcpy(data + i * ETH_GSTRING_LEN,
390 skge_stats[i].name, ETH_GSTRING_LEN);
391 break;
392 }
393}
394
395static void skge_get_ring_param(struct net_device *dev,
396 struct ethtool_ringparam *p)
397{
398 struct skge_port *skge = netdev_priv(dev);
399
400 p->rx_max_pending = MAX_RX_RING_SIZE;
401 p->tx_max_pending = MAX_TX_RING_SIZE;
402 p->rx_mini_max_pending = 0;
403 p->rx_jumbo_max_pending = 0;
404
405 p->rx_pending = skge->rx_ring.count;
406 p->tx_pending = skge->tx_ring.count;
407 p->rx_mini_pending = 0;
408 p->rx_jumbo_pending = 0;
409}
410
411static int skge_set_ring_param(struct net_device *dev,
412 struct ethtool_ringparam *p)
413{
414 struct skge_port *skge = netdev_priv(dev);
415
416 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
417 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
418 return -EINVAL;
419
420 skge->rx_ring.count = p->rx_pending;
421 skge->tx_ring.count = p->tx_pending;
422
423 if (netif_running(dev)) {
424 skge_down(dev);
425 skge_up(dev);
426 }
427
428 return 0;
429}
430
431static u32 skge_get_msglevel(struct net_device *netdev)
432{
433 struct skge_port *skge = netdev_priv(netdev);
434 return skge->msg_enable;
435}
436
437static void skge_set_msglevel(struct net_device *netdev, u32 value)
438{
439 struct skge_port *skge = netdev_priv(netdev);
440 skge->msg_enable = value;
441}
442
443static int skge_nway_reset(struct net_device *dev)
444{
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
447 int port = skge->port;
448
449 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
450 return -EINVAL;
451
452 spin_lock_bh(&hw->phy_lock);
453 if (hw->chip_id == CHIP_ID_GENESIS) {
454 genesis_reset(hw, port);
455 genesis_mac_init(hw, port);
456 } else {
457 yukon_reset(hw, port);
458 yukon_init(hw, port);
459 }
460 spin_unlock_bh(&hw->phy_lock);
461 return 0;
462}
463
464static int skge_set_sg(struct net_device *dev, u32 data)
465{
466 struct skge_port *skge = netdev_priv(dev);
467 struct skge_hw *hw = skge->hw;
468
469 if (hw->chip_id == CHIP_ID_GENESIS && data)
470 return -EOPNOTSUPP;
471 return ethtool_op_set_sg(dev, data);
472}
473
474static int skge_set_tx_csum(struct net_device *dev, u32 data)
475{
476 struct skge_port *skge = netdev_priv(dev);
477 struct skge_hw *hw = skge->hw;
478
479 if (hw->chip_id == CHIP_ID_GENESIS && data)
480 return -EOPNOTSUPP;
481
482 return ethtool_op_set_tx_csum(dev, data);
483}
484
485static u32 skge_get_rx_csum(struct net_device *dev)
486{
487 struct skge_port *skge = netdev_priv(dev);
488
489 return skge->rx_csum;
490}
491
492/* Only Yukon supports checksum offload. */
493static int skge_set_rx_csum(struct net_device *dev, u32 data)
494{
495 struct skge_port *skge = netdev_priv(dev);
496
497 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
498 return -EOPNOTSUPP;
499
500 skge->rx_csum = data;
501 return 0;
502}
503
baef58b1
SH		 504static void skge_get_pauseparam(struct net_device *dev,
505 struct ethtool_pauseparam *ecmd)
506{
507 struct skge_port *skge = netdev_priv(dev);
508
509 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
510 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
511 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
512 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
513
514 ecmd->autoneg = skge->autoneg;
515}
516
517static int skge_set_pauseparam(struct net_device *dev,
518 struct ethtool_pauseparam *ecmd)
519{
520 struct skge_port *skge = netdev_priv(dev);
521
522 skge->autoneg = ecmd->autoneg;
523 if (ecmd->rx_pause && ecmd->tx_pause)
524 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 525 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 526 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 527 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 528 skge->flow_control = FLOW_MODE_LOC_SEND;
529 else
530 skge->flow_control = FLOW_MODE_NONE;
531
532 if (netif_running(dev)) {
533 skge_down(dev);
534 skge_up(dev);
535 }
536 return 0;
537}
538
539/* Chip internal frequency for clock calculations */
540static inline u32 hwkhz(const struct skge_hw *hw)
541{
542 if (hw->chip_id == CHIP_ID_GENESIS)
543 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 544 else
545 return 78215; /* or: 78.125 MHz */
546}
547
548/* Chip hz to microseconds */
549static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
550{
551 return (ticks * 1000) / hwkhz(hw);
552}
553
554/* Microseconds to chip hz */
555static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
556{
557 return hwkhz(hw) * usec / 1000;
558}
559
560static int skge_get_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
562{
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566
567 ecmd->rx_coalesce_usecs = 0;
568 ecmd->tx_coalesce_usecs = 0;
569
570 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
571 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
572 u32 msk = skge_read32(hw, B2_IRQM_MSK);
573
574 if (msk & rxirqmask[port])
575 ecmd->rx_coalesce_usecs = delay;
576 if (msk & txirqmask[port])
577 ecmd->tx_coalesce_usecs = delay;
578 }
579
580 return 0;
581}
582
583/* Note: interrupt timer is per board, but can turn on/off per port */
584static int skge_set_coalesce(struct net_device *dev,
585 struct ethtool_coalesce *ecmd)
586{
587 struct skge_port *skge = netdev_priv(dev);
588 struct skge_hw *hw = skge->hw;
589 int port = skge->port;
590 u32 msk = skge_read32(hw, B2_IRQM_MSK);
591 u32 delay = 25;
592
593 if (ecmd->rx_coalesce_usecs == 0)
594 msk &= ~rxirqmask[port];
595 else if (ecmd->rx_coalesce_usecs < 25 ||
596 ecmd->rx_coalesce_usecs > 33333)
597 return -EINVAL;
598 else {
599 msk |= rxirqmask[port];
600 delay = ecmd->rx_coalesce_usecs;
601 }
602
603 if (ecmd->tx_coalesce_usecs == 0)
604 msk &= ~txirqmask[port];
605 else if (ecmd->tx_coalesce_usecs < 25 ||
606 ecmd->tx_coalesce_usecs > 33333)
607 return -EINVAL;
608 else {
609 msk |= txirqmask[port];
610 delay = min(delay, ecmd->rx_coalesce_usecs);
611 }
612
613 skge_write32(hw, B2_IRQM_MSK, msk);
614 if (msk == 0)
615 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
616 else {
617 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
618 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
619 }
620 return 0;
621}
622
623static void skge_led_on(struct skge_hw *hw, int port)
624{
625 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 626 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
baef58b1
SH		 627 skge_write8(hw, B0_LED, LED_STAT_ON);
628
6b0c1480
SH		 629 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
630 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
631 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 632
89bf5f23
SH		 633 /* For Broadcom Phy only */
634 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
baef58b1 635 } else {
6b0c1480
SH		 636 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
637 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 638 PHY_M_LED_MO_DUP(MO_LED_ON) |
639 PHY_M_LED_MO_10(MO_LED_ON) |
640 PHY_M_LED_MO_100(MO_LED_ON) |
641 PHY_M_LED_MO_1000(MO_LED_ON) |
642 PHY_M_LED_MO_RX(MO_LED_ON));
643 }
644}
645
646static void skge_led_off(struct skge_hw *hw, int port)
647{
648 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 649 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
baef58b1
SH		 650 skge_write8(hw, B0_LED, LED_STAT_OFF);
651
6b0c1480
SH		 652 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
653 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
baef58b1 654
89bf5f23
SH		 655 /* Broadcom only */
656 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
baef58b1 657 } else {
6b0c1480
SH		 658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 660 PHY_M_LED_MO_DUP(MO_LED_OFF) |
661 PHY_M_LED_MO_10(MO_LED_OFF) |
662 PHY_M_LED_MO_100(MO_LED_OFF) |
663 PHY_M_LED_MO_1000(MO_LED_OFF) |
664 PHY_M_LED_MO_RX(MO_LED_OFF));
665 }
666}
667
668static void skge_blink_timer(unsigned long data)
669{
670 struct skge_port *skge = (struct skge_port *) data;
671 struct skge_hw *hw = skge->hw;
672 unsigned long flags;
673
674 spin_lock_irqsave(&hw->phy_lock, flags);
675 if (skge->blink_on)
676 skge_led_on(hw, skge->port);
677 else
678 skge_led_off(hw, skge->port);
679 spin_unlock_irqrestore(&hw->phy_lock, flags);
680
681 skge->blink_on = !skge->blink_on;
682 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
683}
684
685/* blink LED's for finding board */
686static int skge_phys_id(struct net_device *dev, u32 data)
687{
688 struct skge_port *skge = netdev_priv(dev);
689
95566065 690 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
baef58b1
SH		 691 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
692
693 /* start blinking */
694 skge->blink_on = 1;
695 mod_timer(&skge->led_blink, jiffies+1);
696
697 msleep_interruptible(data * 1000);
698 del_timer_sync(&skge->led_blink);
699
700 skge_led_off(skge->hw, skge->port);
701
702 return 0;
703}
704
705static struct ethtool_ops skge_ethtool_ops = {
706 .get_settings = skge_get_settings,
707 .set_settings = skge_set_settings,
708 .get_drvinfo = skge_get_drvinfo,
709 .get_regs_len = skge_get_regs_len,
710 .get_regs = skge_get_regs,
711 .get_wol = skge_get_wol,
712 .set_wol = skge_set_wol,
713 .get_msglevel = skge_get_msglevel,
714 .set_msglevel = skge_set_msglevel,
715 .nway_reset = skge_nway_reset,
716 .get_link = ethtool_op_get_link,
717 .get_ringparam = skge_get_ring_param,
718 .set_ringparam = skge_set_ring_param,
719 .get_pauseparam = skge_get_pauseparam,
720 .set_pauseparam = skge_set_pauseparam,
721 .get_coalesce = skge_get_coalesce,
722 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 723 .get_sg = ethtool_op_get_sg,
724 .set_sg = skge_set_sg,
725 .get_tx_csum = ethtool_op_get_tx_csum,
726 .set_tx_csum = skge_set_tx_csum,
727 .get_rx_csum = skge_get_rx_csum,
728 .set_rx_csum = skge_set_rx_csum,
729 .get_strings = skge_get_strings,
730 .phys_id = skge_phys_id,
731 .get_stats_count = skge_get_stats_count,
732 .get_ethtool_stats = skge_get_ethtool_stats,
733};
734
735/*
736 * Allocate ring elements and chain them together
737 * One-to-one association of board descriptors with ring elements
738 */
739static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
740{
741 struct skge_tx_desc *d;
742 struct skge_element *e;
743 int i;
744
745 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
746 if (!ring->start)
747 return -ENOMEM;
748
749 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
750 e->desc = d;
19a33d4e 751 e->skb = NULL;
baef58b1
SH		 752 if (i == ring->count - 1) {
753 e->next = ring->start;
754 d->next_offset = base;
755 } else {
756 e->next = e + 1;
757 d->next_offset = base + (i+1) * sizeof(*d);
758 }
759 }
760 ring->to_use = ring->to_clean = ring->start;
761
762 return 0;
763}
764
19a33d4e 765static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
baef58b1 766{
19a33d4e 767 struct sk_buff *skb = dev_alloc_skb(size);
baef58b1 768
19a33d4e
SH		 769 if (likely(skb)) {
770 skb->dev = dev;
771 skb_reserve(skb, NET_IP_ALIGN);
baef58b1 772 }
19a33d4e
SH		 773 return skb;
774}
baef58b1 775
19a33d4e
SH		 776/* Allocate and setup a new buffer for receiving */
777static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
778 struct sk_buff *skb, unsigned int bufsize)
779{
780 struct skge_rx_desc *rd = e->desc;
781 u64 map;
baef58b1
SH		 782
783 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
784 PCI_DMA_FROMDEVICE);
785
786 rd->dma_lo = map;
787 rd->dma_hi = map >> 32;
788 e->skb = skb;
789 rd->csum1_start = ETH_HLEN;
790 rd->csum2_start = ETH_HLEN;
791 rd->csum1 = 0;
792 rd->csum2 = 0;
793
794 wmb();
795
796 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
797 pci_unmap_addr_set(e, mapaddr, map);
798 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 799}
800
19a33d4e
SH		 801/* Resume receiving using existing skb,
802 * Note: DMA address is not changed by chip.
803 * MTU not changed while receiver active.
804 */
805static void skge_rx_reuse(struct skge_element *e, unsigned int size)
806{
807 struct skge_rx_desc *rd = e->desc;
808
809 rd->csum2 = 0;
810 rd->csum2_start = ETH_HLEN;
811
812 wmb();
813
814 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
815}
816
817
818/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 819static void skge_rx_clean(struct skge_port *skge)
820{
821 struct skge_hw *hw = skge->hw;
822 struct skge_ring *ring = &skge->rx_ring;
823 struct skge_element *e;
824
19a33d4e
SH		 825 e = ring->start;
826 do {
baef58b1
SH		 827 struct skge_rx_desc *rd = e->desc;
828 rd->control = 0;
19a33d4e
SH		 829 if (e->skb) {
830 pci_unmap_single(hw->pdev,
831 pci_unmap_addr(e, mapaddr),
832 pci_unmap_len(e, maplen),
833 PCI_DMA_FROMDEVICE);
834 dev_kfree_skb(e->skb);
835 e->skb = NULL;
836 }
837 } while ((e = e->next) != ring->start);
baef58b1
SH		 838}
839
19a33d4e 840
baef58b1 841/* Allocate buffers for receive ring
19a33d4e 842 * For receive: to_clean is next received frame.
baef58b1
SH		 843 */
844static int skge_rx_fill(struct skge_port *skge)
845{
846 struct skge_ring *ring = &skge->rx_ring;
847 struct skge_element *e;
19a33d4e 848 unsigned int bufsize = skge->rx_buf_size;
baef58b1 849
19a33d4e
SH		 850 e = ring->start;
851 do {
852 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
baef58b1 853
19a33d4e
SH		 854 if (!skb)
855 return -ENOMEM;
856
857 skge_rx_setup(skge, e, skb, bufsize);
858 } while ( (e = e->next) != ring->start);
baef58b1 859
19a33d4e
SH		 860 ring->to_clean = ring->start;
861 return 0;
baef58b1
SH		 862}
863
864static void skge_link_up(struct skge_port *skge)
865{
866 netif_carrier_on(skge->netdev);
867 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
868 netif_wake_queue(skge->netdev);
869
870 if (netif_msg_link(skge))
871 printk(KERN_INFO PFX
872 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
873 skge->netdev->name, skge->speed,
874 skge->duplex == DUPLEX_FULL ? "full" : "half",
875 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
876 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
877 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
878 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
879 "unknown");
880}
881
882static void skge_link_down(struct skge_port *skge)
883{
884 netif_carrier_off(skge->netdev);
885 netif_stop_queue(skge->netdev);
886
887 if (netif_msg_link(skge))
888 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
889}
890
6b0c1480 891static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 892{
893 int i;
894 u16 v;
895
6b0c1480
SH		 896 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
897 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 898
89bf5f23
SH		 899 /* Need to wait for external PHY */
900 for (i = 0; i < PHY_RETRIES; i++) {
901 udelay(1);
902 if (xm_read16(hw, port, XM_MMU_CMD)
903 & XM_MMU_PHY_RDY)
904 goto ready;
baef58b1
SH		 905 }
906
89bf5f23
SH		 907 printk(KERN_WARNING PFX "%s: phy read timed out\n",
908 hw->dev[port]->name);
909 return 0;
910 ready:
911 v = xm_read16(hw, port, XM_PHY_DATA);
912
baef58b1
SH		 913 return v;
914}
915
6b0c1480 916static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 917{
918 int i;
919
6b0c1480 920 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 921 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 922 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 923 goto ready;
89bf5f23 924 udelay(1);
baef58b1
SH		 925 }
926 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
927 hw->dev[port]->name);
928
929
930 ready:
6b0c1480 931 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 932 for (i = 0; i < PHY_RETRIES; i++) {
933 udelay(1);
6b0c1480 934 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 935 return;
936 }
937 printk(KERN_WARNING PFX "%s: phy write timed out\n",
938 hw->dev[port]->name);
939}
940
941static void genesis_init(struct skge_hw *hw)
942{
943 /* set blink source counter */
944 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
945 skge_write8(hw, B2_BSC_CTRL, BSC_START);
946
947 /* configure mac arbiter */
948 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
949
950 /* configure mac arbiter timeout values */
951 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
952 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
953 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
954 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
955
956 skge_write8(hw, B3_MA_RCINI_RX1, 0);
957 skge_write8(hw, B3_MA_RCINI_RX2, 0);
958 skge_write8(hw, B3_MA_RCINI_TX1, 0);
959 skge_write8(hw, B3_MA_RCINI_TX2, 0);
960
961 /* configure packet arbiter timeout */
962 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
963 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
964 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
965 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
966 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
967}
968
969static void genesis_reset(struct skge_hw *hw, int port)
970{
45bada65 971 const u8 zero[8] = { 0 };
baef58b1
SH		 972
973 /* reset the statistics module */
6b0c1480
SH		 974 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
975 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
976 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
977 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
978 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 979
89bf5f23
SH		 980 /* disable Broadcom PHY IRQ */
981 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 982
45bada65 983 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 984}
985
986
45bada65
SH		 987/* Convert mode to MII values */
988static const u16 phy_pause_map[] = {
989 [FLOW_MODE_NONE] = 0,
990 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
991 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
992 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
993};
994
995
996/* Check status of Broadcom phy link */
997static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 998{
45bada65
SH		 999 struct net_device *dev = hw->dev[port];
1000 struct skge_port *skge = netdev_priv(dev);
1001 u16 status;
1002
1003 /* read twice because of latch */
1004 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1005 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1006
1007 pr_debug("bcom_check_link status=0x%x\n", status);
1008
1009 if ((status & PHY_ST_LSYNC) == 0) {
1010 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1011 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1012 xm_write16(hw, port, XM_MMU_CMD, cmd);
1013 /* dummy read to ensure writing */
1014 (void) xm_read16(hw, port, XM_MMU_CMD);
1015
1016 if (netif_carrier_ok(dev))
1017 skge_link_down(skge);
1018 } else {
1019 if (skge->autoneg == AUTONEG_ENABLE &&
1020 (status & PHY_ST_AN_OVER)) {
1021 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1022 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1023
1024 if (lpa & PHY_B_AN_RF) {
1025 printk(KERN_NOTICE PFX "%s: remote fault\n",
1026 dev->name);
1027 return;
1028 }
1029
1030 /* Check Duplex mismatch */
1031 switch(aux & PHY_B_AS_AN_RES_MSK) {
1032 case PHY_B_RES_1000FD:
1033 skge->duplex = DUPLEX_FULL;
1034 break;
1035 case PHY_B_RES_1000HD:
1036 skge->duplex = DUPLEX_HALF;
1037 break;
1038 default:
1039 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1040 dev->name);
1041 return;
1042 }
1043
1044
1045 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1046 switch (aux & PHY_B_AS_PAUSE_MSK) {
1047 case PHY_B_AS_PAUSE_MSK:
1048 skge->flow_control = FLOW_MODE_SYMMETRIC;
1049 break;
1050 case PHY_B_AS_PRR:
1051 skge->flow_control = FLOW_MODE_REM_SEND;
1052 break;
1053 case PHY_B_AS_PRT:
1054 skge->flow_control = FLOW_MODE_LOC_SEND;
1055 break;
1056 default:
1057 skge->flow_control = FLOW_MODE_NONE;
1058 }
1059
1060 skge->speed = SPEED_1000;
1061 }
1062
1063 if (!netif_carrier_ok(dev))
1064 genesis_link_up(skge);
1065 }
1066}
1067
1068/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1069 * Phy on for 100 or 10Mbit operation
1070 */
1071static void bcom_phy_init(struct skge_port *skge, int jumbo)
1072{
1073 struct skge_hw *hw = skge->hw;
1074 int port = skge->port;
baef58b1 1075 int i;
45bada65 1076 u16 id1, r, ext, ctl;
baef58b1
SH		 1077
1078 /* magic workaround patterns for Broadcom */
1079 static const struct {
1080 u16 reg;
1081 u16 val;
1082 } A1hack[] = {
1083 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1084 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1085 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1086 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1087 }, C0hack[] = {
1088 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1089 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1090 };
1091
45bada65
SH		 1092 pr_debug("bcom_phy_init\n");
1093
1094 /* read Id from external PHY (all have the same address) */
1095 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1096
1097 /* Optimize MDIO transfer by suppressing preamble. */
1098 r = xm_read16(hw, port, XM_MMU_CMD);
1099 r |= XM_MMU_NO_PRE;
1100 xm_write16(hw, port, XM_MMU_CMD,r);
1101
1102 switch(id1) {
1103 case PHY_BCOM_ID1_C0:
1104 /*
1105 * Workaround BCOM Errata for the C0 type.
1106 * Write magic patterns to reserved registers.
1107 */
1108 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1109 xm_phy_write(hw, port,
1110 C0hack[i].reg, C0hack[i].val);
1111
1112 break;
1113 case PHY_BCOM_ID1_A1:
1114 /*
1115 * Workaround BCOM Errata for the A1 type.
1116 * Write magic patterns to reserved registers.
1117 */
1118 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1119 xm_phy_write(hw, port,
1120 A1hack[i].reg, A1hack[i].val);
1121 break;
1122 }
1123
1124 /*
1125 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1126 * Disable Power Management after reset.
1127 */
1128 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1129 r |= PHY_B_AC_DIS_PM;
1130 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1131
1132 /* Dummy read */
1133 xm_read16(hw, port, XM_ISRC);
1134
1135 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1136 ctl = PHY_CT_SP1000; /* always 1000mbit */
1137
1138 if (skge->autoneg == AUTONEG_ENABLE) {
1139 /*
1140 * Workaround BCOM Errata #1 for the C5 type.
1141 * 1000Base-T Link Acquisition Failure in Slave Mode
1142 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1143 */
1144 u16 adv = PHY_B_1000C_RD;
1145 if (skge->advertising & ADVERTISED_1000baseT_Half)
1146 adv |= PHY_B_1000C_AHD;
1147 if (skge->advertising & ADVERTISED_1000baseT_Full)
1148 adv |= PHY_B_1000C_AFD;
1149 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1150
1151 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1152 } else {
1153 if (skge->duplex == DUPLEX_FULL)
1154 ctl |= PHY_CT_DUP_MD;
1155 /* Force to slave */
1156 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1157 }
1158
1159 /* Set autonegotiation pause parameters */
1160 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1161 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1162
1163 /* Handle Jumbo frames */
1164 if (jumbo) {
1165 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1166 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1167
1168 ext |= PHY_B_PEC_HIGH_LA;
1169
1170 }
1171
1172 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1173 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1174
1175 /* Use link status change interrrupt */
1176 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1177
1178 bcom_check_link(hw, port);
1179}
1180
1181static void genesis_mac_init(struct skge_hw *hw, int port)
1182{
1183 struct net_device *dev = hw->dev[port];
1184 struct skge_port *skge = netdev_priv(dev);
1185 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1186 int i;
1187 u32 r;
1188 const u8 zero[6] = { 0 };
1189
1190 /* Clear MIB counters */
1191 xm_write16(hw, port, XM_STAT_CMD,
1192 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1193 /* Clear two times according to Errata #3 */
1194 xm_write16(hw, port, XM_STAT_CMD,
1195 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1
SH		 1196
1197 /* initialize Rx, Tx and Link LED */
6b0c1480
SH		 1198 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1199 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 1200
6b0c1480
SH		 1201 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1202 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 1203
1204 /* Unreset the XMAC. */
6b0c1480 1205 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1206
1207 /*
1208 * Perform additional initialization for external PHYs,
1209 * namely for the 1000baseTX cards that use the XMAC's
1210 * GMII mode.
1211 */
1212 spin_lock_bh(&hw->phy_lock);
45bada65 1213 /* Take external Phy out of reset */
89bf5f23
SH		 1214 r = skge_read32(hw, B2_GP_IO);
1215 if (port == 0)
1216 r |= GP_DIR_0|GP_IO_0;
1217 else
1218 r |= GP_DIR_2|GP_IO_2;
1219
1220 skge_write32(hw, B2_GP_IO, r);
1221 skge_read32(hw, B2_GP_IO);
45bada65 1222 spin_unlock_bh(&hw->phy_lock);
89bf5f23 1223
45bada65 1224 /* Enable GMII interfac */
89bf5f23
SH		 1225 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1226
45bada65 1227 bcom_phy_init(skge, jumbo);
89bf5f23 1228
45bada65
SH		 1229 /* Set Station Address */
1230 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1231
45bada65
SH		 1232 /* We don't use match addresses so clear */
1233 for (i = 1; i < 16; i++)
1234 xm_outaddr(hw, port, XM_EXM(i), zero);
1235
1236 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1237 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1238
1239 /* We don't need the FCS appended to the packet. */
1240 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1241 if (jumbo)
1242 r |= XM_RX_BIG_PK_OK;
89bf5f23 1243
45bada65 1244 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1245 /*
45bada65
SH		 1246 * If in manual half duplex mode the other side might be in
1247 * full duplex mode, so ignore if a carrier extension is not seen
1248 * on frames received
89bf5f23 1249 */
45bada65 1250 r |= XM_RX_DIS_CEXT;
baef58b1 1251 }
45bada65 1252 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1253
baef58b1
SH		 1254
1255 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1256 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1257
1258 /*
1259 * Bump up the transmit threshold. This helps hold off transmit
1260 * underruns when we're blasting traffic from both ports at once.
1261 */
1262 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1263
1264 /*
1265 * Enable the reception of all error frames. This is is
1266 * a necessary evil due to the design of the XMAC. The
1267 * XMAC's receive FIFO is only 8K in size, however jumbo
1268 * frames can be up to 9000 bytes in length. When bad
1269 * frame filtering is enabled, the XMAC's RX FIFO operates
1270 * in 'store and forward' mode. For this to work, the
1271 * entire frame has to fit into the FIFO, but that means
1272 * that jumbo frames larger than 8192 bytes will be
1273 * truncated. Disabling all bad frame filtering causes
1274 * the RX FIFO to operate in streaming mode, in which
1275 * case the XMAC will start transfering frames out of the
1276 * RX FIFO as soon as the FIFO threshold is reached.
1277 */
45bada65 1278 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1279
baef58b1
SH		 1280
1281 /*
45bada65
SH		 1282 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1283 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1284 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1285 */
45bada65
SH		 1286 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1287
1288 /*
1289 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1290 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1291 * and 'Octets Tx OK Hi Cnt Ov'.
1292 */
1293 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1294
1295 /* Configure MAC arbiter */
1296 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1297
1298 /* configure timeout values */
1299 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1300 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1301 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1302 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1303
1304 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1305 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1306 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1307 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1308
1309 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1310 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1311 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1312 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1313
1314 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1315 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1316 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1317 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1318
45bada65 1319 if (jumbo) {
baef58b1 1320 /* Enable frame flushing if jumbo frames used */
6b0c1480 1321 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1322 } else {
1323 /* enable timeout timers if normal frames */
1324 skge_write16(hw, B3_PA_CTRL,
45bada65 1325 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1326 }
baef58b1
SH		 1327}
1328
1329static void genesis_stop(struct skge_port *skge)
1330{
1331 struct skge_hw *hw = skge->hw;
1332 int port = skge->port;
89bf5f23 1333 u32 reg;
baef58b1
SH		 1334
1335 /* Clear Tx packet arbiter timeout IRQ */
1336 skge_write16(hw, B3_PA_CTRL,
1337 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1338
1339 /*
1340 * If the transfer stucks at the MAC the STOP command will not
1341 * terminate if we don't flush the XMAC's transmit FIFO !
1342 */
6b0c1480
SH		 1343 xm_write32(hw, port, XM_MODE,
1344 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1345
1346
1347 /* Reset the MAC */
6b0c1480 1348 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1349
1350 /* For external PHYs there must be special handling */
89bf5f23
SH		 1351 reg = skge_read32(hw, B2_GP_IO);
1352 if (port == 0) {
1353 reg |= GP_DIR_0;
1354 reg &= ~GP_IO_0;
1355 } else {
1356 reg |= GP_DIR_2;
1357 reg &= ~GP_IO_2;
baef58b1 1358 }
89bf5f23
SH		 1359 skge_write32(hw, B2_GP_IO, reg);
1360 skge_read32(hw, B2_GP_IO);
baef58b1 1361
6b0c1480
SH		 1362 xm_write16(hw, port, XM_MMU_CMD,
1363 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1364 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1365
6b0c1480 1366 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1367}
1368
1369
1370static void genesis_get_stats(struct skge_port *skge, u64 *data)
1371{
1372 struct skge_hw *hw = skge->hw;
1373 int port = skge->port;
1374 int i;
1375 unsigned long timeout = jiffies + HZ;
1376
6b0c1480 1377 xm_write16(hw, port,
baef58b1
SH		 1378 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1379
1380 /* wait for update to complete */
6b0c1480 1381 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1382 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1383 if (time_after(jiffies, timeout))
1384 break;
1385 udelay(10);
1386 }
1387
1388 /* special case for 64 bit octet counter */
6b0c1480
SH		 1389 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1390 | xm_read32(hw, port, XM_TXO_OK_LO);
1391 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1392 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1393
1394 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1395 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1396}
1397
1398static void genesis_mac_intr(struct skge_hw *hw, int port)
1399{
1400 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1401 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1402
7e676d91
SH		 1403 if (netif_msg_intr(skge))
1404 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1405 skge->netdev->name, status);
baef58b1
SH		 1406
1407 if (status & XM_IS_TXF_UR) {
6b0c1480 1408 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1409 ++skge->net_stats.tx_fifo_errors;
1410 }
1411 if (status & XM_IS_RXF_OV) {
6b0c1480 1412 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1413 ++skge->net_stats.rx_fifo_errors;
1414 }
1415}
1416
6b0c1480 1417static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1418{
1419 int i;
1420
6b0c1480
SH		 1421 gma_write16(hw, port, GM_SMI_DATA, val);
1422 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1423 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1424 for (i = 0; i < PHY_RETRIES; i++) {
1425 udelay(1);
1426
6b0c1480 1427 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1428 break;
1429 }
1430}
1431
6b0c1480 1432static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1433{
1434 int i;
1435
6b0c1480 1436 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1437 GM_SMI_CT_PHY_AD(hw->phy_addr)
1438 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1439
1440 for (i = 0; i < PHY_RETRIES; i++) {
1441 udelay(1);
6b0c1480 1442 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1443 goto ready;
1444 }
1445
1446 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1447 hw->dev[port]->name);
1448 return 0;
1449 ready:
6b0c1480 1450 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1451}
1452
baef58b1
SH		 1453static void genesis_link_up(struct skge_port *skge)
1454{
1455 struct skge_hw *hw = skge->hw;
1456 int port = skge->port;
1457 u16 cmd;
1458 u32 mode, msk;
1459
1460 pr_debug("genesis_link_up\n");
6b0c1480 1461 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1462
1463 /*
1464 * enabling pause frame reception is required for 1000BT
1465 * because the XMAC is not reset if the link is going down
1466 */
1467 if (skge->flow_control == FLOW_MODE_NONE ||
1468 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1469 /* Disable Pause Frame Reception */
baef58b1
SH		 1470 cmd |= XM_MMU_IGN_PF;
1471 else
1472 /* Enable Pause Frame Reception */
1473 cmd &= ~XM_MMU_IGN_PF;
1474
6b0c1480 1475 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1476
6b0c1480 1477 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1478 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1479 skge->flow_control == FLOW_MODE_LOC_SEND) {
1480 /*
1481 * Configure Pause Frame Generation
1482 * Use internal and external Pause Frame Generation.
1483 * Sending pause frames is edge triggered.
1484 * Send a Pause frame with the maximum pause time if
1485 * internal oder external FIFO full condition occurs.
1486 * Send a zero pause time frame to re-start transmission.
1487 */
1488 /* XM_PAUSE_DA = '010000C28001' (default) */
1489 /* XM_MAC_PTIME = 0xffff (maximum) */
1490 /* remember this value is defined in big endian (!) */
6b0c1480 1491 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1492
1493 mode |= XM_PAUSE_MODE;
6b0c1480 1494 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1495 } else {
1496 /*
1497 * disable pause frame generation is required for 1000BT
1498 * because the XMAC is not reset if the link is going down
1499 */
1500 /* Disable Pause Mode in Mode Register */
1501 mode &= ~XM_PAUSE_MODE;
1502
6b0c1480 1503 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1504 }
1505
6b0c1480 1506 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1507
1508 msk = XM_DEF_MSK;
89bf5f23
SH		 1509 /* disable GP0 interrupt bit for external Phy */
1510 msk |= XM_IS_INP_ASS;
baef58b1 1511
6b0c1480
SH		 1512 xm_write16(hw, port, XM_IMSK, msk);
1513 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1514
1515 /* get MMU Command Reg. */
6b0c1480 1516 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1517 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1518 cmd |= XM_MMU_GMII_FD;
1519
89bf5f23
SH		 1520 /*
1521 * Workaround BCOM Errata (#10523) for all BCom Phys
1522 * Enable Power Management after link up
1523 */
1524 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1525 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1526 & ~PHY_B_AC_DIS_PM);
1527 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1528
1529 /* enable Rx/Tx */
6b0c1480 1530 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1531 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1532 skge_link_up(skge);
1533}
1534
1535
45bada65 1536static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1537{
1538 struct skge_hw *hw = skge->hw;
1539 int port = skge->port;
45bada65
SH		 1540 u16 isrc;
1541
1542 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1543 if (netif_msg_intr(skge))
1544 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1545 skge->netdev->name, isrc);
baef58b1 1546
45bada65
SH		 1547 if (isrc & PHY_B_IS_PSE)
1548 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1549 hw->dev[port]->name);
baef58b1
SH		 1550
1551 /* Workaround BCom Errata:
1552 * enable and disable loopback mode if "NO HCD" occurs.
1553 */
45bada65 1554 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1555 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1556 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1557 ctrl | PHY_CT_LOOP);
6b0c1480 1558 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1559 ctrl & ~PHY_CT_LOOP);
1560 }
1561
45bada65
SH		 1562 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1563 bcom_check_link(hw, port);
baef58b1 1564
baef58b1
SH		 1565}
1566
1567/* Marvell Phy Initailization */
1568static void yukon_init(struct skge_hw *hw, int port)
1569{
1570 struct skge_port *skge = netdev_priv(hw->dev[port]);
1571 u16 ctrl, ct1000, adv;
1572 u16 ledctrl, ledover;
1573
1574 pr_debug("yukon_init\n");
1575 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1576 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1577
1578 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1579 PHY_M_EC_MAC_S_MSK);
1580 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1581
c506a509 1582 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1583
6b0c1480 1584 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1585 }
1586
6b0c1480 1587 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1588 if (skge->autoneg == AUTONEG_DISABLE)
1589 ctrl &= ~PHY_CT_ANE;
1590
1591 ctrl |= PHY_CT_RESET;
6b0c1480 1592 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1593
1594 ctrl = 0;
1595 ct1000 = 0;
b18f2091 1596 adv = PHY_AN_CSMA;
baef58b1
SH		 1597
1598 if (skge->autoneg == AUTONEG_ENABLE) {
1599 if (iscopper(hw)) {
1600 if (skge->advertising & ADVERTISED_1000baseT_Full)
1601 ct1000 |= PHY_M_1000C_AFD;
1602 if (skge->advertising & ADVERTISED_1000baseT_Half)
1603 ct1000 |= PHY_M_1000C_AHD;
1604 if (skge->advertising & ADVERTISED_100baseT_Full)
1605 adv |= PHY_M_AN_100_FD;
1606 if (skge->advertising & ADVERTISED_100baseT_Half)
1607 adv |= PHY_M_AN_100_HD;
1608 if (skge->advertising & ADVERTISED_10baseT_Full)
1609 adv |= PHY_M_AN_10_FD;
1610 if (skge->advertising & ADVERTISED_10baseT_Half)
1611 adv |= PHY_M_AN_10_HD;
45bada65 1612 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1613 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1614
45bada65
SH		 1615 /* Set Flow-control capabilities */
1616 adv |= phy_pause_map[skge->flow_control];
1617
baef58b1
SH		 1618 /* Restart Auto-negotiation */
1619 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1620 } else {
1621 /* forced speed/duplex settings */
1622 ct1000 = PHY_M_1000C_MSE;
1623
1624 if (skge->duplex == DUPLEX_FULL)
1625 ctrl |= PHY_CT_DUP_MD;
1626
1627 switch (skge->speed) {
1628 case SPEED_1000:
1629 ctrl |= PHY_CT_SP1000;
1630 break;
1631 case SPEED_100:
1632 ctrl |= PHY_CT_SP100;
1633 break;
1634 }
1635
1636 ctrl |= PHY_CT_RESET;
1637 }
1638
c506a509 1639 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1640
6b0c1480
SH		 1641 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1642 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1643
1644 /* Setup Phy LED's */
1645 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1646 ledover = 0;
1647
c506a509 1648 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
baef58b1 1649
c506a509
SH		 1650 /* turn off the Rx LED (LED_RX) */
1651 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
baef58b1
SH		 1652
1653 /* disable blink mode (LED_DUPLEX) on collisions */
1654 ctrl |= PHY_M_LEDC_DP_CTRL;
6b0c1480 1655 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
baef58b1
SH		 1656
1657 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1658 /* turn on 100 Mbps LED (LED_LINK100) */
1659 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1660 }
1661
1662 if (ledover)
6b0c1480 1663 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
baef58b1
SH		 1664
1665 /* Enable phy interrupt on autonegotiation complete (or link up) */
1666 if (skge->autoneg == AUTONEG_ENABLE)
6b0c1480 1667 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
baef58b1 1668 else
6b0c1480 1669 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1670}
1671
1672static void yukon_reset(struct skge_hw *hw, int port)
1673{
6b0c1480
SH		 1674 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1675 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1676 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1677 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1678 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1679
6b0c1480
SH		 1680 gma_write16(hw, port, GM_RX_CTRL,
1681 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1682 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1683}
1684
1685static void yukon_mac_init(struct skge_hw *hw, int port)
1686{
1687 struct skge_port *skge = netdev_priv(hw->dev[port]);
1688 int i;
1689 u32 reg;
1690 const u8 *addr = hw->dev[port]->dev_addr;
1691
1692 /* WA code for COMA mode -- set PHY reset */
1693 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1694 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1695 skge_write32(hw, B2_GP_IO,
1696 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1697
1698 /* hard reset */
6b0c1480
SH		 1699 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1700 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1701
1702 /* WA code for COMA mode -- clear PHY reset */
1703 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1704 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1705 skge_write32(hw, B2_GP_IO,
1706 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1707 & ~GP_IO_9);
1708
1709 /* Set hardware config mode */
1710 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1711 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1712 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1713
1714 /* Clear GMC reset */
6b0c1480
SH		 1715 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1716 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1717 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1718 if (skge->autoneg == AUTONEG_DISABLE) {
1719 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1720 gma_write16(hw, port, GM_GP_CTRL,
1721 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1722
1723 switch (skge->speed) {
1724 case SPEED_1000:
1725 reg |= GM_GPCR_SPEED_1000;
1726 /* fallthru */
1727 case SPEED_100:
1728 reg |= GM_GPCR_SPEED_100;
1729 }
1730
1731 if (skge->duplex == DUPLEX_FULL)
1732 reg |= GM_GPCR_DUP_FULL;
1733 } else
1734 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1735 switch (skge->flow_control) {
1736 case FLOW_MODE_NONE:
6b0c1480 1737 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1738 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1739 break;
1740 case FLOW_MODE_LOC_SEND:
1741 /* disable Rx flow-control */
1742 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1743 }
1744
6b0c1480 1745 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1
SH		 1746 skge_read16(hw, GMAC_IRQ_SRC);
1747
1748 spin_lock_bh(&hw->phy_lock);
1749 yukon_init(hw, port);
1750 spin_unlock_bh(&hw->phy_lock);
1751
1752 /* MIB clear */
6b0c1480
SH		 1753 reg = gma_read16(hw, port, GM_PHY_ADDR);
1754 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1755
1756 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1757 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1758 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1759
1760 /* transmit control */
6b0c1480 1761 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1762
1763 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1764 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1765 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1766
1767 /* transmit flow control */
6b0c1480 1768 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1769
1770 /* transmit parameter */
6b0c1480 1771 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1772 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1773 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1774 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1775
1776 /* serial mode register */
1777 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1778 if (hw->dev[port]->mtu > 1500)
1779 reg |= GM_SMOD_JUMBO_ENA;
1780
6b0c1480 1781 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1782
1783 /* physical address: used for pause frames */
6b0c1480 1784 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1785 /* virtual address for data */
6b0c1480 1786 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1787
1788 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1789 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1790 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1791 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1792
1793 /* Initialize Mac Fifo */
1794
1795 /* Configure Rx MAC FIFO */
6b0c1480 1796 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1797 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1798 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1799 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1 1800 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1801 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1802 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1803 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
baef58b1
SH		 1804
1805 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1806 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1807 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1808}
1809
1810static void yukon_stop(struct skge_port *skge)
1811{
1812 struct skge_hw *hw = skge->hw;
1813 int port = skge->port;
1814
1815 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1816 hw->chip_rev == CHIP_REV_YU_LITE_A3) {
baef58b1
SH		 1817 skge_write32(hw, B2_GP_IO,
1818 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1819 }
1820
6b0c1480
SH		 1821 gma_write16(hw, port, GM_GP_CTRL,
1822 gma_read16(hw, port, GM_GP_CTRL)
baef58b1 1823 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1824 gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1825
1826 /* set GPHY Control reset */
6b0c1480
SH		 1827 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1828 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
baef58b1
SH		 1829}
1830
1831static void yukon_get_stats(struct skge_port *skge, u64 *data)
1832{
1833 struct skge_hw *hw = skge->hw;
1834 int port = skge->port;
1835 int i;
1836
6b0c1480
SH		 1837 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1838 | gma_read32(hw, port, GM_TXO_OK_LO);
1839 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1840 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1841
1842 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1843 data[i] = gma_read32(hw, port,
baef58b1
SH		 1844 skge_stats[i].gma_offset);
1845}
1846
1847static void yukon_mac_intr(struct skge_hw *hw, int port)
1848{
7e676d91
SH		 1849 struct net_device *dev = hw->dev[port];
1850 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1851 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1852
7e676d91
SH		 1853 if (netif_msg_intr(skge))
1854 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1855 dev->name, status);
1856
baef58b1
SH		 1857 if (status & GM_IS_RX_FF_OR) {
1858 ++skge->net_stats.rx_fifo_errors;
6b0c1480 1859 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
baef58b1
SH		 1860 }
1861 if (status & GM_IS_TX_FF_UR) {
1862 ++skge->net_stats.tx_fifo_errors;
6b0c1480 1863 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
baef58b1
SH		 1864 }
1865
1866}
1867
1868static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1869{
95566065 1870 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1871 case PHY_M_PS_SPEED_1000:
1872 return SPEED_1000;
1873 case PHY_M_PS_SPEED_100:
1874 return SPEED_100;
1875 default:
1876 return SPEED_10;
1877 }
1878}
1879
1880static void yukon_link_up(struct skge_port *skge)
1881{
1882 struct skge_hw *hw = skge->hw;
1883 int port = skge->port;
1884 u16 reg;
1885
1886 pr_debug("yukon_link_up\n");
1887
1888 /* Enable Transmit FIFO Underrun */
1889 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1890
6b0c1480 1891 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1892 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1893 reg |= GM_GPCR_DUP_FULL;
1894
1895 /* enable Rx/Tx */
1896 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1897 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1898
6b0c1480 1899 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1900 skge_link_up(skge);
1901}
1902
1903static void yukon_link_down(struct skge_port *skge)
1904{
1905 struct skge_hw *hw = skge->hw;
1906 int port = skge->port;
1907
1908 pr_debug("yukon_link_down\n");
6b0c1480
SH		 1909 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1910 gm_phy_write(hw, port, GM_GP_CTRL,
1911 gm_phy_read(hw, port, GM_GP_CTRL)
baef58b1
SH		 1912 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1913
c506a509 1914 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1915 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1916 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1917 gm_phy_read(hw, port,
baef58b1
SH		 1918 PHY_MARV_AUNE_ADV)
1919 | PHY_M_AN_ASP);
1920
1921 }
1922
1923 yukon_reset(hw, port);
1924 skge_link_down(skge);
1925
1926 yukon_init(hw, port);
1927}
1928
1929static void yukon_phy_intr(struct skge_port *skge)
1930{
1931 struct skge_hw *hw = skge->hw;
1932 int port = skge->port;
1933 const char *reason = NULL;
1934 u16 istatus, phystat;
1935
6b0c1480
SH		 1936 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1937 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1938
1939 if (netif_msg_intr(skge))
1940 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1941 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1942
1943 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1944 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1945 & PHY_M_AN_RF) {
1946 reason = "remote fault";
1947 goto failed;
1948 }
1949
c506a509 1950 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1951 reason = "master/slave fault";
1952 goto failed;
1953 }
1954
1955 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1956 reason = "speed/duplex";
1957 goto failed;
1958 }
1959
1960 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1961 ? DUPLEX_FULL : DUPLEX_HALF;
1962 skge->speed = yukon_speed(hw, phystat);
1963
baef58b1
SH		 1964 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1965 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1966 case PHY_M_PS_PAUSE_MSK:
1967 skge->flow_control = FLOW_MODE_SYMMETRIC;
1968 break;
1969 case PHY_M_PS_RX_P_EN:
1970 skge->flow_control = FLOW_MODE_REM_SEND;
1971 break;
1972 case PHY_M_PS_TX_P_EN:
1973 skge->flow_control = FLOW_MODE_LOC_SEND;
1974 break;
1975 default:
1976 skge->flow_control = FLOW_MODE_NONE;
1977 }
1978
1979 if (skge->flow_control == FLOW_MODE_NONE ||
1980 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1981 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1982 else
6b0c1480 1983 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1984 yukon_link_up(skge);
1985 return;
1986 }
1987
1988 if (istatus & PHY_M_IS_LSP_CHANGE)
1989 skge->speed = yukon_speed(hw, phystat);
1990
1991 if (istatus & PHY_M_IS_DUP_CHANGE)
1992 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1993 if (istatus & PHY_M_IS_LST_CHANGE) {
1994 if (phystat & PHY_M_PS_LINK_UP)
1995 yukon_link_up(skge);
1996 else
1997 yukon_link_down(skge);
1998 }
1999 return;
2000 failed:
2001 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2002 skge->netdev->name, reason);
2003
2004 /* XXX restart autonegotiation? */
2005}
2006
2007static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2008{
2009 u32 end;
2010
2011 start /= 8;
2012 len /= 8;
2013 end = start + len - 1;
2014
2015 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2016 skge_write32(hw, RB_ADDR(q, RB_START), start);
2017 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2018 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2019 skge_write32(hw, RB_ADDR(q, RB_END), end);
2020
2021 if (q == Q_R1 || q == Q_R2) {
2022 /* Set thresholds on receive queue's */
2023 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2024 start + (2*len)/3);
2025 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2026 start + (len/3));
2027 } else {
2028 /* Enable store & forward on Tx queue's because
2029 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2030 */
2031 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2032 }
2033
2034 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2035}
2036
2037/* Setup Bus Memory Interface */
2038static void skge_qset(struct skge_port *skge, u16 q,
2039 const struct skge_element *e)
2040{
2041 struct skge_hw *hw = skge->hw;
2042 u32 watermark = 0x600;
2043 u64 base = skge->dma + (e->desc - skge->mem);
2044
2045 /* optimization to reduce window on 32bit/33mhz */
2046 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2047 watermark /= 2;
2048
2049 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2050 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2051 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2052 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2053}
2054
2055static int skge_up(struct net_device *dev)
2056{
2057 struct skge_port *skge = netdev_priv(dev);
2058 struct skge_hw *hw = skge->hw;
2059 int port = skge->port;
2060 u32 chunk, ram_addr;
2061 size_t rx_size, tx_size;
2062 int err;
2063
2064 if (netif_msg_ifup(skge))
2065 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2066
19a33d4e
SH		 2067 if (dev->mtu > RX_BUF_SIZE)
2068 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2069 else
2070 skge->rx_buf_size = RX_BUF_SIZE;
2071
2072
baef58b1
SH		 2073 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2074 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2075 skge->mem_size = tx_size + rx_size;
2076 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2077 if (!skge->mem)
2078 return -ENOMEM;
2079
2080 memset(skge->mem, 0, skge->mem_size);
2081
2082 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2083 goto free_pci_mem;
2084
19a33d4e
SH		 2085 err = skge_rx_fill(skge);
2086 if (err)
baef58b1
SH		 2087 goto free_rx_ring;
2088
2089 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2090 skge->dma + rx_size)))
2091 goto free_rx_ring;
2092
2093 skge->tx_avail = skge->tx_ring.count - 1;
2094
7e676d91
SH		 2095 /* Enable IRQ from port */
2096 hw->intr_mask |= portirqmask[port];
2097 skge_write32(hw, B0_IMSK, hw->intr_mask);
2098
baef58b1
SH		 2099 /* Initialze MAC */
2100 if (hw->chip_id == CHIP_ID_GENESIS)
2101 genesis_mac_init(hw, port);
2102 else
2103 yukon_mac_init(hw, port);
2104
2105 /* Configure RAMbuffers */
981d0377 2106 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2107 ram_addr = hw->ram_offset + 2 * chunk * port;
2108
2109 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2110 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2111
2112 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2113 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2114 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2115
2116 /* Start receiver BMU */
2117 wmb();
2118 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2119
2120 pr_debug("skge_up completed\n");
2121 return 0;
2122
2123 free_rx_ring:
2124 skge_rx_clean(skge);
2125 kfree(skge->rx_ring.start);
2126 free_pci_mem:
2127 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2128
2129 return err;
2130}
2131
2132static int skge_down(struct net_device *dev)
2133{
2134 struct skge_port *skge = netdev_priv(dev);
2135 struct skge_hw *hw = skge->hw;
2136 int port = skge->port;
2137
2138 if (netif_msg_ifdown(skge))
2139 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2140
2141 netif_stop_queue(dev);
2142
2143 del_timer_sync(&skge->led_blink);
baef58b1
SH		 2144
2145 /* Stop transmitter */
2146 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2147 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2148 RB_RST_SET|RB_DIS_OP_MD);
2149
2150 if (hw->chip_id == CHIP_ID_GENESIS)
2151 genesis_stop(skge);
2152 else
2153 yukon_stop(skge);
2154
2155 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2156 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2157 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2158
2159 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2160 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2161 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2162
2163 /* Reset PCI FIFO */
2164 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2165 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2166
2167 /* Reset the RAM Buffer async Tx queue */
2168 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2169 /* stop receiver */
2170 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2171 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2172 RB_RST_SET|RB_DIS_OP_MD);
2173 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2174
2175 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2176 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2177 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2178 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2179 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
baef58b1 2180 } else {
6b0c1480
SH		 2181 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2182 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2183 }
2184
2185 /* turn off led's */
2186 skge_write16(hw, B0_LED, LED_STAT_OFF);
2187
2188 skge_tx_clean(skge);
2189 skge_rx_clean(skge);
2190
2191 kfree(skge->rx_ring.start);
2192 kfree(skge->tx_ring.start);
2193 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2194 return 0;
2195}
2196
2197static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2198{
2199 struct skge_port *skge = netdev_priv(dev);
2200 struct skge_hw *hw = skge->hw;
2201 struct skge_ring *ring = &skge->tx_ring;
2202 struct skge_element *e;
2203 struct skge_tx_desc *td;
2204 int i;
2205 u32 control, len;
2206 u64 map;
2207 unsigned long flags;
2208
2209 skb = skb_padto(skb, ETH_ZLEN);
2210 if (!skb)
2211 return NETDEV_TX_OK;
2212
2213 local_irq_save(flags);
2214 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2215 /* Collision - tell upper layer to requeue */
2216 local_irq_restore(flags);
2217 return NETDEV_TX_LOCKED;
2218 }
baef58b1
SH		 2219
2220 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2221 netif_stop_queue(dev);
2222 spin_unlock_irqrestore(&skge->tx_lock, flags);
2223
2224 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2225 dev->name);
2226 return NETDEV_TX_BUSY;
2227 }
2228
2229 e = ring->to_use;
2230 td = e->desc;
2231 e->skb = skb;
2232 len = skb_headlen(skb);
2233 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2234 pci_unmap_addr_set(e, mapaddr, map);
2235 pci_unmap_len_set(e, maplen, len);
2236
2237 td->dma_lo = map;
2238 td->dma_hi = map >> 32;
2239
2240 if (skb->ip_summed == CHECKSUM_HW) {
2241 const struct iphdr *ip
2242 = (const struct iphdr *) (skb->data + ETH_HLEN);
2243 int offset = skb->h.raw - skb->data;
2244
2245 /* This seems backwards, but it is what the sk98lin
2246 * does. Looks like hardware is wrong?
2247 */
2248 if (ip->protocol == IPPROTO_UDP
981d0377 2249 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2250 control = BMU_TCP_CHECK;
2251 else
2252 control = BMU_UDP_CHECK;
2253
2254 td->csum_offs = 0;
2255 td->csum_start = offset;
2256 td->csum_write = offset + skb->csum;
2257 } else
2258 control = BMU_CHECK;
2259
2260 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2261 control |= BMU_EOF| BMU_IRQ_EOF;
2262 else {
2263 struct skge_tx_desc *tf = td;
2264
2265 control |= BMU_STFWD;
2266 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2267 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2268
2269 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2270 frag->size, PCI_DMA_TODEVICE);
2271
2272 e = e->next;
2273 e->skb = NULL;
2274 tf = e->desc;
2275 tf->dma_lo = map;
2276 tf->dma_hi = (u64) map >> 32;
2277 pci_unmap_addr_set(e, mapaddr, map);
2278 pci_unmap_len_set(e, maplen, frag->size);
2279
2280 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2281 }
2282 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2283 }
2284 /* Make sure all the descriptors written */
2285 wmb();
2286 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2287 wmb();
2288
2289 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2290
2291 if (netif_msg_tx_queued(skge))
0b2d7fea 2292 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2293 dev->name, e - ring->start, skb->len);
2294
2295 ring->to_use = e->next;
2296 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2297 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2298 pr_debug("%s: transmit queue full\n", dev->name);
2299 netif_stop_queue(dev);
2300 }
2301
2302 dev->trans_start = jiffies;
2303 spin_unlock_irqrestore(&skge->tx_lock, flags);
2304
2305 return NETDEV_TX_OK;
2306}
2307
2308static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2309{
19a33d4e 2310 /* This ring element can be skb or fragment */
baef58b1
SH		 2311 if (e->skb) {
2312 pci_unmap_single(hw->pdev,
2313 pci_unmap_addr(e, mapaddr),
2314 pci_unmap_len(e, maplen),
2315 PCI_DMA_TODEVICE);
2316 dev_kfree_skb_any(e->skb);
2317 e->skb = NULL;
2318 } else {
2319 pci_unmap_page(hw->pdev,
2320 pci_unmap_addr(e, mapaddr),
2321 pci_unmap_len(e, maplen),
2322 PCI_DMA_TODEVICE);
2323 }
2324}
2325
2326static void skge_tx_clean(struct skge_port *skge)
2327{
2328 struct skge_ring *ring = &skge->tx_ring;
2329 struct skge_element *e;
2330 unsigned long flags;
2331
2332 spin_lock_irqsave(&skge->tx_lock, flags);
2333 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2334 ++skge->tx_avail;
2335 skge_tx_free(skge->hw, e);
2336 }
2337 ring->to_clean = e;
2338 spin_unlock_irqrestore(&skge->tx_lock, flags);
2339}
2340
2341static void skge_tx_timeout(struct net_device *dev)
2342{
2343 struct skge_port *skge = netdev_priv(dev);
2344
2345 if (netif_msg_timer(skge))
2346 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2347
2348 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2349 skge_tx_clean(skge);
2350}
2351
2352static int skge_change_mtu(struct net_device *dev, int new_mtu)
2353{
2354 int err = 0;
19a33d4e 2355 int running = netif_running(dev);
baef58b1 2356
95566065 2357 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2358 return -EINVAL;
2359
baef58b1 2360
19a33d4e 2361 if (running)
baef58b1 2362 skge_down(dev);
19a33d4e
SH		 2363 dev->mtu = new_mtu;
2364 if (running)
baef58b1 2365 skge_up(dev);
baef58b1
SH		 2366
2367 return err;
2368}
2369
2370static void genesis_set_multicast(struct net_device *dev)
2371{
2372 struct skge_port *skge = netdev_priv(dev);
2373 struct skge_hw *hw = skge->hw;
2374 int port = skge->port;
2375 int i, count = dev->mc_count;
2376 struct dev_mc_list *list = dev->mc_list;
2377 u32 mode;
2378 u8 filter[8];
2379
45bada65
SH		 2380 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2381
6b0c1480 2382 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2383 mode |= XM_MD_ENA_HASH;
2384 if (dev->flags & IFF_PROMISC)
2385 mode |= XM_MD_ENA_PROM;
2386 else
2387 mode &= ~XM_MD_ENA_PROM;
2388
2389 if (dev->flags & IFF_ALLMULTI)
2390 memset(filter, 0xff, sizeof(filter));
2391 else {
2392 memset(filter, 0, sizeof(filter));
95566065 2393 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2394 u32 crc, bit;
2395 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2396 bit = ~crc & 0x3f;
baef58b1
SH		 2397 filter[bit/8] |= 1 << (bit%8);
2398 }
2399 }
2400
6b0c1480 2401 xm_write32(hw, port, XM_MODE, mode);
45bada65 2402 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2403}
2404
2405static void yukon_set_multicast(struct net_device *dev)
2406{
2407 struct skge_port *skge = netdev_priv(dev);
2408 struct skge_hw *hw = skge->hw;
2409 int port = skge->port;
2410 struct dev_mc_list *list = dev->mc_list;
2411 u16 reg;
2412 u8 filter[8];
2413
2414 memset(filter, 0, sizeof(filter));
2415
6b0c1480 2416 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2417 reg |= GM_RXCR_UCF_ENA;
2418
2419 if (dev->flags & IFF_PROMISC) /* promiscious */
2420 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2421 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2422 memset(filter, 0xff, sizeof(filter));
2423 else if (dev->mc_count == 0) /* no multicast */
2424 reg &= ~GM_RXCR_MCF_ENA;
2425 else {
2426 int i;
2427 reg |= GM_RXCR_MCF_ENA;
2428
95566065 2429 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2430 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2431 filter[bit/8] |= 1 << (bit%8);
2432 }
2433 }
2434
2435
6b0c1480 2436 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2437 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2438 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2439 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2440 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2441 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2442 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2443 (u16)filter[6] | ((u16)filter[7] << 8));
2444
6b0c1480 2445 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2446}
2447
2448static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2449{
2450 if (hw->chip_id == CHIP_ID_GENESIS)
2451 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2452 else
2453 return (status & GMR_FS_ANY_ERR) ||
2454 (status & GMR_FS_RX_OK) == 0;
2455}
2456
2457static void skge_rx_error(struct skge_port *skge, int slot,
2458 u32 control, u32 status)
2459{
2460 if (netif_msg_rx_err(skge))
2461 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2462 skge->netdev->name, slot, control, status);
2463
19a33d4e 2464 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
baef58b1 2465 skge->net_stats.rx_length_errors++;
19a33d4e
SH		 2466 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2467 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2468 skge->net_stats.rx_length_errors++;
2469 if (status & XMR_FS_FRA_ERR)
2470 skge->net_stats.rx_frame_errors++;
2471 if (status & XMR_FS_FCS_ERR)
2472 skge->net_stats.rx_crc_errors++;
2473 } else {
2474 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2475 skge->net_stats.rx_length_errors++;
2476 if (status & GMR_FS_FRAGMENT)
2477 skge->net_stats.rx_frame_errors++;
2478 if (status & GMR_FS_CRC_ERR)
2479 skge->net_stats.rx_crc_errors++;
2480 }
2481}
2482
2483/* Get receive buffer from descriptor.
2484 * Handles copy of small buffers and reallocation failures
2485 */
2486static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2487 struct skge_element *e,
2488 unsigned int len)
2489{
2490 struct sk_buff *nskb, *skb;
2491
2492 if (len < RX_COPY_THRESHOLD) {
2493 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2494 if (unlikely(!nskb))
2495 return NULL;
2496
2497 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2498 pci_unmap_addr(e, mapaddr),
2499 len, PCI_DMA_FROMDEVICE);
2500 memcpy(nskb->data, e->skb->data, len);
2501 pci_dma_sync_single_for_device(skge->hw->pdev,
2502 pci_unmap_addr(e, mapaddr),
2503 len, PCI_DMA_FROMDEVICE);
2504
2505 if (skge->rx_csum) {
2506 struct skge_rx_desc *rd = e->desc;
2507 nskb->csum = le16_to_cpu(rd->csum2);
2508 nskb->ip_summed = CHECKSUM_HW;
baef58b1 2509 }
19a33d4e
SH		 2510 skge_rx_reuse(e, skge->rx_buf_size);
2511 return nskb;
2512 } else {
2513 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2514 if (unlikely(!nskb))
2515 return NULL;
2516
2517 pci_unmap_single(skge->hw->pdev,
2518 pci_unmap_addr(e, mapaddr),
2519 pci_unmap_len(e, maplen),
2520 PCI_DMA_FROMDEVICE);
2521 skb = e->skb;
2522 if (skge->rx_csum) {
2523 struct skge_rx_desc *rd = e->desc;
2524 skb->csum = le16_to_cpu(rd->csum2);
2525 skb->ip_summed = CHECKSUM_HW;
2526 }
2527
2528 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2529 return skb;
baef58b1
SH		 2530 }
2531}
2532
19a33d4e 2533
baef58b1
SH		 2534static int skge_poll(struct net_device *dev, int *budget)
2535{
2536 struct skge_port *skge = netdev_priv(dev);
2537 struct skge_hw *hw = skge->hw;
2538 struct skge_ring *ring = &skge->rx_ring;
2539 struct skge_element *e;
2540 unsigned int to_do = min(dev->quota, *budget);
2541 unsigned int work_done = 0;
7e676d91
SH		 2542
2543 pr_debug("skge_poll\n");
baef58b1 2544
19a33d4e 2545 for (e = ring->to_clean; work_done < to_do; e = e->next) {
baef58b1 2546 struct skge_rx_desc *rd = e->desc;
19a33d4e 2547 struct sk_buff *skb;
baef58b1
SH		 2548 u32 control, len, status;
2549
2550 rmb();
2551 control = rd->control;
2552 if (control & BMU_OWN)
2553 break;
2554
2555 len = control & BMU_BBC;
baef58b1 2556 status = rd->status;
19a33d4e
SH		 2557
2558 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2559 || bad_phy_status(hw, status))) {
baef58b1 2560 skge_rx_error(skge, e - ring->start, control, status);
19a33d4e 2561 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2562 continue;
2563 }
2564
2565 if (netif_msg_rx_status(skge))
0b2d7fea 2566 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2567 dev->name, e - ring->start, rd->status, len);
2568
19a33d4e
SH		 2569 skb = skge_rx_get(skge, e, len);
2570 if (likely(skb)) {
2571 skb_put(skb, len);
2572 skb->protocol = eth_type_trans(skb, dev);
baef58b1 2573
19a33d4e
SH		 2574 dev->last_rx = jiffies;
2575 netif_receive_skb(skb);
baef58b1 2576
19a33d4e
SH		 2577 ++work_done;
2578 } else
2579 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2580 }
2581 ring->to_clean = e;
2582
baef58b1
SH		 2583 /* restart receiver */
2584 wmb();
2585 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2586 CSR_START | CSR_IRQ_CL_F);
2587
19a33d4e
SH		 2588 *budget -= work_done;
2589 dev->quota -= work_done;
2590
2591 if (work_done >= to_do)
2592 return 1; /* not done */
baef58b1 2593
19a33d4e
SH		 2594 local_irq_disable();
2595 __netif_rx_complete(dev);
2596 hw->intr_mask |= portirqmask[skge->port];
2597 skge_write32(hw, B0_IMSK, hw->intr_mask);
2598 local_irq_enable();
2599 return 0;
baef58b1
SH		 2600}
2601
2602static inline void skge_tx_intr(struct net_device *dev)
2603{
2604 struct skge_port *skge = netdev_priv(dev);
2605 struct skge_hw *hw = skge->hw;
2606 struct skge_ring *ring = &skge->tx_ring;
2607 struct skge_element *e;
2608
2609 spin_lock(&skge->tx_lock);
95566065 2610 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2611 struct skge_tx_desc *td = e->desc;
2612 u32 control;
2613
2614 rmb();
2615 control = td->control;
2616 if (control & BMU_OWN)
2617 break;
2618
2619 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2620 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2621 dev->name, e - ring->start, td->status);
2622
2623 skge_tx_free(hw, e);
2624 e->skb = NULL;
2625 ++skge->tx_avail;
2626 }
2627 ring->to_clean = e;
2628 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2629
2630 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2631 netif_wake_queue(dev);
2632
2633 spin_unlock(&skge->tx_lock);
2634}
2635
2636static void skge_mac_parity(struct skge_hw *hw, int port)
2637{
2638 printk(KERN_ERR PFX "%s: mac data parity error\n",
2639 hw->dev[port] ? hw->dev[port]->name
2640 : (port == 0 ? "(port A)": "(port B"));
2641
2642 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2643 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2644 MFF_CLR_PERR);
2645 else
2646 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2647 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2648 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2649 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2650}
2651
2652static void skge_pci_clear(struct skge_hw *hw)
2653{
2654 u16 status;
2655
467b3417 2656 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2657 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2658 pci_write_config_word(hw->pdev, PCI_STATUS,
2659 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2660 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2661}
2662
2663static void skge_mac_intr(struct skge_hw *hw, int port)
2664{
95566065 2665 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2666 genesis_mac_intr(hw, port);
2667 else
2668 yukon_mac_intr(hw, port);
2669}
2670
2671/* Handle device specific framing and timeout interrupts */
2672static void skge_error_irq(struct skge_hw *hw)
2673{
2674 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2675
2676 if (hw->chip_id == CHIP_ID_GENESIS) {
2677 /* clear xmac errors */
2678 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
6b0c1480 2679 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
baef58b1 2680 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
6b0c1480 2681 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
baef58b1
SH		 2682 } else {
2683 /* Timestamp (unused) overflow */
2684 if (hwstatus & IS_IRQ_TIST_OV)
2685 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2686
2687 if (hwstatus & IS_IRQ_SENSOR) {
2688 /* no sensors on 32-bit Yukon */
2689 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2690 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2691 skge_write32(hw, B0_HWE_IMSK,
2692 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2693 } else
2694 printk(KERN_WARNING PFX "sensor interrupt\n");
2695 }
2696
2697
2698 }
2699
2700 if (hwstatus & IS_RAM_RD_PAR) {
2701 printk(KERN_ERR PFX "Ram read data parity error\n");
2702 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2703 }
2704
2705 if (hwstatus & IS_RAM_WR_PAR) {
2706 printk(KERN_ERR PFX "Ram write data parity error\n");
2707 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2708 }
2709
2710 if (hwstatus & IS_M1_PAR_ERR)
2711 skge_mac_parity(hw, 0);
2712
2713 if (hwstatus & IS_M2_PAR_ERR)
2714 skge_mac_parity(hw, 1);
2715
2716 if (hwstatus & IS_R1_PAR_ERR)
2717 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2718
2719 if (hwstatus & IS_R2_PAR_ERR)
2720 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2721
2722 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2723 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2724 hwstatus);
2725
2726 skge_pci_clear(hw);
2727
2728 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2729 if (hwstatus & IS_IRQ_STAT) {
2730 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2731 hwstatus);
2732 hw->intr_mask &= ~IS_HW_ERR;
2733 }
2734 }
2735}
2736
2737/*
2738 * Interrrupt from PHY are handled in tasklet (soft irq)
2739 * because accessing phy registers requires spin wait which might
2740 * cause excess interrupt latency.
2741 */
2742static void skge_extirq(unsigned long data)
2743{
2744 struct skge_hw *hw = (struct skge_hw *) data;
2745 int port;
2746
2747 spin_lock(&hw->phy_lock);
2748 for (port = 0; port < 2; port++) {
2749 struct net_device *dev = hw->dev[port];
2750
2751 if (dev && netif_running(dev)) {
2752 struct skge_port *skge = netdev_priv(dev);
2753
2754 if (hw->chip_id != CHIP_ID_GENESIS)
2755 yukon_phy_intr(skge);
89bf5f23 2756 else
45bada65 2757 bcom_phy_intr(skge);
baef58b1
SH		 2758 }
2759 }
2760 spin_unlock(&hw->phy_lock);
2761
2762 local_irq_disable();
2763 hw->intr_mask |= IS_EXT_REG;
2764 skge_write32(hw, B0_IMSK, hw->intr_mask);
2765 local_irq_enable();
2766}
2767
2768static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2769{
2770 struct skge_hw *hw = dev_id;
2771 u32 status = skge_read32(hw, B0_SP_ISRC);
2772
2773 if (status == 0 || status == ~0) /* hotplug or shared irq */
2774 return IRQ_NONE;
2775
2776 status &= hw->intr_mask;
7e676d91 2777 if (status & IS_R1_F) {
baef58b1 2778 hw->intr_mask &= ~IS_R1_F;
7e676d91 2779 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2780 }
2781
7e676d91 2782 if (status & IS_R2_F) {
baef58b1 2783 hw->intr_mask &= ~IS_R2_F;
7e676d91 2784 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2785 }
2786
2787 if (status & IS_XA1_F)
2788 skge_tx_intr(hw->dev[0]);
2789
2790 if (status & IS_XA2_F)
2791 skge_tx_intr(hw->dev[1]);
2792
d25f5a67
SH		 2793 if (status & IS_PA_TO_RX1) {
2794 struct skge_port *skge = netdev_priv(hw->dev[0]);
2795 ++skge->net_stats.rx_over_errors;
2796 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2797 }
2798
2799 if (status & IS_PA_TO_RX2) {
2800 struct skge_port *skge = netdev_priv(hw->dev[1]);
2801 ++skge->net_stats.rx_over_errors;
2802 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2803 }
2804
2805 if (status & IS_PA_TO_TX1)
2806 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2807
2808 if (status & IS_PA_TO_TX2)
2809 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2810
baef58b1
SH		 2811 if (status & IS_MAC1)
2812 skge_mac_intr(hw, 0);
95566065 2813
baef58b1
SH		 2814 if (status & IS_MAC2)
2815 skge_mac_intr(hw, 1);
2816
2817 if (status & IS_HW_ERR)
2818 skge_error_irq(hw);
2819
2820 if (status & IS_EXT_REG) {
2821 hw->intr_mask &= ~IS_EXT_REG;
2822 tasklet_schedule(&hw->ext_tasklet);
2823 }
2824
7e676d91 2825 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2826
2827 return IRQ_HANDLED;
2828}
2829
2830#ifdef CONFIG_NET_POLL_CONTROLLER
2831static void skge_netpoll(struct net_device *dev)
2832{
2833 struct skge_port *skge = netdev_priv(dev);
2834
2835 disable_irq(dev->irq);
2836 skge_intr(dev->irq, skge->hw, NULL);
2837 enable_irq(dev->irq);
2838}
2839#endif
2840
2841static int skge_set_mac_address(struct net_device *dev, void *p)
2842{
2843 struct skge_port *skge = netdev_priv(dev);
2844 struct sockaddr *addr = p;
2845 int err = 0;
2846
2847 if (!is_valid_ether_addr(addr->sa_data))
2848 return -EADDRNOTAVAIL;
2849
2850 skge_down(dev);
2851 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2852 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2853 dev->dev_addr, ETH_ALEN);
2854 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2855 dev->dev_addr, ETH_ALEN);
2856 if (dev->flags & IFF_UP)
2857 err = skge_up(dev);
2858 return err;
2859}
2860
2861static const struct {
2862 u8 id;
2863 const char *name;
2864} skge_chips[] = {
2865 { CHIP_ID_GENESIS, "Genesis" },
2866 { CHIP_ID_YUKON, "Yukon" },
2867 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2868 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2869};
2870
2871static const char *skge_board_name(const struct skge_hw *hw)
2872{
2873 int i;
2874 static char buf[16];
2875
2876 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2877 if (skge_chips[i].id == hw->chip_id)
2878 return skge_chips[i].name;
2879
2880 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2881 return buf;
2882}
2883
2884
2885/*
2886 * Setup the board data structure, but don't bring up
2887 * the port(s)
2888 */
2889static int skge_reset(struct skge_hw *hw)
2890{
2891 u16 ctst;
981d0377
SH		 2892 u8 t8, mac_cfg;
2893 int i;
baef58b1
SH		 2894
2895 ctst = skge_read16(hw, B0_CTST);
2896
2897 /* do a SW reset */
2898 skge_write8(hw, B0_CTST, CS_RST_SET);
2899 skge_write8(hw, B0_CTST, CS_RST_CLR);
2900
2901 /* clear PCI errors, if any */
2902 skge_pci_clear(hw);
2903
2904 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2905
2906 /* restore CLK_RUN bits (for Yukon-Lite) */
2907 skge_write16(hw, B0_CTST,
2908 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2909
2910 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2911 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2912 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2913
95566065 2914 switch (hw->chip_id) {
baef58b1
SH		 2915 case CHIP_ID_GENESIS:
2916 switch (hw->phy_type) {
baef58b1
SH		 2917 case SK_PHY_BCOM:
2918 hw->phy_addr = PHY_ADDR_BCOM;
2919 break;
2920 default:
2921 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2922 pci_name(hw->pdev), hw->phy_type);
2923 return -EOPNOTSUPP;
2924 }
2925 break;
2926
2927 case CHIP_ID_YUKON:
2928 case CHIP_ID_YUKON_LITE:
2929 case CHIP_ID_YUKON_LP:
2930 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2931 hw->phy_type = SK_PHY_MARV_COPPER;
2932
2933 hw->phy_addr = PHY_ADDR_MARV;
2934 if (!iscopper(hw))
2935 hw->phy_type = SK_PHY_MARV_FIBER;
2936
2937 break;
2938
2939 default:
2940 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2941 pci_name(hw->pdev), hw->chip_id);
2942 return -EOPNOTSUPP;
2943 }
2944
981d0377
SH		 2945 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2946 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2947 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 2948
2949 /* read the adapters RAM size */
2950 t8 = skge_read8(hw, B2_E_0);
2951 if (hw->chip_id == CHIP_ID_GENESIS) {
2952 if (t8 == 3) {
2953 /* special case: 4 x 64k x 36, offset = 0x80000 */
2954 hw->ram_size = 0x100000;
2955 hw->ram_offset = 0x80000;
2956 } else
2957 hw->ram_size = t8 * 512;
2958 }
2959 else if (t8 == 0)
2960 hw->ram_size = 0x20000;
2961 else
2962 hw->ram_size = t8 * 4096;
2963
2964 if (hw->chip_id == CHIP_ID_GENESIS)
2965 genesis_init(hw);
2966 else {
2967 /* switch power to VCC (WA for VAUX problem) */
2968 skge_write8(hw, B0_POWER_CTRL,
2969 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
981d0377 2970 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 2971 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2972 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 2973 }
2974 }
2975
2976 /* turn off hardware timer (unused) */
2977 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2978 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2979 skge_write8(hw, B0_LED, LED_STAT_ON);
2980
2981 /* enable the Tx Arbiters */
981d0377 2982 for (i = 0; i < hw->ports; i++)
6b0c1480 2983 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 2984
2985 /* Initialize ram interface */
2986 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2987
2988 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2989 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2990 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2991 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2992 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2993 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2994 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2995 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2996 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2997 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2998 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2999 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3000
3001 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3002
3003 /* Set interrupt moderation for Transmit only
3004 * Receive interrupts avoided by NAPI
3005 */
3006 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3007 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3008 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3009
7e676d91 3010 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 3011 skge_write32(hw, B0_IMSK, hw->intr_mask);
3012
3013 if (hw->chip_id != CHIP_ID_GENESIS)
3014 skge_write8(hw, GMAC_IRQ_MSK, 0);
3015
3016 spin_lock_bh(&hw->phy_lock);
981d0377 3017 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3018 if (hw->chip_id == CHIP_ID_GENESIS)
3019 genesis_reset(hw, i);
3020 else
3021 yukon_reset(hw, i);
3022 }
3023 spin_unlock_bh(&hw->phy_lock);
3024
3025 return 0;
3026}
3027
3028/* Initialize network device */
981d0377
SH		 3029static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3030 int highmem)
baef58b1
SH		 3031{
3032 struct skge_port *skge;
3033 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3034
3035 if (!dev) {
3036 printk(KERN_ERR "skge etherdev alloc failed");
3037 return NULL;
3038 }
3039
3040 SET_MODULE_OWNER(dev);
3041 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3042 dev->open = skge_up;
3043 dev->stop = skge_down;
3044 dev->hard_start_xmit = skge_xmit_frame;
3045 dev->get_stats = skge_get_stats;
3046 if (hw->chip_id == CHIP_ID_GENESIS)
3047 dev->set_multicast_list = genesis_set_multicast;
3048 else
3049 dev->set_multicast_list = yukon_set_multicast;
3050
3051 dev->set_mac_address = skge_set_mac_address;
3052 dev->change_mtu = skge_change_mtu;
3053 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3054 dev->tx_timeout = skge_tx_timeout;
3055 dev->watchdog_timeo = TX_WATCHDOG;
3056 dev->poll = skge_poll;
3057 dev->weight = NAPI_WEIGHT;
3058#ifdef CONFIG_NET_POLL_CONTROLLER
3059 dev->poll_controller = skge_netpoll;
3060#endif
3061 dev->irq = hw->pdev->irq;
3062 dev->features = NETIF_F_LLTX;
981d0377
SH		 3063 if (highmem)
3064 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3065
3066 skge = netdev_priv(dev);
3067 skge->netdev = dev;
3068 skge->hw = hw;
3069 skge->msg_enable = netif_msg_init(debug, default_msg);
3070 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3071 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3072
3073 /* Auto speed and flow control */
3074 skge->autoneg = AUTONEG_ENABLE;
3075 skge->flow_control = FLOW_MODE_SYMMETRIC;
3076 skge->duplex = -1;
3077 skge->speed = -1;
31b619c5 3078 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3079
3080 hw->dev[port] = dev;
3081
3082 skge->port = port;
3083
3084 spin_lock_init(&skge->tx_lock);
3085
baef58b1
SH		 3086 init_timer(&skge->led_blink);
3087 skge->led_blink.function = skge_blink_timer;
3088 skge->led_blink.data = (unsigned long) skge;
3089
3090 if (hw->chip_id != CHIP_ID_GENESIS) {
3091 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3092 skge->rx_csum = 1;
3093 }
3094
3095 /* read the mac address */
3096 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3097
3098 /* device is off until link detection */
3099 netif_carrier_off(dev);
3100 netif_stop_queue(dev);
3101
3102 return dev;
3103}
3104
3105static void __devinit skge_show_addr(struct net_device *dev)
3106{
3107 const struct skge_port *skge = netdev_priv(dev);
3108
3109 if (netif_msg_probe(skge))
3110 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3111 dev->name,
3112 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3113 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3114}
3115
3116static int __devinit skge_probe(struct pci_dev *pdev,
3117 const struct pci_device_id *ent)
3118{
3119 struct net_device *dev, *dev1;
3120 struct skge_hw *hw;
3121 int err, using_dac = 0;
3122
3123 if ((err = pci_enable_device(pdev))) {
3124 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3125 pci_name(pdev));
3126 goto err_out;
3127 }
3128
3129 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3130 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3131 pci_name(pdev));
3132 goto err_out_disable_pdev;
3133 }
3134
3135 pci_set_master(pdev);
3136
3137 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3138 using_dac = 1;
3139 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3140 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3141 pci_name(pdev));
3142 goto err_out_free_regions;
3143 }
3144
3145#ifdef __BIG_ENDIAN
3146 /* byte swap decriptors in hardware */
3147 {
3148 u32 reg;
3149
3150 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3151 reg |= PCI_REV_DESC;
3152 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3153 }
3154#endif
3155
3156 err = -ENOMEM;
3157 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3158 if (!hw) {
3159 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3160 pci_name(pdev));
3161 goto err_out_free_regions;
3162 }
3163
3164 memset(hw, 0, sizeof(*hw));
3165 hw->pdev = pdev;
3166 spin_lock_init(&hw->phy_lock);
3167 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3168
3169 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3170 if (!hw->regs) {
3171 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3172 pci_name(pdev));
3173 goto err_out_free_hw;
3174 }
3175
3176 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3177 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3178 pci_name(pdev), pdev->irq);
3179 goto err_out_iounmap;
3180 }
3181 pci_set_drvdata(pdev, hw);
3182
3183 err = skge_reset(hw);
3184 if (err)
3185 goto err_out_free_irq;
3186
3187 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3188 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3189 skge_board_name(hw), hw->chip_rev);
baef58b1 3190
981d0377 3191 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3192 goto err_out_led_off;
3193
baef58b1
SH		 3194 if ((err = register_netdev(dev))) {
3195 printk(KERN_ERR PFX "%s: cannot register net device\n",
3196 pci_name(pdev));
3197 goto err_out_free_netdev;
3198 }
3199
3200 skge_show_addr(dev);
3201
981d0377 3202 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3203 if (register_netdev(dev1) == 0)
3204 skge_show_addr(dev1);
3205 else {
3206 /* Failure to register second port need not be fatal */
3207 printk(KERN_WARNING PFX "register of second port failed\n");
3208 hw->dev[1] = NULL;
3209 free_netdev(dev1);
3210 }
3211 }
3212
3213 return 0;
3214
3215err_out_free_netdev:
3216 free_netdev(dev);
3217err_out_led_off:
3218 skge_write16(hw, B0_LED, LED_STAT_OFF);
3219err_out_free_irq:
3220 free_irq(pdev->irq, hw);
3221err_out_iounmap:
3222 iounmap(hw->regs);
3223err_out_free_hw:
3224 kfree(hw);
3225err_out_free_regions:
3226 pci_release_regions(pdev);
3227err_out_disable_pdev:
3228 pci_disable_device(pdev);
3229 pci_set_drvdata(pdev, NULL);
3230err_out:
3231 return err;
3232}
3233
3234static void __devexit skge_remove(struct pci_dev *pdev)
3235{
3236 struct skge_hw *hw = pci_get_drvdata(pdev);
3237 struct net_device *dev0, *dev1;
3238
95566065 3239 if (!hw)
baef58b1
SH		 3240 return;
3241
3242 if ((dev1 = hw->dev[1]))
3243 unregister_netdev(dev1);
3244 dev0 = hw->dev[0];
3245 unregister_netdev(dev0);
3246
3247 tasklet_kill(&hw->ext_tasklet);
3248
3249 free_irq(pdev->irq, hw);
3250 pci_release_regions(pdev);
3251 pci_disable_device(pdev);
3252 if (dev1)
3253 free_netdev(dev1);
3254 free_netdev(dev0);
3255 skge_write16(hw, B0_LED, LED_STAT_OFF);
3256 iounmap(hw->regs);
3257 kfree(hw);
3258 pci_set_drvdata(pdev, NULL);
3259}
3260
3261#ifdef CONFIG_PM
2a569579 3262static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3263{
3264 struct skge_hw *hw = pci_get_drvdata(pdev);
3265 int i, wol = 0;
3266
95566065 3267 for (i = 0; i < 2; i++) {
baef58b1
SH		 3268 struct net_device *dev = hw->dev[i];
3269
3270 if (dev) {
3271 struct skge_port *skge = netdev_priv(dev);
3272 if (netif_running(dev)) {
3273 netif_carrier_off(dev);
3274 skge_down(dev);
3275 }
3276 netif_device_detach(dev);
3277 wol |= skge->wol;
3278 }
3279 }
3280
3281 pci_save_state(pdev);
2a569579 3282 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3283 pci_disable_device(pdev);
3284 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3285
3286 return 0;
3287}
3288
3289static int skge_resume(struct pci_dev *pdev)
3290{
3291 struct skge_hw *hw = pci_get_drvdata(pdev);
3292 int i;
3293
3294 pci_set_power_state(pdev, PCI_D0);
3295 pci_restore_state(pdev);
3296 pci_enable_wake(pdev, PCI_D0, 0);
3297
3298 skge_reset(hw);
3299
95566065 3300 for (i = 0; i < 2; i++) {
baef58b1
SH		 3301 struct net_device *dev = hw->dev[i];
3302 if (dev) {
3303 netif_device_attach(dev);
95566065 3304 if (netif_running(dev))
baef58b1
SH		 3305 skge_up(dev);
3306 }
3307 }
3308 return 0;
3309}
3310#endif
3311
3312static struct pci_driver skge_driver = {
3313 .name = DRV_NAME,
3314 .id_table = skge_id_table,
3315 .probe = skge_probe,
3316 .remove = __devexit_p(skge_remove),
3317#ifdef CONFIG_PM
3318 .suspend = skge_suspend,
3319 .resume = skge_resume,
3320#endif
3321};
3322
3323static int __init skge_init_module(void)
3324{
3325 return pci_module_init(&skge_driver);
3326}
3327
3328static void __exit skge_cleanup_module(void)
3329{
3330 pci_unregister_driver(&skge_driver);
3331}
3332
3333module_init(skge_init_module);
3334module_exit(skge_cleanup_module);
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