[linux.git] / arch / sh / kernel / cpu / sh4a / setup-sh7723.c

/*
 * SH7723 Setup
 *
 *  Copyright (C) 2008  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/mm.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
#include <linux/sh_cmt.h>
#include <asm/clock.h>
#include <asm/mmzone.h>

static struct uio_info vpu_platform_data = {
	.name = "VPU5",
	.version = "0",
	.irq = 60,
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe902807,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu0_platform_data = {
	.name = "VEU2H",
	.version = "0",
	.irq = 54,
};

static struct resource veu0_resources[] = {
	[0] = {
		.name	= "VEU2H0",
		.start	= 0xfe920000,
		.end	= 0xfe92027b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu0_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu0_platform_data,
	},
	.resource	= veu0_resources,
	.num_resources	= ARRAY_SIZE(veu0_resources),
};

static struct uio_info veu1_platform_data = {
	.name = "VEU2H",
	.version = "0",
	.irq = 27,
};

static struct resource veu1_resources[] = {
	[0] = {
		.name	= "VEU2H1",
		.start	= 0xfe924000,
		.end	= 0xfe92427b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu1_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &veu1_platform_data,
	},
	.resource	= veu1_resources,
	.num_resources	= ARRAY_SIZE(veu1_resources),
};

static struct sh_cmt_config cmt_platform_data = {
	.name = "CMT",
	.channel_offset = 0x60,
	.timer_bit = 5,
	.clk = "cmt0",
	.clockevent_rating = 125,
	.clocksource_rating = 200,
};

static struct resource cmt_resources[] = {
	[0] = {
		.name	= "CMT",
		.start	= 0x044a0060,
		.end	= 0x044a006b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 104,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
};

static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase        = 0xffe00000,
		.flags          = UPF_BOOT_AUTOCONF,
		.type           = PORT_SCIF,
		.irqs           = { 80, 80, 80, 80 },
	},{
		.mapbase        = 0xffe10000,
		.flags          = UPF_BOOT_AUTOCONF,
		.type           = PORT_SCIF,
		.irqs           = { 81, 81, 81, 81 },
	},{
		.mapbase        = 0xffe20000,
		.flags          = UPF_BOOT_AUTOCONF,
		.type           = PORT_SCIF,
		.irqs           = { 82, 82, 82, 82 },
	},{
		.mapbase	= 0xa4e30000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIFA,
		.irqs		= { 56, 56, 56, 56 },
	},{
		.mapbase	= 0xa4e40000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIFA,
		.irqs		= { 88, 88, 88, 88 },
	},{
		.mapbase	= 0xa4e50000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIFA,
		.irqs		= { 109, 109, 109, 109 },
	}, {
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xa465fec0,
		.end	= 0xa465fec0 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Period IRQ */
		.start	= 69,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* Carry IRQ */
		.start	= 70,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		/* Alarm IRQ */
		.start	= 68,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct resource sh7723_usb_host_resources[] = {
	[0] = {
		.name	= "r8a66597_hcd",
		.start	= 0xa4d80000,
		.end	= 0xa4d800ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 65,
		.end	= 65,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device sh7723_usb_host_device = {
	.name		= "r8a66597_hcd",
	.id		= 0,
	.dev = {
		.dma_mask		= NULL,         /*  not use dma */
		.coherent_dma_mask	= 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sh7723_usb_host_resources),
	.resource	= sh7723_usb_host_resources,
};

static struct resource iic_resources[] = {
	[0] = {
		.name	= "IIC",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 96,
		.end    = 99,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic_resources),
	.resource       = iic_resources,
};

static struct platform_device *sh7723_devices[] __initdata = {
	&cmt_device,
	&sci_device,
	&rtc_device,
	&iic_device,
	&sh7723_usb_host_device,
	&vpu_device,
	&veu0_device,
	&veu1_device,
};

static int __init sh7723_devices_setup(void)
{
	clk_always_enable("meram0"); /* MERAM */
	clk_always_enable("rtc0"); /* RTC */
	clk_always_enable("veu1"); /* VEU2H1 */
	clk_always_enable("veu0"); /* VEU2H0 */
	clk_always_enable("vpu0"); /* VPU */

	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);

	return platform_add_devices(sh7723_devices,
				    ARRAY_SIZE(sh7723_devices));
}
__initcall(sh7723_devices_setup);

static struct platform_device *sh7723_early_devices[] __initdata = {
	&cmt_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7723_early_devices,
				   ARRAY_SIZE(sh7723_early_devices));
}

enum {
	UNUSED=0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	HUDI,
	DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
	_2DG_TRI,_2DG_INI,_2DG_CEI,
	DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
	VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
	SCIFA_SCIFA0,
	VPU_VPUI,
	TPU_TPUI,
	ADC_ADI,
	USB_USI0,
	RTC_ATI,RTC_PRI,RTC_CUI,
	DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
	DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
	KEYSC_KEYI,
	SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
	MSIOF_MSIOFI0,MSIOF_MSIOFI1,
	SCIFA_SCIFA1,
	FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
	I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
	SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
	CMT_CMTI,
	TSIF_TSIFI,
	SIU_SIUI,
	SCIFA_SCIFA2,
	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
	IRDA_IRDAI,
	ATAPI_ATAPII,
	SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
	VEU2H1_VEU2HI,
	LCDC_LCDCI,
	TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,

	/* interrupt groups */
	DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
	SDHI1, RTC, DMAC1B, SDHI0,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),

	INTC_VECT(DMAC1A_DEI0,0x700),
	INTC_VECT(DMAC1A_DEI1,0x720),
	INTC_VECT(DMAC1A_DEI2,0x740),
	INTC_VECT(DMAC1A_DEI3,0x760),

	INTC_VECT(_2DG_TRI, 0x780),
	INTC_VECT(_2DG_INI, 0x7A0),
	INTC_VECT(_2DG_CEI, 0x7C0),

	INTC_VECT(DMAC0A_DEI0,0x800),
	INTC_VECT(DMAC0A_DEI1,0x820),
	INTC_VECT(DMAC0A_DEI2,0x840),
	INTC_VECT(DMAC0A_DEI3,0x860),

	INTC_VECT(VIO_CEUI,0x880),
	INTC_VECT(VIO_BEUI,0x8A0),
	INTC_VECT(VIO_VEU2HI,0x8C0),
	INTC_VECT(VIO_VOUI,0x8E0),

	INTC_VECT(SCIFA_SCIFA0,0x900),
	INTC_VECT(VPU_VPUI,0x980),
	INTC_VECT(TPU_TPUI,0x9A0),
	INTC_VECT(ADC_ADI,0x9E0),
	INTC_VECT(USB_USI0,0xA20),

	INTC_VECT(RTC_ATI,0xA80),
	INTC_VECT(RTC_PRI,0xAA0),
	INTC_VECT(RTC_CUI,0xAC0),

	INTC_VECT(DMAC1B_DEI4,0xB00),
	INTC_VECT(DMAC1B_DEI5,0xB20),
	INTC_VECT(DMAC1B_DADERR,0xB40),

	INTC_VECT(DMAC0B_DEI4,0xB80),
	INTC_VECT(DMAC0B_DEI5,0xBA0),
	INTC_VECT(DMAC0B_DADERR,0xBC0),

	INTC_VECT(KEYSC_KEYI,0xBE0),
	INTC_VECT(SCIF_SCIF0,0xC00),
	INTC_VECT(SCIF_SCIF1,0xC20),
	INTC_VECT(SCIF_SCIF2,0xC40),
	INTC_VECT(MSIOF_MSIOFI0,0xC80),
	INTC_VECT(MSIOF_MSIOFI1,0xCA0),
	INTC_VECT(SCIFA_SCIFA1,0xD00),

	INTC_VECT(FLCTL_FLSTEI,0xD80),
	INTC_VECT(FLCTL_FLTENDI,0xDA0),
	INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
	INTC_VECT(FLCTL_FLTREQ1I,0xDE0),

	INTC_VECT(I2C_ALI,0xE00),
	INTC_VECT(I2C_TACKI,0xE20),
	INTC_VECT(I2C_WAITI,0xE40),
	INTC_VECT(I2C_DTEI,0xE60),

	INTC_VECT(SDHI0_SDHII0,0xE80),
	INTC_VECT(SDHI0_SDHII1,0xEA0),
	INTC_VECT(SDHI0_SDHII2,0xEC0),

	INTC_VECT(CMT_CMTI,0xF00),
	INTC_VECT(TSIF_TSIFI,0xF20),
	INTC_VECT(SIU_SIUI,0xF80),
	INTC_VECT(SCIFA_SCIFA2,0xFA0),

	INTC_VECT(TMU0_TUNI0,0x400),
	INTC_VECT(TMU0_TUNI1,0x420),
	INTC_VECT(TMU0_TUNI2,0x440),

	INTC_VECT(IRDA_IRDAI,0x480),
	INTC_VECT(ATAPI_ATAPII,0x4A0),

	INTC_VECT(SDHI1_SDHII0,0x4E0),
	INTC_VECT(SDHI1_SDHII1,0x500),
	INTC_VECT(SDHI1_SDHII2,0x520),

	INTC_VECT(VEU2H1_VEU2HI,0x560),
	INTC_VECT(LCDC_LCDCI,0x580),

	INTC_VECT(TMU1_TUNI0,0x920),
	INTC_VECT(TMU1_TUNI1,0x940),
	INTC_VECT(TMU1_TUNI2,0x960),

};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
	INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
	INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
	INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
	INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
	INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
	INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
	INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
	INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
	INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
	INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	  { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
	  { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
			     mask_registers, prio_registers, sense_registers,
			     ack_registers);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}
Commit	Line	Data
178dd0cd PM	1	/*
	2	* SH7723 Setup
	3	*
	4	* Copyright (C) 2008 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
	13	#include <linux/mm.h>
	14	#include <linux/serial_sci.h>
6874548c	15	#include <linux/uio_driver.h>
424f59d0	16	#include <linux/sh_cmt.h>
9ca6ecac	17	#include <asm/clock.h>
178dd0cd PM	18	#include <asm/mmzone.h>
178dd0cd PM	19
6874548c MD	20	static struct uio_info vpu_platform_data = {
	21	.name = "VPU5",
	22	.version = "0",
	23	.irq = 60,
	24	};
	25
	26	static struct resource vpu_resources[] = {
	27	[0] = {
	28	.name = "VPU",
	29	.start = 0xfe900000,
	30	.end = 0xfe902807,
	31	.flags = IORESOURCE_MEM,
	32	},
1eca5c92 MD	33	[1] = {
	34	/* place holder for contiguous memory */
	35	},
6874548c MD	36	};
	37
	38	static struct platform_device vpu_device = {
	39	.name = "uio_pdrv_genirq",
	40	.id = 0,
	41	.dev = {
	42	.platform_data = &vpu_platform_data,
	43	},
	44	.resource = vpu_resources,
	45	.num_resources = ARRAY_SIZE(vpu_resources),
	46	};
	47
	48	static struct uio_info veu0_platform_data = {
2a5323cd	49	.name = "VEU2H",
6874548c MD	50	.version = "0",
	51	.irq = 54,
	52	};
	53
	54	static struct resource veu0_resources[] = {
	55	[0] = {
	56	.name = "VEU2H0",
	57	.start = 0xfe920000,
	58	.end = 0xfe92027b,
	59	.flags = IORESOURCE_MEM,
	60	},
1eca5c92 MD	61	[1] = {
	62	/* place holder for contiguous memory */
	63	},
6874548c MD	64	};
	65
	66	static struct platform_device veu0_device = {
	67	.name = "uio_pdrv_genirq",
	68	.id = 1,
	69	.dev = {
	70	.platform_data = &veu0_platform_data,
	71	},
	72	.resource = veu0_resources,
	73	.num_resources = ARRAY_SIZE(veu0_resources),
	74	};
	75
	76	static struct uio_info veu1_platform_data = {
2a5323cd	77	.name = "VEU2H",
6874548c MD	78	.version = "0",
	79	.irq = 27,
	80	};
	81
	82	static struct resource veu1_resources[] = {
	83	[0] = {
	84	.name = "VEU2H1",
	85	.start = 0xfe924000,
	86	.end = 0xfe92427b,
	87	.flags = IORESOURCE_MEM,
	88	},
1eca5c92 MD	89	[1] = {
	90	/* place holder for contiguous memory */
	91	},
6874548c MD	92	};
	93
	94	static struct platform_device veu1_device = {
	95	.name = "uio_pdrv_genirq",
	96	.id = 2,
	97	.dev = {
	98	.platform_data = &veu1_platform_data,
	99	},
	100	.resource = veu1_resources,
	101	.num_resources = ARRAY_SIZE(veu1_resources),
	102	};
	103
424f59d0 MD	104	static struct sh_cmt_config cmt_platform_data = {
	105	.name = "CMT",
	106	.channel_offset = 0x60,
	107	.timer_bit = 5,
	108	.clk = "cmt0",
	109	.clockevent_rating = 125,
	110	.clocksource_rating = 200,
	111	};
	112
	113	static struct resource cmt_resources[] = {
	114	[0] = {
	115	.name = "CMT",
	116	.start = 0x044a0060,
	117	.end = 0x044a006b,
	118	.flags = IORESOURCE_MEM,
	119	},
	120	[1] = {
	121	.start = 104,
	122	.flags = IORESOURCE_IRQ,
	123	},
	124	};
	125
	126	static struct platform_device cmt_device = {
	127	.name = "sh_cmt",
	128	.id = 0,
	129	.dev = {
	130	.platform_data = &cmt_platform_data,
	131	},
	132	.resource = cmt_resources,
	133	.num_resources = ARRAY_SIZE(cmt_resources),
	134	};
	135
178dd0cd PM	136	static struct plat_sci_port sci_platform_data[] = {
178dd0cd PM	137	{
576b9187 YG	138	.mapbase = 0xffe00000,
	139	.flags = UPF_BOOT_AUTOCONF,
	140	.type = PORT_SCIF,
	141	.irqs = { 80, 80, 80, 80 },
	142	},{
	143	.mapbase = 0xffe10000,
	144	.flags = UPF_BOOT_AUTOCONF,
	145	.type = PORT_SCIF,
	146	.irqs = { 81, 81, 81, 81 },
	147	},{
	148	.mapbase = 0xffe20000,
	149	.flags = UPF_BOOT_AUTOCONF,
	150	.type = PORT_SCIF,
	151	.irqs = { 82, 82, 82, 82 },
	152	},{
178dd0cd PM	153	.mapbase = 0xa4e30000,
178dd0cd PM	154	.flags = UPF_BOOT_AUTOCONF,
51ee3d92	155	.type = PORT_SCIFA,
178dd0cd PM	156	.irqs = { 56, 56, 56, 56 },
	157	},{
	158	.mapbase = 0xa4e40000,
	159	.flags = UPF_BOOT_AUTOCONF,
51ee3d92	160	.type = PORT_SCIFA,
178dd0cd PM	161	.irqs = { 88, 88, 88, 88 },
	162	},{
	163	.mapbase = 0xa4e50000,
	164	.flags = UPF_BOOT_AUTOCONF,
51ee3d92	165	.type = PORT_SCIFA,
178dd0cd PM	166	.irqs = { 109, 109, 109, 109 },
	167	}, {
	168	.flags = 0,
	169	}
	170	};
	171
	172	static struct platform_device sci_device = {
	173	.name = "sh-sci",
	174	.id = -1,
	175	.dev = {
	176	.platform_data = sci_platform_data,
	177	},
	178	};
	179
	180	static struct resource rtc_resources[] = {
	181	[0] = {
	182	.start = 0xa465fec0,
	183	.end = 0xa465fec0 + 0x58 - 1,
	184	.flags = IORESOURCE_IO,
	185	},
	186	[1] = {
	187	/* Period IRQ */
	188	.start = 69,
	189	.flags = IORESOURCE_IRQ,
	190	},
	191	[2] = {
	192	/* Carry IRQ */
	193	.start = 70,
	194	.flags = IORESOURCE_IRQ,
	195	},
	196	[3] = {
	197	/* Alarm IRQ */
	198	.start = 68,
	199	.flags = IORESOURCE_IRQ,
	200	},
	201	};
	202
	203	static struct platform_device rtc_device = {
	204	.name = "sh-rtc",
	205	.id = -1,
	206	.num_resources = ARRAY_SIZE(rtc_resources),
	207	.resource = rtc_resources,
	208	};
	209
b8858eed YS	210	static struct resource sh7723_usb_host_resources[] = {
	211	[0] = {
	212	.name = "r8a66597_hcd",
	213	.start = 0xa4d80000,
	214	.end = 0xa4d800ff,
	215	.flags = IORESOURCE_MEM,
	216	},
	217	[1] = {
	218	.start = 65,
	219	.end = 65,
	220	.flags = IORESOURCE_IRQ,
	221	},
	222	};
	223
	224	static struct platform_device sh7723_usb_host_device = {
	225	.name = "r8a66597_hcd",
	226	.id = 0,
	227	.dev = {
	228	.dma_mask = NULL, /* not use dma */
	229	.coherent_dma_mask = 0xffffffff,
	230	},
	231	.num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
	232	.resource = sh7723_usb_host_resources,
	233	};
	234
da7d3029 MD	235	static struct resource iic_resources[] = {
	236	[0] = {
	237	.name = "IIC",
	238	.start = 0x04470000,
	239	.end = 0x04470017,
	240	.flags = IORESOURCE_MEM,
	241	},
	242	[1] = {
	243	.start = 96,
	244	.end = 99,
	245	.flags = IORESOURCE_IRQ,
	246	},
	247	};
	248
	249	static struct platform_device iic_device = {
	250	.name = "i2c-sh_mobile",
a5616bd0	251	.id = 0, /* "i2c0" clock */
da7d3029 MD	252	.num_resources = ARRAY_SIZE(iic_resources),
	253	.resource = iic_resources,
	254	};
	255
178dd0cd	256	static struct platform_device *sh7723_devices[] __initdata = {
424f59d0	257	&cmt_device,
178dd0cd PM	258	&sci_device,
178dd0cd PM	259	&rtc_device,
da7d3029	260	&iic_device,
b8858eed	261	&sh7723_usb_host_device,
6874548c MD	262	&vpu_device,
	263	&veu0_device,
	264	&veu1_device,
178dd0cd PM	265	};
	266
	267	static int __init sh7723_devices_setup(void)
	268	{
ef6aff68 MD	269	clk_always_enable("meram0"); /* MERAM */
	270	clk_always_enable("rtc0"); /* RTC */
	271	clk_always_enable("veu1"); /* VEU2H1 */
	272	clk_always_enable("veu0"); /* VEU2H0 */
	273	clk_always_enable("vpu0"); /* VPU */
9ca6ecac	274
1eca5c92 MD	275	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
	276	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
	277	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
9ca6ecac	278
178dd0cd PM	279	return platform_add_devices(sh7723_devices,
	280	ARRAY_SIZE(sh7723_devices));
	281	}
	282	__initcall(sh7723_devices_setup);
	283
28fde686 MD	284	static struct platform_device *sh7723_early_devices[] __initdata = {
	285	&cmt_device,
	286	};
	287
	288	void __init plat_early_device_setup(void)
	289	{
	290	early_platform_add_devices(sh7723_early_devices,
	291	ARRAY_SIZE(sh7723_early_devices));
	292	}
	293
178dd0cd PM	294	enum {
	295	UNUSED=0,
	296
	297	/* interrupt sources */
	298	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	299	HUDI,
	300	DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
	301	_2DG_TRI,_2DG_INI,_2DG_CEI,
	302	DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
	303	VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
	304	SCIFA_SCIFA0,
	305	VPU_VPUI,
	306	TPU_TPUI,
	307	ADC_ADI,
	308	USB_USI0,
	309	RTC_ATI,RTC_PRI,RTC_CUI,
	310	DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
	311	DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
	312	KEYSC_KEYI,
	313	SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
	314	MSIOF_MSIOFI0,MSIOF_MSIOFI1,
	315	SCIFA_SCIFA1,
	316	FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
	317	I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
	318	SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
	319	CMT_CMTI,
	320	TSIF_TSIFI,
	321	SIU_SIUI,
	322	SCIFA_SCIFA2,
	323	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
	324	IRDA_IRDAI,
	325	ATAPI_ATAPII,
	326	SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
	327	VEU2H1_VEU2HI,
	328	LCDC_LCDCI,
	329	TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
	330
	331	/* interrupt groups */
	332	DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
	333	SDHI1, RTC, DMAC1B, SDHI0,
	334	};
	335
	336	static struct intc_vect vectors[] __initdata = {
	337	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	338	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	339	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	340	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	341
	342	INTC_VECT(DMAC1A_DEI0,0x700),
	343	INTC_VECT(DMAC1A_DEI1,0x720),
	344	INTC_VECT(DMAC1A_DEI2,0x740),
	345	INTC_VECT(DMAC1A_DEI3,0x760),
	346
	347	INTC_VECT(_2DG_TRI, 0x780),
	348	INTC_VECT(_2DG_INI, 0x7A0),
	349	INTC_VECT(_2DG_CEI, 0x7C0),
	350
	351	INTC_VECT(DMAC0A_DEI0,0x800),
	352	INTC_VECT(DMAC0A_DEI1,0x820),
	353	INTC_VECT(DMAC0A_DEI2,0x840),
	354	INTC_VECT(DMAC0A_DEI3,0x860),
	355
	356	INTC_VECT(VIO_CEUI,0x880),
	357	INTC_VECT(VIO_BEUI,0x8A0),
358	INTC_VECT(VIO_VEU2HI,0x8C0),
359	INTC_VECT(VIO_VOUI,0x8E0),
360
361	INTC_VECT(SCIFA_SCIFA0,0x900),
76013044	362	INTC_VECT(VPU_VPUI,0x980),
178dd0cd PM	363	INTC_VECT(TPU_TPUI,0x9A0),
	364	INTC_VECT(ADC_ADI,0x9E0),
	365	INTC_VECT(USB_USI0,0xA20),
	366
	367	INTC_VECT(RTC_ATI,0xA80),
	368	INTC_VECT(RTC_PRI,0xAA0),
	369	INTC_VECT(RTC_CUI,0xAC0),
	370
	371	INTC_VECT(DMAC1B_DEI4,0xB00),
	372	INTC_VECT(DMAC1B_DEI5,0xB20),
	373	INTC_VECT(DMAC1B_DADERR,0xB40),
	374
	375	INTC_VECT(DMAC0B_DEI4,0xB80),
	376	INTC_VECT(DMAC0B_DEI5,0xBA0),
	377	INTC_VECT(DMAC0B_DADERR,0xBC0),
	378
	379	INTC_VECT(KEYSC_KEYI,0xBE0),
	380	INTC_VECT(SCIF_SCIF0,0xC00),
	381	INTC_VECT(SCIF_SCIF1,0xC20),
	382	INTC_VECT(SCIF_SCIF2,0xC40),
	383	INTC_VECT(MSIOF_MSIOFI0,0xC80),
	384	INTC_VECT(MSIOF_MSIOFI1,0xCA0),
	385	INTC_VECT(SCIFA_SCIFA1,0xD00),
	386
	387	INTC_VECT(FLCTL_FLSTEI,0xD80),
	388	INTC_VECT(FLCTL_FLTENDI,0xDA0),
	389	INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
	390	INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
	391
	392	INTC_VECT(I2C_ALI,0xE00),
	393	INTC_VECT(I2C_TACKI,0xE20),
	394	INTC_VECT(I2C_WAITI,0xE40),
	395	INTC_VECT(I2C_DTEI,0xE60),
	396
	397	INTC_VECT(SDHI0_SDHII0,0xE80),
	398	INTC_VECT(SDHI0_SDHII1,0xEA0),
	399	INTC_VECT(SDHI0_SDHII2,0xEC0),
	400
	401	INTC_VECT(CMT_CMTI,0xF00),
	402	INTC_VECT(TSIF_TSIFI,0xF20),
	403	INTC_VECT(SIU_SIUI,0xF80),
	404	INTC_VECT(SCIFA_SCIFA2,0xFA0),
	405
	406	INTC_VECT(TMU0_TUNI0,0x400),
	407	INTC_VECT(TMU0_TUNI1,0x420),
	408	INTC_VECT(TMU0_TUNI2,0x440),
	409
	410	INTC_VECT(IRDA_IRDAI,0x480),
	411	INTC_VECT(ATAPI_ATAPII,0x4A0),
	412
	413	INTC_VECT(SDHI1_SDHII0,0x4E0),
	414	INTC_VECT(SDHI1_SDHII1,0x500),
	415	INTC_VECT(SDHI1_SDHII2,0x520),
	416
	417	INTC_VECT(VEU2H1_VEU2HI,0x560),
	418	INTC_VECT(LCDC_LCDCI,0x580),
	419
	420	INTC_VECT(TMU1_TUNI0,0x920),
	421	INTC_VECT(TMU1_TUNI1,0x940),
	422	INTC_VECT(TMU1_TUNI2,0x960),
	423
	424	};
	425
	426	static struct intc_group groups[] __initdata = {
427	INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
428	INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
429	INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
430	INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
431	INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
432	INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
433	INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
434	INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
435	INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
436	INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
437	INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
438	};
439
440	static struct intc_mask_reg mask_registers[] __initdata = {
441	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
442	{ 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
443	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
444	{ VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
445	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
446	{ 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
447	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
448	{ DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
449	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
450	{ 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
451	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
452	{ KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
453	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
454	{ 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
455	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
456	{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
457	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
458	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
459	{ 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
460	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
461	{ 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
462	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
463	{ 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
464	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
465	{ 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
466	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
467	{ 0,0,0,0,0,0,0,ATAPI_ATAPII } },
468	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
469	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
470	};
471
472	static struct intc_prio_reg prio_registers[] __initdata = {
473	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
474	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
475	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
476	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
477	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
478	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
479	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
480	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
481	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
482	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
483	{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
484	{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
485	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
486	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
487	};
488
489	static struct intc_sense_reg sense_registers[] __initdata = {
490	{ 0xa414001c, 16, 2, /* ICR1 */
491	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
492	};
493
6bdfb22a YS	494	static struct intc_mask_reg ack_registers[] __initdata = {
	495	{ 0xa4140024, 0, 8, /* INTREQ00 */
	496	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	497	};
	498
	499	static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
	500	mask_registers, prio_registers, sense_registers,
	501	ack_registers);
178dd0cd PM	502
	503	void __init plat_irq_setup(void)
	504	{
	505	register_intc_controller(&intc_desc);
	506	}