[linux.git] / drivers / clocksource / samsung_pwm_timer.c

/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * samsung - Common hr-timer support (s3c and s5p)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>

#include <clocksource/samsung_pwm.h>


/*
 * Clocksource driver
 */

#define REG_TCFG0			0x00
#define REG_TCFG1			0x04
#define REG_TCON			0x08
#define REG_TINT_CSTAT			0x44

#define REG_TCNTB(chan)			(0x0c + 12 * (chan))
#define REG_TCMPB(chan)			(0x10 + 12 * (chan))

#define TCFG0_PRESCALER_MASK		0xff
#define TCFG0_PRESCALER1_SHIFT		8

#define TCFG1_SHIFT(x)	  		((x) * 4)
#define TCFG1_MUX_MASK	  		0xf

/*
 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
 * bits (one channel) after channel 0, so channels have different numbering
 * when accessing TCON register.
 *
 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
 * in its set of bits is 2 as opposed to 3 for other channels.
 */
#define TCON_START(chan)		(1 << (4 * (chan) + 0))
#define TCON_MANUALUPDATE(chan)		(1 << (4 * (chan) + 1))
#define TCON_INVERT(chan)		(1 << (4 * (chan) + 2))
#define _TCON_AUTORELOAD(chan)		(1 << (4 * (chan) + 3))
#define _TCON_AUTORELOAD4(chan)		(1 << (4 * (chan) + 2))
#define TCON_AUTORELOAD(chan)		\
	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))

DEFINE_SPINLOCK(samsung_pwm_lock);
EXPORT_SYMBOL(samsung_pwm_lock);

struct samsung_pwm_clocksource {
	void __iomem *base;
	void __iomem *source_reg;
	unsigned int irq[SAMSUNG_PWM_NUM];
	struct samsung_pwm_variant variant;

	struct clk *timerclk;

	unsigned int event_id;
	unsigned int source_id;
	unsigned int tcnt_max;
	unsigned int tscaler_div;
	unsigned int tdiv;

	unsigned long clock_count_per_tick;
};

static struct samsung_pwm_clocksource pwm;

static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
{
	unsigned long flags;
	u8 shift = 0;
	u32 reg;

	if (channel >= 2)
		shift = TCFG0_PRESCALER1_SHIFT;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG0);
	reg &= ~(TCFG0_PRESCALER_MASK << shift);
	reg |= (prescale - 1) << shift;
	writel(reg, pwm.base + REG_TCFG0);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
{
	u8 shift = TCFG1_SHIFT(channel);
	unsigned long flags;
	u32 reg;
	u8 bits;

	bits = (fls(divisor) - 1) - pwm.variant.div_base;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG1);
	reg &= ~(TCFG1_MUX_MASK << shift);
	reg |= bits << shift;
	writel(reg, pwm.base + REG_TCFG1);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_stop(unsigned int channel)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);
	tcon &= ~TCON_START(channel);
	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
{
	unsigned long tcon;
	unsigned long flags;
	unsigned int tcon_chan = channel;

	if (tcon_chan > 0)
		++tcon_chan;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);

	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
	tcon |= TCON_MANUALUPDATE(tcon_chan);

	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_start(unsigned int channel, bool periodic)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);

	tcon &= ~TCON_MANUALUPDATE(channel);
	tcon |= TCON_START(channel);

	if (periodic)
		tcon |= TCON_AUTORELOAD(channel);
	else
		tcon &= ~TCON_AUTORELOAD(channel);

	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static int samsung_set_next_event(unsigned long cycles,
				struct clock_event_device *evt)
{
	/*
	 * This check is needed to account for internal rounding
	 * errors inside clockevents core, which might result in
	 * passing cycles = 0, which in turn would not generate any
	 * timer interrupt and hang the system.
	 *
	 * Another solution would be to set up the clockevent device
	 * with min_delta = 2, but this would unnecessarily increase
	 * the minimum sleep period.
	 */
	if (!cycles)
		cycles = 1;

	samsung_time_setup(pwm.event_id, cycles);
	samsung_time_start(pwm.event_id, false);

	return 0;
}

static int samsung_shutdown(struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);
	return 0;
}

static int samsung_set_periodic(struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);
	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	samsung_time_start(pwm.event_id, true);
	return 0;
}

static void samsung_clockevent_resume(struct clock_event_device *cev)
{
	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static struct clock_event_device time_event_device = {
	.name			= "samsung_event_timer",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 200,
	.set_next_event		= samsung_set_next_event,
	.set_state_shutdown	= samsung_shutdown,
	.set_state_periodic	= samsung_set_periodic,
	.set_state_oneshot	= samsung_shutdown,
	.tick_resume		= samsung_shutdown,
	.resume			= samsung_clockevent_resume,
};

static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction samsung_clock_event_irq = {
	.name		= "samsung_time_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= samsung_clock_event_isr,
	.dev_id		= &time_event_device,
};

static void __init samsung_clockevent_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;
	unsigned int irq_number;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
	pwm.clock_count_per_tick = clock_rate / HZ;

	time_event_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&time_event_device,
						clock_rate, 1, pwm.tcnt_max);

	irq_number = pwm.irq[pwm.event_id];
	setup_irq(irq_number, &samsung_clock_event_irq);

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static void samsung_clocksource_suspend(struct clocksource *cs)
{
	samsung_time_stop(pwm.source_id);
}

static void samsung_clocksource_resume(struct clocksource *cs)
{
	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);
}

static u64 notrace samsung_clocksource_read(struct clocksource *c)
{
	return ~readl_relaxed(pwm.source_reg);
}

static struct clocksource samsung_clocksource = {
	.name		= "samsung_clocksource_timer",
	.rating		= 250,
	.read		= samsung_clocksource_read,
	.suspend	= samsung_clocksource_suspend,
	.resume		= samsung_clocksource_resume,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by U300 implementation.)
 */
static u64 notrace samsung_read_sched_clock(void)
{
	return samsung_clocksource_read(NULL);
}

static int __init samsung_clocksource_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);

	if (pwm.source_id == 4)
		pwm.source_reg = pwm.base + 0x40;
	else
		pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;

	sched_clock_register(samsung_read_sched_clock,
						pwm.variant.bits, clock_rate);

	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
	return clocksource_register_hz(&samsung_clocksource, clock_rate);
}

static void __init samsung_timer_resources(void)
{
	clk_prepare_enable(pwm.timerclk);

	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	if (pwm.variant.bits == 16) {
		pwm.tscaler_div = 25;
		pwm.tdiv = 2;
	} else {
		pwm.tscaler_div = 2;
		pwm.tdiv = 1;
	}
}

/*
 * PWM master driver
 */
static int __init _samsung_pwm_clocksource_init(void)
{
	u8 mask;
	int channel;

	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
	channel = fls(mask) - 1;
	if (channel < 0) {
		pr_crit("failed to find PWM channel for clocksource\n");
		return -EINVAL;
	}
	pwm.source_id = channel;

	mask &= ~(1 << channel);
	channel = fls(mask) - 1;
	if (channel < 0) {
		pr_crit("failed to find PWM channel for clock event\n");
		return -EINVAL;
	}
	pwm.event_id = channel;

	samsung_timer_resources();
	samsung_clockevent_init();

	return samsung_clocksource_init();
}

void __init samsung_pwm_clocksource_init(void __iomem *base,
			unsigned int *irqs, struct samsung_pwm_variant *variant)
{
	pwm.base = base;
	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));

	pwm.timerclk = clk_get(NULL, "timers");
	if (IS_ERR(pwm.timerclk))
		panic("failed to get timers clock for timer");

	_samsung_pwm_clocksource_init();
}

#ifdef CONFIG_TIMER_OF
static int __init samsung_pwm_alloc(struct device_node *np,
				    const struct samsung_pwm_variant *variant)
{
	struct property *prop;
	const __be32 *cur;
	u32 val;
	int i;

	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
		pwm.irq[i] = irq_of_parse_and_map(np, i);

	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
		if (val >= SAMSUNG_PWM_NUM) {
			pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
								__func__);
			continue;
		}
		pwm.variant.output_mask |= 1 << val;
	}

	pwm.base = of_iomap(np, 0);
	if (!pwm.base) {
		pr_err("%s: failed to map PWM registers\n", __func__);
		return -ENXIO;
	}

	pwm.timerclk = of_clk_get_by_name(np, "timers");
	if (IS_ERR(pwm.timerclk)) {
		pr_crit("failed to get timers clock for timer\n");
		return PTR_ERR(pwm.timerclk);
	}

	return _samsung_pwm_clocksource_init();
}

static const struct samsung_pwm_variant s3c24xx_variant = {
	.bits		= 16,
	.div_base	= 1,
	.has_tint_cstat	= false,
	.tclk_mask	= (1 << 4),
};

static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s3c24xx_variant);
}
TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);

static const struct samsung_pwm_variant s3c64xx_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s3c64xx_variant);
}
TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p64x0_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= 0,
};

static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s5p64x0_variant);
}
TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 5),
};

static int __init s5p_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s5p_variant);
}
TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
#endif
Commit	Line	Data
f1189989 TF	1	/*
	2	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com/
	4	*
	5	* samsung - Common hr-timer support (s3c and s5p)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/clockchips.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/slab.h>
38ff87f7	24	#include <linux/sched_clock.h>
f1189989 TF	25
	26	#include <clocksource/samsung_pwm.h>
	27
f1189989 TF	28
	29	/*
	30	* Clocksource driver
	31	*/
	32
	33	#define REG_TCFG0 0x00
	34	#define REG_TCFG1 0x04
	35	#define REG_TCON 0x08
	36	#define REG_TINT_CSTAT 0x44
	37
	38	#define REG_TCNTB(chan) (0x0c + 12 * (chan))
	39	#define REG_TCMPB(chan) (0x10 + 12 * (chan))
	40
	41	#define TCFG0_PRESCALER_MASK 0xff
	42	#define TCFG0_PRESCALER1_SHIFT 8
	43
	44	#define TCFG1_SHIFT(x) ((x) * 4)
	45	#define TCFG1_MUX_MASK 0xf
	46
ceea1241 TF	47	/*
	48	* Each channel occupies 4 bits in TCON register, but there is a gap of 4
	49	* bits (one channel) after channel 0, so channels have different numbering
	50	* when accessing TCON register.
	51	*
	52	* In addition, the location of autoreload bit for channel 4 (TCON channel 5)
	53	* in its set of bits is 2 as opposed to 3 for other channels.
	54	*/
f1189989 TF	55	#define TCON_START(chan) (1 << (4 * (chan) + 0))
	56	#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
	57	#define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
ceea1241 TF	58	#define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
	59	#define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2))
	60	#define TCON_AUTORELOAD(chan) \
	61	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
f1189989	62
7aac482e TF	63	DEFINE_SPINLOCK(samsung_pwm_lock);
	64	EXPORT_SYMBOL(samsung_pwm_lock);
	65
030c2a1e TF	66	struct samsung_pwm_clocksource {
030c2a1e TF	67	void __iomem *base;
61d7e205	68	void __iomem *source_reg;
030c2a1e TF	69	unsigned int irq[SAMSUNG_PWM_NUM];
	70	struct samsung_pwm_variant variant;
	71
	72	struct clk *timerclk;
	73
f1189989 TF	74	unsigned int event_id;
	75	unsigned int source_id;
	76	unsigned int tcnt_max;
	77	unsigned int tscaler_div;
	78	unsigned int tdiv;
030c2a1e TF	79
030c2a1e TF	80	unsigned long clock_count_per_tick;
f1189989 TF	81	};
f1189989 TF	82
030c2a1e	83	static struct samsung_pwm_clocksource pwm;
f1189989	84
030c2a1e	85	static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
f1189989 TF	86	{
	87	unsigned long flags;
	88	u8 shift = 0;
	89	u32 reg;
	90
	91	if (channel >= 2)
	92	shift = TCFG0_PRESCALER1_SHIFT;
	93
7aac482e	94	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	95
030c2a1e	96	reg = readl(pwm.base + REG_TCFG0);
f1189989 TF	97	reg &= ~(TCFG0_PRESCALER_MASK << shift);
f1189989 TF	98	reg \|= (prescale - 1) << shift;
030c2a1e	99	writel(reg, pwm.base + REG_TCFG0);
f1189989	100
7aac482e	101	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	102	}
f1189989 TF	103
030c2a1e	104	static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
f1189989 TF	105	{
	106	u8 shift = TCFG1_SHIFT(channel);
	107	unsigned long flags;
	108	u32 reg;
	109	u8 bits;
	110
030c2a1e	111	bits = (fls(divisor) - 1) - pwm.variant.div_base;
f1189989	112
7aac482e	113	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	114
030c2a1e	115	reg = readl(pwm.base + REG_TCFG1);
f1189989 TF	116	reg &= ~(TCFG1_MUX_MASK << shift);
f1189989 TF	117	reg \|= bits << shift;
030c2a1e	118	writel(reg, pwm.base + REG_TCFG1);
f1189989	119
7aac482e	120	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	121	}
	122
	123	static void samsung_time_stop(unsigned int channel)
	124	{
	125	unsigned long tcon;
	126	unsigned long flags;
	127
	128	if (channel > 0)
	129	++channel;
	130
7aac482e	131	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	132
7cc06179	133	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989	134	tcon &= ~TCON_START(channel);
7cc06179	135	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	136
7aac482e	137	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	138	}
	139
	140	static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
	141	{
	142	unsigned long tcon;
	143	unsigned long flags;
	144	unsigned int tcon_chan = channel;
	145
	146	if (tcon_chan > 0)
	147	++tcon_chan;
	148
7aac482e	149	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	150
7cc06179	151	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989	152
f1189989 TF	153	tcon &= ~(TCON_START(tcon_chan) \| TCON_AUTORELOAD(tcon_chan));
	154	tcon \|= TCON_MANUALUPDATE(tcon_chan);
	155
7cc06179 ML	156	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
	157	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
	158	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	159
7aac482e	160	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	161	}
	162
	163	static void samsung_time_start(unsigned int channel, bool periodic)
	164	{
	165	unsigned long tcon;
	166	unsigned long flags;
	167
	168	if (channel > 0)
	169	++channel;
	170
7aac482e	171	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	172
7cc06179	173	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989 TF	174
	175	tcon &= ~TCON_MANUALUPDATE(channel);
	176	tcon \|= TCON_START(channel);
	177
	178	if (periodic)
	179	tcon \|= TCON_AUTORELOAD(channel);
	180	else
	181	tcon &= ~TCON_AUTORELOAD(channel);
	182
7cc06179	183	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	184
7aac482e	185	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	186	}
	187
	188	static int samsung_set_next_event(unsigned long cycles,
	189	struct clock_event_device *evt)
	190	{
81d4f7bf TF	191	/*
	192	* This check is needed to account for internal rounding
	193	* errors inside clockevents core, which might result in
	194	* passing cycles = 0, which in turn would not generate any
	195	* timer interrupt and hang the system.
	196	*
	197	* Another solution would be to set up the clockevent device
	198	* with min_delta = 2, but this would unnecessarily increase
	199	* the minimum sleep period.
	200	*/
	201	if (!cycles)
	202	cycles = 1;
	203
030c2a1e TF	204	samsung_time_setup(pwm.event_id, cycles);
030c2a1e TF	205	samsung_time_start(pwm.event_id, false);
f1189989 TF	206
	207	return 0;
	208	}
	209
b49b5704	210	static int samsung_shutdown(struct clock_event_device *evt)
f1189989	211	{
030c2a1e	212	samsung_time_stop(pwm.event_id);
b49b5704 VK	213	return 0;
b49b5704 VK	214	}
f1189989	215
b49b5704 VK	216	static int samsung_set_periodic(struct clock_event_device *evt)
	217	{
	218	samsung_time_stop(pwm.event_id);
	219	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	220	samsung_time_start(pwm.event_id, true);
	221	return 0;
f1189989 TF	222	}
f1189989 TF	223
0b96258b TF	224	static void samsung_clockevent_resume(struct clock_event_device *cev)
	225	{
	226	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	227	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
	228
	229	if (pwm.variant.has_tint_cstat) {
	230	u32 mask = (1 << pwm.event_id);
	231	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
	232	}
	233	}
	234
f1189989	235	static struct clock_event_device time_event_device = {
b49b5704 VK	236	.name = "samsung_event_timer",
	237	.features = CLOCK_EVT_FEAT_PERIODIC \|
	238	CLOCK_EVT_FEAT_ONESHOT,
	239	.rating = 200,
	240	.set_next_event = samsung_set_next_event,
	241	.set_state_shutdown = samsung_shutdown,
	242	.set_state_periodic = samsung_set_periodic,
	243	.set_state_oneshot = samsung_shutdown,
	244	.tick_resume = samsung_shutdown,
	245	.resume = samsung_clockevent_resume,
f1189989 TF	246	};
	247
	248	static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
	249	{
	250	struct clock_event_device *evt = dev_id;
	251
030c2a1e TF	252	if (pwm.variant.has_tint_cstat) {
	253	u32 mask = (1 << pwm.event_id);
	254	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	255	}
	256
	257	evt->event_handler(evt);
	258
	259	return IRQ_HANDLED;
	260	}
	261
	262	static struct irqaction samsung_clock_event_irq = {
	263	.name = "samsung_time_irq",
38c30a84	264	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
f1189989 TF	265	.handler = samsung_clock_event_isr,
	266	.dev_id = &time_event_device,
	267	};
	268
	269	static void __init samsung_clockevent_init(void)
	270	{
	271	unsigned long pclk;
	272	unsigned long clock_rate;
	273	unsigned int irq_number;
	274
030c2a1e	275	pclk = clk_get_rate(pwm.timerclk);
f1189989	276
030c2a1e TF	277	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
030c2a1e TF	278	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
f1189989	279
030c2a1e TF	280	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
030c2a1e TF	281	pwm.clock_count_per_tick = clock_rate / HZ;
f1189989 TF	282
f1189989 TF	283	time_event_device.cpumask = cpumask_of(0);
e9b852b8 TF	284	clockevents_config_and_register(&time_event_device,
e9b852b8 TF	285	clock_rate, 1, pwm.tcnt_max);
f1189989	286
030c2a1e	287	irq_number = pwm.irq[pwm.event_id];
f1189989 TF	288	setup_irq(irq_number, &samsung_clock_event_irq);
f1189989 TF	289
030c2a1e TF	290	if (pwm.variant.has_tint_cstat) {
	291	u32 mask = (1 << pwm.event_id);
	292	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	293	}
	294	}
	295
0b96258b	296	static void samsung_clocksource_suspend(struct clocksource *cs)
f1189989	297	{
0b96258b	298	samsung_time_stop(pwm.source_id);
f1189989 TF	299	}
f1189989 TF	300
0b96258b TF	301	static void samsung_clocksource_resume(struct clocksource *cs)
	302	{
	303	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	304	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
	305
	306	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	307	samsung_time_start(pwm.source_id, true);
	308	}
	309
a5a1d1c2	310	static u64 notrace samsung_clocksource_read(struct clocksource *c)
6792e636 TF	311	{
	312	return ~readl_relaxed(pwm.source_reg);
	313	}
	314
	315	static struct clocksource samsung_clocksource = {
	316	.name = "samsung_clocksource_timer",
	317	.rating = 250,
	318	.read = samsung_clocksource_read,
0b96258b TF	319	.suspend = samsung_clocksource_suspend,
0b96258b TF	320	.resume = samsung_clocksource_resume,
6792e636 TF	321	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	322	};
	323
f1189989 TF	324	/*
	325	* Override the global weak sched_clock symbol with this
	326	* local implementation which uses the clocksource to get some
	327	* better resolution when scheduling the kernel. We accept that
	328	* this wraps around for now, since it is just a relative time
	329	* stamp. (Inspired by U300 implementation.)
	330	*/
2902b30e	331	static u64 notrace samsung_read_sched_clock(void)
f1189989	332	{
6792e636	333	return samsung_clocksource_read(NULL);
f1189989 TF	334	}
f1189989 TF	335
0993f57b	336	static int __init samsung_clocksource_init(void)
f1189989	337	{
f1189989 TF	338	unsigned long pclk;
f1189989 TF	339	unsigned long clock_rate;
f1189989	340
030c2a1e	341	pclk = clk_get_rate(pwm.timerclk);
f1189989	342
030c2a1e TF	343	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
030c2a1e TF	344	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
f1189989	345
030c2a1e	346	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
f1189989	347
030c2a1e TF	348	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	349	samsung_time_start(pwm.source_id, true);
f1189989	350
61d7e205 TF	351	if (pwm.source_id == 4)
	352	pwm.source_reg = pwm.base + 0x40;
	353	else
	354	pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
	355
2902b30e	356	sched_clock_register(samsung_read_sched_clock,
030c2a1e	357	pwm.variant.bits, clock_rate);
f1189989	358
6792e636	359	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
0993f57b	360	return clocksource_register_hz(&samsung_clocksource, clock_rate);
f1189989 TF	361	}
	362
	363	static void __init samsung_timer_resources(void)
	364	{
030c2a1e	365	clk_prepare_enable(pwm.timerclk);
f1189989	366
030c2a1e TF	367	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	368	if (pwm.variant.bits == 16) {
	369	pwm.tscaler_div = 25;
	370	pwm.tdiv = 2;
f1189989	371	} else {
030c2a1e TF	372	pwm.tscaler_div = 2;
030c2a1e TF	373	pwm.tdiv = 1;
f1189989 TF	374	}
	375	}
	376
	377	/*
	378	* PWM master driver
	379	*/
0993f57b	380	static int __init _samsung_pwm_clocksource_init(void)
f1189989 TF	381	{
	382	u8 mask;
	383	int channel;
	384
030c2a1e	385	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
f1189989	386	channel = fls(mask) - 1;
0993f57b	387	if (channel < 0) {
ac9ce6d1	388	pr_crit("failed to find PWM channel for clocksource\n");
0993f57b DL	389	return -EINVAL;
0993f57b DL	390	}
030c2a1e	391	pwm.source_id = channel;
f1189989 TF	392
	393	mask &= ~(1 << channel);
	394	channel = fls(mask) - 1;
0993f57b	395	if (channel < 0) {
ac9ce6d1	396	pr_crit("failed to find PWM channel for clock event\n");
0993f57b DL	397	return -EINVAL;
0993f57b DL	398	}
030c2a1e	399	pwm.event_id = channel;
f1189989 TF	400
	401	samsung_timer_resources();
	402	samsung_clockevent_init();
0993f57b DL	403
0993f57b DL	404	return samsung_clocksource_init();
f1189989 TF	405	}
f1189989 TF	406
f9bb48a2 TF	407	void __init samsung_pwm_clocksource_init(void __iomem *base,
	408	unsigned int irqs, struct samsung_pwm_variant variant)
	409	{
	410	pwm.base = base;
	411	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	412	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
	413
a1fa6f50 TF	414	pwm.timerclk = clk_get(NULL, "timers");
	415	if (IS_ERR(pwm.timerclk))
	416	panic("failed to get timers clock for timer");
	417
f9bb48a2 TF	418	_samsung_pwm_clocksource_init();
	419	}
	420
bb0eb050	421	#ifdef CONFIG_TIMER_OF
0993f57b DL	422	static int __init samsung_pwm_alloc(struct device_node *np,
0993f57b DL	423	const struct samsung_pwm_variant *variant)
f1189989	424	{
f1189989 TF	425	struct property *prop;
	426	const __be32 *cur;
	427	u32 val;
	428	int i;
	429
030c2a1e	430	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
f1189989	431	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
030c2a1e	432	pwm.irq[i] = irq_of_parse_and_map(np, i);
f1189989 TF	433
	434	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
	435	if (val >= SAMSUNG_PWM_NUM) {
	436	pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
	437	__func__);
	438	continue;
	439	}
030c2a1e	440	pwm.variant.output_mask \|= 1 << val;
f1189989 TF	441	}
f1189989 TF	442
e2415489	443	pwm.base = of_iomap(np, 0);
030c2a1e	444	if (!pwm.base) {
f1189989	445	pr_err("%s: failed to map PWM registers\n", __func__);
0993f57b	446	return -ENXIO;
f1189989 TF	447	}
f1189989 TF	448
a1fa6f50	449	pwm.timerclk = of_clk_get_by_name(np, "timers");
0993f57b	450	if (IS_ERR(pwm.timerclk)) {
ac9ce6d1	451	pr_crit("failed to get timers clock for timer\n");
0993f57b DL	452	return PTR_ERR(pwm.timerclk);
0993f57b DL	453	}
a1fa6f50	454
0993f57b	455	return _samsung_pwm_clocksource_init();
f1189989 TF	456	}
	457
	458	static const struct samsung_pwm_variant s3c24xx_variant = {
	459	.bits = 16,
	460	.div_base = 1,
	461	.has_tint_cstat = false,
	462	.tclk_mask = (1 << 4),
	463	};
	464
0993f57b	465	static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
f1189989	466	{
0993f57b	467	return samsung_pwm_alloc(np, &s3c24xx_variant);
f1189989	468	}
17273395	469	TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
f1189989 TF	470
	471	static const struct samsung_pwm_variant s3c64xx_variant = {
	472	.bits = 32,
	473	.div_base = 0,
	474	.has_tint_cstat = true,
	475	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	476	};
	477
0993f57b	478	static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
f1189989	479	{
0993f57b	480	return samsung_pwm_alloc(np, &s3c64xx_variant);
f1189989	481	}
17273395	482	TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
f1189989 TF	483
	484	static const struct samsung_pwm_variant s5p64x0_variant = {
	485	.bits = 32,
	486	.div_base = 0,
	487	.has_tint_cstat = true,
	488	.tclk_mask = 0,
	489	};
	490
0993f57b	491	static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
f1189989	492	{
0993f57b	493	return samsung_pwm_alloc(np, &s5p64x0_variant);
f1189989	494	}
17273395	495	TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
f1189989 TF	496
	497	static const struct samsung_pwm_variant s5p_variant = {
	498	.bits = 32,
	499	.div_base = 0,
	500	.has_tint_cstat = true,
	501	.tclk_mask = (1 << 5),
	502	};
	503
0993f57b	504	static int __init s5p_pwm_clocksource_init(struct device_node *np)
f1189989	505	{
0993f57b	506	return samsung_pwm_alloc(np, &s5p_variant);
f1189989	507	}
17273395	508	TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
f9bb48a2	509	#endif