[linux.git] / drivers / spi / spi-jcore.c

/*
 * J-Core SPI controller driver
 *
 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
 *
 * Current version by Rich Felker
 * Based loosely on initial version by Oleksandr G Zhadan
 *
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/delay.h>

#define DRV_NAME	"jcore_spi"

#define CTRL_REG	0x0
#define DATA_REG	0x4

#define JCORE_SPI_CTRL_XMIT		0x02
#define JCORE_SPI_STAT_BUSY		0x02
#define JCORE_SPI_CTRL_LOOP		0x08
#define JCORE_SPI_CTRL_CS_BITS		0x15

#define JCORE_SPI_WAIT_RDY_MAX_LOOP	2000000

struct jcore_spi {
	struct spi_master *master;
	void __iomem *base;
	unsigned int cs_reg;
	unsigned int speed_reg;
	unsigned int speed_hz;
	unsigned int clock_freq;
};

static int jcore_spi_wait(void __iomem *ctrl_reg)
{
	unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;

	do {
		if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
			return 0;
		cpu_relax();
	} while (--timeout);

	return -EBUSY;
}

static void jcore_spi_program(struct jcore_spi *hw)
{
	void __iomem *ctrl_reg = hw->base + CTRL_REG;

	if (jcore_spi_wait(ctrl_reg))
		dev_err(hw->master->dev.parent,
			"timeout waiting to program ctrl reg.\n");

	writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
}

static void jcore_spi_chipsel(struct spi_device *spi, bool value)
{
	struct jcore_spi *hw = spi_master_get_devdata(spi->master);
	u32 csbit = 1U << (2 * spi->chip_select);

	dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);

	if (value)
		hw->cs_reg |= csbit;
	else
		hw->cs_reg &= ~csbit;

	jcore_spi_program(hw);
}

static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
{
	if (speed == hw->speed_hz) return;
	hw->speed_hz = speed;
	if (speed >= hw->clock_freq / 2)
		hw->speed_reg = 0;
	else
		hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;
	jcore_spi_program(hw);
	dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n",
		speed, hw->speed_reg);
}

static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,
			  struct spi_transfer *t)
{
	struct jcore_spi *hw = spi_master_get_devdata(master);

	void __iomem *ctrl_reg = hw->base + CTRL_REG;
	void __iomem *data_reg = hw->base + DATA_REG;
	u32 xmit;

	/* data buffers */
	const unsigned char *tx;
	unsigned char *rx;
	unsigned int len;
	unsigned int count;

	jcore_spi_baudrate(hw, t->speed_hz);

	xmit = hw->cs_reg | hw->speed_reg | JCORE_SPI_CTRL_XMIT;
	tx = t->tx_buf;
	rx = t->rx_buf;
	len = t->len;

	for (count = 0; count < len; count++) {
		if (jcore_spi_wait(ctrl_reg))
			break;

		writel(tx ? *tx++ : 0, data_reg);
		writel(xmit, ctrl_reg);

		if (jcore_spi_wait(ctrl_reg))
			break;

		if (rx)
			*rx++ = readl(data_reg);
	}

	spi_finalize_current_transfer(master);

	if (count < len)
		return -EREMOTEIO;

	return 0;
}

static int jcore_spi_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct jcore_spi *hw;
	struct spi_master *master;
	struct resource *res;
	u32 clock_freq;
	struct clk *clk;
	int err = -ENODEV;

	master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi));
	if (!master)
		return err;

	/* Setup the master state. */
	master->num_chipselect = 3;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
	master->transfer_one = jcore_spi_txrx;
	master->set_cs = jcore_spi_chipsel;
	master->dev.of_node = node;
	master->bus_num = pdev->id;

	hw = spi_master_get_devdata(master);
	hw->master = master;
	platform_set_drvdata(pdev, hw);

	/* Find and map our resources */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		goto exit_busy;
	if (!devm_request_mem_region(&pdev->dev, res->start,
				     resource_size(res), pdev->name))
		goto exit_busy;
	hw->base = devm_ioremap_nocache(&pdev->dev, res->start,
					resource_size(res));
	if (!hw->base)
		goto exit_busy;

	/*
	 * The SPI clock rate controlled via a configurable clock divider
	 * which is applied to the reference clock. A 50 MHz reference is
	 * most suitable for obtaining standard SPI clock rates, but some
	 * designs may have a different reference clock, and the DT must
	 * make the driver aware so that it can properly program the
	 * requested rate. If the clock is omitted, 50 MHz is assumed.
	 */
	clock_freq = 50000000;
	clk = devm_clk_get(&pdev->dev, "ref_clk");
	if (!IS_ERR(clk)) {
		if (clk_prepare_enable(clk) == 0) {
			clock_freq = clk_get_rate(clk);
			clk_disable_unprepare(clk);
		} else
			dev_warn(&pdev->dev, "could not enable ref_clk\n");
	}
	hw->clock_freq = clock_freq;

	/* Initialize all CS bits to high. */
	hw->cs_reg = JCORE_SPI_CTRL_CS_BITS;
	jcore_spi_baudrate(hw, 400000);

	/* Register our spi controller */
	err = devm_spi_register_master(&pdev->dev, master);
	if (err)
		goto exit;

	return 0;

exit_busy:
	err = -EBUSY;
exit:
	spi_master_put(master);
	return err;
}

static const struct of_device_id jcore_spi_of_match[] = {
	{ .compatible = "jcore,spi2" },
	{},
};
MODULE_DEVICE_TABLE(of, jcore_spi_of_match);

static struct platform_driver jcore_spi_driver = {
	.probe = jcore_spi_probe,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = jcore_spi_of_match,
	},
};

module_platform_driver(jcore_spi_driver);

MODULE_DESCRIPTION("J-Core SPI driver");
MODULE_AUTHOR("Rich Felker <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
2cb1b3b3 RF	1	/*
	2	* J-Core SPI controller driver
	3	*
	4	* Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
	5	*
	6	* Current version by Rich Felker
	7	* Based loosely on initial version by Oleksandr G Zhadan
	8	*
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/errno.h>
	13	#include <linux/module.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/spi/spi.h>
	16	#include <linux/clk.h>
	17	#include <linux/err.h>
	18	#include <linux/io.h>
	19	#include <linux/of.h>
	20	#include <linux/delay.h>
	21
	22	#define DRV_NAME "jcore_spi"
	23
	24	#define CTRL_REG 0x0
	25	#define DATA_REG 0x4
	26
	27	#define JCORE_SPI_CTRL_XMIT 0x02
	28	#define JCORE_SPI_STAT_BUSY 0x02
	29	#define JCORE_SPI_CTRL_LOOP 0x08
	30	#define JCORE_SPI_CTRL_CS_BITS 0x15
	31
	32	#define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000
	33
	34	struct jcore_spi {
	35	struct spi_master *master;
	36	void __iomem *base;
	37	unsigned int cs_reg;
	38	unsigned int speed_reg;
	39	unsigned int speed_hz;
	40	unsigned int clock_freq;
	41	};
	42
	43	static int jcore_spi_wait(void __iomem *ctrl_reg)
	44	{
	45	unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;
	46
	47	do {
	48	if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
	49	return 0;
	50	cpu_relax();
	51	} while (--timeout);
	52
	53	return -EBUSY;
	54	}
	55
	56	static void jcore_spi_program(struct jcore_spi *hw)
	57	{
	58	void __iomem *ctrl_reg = hw->base + CTRL_REG;
	59
	60	if (jcore_spi_wait(ctrl_reg))
	61	dev_err(hw->master->dev.parent,
	62	"timeout waiting to program ctrl reg.\n");
	63
	64	writel(hw->cs_reg \| hw->speed_reg, ctrl_reg);
65	}
66
67	static void jcore_spi_chipsel(struct spi_device *spi, bool value)
68	{
69	struct jcore_spi *hw = spi_master_get_devdata(spi->master);
70	u32 csbit = 1U << (2 * spi->chip_select);
71
72	dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);
73
74	if (value)
75	hw->cs_reg \|= csbit;
76	else
77	hw->cs_reg &= ~csbit;
78
79	jcore_spi_program(hw);
80	}
81
82	static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
83	{
84	if (speed == hw->speed_hz) return;
85	hw->speed_hz = speed;
86	if (speed >= hw->clock_freq / 2)
87	hw->speed_reg = 0;
88	else
89	hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;
90	jcore_spi_program(hw);
91	dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n",
92	speed, hw->speed_reg);
93	}
94
95	static int jcore_spi_txrx(struct spi_master master, struct spi_device spi,
96	struct spi_transfer *t)
97	{
98	struct jcore_spi *hw = spi_master_get_devdata(master);
99
100	void __iomem *ctrl_reg = hw->base + CTRL_REG;
101	void __iomem *data_reg = hw->base + DATA_REG;
102	u32 xmit;
103
104	/* data buffers */
105	const unsigned char *tx;
106	unsigned char *rx;
107	unsigned int len;
108	unsigned int count;
109
110	jcore_spi_baudrate(hw, t->speed_hz);
111
112	xmit = hw->cs_reg \| hw->speed_reg \| JCORE_SPI_CTRL_XMIT;
113	tx = t->tx_buf;
114	rx = t->rx_buf;
115	len = t->len;
116
117	for (count = 0; count < len; count++) {
118	if (jcore_spi_wait(ctrl_reg))
119	break;
120
121	writel(tx ? *tx++ : 0, data_reg);
122	writel(xmit, ctrl_reg);
123
124	if (jcore_spi_wait(ctrl_reg))
125	break;
126
127	if (rx)
128	*rx++ = readl(data_reg);
129	}
130
131	spi_finalize_current_transfer(master);
132
133	if (count < len)
134	return -EREMOTEIO;
135
136	return 0;
137	}
138
139	static int jcore_spi_probe(struct platform_device *pdev)
140	{
141	struct device_node *node = pdev->dev.of_node;
142	struct jcore_spi *hw;
143	struct spi_master *master;
144	struct resource *res;
145	u32 clock_freq;
146	struct clk *clk;
147	int err = -ENODEV;
148
149	master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi));
150	if (!master)
151	return err;
152
153	/* Setup the master state. */
154	master->num_chipselect = 3;
155	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
156	master->transfer_one = jcore_spi_txrx;
157	master->set_cs = jcore_spi_chipsel;
158	master->dev.of_node = node;
159	master->bus_num = pdev->id;
160
161	hw = spi_master_get_devdata(master);
162	hw->master = master;
163	platform_set_drvdata(pdev, hw);
164
165	/* Find and map our resources */
166	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
167	if (!res)
168	goto exit_busy;
169	if (!devm_request_mem_region(&pdev->dev, res->start,
170	resource_size(res), pdev->name))
171	goto exit_busy;
172	hw->base = devm_ioremap_nocache(&pdev->dev, res->start,
173	resource_size(res));
174	if (!hw->base)
175	goto exit_busy;
176
177	/*
178	* The SPI clock rate controlled via a configurable clock divider
179	* which is applied to the reference clock. A 50 MHz reference is
180	* most suitable for obtaining standard SPI clock rates, but some
181	* designs may have a different reference clock, and the DT must
182	* make the driver aware so that it can properly program the
183	* requested rate. If the clock is omitted, 50 MHz is assumed.
184	*/
185	clock_freq = 50000000;
186	clk = devm_clk_get(&pdev->dev, "ref_clk");
7c2861a6 AK	187	if (!IS_ERR(clk)) {
7c2861a6 AK	188	if (clk_prepare_enable(clk) == 0) {
2cb1b3b3	189	clock_freq = clk_get_rate(clk);
7c2861a6 AK	190	clk_disable_unprepare(clk);
7c2861a6 AK	191	} else
2cb1b3b3 RF	192	dev_warn(&pdev->dev, "could not enable ref_clk\n");
	193	}
	194	hw->clock_freq = clock_freq;
	195
	196	/* Initialize all CS bits to high. */
	197	hw->cs_reg = JCORE_SPI_CTRL_CS_BITS;
	198	jcore_spi_baudrate(hw, 400000);
	199
	200	/* Register our spi controller */
	201	err = devm_spi_register_master(&pdev->dev, master);
7c2861a6	202	if (err)
2cb1b3b3 RF	203	goto exit;
	204
	205	return 0;
	206
	207	exit_busy:
	208	err = -EBUSY;
	209	exit:
2cb1b3b3 RF	210	spi_master_put(master);
	211	return err;
	212	}
	213
	214	static const struct of_device_id jcore_spi_of_match[] = {
	215	{ .compatible = "jcore,spi2" },
	216	{},
	217	};
aa12c1ab	218	MODULE_DEVICE_TABLE(of, jcore_spi_of_match);
2cb1b3b3 RF	219
	220	static struct platform_driver jcore_spi_driver = {
	221	.probe = jcore_spi_probe,
	222	.driver = {
	223	.name = DRV_NAME,
	224	.of_match_table = jcore_spi_of_match,
	225	},
	226	};
	227
	228	module_platform_driver(jcore_spi_driver);
	229
	230	MODULE_DESCRIPTION("J-Core SPI driver");
	231	MODULE_AUTHOR("Rich Felker <[email protected]>");
	232	MODULE_LICENSE("GPL");
	233	MODULE_ALIAS("platform:" DRV_NAME);