[linux.git] / drivers / fpga / altera-ps-spi.c

/*
 * Altera Passive Serial SPI Driver
 *
 *  Copyright (c) 2017 United Western Technologies, Corporation
 *
 *  Joshua Clayton <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * Manage Altera FPGA firmware that is loaded over SPI using the passive
 * serial configuration method.
 * Firmware must be in binary "rbf" format.
 * Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
 * May work on other Altera FPGAs.
 */

#include <linux/bitrev.h>
#include <linux/delay.h>
#include <linux/fpga/fpga-mgr.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
#include <linux/spi/spi.h>
#include <linux/sizes.h>

enum altera_ps_devtype {
	CYCLONE5,
	ARRIA10,
};

struct altera_ps_data {
	enum altera_ps_devtype devtype;
	int status_wait_min_us;
	int status_wait_max_us;
	int t_cfg_us;
	int t_st2ck_us;
};

struct altera_ps_conf {
	struct gpio_desc *config;
	struct gpio_desc *confd;
	struct gpio_desc *status;
	struct spi_device *spi;
	const struct altera_ps_data *data;
	u32 info_flags;
	char mgr_name[64];
};

/*          |   Arria 10  |   Cyclone5  |   Stratix5  |
 * t_CF2ST0 |     [; 600] |     [; 600] |     [; 600] |ns
 * t_CFG    |        [2;] |        [2;] |        [2;] |µs
 * t_STATUS | [268; 3000] | [268; 1506] | [268; 1506] |µs
 * t_CF2ST1 |    [; 3000] |    [; 1506] |    [; 1506] |µs
 * t_CF2CK  |     [3010;] |     [1506;] |     [1506;] |µs
 * t_ST2CK  |       [10;] |        [2;] |        [2;] |µs
 * t_CD2UM  |  [175; 830] |  [175; 437] |  [175; 437] |µs
 */
static struct altera_ps_data c5_data = {
	/* these values for Cyclone5 are compatible with Stratix5 */
	.devtype = CYCLONE5,
	.status_wait_min_us = 268,
	.status_wait_max_us = 1506,
	.t_cfg_us = 2,
	.t_st2ck_us = 2,
};

static struct altera_ps_data a10_data = {
	.devtype = ARRIA10,
	.status_wait_min_us = 268,  /* min(t_STATUS) */
	.status_wait_max_us = 3000, /* max(t_CF2ST1) */
	.t_cfg_us = 2,    /* max { min(t_CFG), max(tCF2ST0) } */
	.t_st2ck_us = 10, /* min(t_ST2CK) */
};

static const struct of_device_id of_ef_match[] = {
	{ .compatible = "altr,fpga-passive-serial", .data = &c5_data },
	{ .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
	{}
};
MODULE_DEVICE_TABLE(of, of_ef_match);

static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
{
	struct altera_ps_conf *conf = mgr->priv;

	if (gpiod_get_value_cansleep(conf->status))
		return FPGA_MGR_STATE_RESET;

	return FPGA_MGR_STATE_UNKNOWN;
}

static inline void altera_ps_delay(int delay_us)
{
	if (delay_us > 10)
		usleep_range(delay_us, delay_us + 5);
	else
		udelay(delay_us);
}

static int altera_ps_write_init(struct fpga_manager *mgr,
				struct fpga_image_info *info,
				const char *buf, size_t count)
{
	struct altera_ps_conf *conf = mgr->priv;
	int min, max, waits;
	int i;

	conf->info_flags = info->flags;

	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
		return -EINVAL;
	}

	gpiod_set_value_cansleep(conf->config, 1);

	/* wait min reset pulse time */
	altera_ps_delay(conf->data->t_cfg_us);

	if (!gpiod_get_value_cansleep(conf->status)) {
		dev_err(&mgr->dev, "Status pin failed to show a reset\n");
		return -EIO;
	}

	gpiod_set_value_cansleep(conf->config, 0);

	min = conf->data->status_wait_min_us;
	max = conf->data->status_wait_max_us;
	waits = max / min;
	if (max % min)
		waits++;

	/* wait for max { max(t_STATUS), max(t_CF2ST1) } */
	for (i = 0; i < waits; i++) {
		usleep_range(min, min + 10);
		if (!gpiod_get_value_cansleep(conf->status)) {
			/* wait for min(t_ST2CK)*/
			altera_ps_delay(conf->data->t_st2ck_us);
			return 0;
		}
	}

	dev_err(&mgr->dev, "Status pin not ready.\n");
	return -EIO;
}

static void rev_buf(char *buf, size_t len)
{
	u32 *fw32 = (u32 *)buf;
	size_t extra_bytes = (len & 0x03);
	const u32 *fw_end = (u32 *)(buf + len - extra_bytes);

	/* set buffer to lsb first */
	while (fw32 < fw_end) {
		*fw32 = bitrev8x4(*fw32);
		fw32++;
	}

	if (extra_bytes) {
		buf = (char *)fw_end;
		while (extra_bytes) {
			*buf = bitrev8(*buf);
			buf++;
			extra_bytes--;
		}
	}
}

static int altera_ps_write(struct fpga_manager *mgr, const char *buf,
			   size_t count)
{
	struct altera_ps_conf *conf = mgr->priv;
	const char *fw_data = buf;
	const char *fw_data_end = fw_data + count;

	while (fw_data < fw_data_end) {
		int ret;
		size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);

		if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
			rev_buf((char *)fw_data, stride);

		ret = spi_write(conf->spi, fw_data, stride);
		if (ret) {
			dev_err(&mgr->dev, "spi error in firmware write: %d\n",
				ret);
			return ret;
		}
		fw_data += stride;
	}

	return 0;
}

static int altera_ps_write_complete(struct fpga_manager *mgr,
				    struct fpga_image_info *info)
{
	struct altera_ps_conf *conf = mgr->priv;
	const char dummy[] = {0};
	int ret;

	if (gpiod_get_value_cansleep(conf->status)) {
		dev_err(&mgr->dev, "Error during configuration.\n");
		return -EIO;
	}

	if (!IS_ERR(conf->confd)) {
		if (!gpiod_get_raw_value_cansleep(conf->confd)) {
			dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
			return -EIO;
		}
	}

	/*
	 * After CONF_DONE goes high, send two additional falling edges on DCLK
	 * to begin initialization and enter user mode
	 */
	ret = spi_write(conf->spi, dummy, 1);
	if (ret) {
		dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
		return ret;
	}

	return 0;
}

static const struct fpga_manager_ops altera_ps_ops = {
	.state = altera_ps_state,
	.write_init = altera_ps_write_init,
	.write = altera_ps_write,
	.write_complete = altera_ps_write_complete,
};

static int altera_ps_probe(struct spi_device *spi)
{
	struct altera_ps_conf *conf;
	const struct of_device_id *of_id;

	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
	if (!conf)
		return -ENOMEM;

	of_id = of_match_device(of_ef_match, &spi->dev);
	if (!of_id)
		return -ENODEV;

	conf->data = of_id->data;
	conf->spi = spi;
	conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH);
	if (IS_ERR(conf->config)) {
		dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
			PTR_ERR(conf->config));
		return PTR_ERR(conf->config);
	}

	conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
	if (IS_ERR(conf->status)) {
		dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
			PTR_ERR(conf->status));
		return PTR_ERR(conf->status);
	}

	conf->confd = devm_gpiod_get(&spi->dev, "confd", GPIOD_IN);
	if (IS_ERR(conf->confd)) {
		dev_warn(&spi->dev, "Not using confd gpio: %ld\n",
			 PTR_ERR(conf->confd));
	}

	/* Register manager with unique name */
	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
		 dev_driver_string(&spi->dev), dev_name(&spi->dev));

	return fpga_mgr_register(&spi->dev, conf->mgr_name,
				 &altera_ps_ops, conf);
}

static int altera_ps_remove(struct spi_device *spi)
{
	fpga_mgr_unregister(&spi->dev);

	return 0;
}

static const struct spi_device_id altera_ps_spi_ids[] = {
	{"cyclone-ps-spi", 0},
	{}
};
MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);

static struct spi_driver altera_ps_driver = {
	.driver = {
		.name = "altera-ps-spi",
		.owner = THIS_MODULE,
		.of_match_table = of_match_ptr(of_ef_match),
	},
	.id_table = altera_ps_spi_ids,
	.probe = altera_ps_probe,
	.remove = altera_ps_remove,
};

module_spi_driver(altera_ps_driver)

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Joshua Clayton <[email protected]>");
MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");
Commit	Line	Data
5692fae0 JC	1	/*
	2	* Altera Passive Serial SPI Driver
	3	*
	4	* Copyright (c) 2017 United Western Technologies, Corporation
	5	*
	6	* Joshua Clayton <[email protected]>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* Manage Altera FPGA firmware that is loaded over SPI using the passive
	13	* serial configuration method.
	14	* Firmware must be in binary "rbf" format.
	15	* Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
	16	* May work on other Altera FPGAs.
	17	*/
	18
	19	#include <linux/bitrev.h>
	20	#include <linux/delay.h>
	21	#include <linux/fpga/fpga-mgr.h>
	22	#include <linux/gpio/consumer.h>
	23	#include <linux/module.h>
	24	#include <linux/of_gpio.h>
	25	#include <linux/of_device.h>
	26	#include <linux/spi/spi.h>
	27	#include <linux/sizes.h>
	28
	29	enum altera_ps_devtype {
	30	CYCLONE5,
	31	ARRIA10,
	32	};
	33
	34	struct altera_ps_data {
	35	enum altera_ps_devtype devtype;
	36	int status_wait_min_us;
	37	int status_wait_max_us;
	38	int t_cfg_us;
	39	int t_st2ck_us;
	40	};
	41
	42	struct altera_ps_conf {
	43	struct gpio_desc *config;
	44	struct gpio_desc *confd;
	45	struct gpio_desc *status;
	46	struct spi_device *spi;
	47	const struct altera_ps_data *data;
	48	u32 info_flags;
	49	char mgr_name[64];
	50	};
	51
	52	/* \| Arria 10 \| Cyclone5 \| Stratix5 \|
	53	* t_CF2ST0 \| [; 600] \| [; 600] \| [; 600] \|ns
	54	* t_CFG \| [2;] \| [2;] \| [2;] \|µs
	55	* t_STATUS \| [268; 3000] \| [268; 1506] \| [268; 1506] \|µs
	56	* t_CF2ST1 \| [; 3000] \| [; 1506] \| [; 1506] \|µs
	57	* t_CF2CK \| [3010;] \| [1506;] \| [1506;] \|µs
	58	* t_ST2CK \| [10;] \| [2;] \| [2;] \|µs
	59	* t_CD2UM \| [175; 830] \| [175; 437] \| [175; 437] \|µs
	60	*/
	61	static struct altera_ps_data c5_data = {
	62	/* these values for Cyclone5 are compatible with Stratix5 */
	63	.devtype = CYCLONE5,
	64	.status_wait_min_us = 268,
65	.status_wait_max_us = 1506,
66	.t_cfg_us = 2,
67	.t_st2ck_us = 2,
68	};
69
70	static struct altera_ps_data a10_data = {
71	.devtype = ARRIA10,
72	.status_wait_min_us = 268, /* min(t_STATUS) */
73	.status_wait_max_us = 3000, /* max(t_CF2ST1) */
74	.t_cfg_us = 2, /* max { min(t_CFG), max(tCF2ST0) } */
75	.t_st2ck_us = 10, /* min(t_ST2CK) */
76	};
77
78	static const struct of_device_id of_ef_match[] = {
79	{ .compatible = "altr,fpga-passive-serial", .data = &c5_data },
80	{ .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
81	{}
82	};
83	MODULE_DEVICE_TABLE(of, of_ef_match);
84
85	static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
86	{
87	struct altera_ps_conf *conf = mgr->priv;
88
89	if (gpiod_get_value_cansleep(conf->status))
90	return FPGA_MGR_STATE_RESET;
91
92	return FPGA_MGR_STATE_UNKNOWN;
93	}
94
95	static inline void altera_ps_delay(int delay_us)
96	{
97	if (delay_us > 10)
98	usleep_range(delay_us, delay_us + 5);
99	else
100	udelay(delay_us);
101	}
102
103	static int altera_ps_write_init(struct fpga_manager *mgr,
104	struct fpga_image_info *info,
105	const char *buf, size_t count)
106	{
107	struct altera_ps_conf *conf = mgr->priv;
108	int min, max, waits;
109	int i;
110
111	conf->info_flags = info->flags;
112
113	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
114	dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
115	return -EINVAL;
116	}
117
118	gpiod_set_value_cansleep(conf->config, 1);
119
120	/* wait min reset pulse time */
121	altera_ps_delay(conf->data->t_cfg_us);
122
123	if (!gpiod_get_value_cansleep(conf->status)) {
124	dev_err(&mgr->dev, "Status pin failed to show a reset\n");
125	return -EIO;
126	}
127
128	gpiod_set_value_cansleep(conf->config, 0);
129
130	min = conf->data->status_wait_min_us;
131	max = conf->data->status_wait_max_us;
132	waits = max / min;
133	if (max % min)
134	waits++;
135
136	/* wait for max { max(t_STATUS), max(t_CF2ST1) } */
137	for (i = 0; i < waits; i++) {
138	usleep_range(min, min + 10);
139	if (!gpiod_get_value_cansleep(conf->status)) {
140	/* wait for min(t_ST2CK)*/
141	altera_ps_delay(conf->data->t_st2ck_us);
142	return 0;
143	}
144	}
145
146	dev_err(&mgr->dev, "Status pin not ready.\n");
147	return -EIO;
148	}
149
150	static void rev_buf(char *buf, size_t len)
151	{
fcfe18f8 JC	152	u32 fw32 = (u32 )buf;
	153	size_t extra_bytes = (len & 0x03);
	154	const u32 fw_end = (u32 )(buf + len - extra_bytes);
5692fae0 JC	155
5692fae0 JC	156	/* set buffer to lsb first */
fcfe18f8 JC	157	while (fw32 < fw_end) {
	158	fw32 = bitrev8x4(fw32);
	159	fw32++;
	160	}
	161
	162	if (extra_bytes) {
	163	buf = (char *)fw_end;
	164	while (extra_bytes) {
	165	buf = bitrev8(buf);
	166	buf++;
	167	extra_bytes--;
	168	}
5692fae0 JC	169	}
	170	}
	171
	172	static int altera_ps_write(struct fpga_manager mgr, const char buf,
	173	size_t count)
	174	{
	175	struct altera_ps_conf *conf = mgr->priv;
	176	const char *fw_data = buf;
	177	const char *fw_data_end = fw_data + count;
	178
	179	while (fw_data < fw_data_end) {
	180	int ret;
	181	size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);
	182
	183	if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
	184	rev_buf((char *)fw_data, stride);
	185
	186	ret = spi_write(conf->spi, fw_data, stride);
	187	if (ret) {
	188	dev_err(&mgr->dev, "spi error in firmware write: %d\n",
	189	ret);
	190	return ret;
	191	}
	192	fw_data += stride;
	193	}
	194
	195	return 0;
	196	}
	197
	198	static int altera_ps_write_complete(struct fpga_manager *mgr,
	199	struct fpga_image_info *info)
	200	{
	201	struct altera_ps_conf *conf = mgr->priv;
	202	const char dummy[] = {0};
	203	int ret;
	204
	205	if (gpiod_get_value_cansleep(conf->status)) {
	206	dev_err(&mgr->dev, "Error during configuration.\n");
	207	return -EIO;
	208	}
	209
	210	if (!IS_ERR(conf->confd)) {
	211	if (!gpiod_get_raw_value_cansleep(conf->confd)) {
	212	dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
	213	return -EIO;
	214	}
	215	}
	216
	217	/*
	218	* After CONF_DONE goes high, send two additional falling edges on DCLK
	219	* to begin initialization and enter user mode
	220	*/
	221	ret = spi_write(conf->spi, dummy, 1);
	222	if (ret) {
	223	dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
	224	return ret;
	225	}
	226
	227	return 0;
	228	}
	229
	230	static const struct fpga_manager_ops altera_ps_ops = {
	231	.state = altera_ps_state,
	232	.write_init = altera_ps_write_init,
233	.write = altera_ps_write,
234	.write_complete = altera_ps_write_complete,
235	};
236
237	static int altera_ps_probe(struct spi_device *spi)
238	{
239	struct altera_ps_conf *conf;
240	const struct of_device_id *of_id;
241
242	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
243	if (!conf)
244	return -ENOMEM;
245
246	of_id = of_match_device(of_ef_match, &spi->dev);
247	if (!of_id)
248	return -ENODEV;
249
250	conf->data = of_id->data;
251	conf->spi = spi;
252	conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH);
253	if (IS_ERR(conf->config)) {
254	dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
255	PTR_ERR(conf->config));
256	return PTR_ERR(conf->config);
257	}
258
259	conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
260	if (IS_ERR(conf->status)) {
261	dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
262	PTR_ERR(conf->status));
263	return PTR_ERR(conf->status);
264	}
265
266	conf->confd = devm_gpiod_get(&spi->dev, "confd", GPIOD_IN);
267	if (IS_ERR(conf->confd)) {
268	dev_warn(&spi->dev, "Not using confd gpio: %ld\n",
269	PTR_ERR(conf->confd));
270	}
271
272	/* Register manager with unique name */
273	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
274	dev_driver_string(&spi->dev), dev_name(&spi->dev));
275
276	return fpga_mgr_register(&spi->dev, conf->mgr_name,
277	&altera_ps_ops, conf);
278	}
279
280	static int altera_ps_remove(struct spi_device *spi)
281	{
282	fpga_mgr_unregister(&spi->dev);
283
284	return 0;
285	}
286
287	static const struct spi_device_id altera_ps_spi_ids[] = {
288	{"cyclone-ps-spi", 0},
289	{}
290	};
291	MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);
292
293	static struct spi_driver altera_ps_driver = {
294	.driver = {
295	.name = "altera-ps-spi",
296	.owner = THIS_MODULE,
297	.of_match_table = of_match_ptr(of_ef_match),
298	},
299	.id_table = altera_ps_spi_ids,
300	.probe = altera_ps_probe,
301	.remove = altera_ps_remove,
302	};
303
304	module_spi_driver(altera_ps_driver)
305
306	MODULE_LICENSE("GPL v2");
307	MODULE_AUTHOR("Joshua Clayton <[email protected]>");
308	MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");