[linux.git] / drivers / clk / clk-nomadik.c

/*
 * Nomadik clock implementation
 * Copyright (C) 2013 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * Author: Linus Walleij <[email protected]>
 */

#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt

#include <linux/bitops.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/reboot.h>

/*
 * The Nomadik clock tree is described in the STN8815A12 DB V4.2
 * reference manual for the chip, page 94 ff.
 * Clock IDs are in the STn8815 Reference Manual table 3, page 27.
 */

#define SRC_CR			0x00U
#define SRC_CR_T0_ENSEL		BIT(15)
#define SRC_CR_T1_ENSEL		BIT(17)
#define SRC_CR_T2_ENSEL		BIT(19)
#define SRC_CR_T3_ENSEL		BIT(21)
#define SRC_CR_T4_ENSEL		BIT(23)
#define SRC_CR_T5_ENSEL		BIT(25)
#define SRC_CR_T6_ENSEL		BIT(27)
#define SRC_CR_T7_ENSEL		BIT(29)
#define SRC_XTALCR		0x0CU
#define SRC_XTALCR_XTALTIMEN	BIT(20)
#define SRC_XTALCR_SXTALDIS	BIT(19)
#define SRC_XTALCR_MXTALSTAT	BIT(2)
#define SRC_XTALCR_MXTALEN	BIT(1)
#define SRC_XTALCR_MXTALOVER	BIT(0)
#define SRC_PLLCR		0x10U
#define SRC_PLLCR_PLLTIMEN	BIT(29)
#define SRC_PLLCR_PLL2EN	BIT(28)
#define SRC_PLLCR_PLL1STAT	BIT(2)
#define SRC_PLLCR_PLL1EN	BIT(1)
#define SRC_PLLCR_PLL1OVER	BIT(0)
#define SRC_PLLFR		0x14U
#define SRC_PCKEN0		0x24U
#define SRC_PCKDIS0		0x28U
#define SRC_PCKENSR0		0x2CU
#define SRC_PCKSR0		0x30U
#define SRC_PCKEN1		0x34U
#define SRC_PCKDIS1		0x38U
#define SRC_PCKENSR1		0x3CU
#define SRC_PCKSR1		0x40U

/* Lock protecting the SRC_CR register */
static DEFINE_SPINLOCK(src_lock);
/* Base address of the SRC */
static void __iomem *src_base;

static int nomadik_clk_reboot_handler(struct notifier_block *this,
				unsigned long code,
				void *unused)
{
	u32 val;

	/* The main chrystal need to be enabled for reboot to work */
	val = readl(src_base + SRC_XTALCR);
	val &= ~SRC_XTALCR_MXTALOVER;
	val |= SRC_XTALCR_MXTALEN;
	pr_crit("force-enabling MXTALO\n");
	writel(val, src_base + SRC_XTALCR);
	return NOTIFY_OK;
}

static struct notifier_block nomadik_clk_reboot_notifier = {
	.notifier_call = nomadik_clk_reboot_handler,
};

static const struct of_device_id nomadik_src_match[] __initconst = {
	{ .compatible = "stericsson,nomadik-src" },
	{ /* sentinel */ }
};

static void __init nomadik_src_init(void)
{
	struct device_node *np;
	u32 val;

	np = of_find_matching_node(NULL, nomadik_src_match);
	if (!np) {
		pr_crit("no matching node for SRC, aborting clock init\n");
		return;
	}
	src_base = of_iomap(np, 0);
	if (!src_base) {
		pr_err("%s: must have src parent node with REGS (%pOFn)\n",
		       __func__, np);
		return;
	}

	/* Set all timers to use the 2.4 MHz TIMCLK */
	val = readl(src_base + SRC_CR);
	val |= SRC_CR_T0_ENSEL;
	val |= SRC_CR_T1_ENSEL;
	val |= SRC_CR_T2_ENSEL;
	val |= SRC_CR_T3_ENSEL;
	val |= SRC_CR_T4_ENSEL;
	val |= SRC_CR_T5_ENSEL;
	val |= SRC_CR_T6_ENSEL;
	val |= SRC_CR_T7_ENSEL;
	writel(val, src_base + SRC_CR);

	val = readl(src_base + SRC_XTALCR);
	pr_info("SXTALO is %s\n",
		(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
	pr_info("MXTAL is %s\n",
		(val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
	if (of_property_read_bool(np, "disable-sxtalo")) {
		/* The machine uses an external oscillator circuit */
		val |= SRC_XTALCR_SXTALDIS;
		pr_info("disabling SXTALO\n");
	}
	if (of_property_read_bool(np, "disable-mxtalo")) {
		/* Disable this too: also run by external oscillator */
		val |= SRC_XTALCR_MXTALOVER;
		val &= ~SRC_XTALCR_MXTALEN;
		pr_info("disabling MXTALO\n");
	}
	writel(val, src_base + SRC_XTALCR);
	register_reboot_notifier(&nomadik_clk_reboot_notifier);
}

/**
 * struct clk_pll1 - Nomadik PLL1 clock
 * @hw: corresponding clock hardware entry
 * @id: PLL instance: 1 or 2
 */
struct clk_pll {
	struct clk_hw hw;
	int id;
};

/**
 * struct clk_src - Nomadik src clock
 * @hw: corresponding clock hardware entry
 * @id: the clock ID
 * @group1: true if the clock is in group1, else it is in group0
 * @clkbit: bit 0...31 corresponding to the clock in each clock register
 */
struct clk_src {
	struct clk_hw hw;
	int id;
	bool group1;
	u32 clkbit;
};

#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
#define to_src(_hw) container_of(_hw, struct clk_src, hw)

static int pll_clk_enable(struct clk_hw *hw)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	spin_lock(&src_lock);
	val = readl(src_base + SRC_PLLCR);
	if (pll->id == 1) {
		if (val & SRC_PLLCR_PLL1OVER) {
			val |= SRC_PLLCR_PLL1EN;
			writel(val, src_base + SRC_PLLCR);
		}
	} else if (pll->id == 2) {
		val |= SRC_PLLCR_PLL2EN;
		writel(val, src_base + SRC_PLLCR);
	}
	spin_unlock(&src_lock);
	return 0;
}

static void pll_clk_disable(struct clk_hw *hw)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	spin_lock(&src_lock);
	val = readl(src_base + SRC_PLLCR);
	if (pll->id == 1) {
		if (val & SRC_PLLCR_PLL1OVER) {
			val &= ~SRC_PLLCR_PLL1EN;
			writel(val, src_base + SRC_PLLCR);
		}
	} else if (pll->id == 2) {
		val &= ~SRC_PLLCR_PLL2EN;
		writel(val, src_base + SRC_PLLCR);
	}
	spin_unlock(&src_lock);
}

static int pll_clk_is_enabled(struct clk_hw *hw)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	val = readl(src_base + SRC_PLLCR);
	if (pll->id == 1) {
		if (val & SRC_PLLCR_PLL1OVER)
			return !!(val & SRC_PLLCR_PLL1EN);
	} else if (pll->id == 2) {
		return !!(val & SRC_PLLCR_PLL2EN);
	}
	return 1;
}

static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	val = readl(src_base + SRC_PLLFR);

	if (pll->id == 1) {
		u8 mul;
		u8 div;

		mul = (val >> 8) & 0x3FU;
		mul += 2;
		div = val & 0x07U;
		return (parent_rate * mul) >> div;
	}

	if (pll->id == 2) {
		u8 mul;

		mul = (val >> 24) & 0x3FU;
		mul += 2;
		return (parent_rate * mul);
	}

	/* Unknown PLL */
	return 0;
}


static const struct clk_ops pll_clk_ops = {
	.enable = pll_clk_enable,
	.disable = pll_clk_disable,
	.is_enabled = pll_clk_is_enabled,
	.recalc_rate = pll_clk_recalc_rate,
};

static struct clk_hw * __init
pll_clk_register(struct device *dev, const char *name,
		 const char *parent_name, u32 id)
{
	int ret;
	struct clk_pll *pll;
	struct clk_init_data init;

	if (id != 1 && id != 2) {
		pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
		return ERR_PTR(-EINVAL);
	}

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &pll_clk_ops;
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);
	pll->hw.init = &init;
	pll->id = id;

	pr_debug("register PLL1 clock \"%s\"\n", name);

	ret = clk_hw_register(dev, &pll->hw);
	if (ret) {
		kfree(pll);
		return ERR_PTR(ret);
	}

	return &pll->hw;
}

/*
 * The Nomadik SRC clocks are gated, but not in the sense that
 * you read-modify-write a register. Instead there are separate
 * clock enable and clock disable registers. Writing a '1' bit in
 * the enable register for a certain clock ungates that clock without
 * affecting the other clocks. The disable register works the opposite
 * way.
 */

static int src_clk_enable(struct clk_hw *hw)
{
	struct clk_src *sclk = to_src(hw);
	u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;

	writel(sclk->clkbit, src_base + enreg);
	/* spin until enabled */
	while (!(readl(src_base + sreg) & sclk->clkbit))
		cpu_relax();
	return 0;
}

static void src_clk_disable(struct clk_hw *hw)
{
	struct clk_src *sclk = to_src(hw);
	u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;

	writel(sclk->clkbit, src_base + disreg);
	/* spin until disabled */
	while (readl(src_base + sreg) & sclk->clkbit)
		cpu_relax();
}

static int src_clk_is_enabled(struct clk_hw *hw)
{
	struct clk_src *sclk = to_src(hw);
	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	u32 val = readl(src_base + sreg);

	return !!(val & sclk->clkbit);
}

static unsigned long
src_clk_recalc_rate(struct clk_hw *hw,
		    unsigned long parent_rate)
{
	return parent_rate;
}

static const struct clk_ops src_clk_ops = {
	.enable = src_clk_enable,
	.disable = src_clk_disable,
	.is_enabled = src_clk_is_enabled,
	.recalc_rate = src_clk_recalc_rate,
};

static struct clk_hw * __init
src_clk_register(struct device *dev, const char *name,
		 const char *parent_name, u8 id)
{
	int ret;
	struct clk_src *sclk;
	struct clk_init_data init;

	sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
	if (!sclk)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &src_clk_ops;
	/* Do not force-disable the static SDRAM controller */
	if (id == 2)
		init.flags = CLK_IGNORE_UNUSED;
	else
		init.flags = 0;
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);
	sclk->hw.init = &init;
	sclk->id = id;
	sclk->group1 = (id > 31);
	sclk->clkbit = BIT(id & 0x1f);

	pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
		 name, id, sclk->group1, sclk->clkbit);

	ret = clk_hw_register(dev, &sclk->hw);
	if (ret) {
		kfree(sclk);
		return ERR_PTR(ret);
	}

	return &sclk->hw;
}

#ifdef CONFIG_DEBUG_FS

static u32 src_pcksr0_boot;
static u32 src_pcksr1_boot;

static const char * const src_clk_names[] = {
	"HCLKDMA0  ",
	"HCLKSMC   ",
	"HCLKSDRAM ",
	"HCLKDMA1  ",
	"HCLKCLCD  ",
	"PCLKIRDA  ",
	"PCLKSSP   ",
	"PCLKUART0 ",
	"PCLKSDI   ",
	"PCLKI2C0  ",
	"PCLKI2C1  ",
	"PCLKUART1 ",
	"PCLMSP0   ",
	"HCLKUSB   ",
	"HCLKDIF   ",
	"HCLKSAA   ",
	"HCLKSVA   ",
	"PCLKHSI   ",
	"PCLKXTI   ",
	"PCLKUART2 ",
	"PCLKMSP1  ",
	"PCLKMSP2  ",
	"PCLKOWM   ",
	"HCLKHPI   ",
	"PCLKSKE   ",
	"PCLKHSEM  ",
	"HCLK3D    ",
	"HCLKHASH  ",
	"HCLKCRYP  ",
	"PCLKMSHC  ",
	"HCLKUSBM  ",
	"HCLKRNG   ",
	"RESERVED  ",
	"RESERVED  ",
	"RESERVED  ",
	"RESERVED  ",
	"CLDCLK    ",
	"IRDACLK   ",
	"SSPICLK   ",
	"UART0CLK  ",
	"SDICLK    ",
	"I2C0CLK   ",
	"I2C1CLK   ",
	"UART1CLK  ",
	"MSPCLK0   ",
	"USBCLK    ",
	"DIFCLK    ",
	"IPI2CCLK  ",
	"IPBMCCLK  ",
	"HSICLKRX  ",
	"HSICLKTX  ",
	"UART2CLK  ",
	"MSPCLK1   ",
	"MSPCLK2   ",
	"OWMCLK    ",
	"RESERVED  ",
	"SKECLK    ",
	"RESERVED  ",
	"3DCLK     ",
	"PCLKMSP3  ",
	"MSPCLK3   ",
	"MSHCCLK   ",
	"USBMCLK   ",
	"RNGCCLK   ",
};

static int nomadik_src_clk_show(struct seq_file *s, void *what)
{
	int i;
	u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
	u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
	u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
	u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);

	seq_puts(s, "Clock:      Boot:   Now:    Request: ASKED:\n");
	for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
		u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
		u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
		u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
		u32 mask = BIT(i & 0x1f);

		seq_printf(s, "%s  %s     %s     %s\n",
			   src_clk_names[i],
			   (pcksrb & mask) ? "on " : "off",
			   (pcksr & mask) ? "on " : "off",
			   (pckreq & mask) ? "on " : "off");
	}
	return 0;
}

static int nomadik_src_clk_open(struct inode *inode, struct file *file)
{
	return single_open(file, nomadik_src_clk_show, NULL);
}

static const struct file_operations nomadik_src_clk_debugfs_ops = {
	.open           = nomadik_src_clk_open,
	.read           = seq_read,
        .llseek         = seq_lseek,
	.release        = single_release,
};

static int __init nomadik_src_clk_init_debugfs(void)
{
	/* Vital for multiplatform */
	if (!src_base)
		return -ENODEV;
	src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
	src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
	debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
			    NULL, NULL, &nomadik_src_clk_debugfs_ops);
	return 0;
}
device_initcall(nomadik_src_clk_init_debugfs);

#endif

static void __init of_nomadik_pll_setup(struct device_node *np)
{
	struct clk_hw *hw;
	const char *clk_name = np->name;
	const char *parent_name;
	u32 pll_id;

	if (!src_base)
		nomadik_src_init();

	if (of_property_read_u32(np, "pll-id", &pll_id)) {
		pr_err("%s: PLL \"%s\" missing pll-id property\n",
			__func__, clk_name);
		return;
	}
	parent_name = of_clk_get_parent_name(np, 0);
	hw = pll_clk_register(NULL, clk_name, parent_name, pll_id);
	if (!IS_ERR(hw))
		of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
}
CLK_OF_DECLARE(nomadik_pll_clk,
	"st,nomadik-pll-clock", of_nomadik_pll_setup);

static void __init of_nomadik_hclk_setup(struct device_node *np)
{
	struct clk_hw *hw;
	const char *clk_name = np->name;
	const char *parent_name;

	if (!src_base)
		nomadik_src_init();

	parent_name = of_clk_get_parent_name(np, 0);
	/*
	 * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
	 */
	hw = clk_hw_register_divider(NULL, clk_name, parent_name,
			   0, src_base + SRC_CR,
			   13, 2,
			   CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
			   &src_lock);
	if (!IS_ERR(hw))
		of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
}
CLK_OF_DECLARE(nomadik_hclk_clk,
	"st,nomadik-hclk-clock", of_nomadik_hclk_setup);

static void __init of_nomadik_src_clk_setup(struct device_node *np)
{
	struct clk_hw *hw;
	const char *clk_name = np->name;
	const char *parent_name;
	u32 clk_id;

	if (!src_base)
		nomadik_src_init();

	if (of_property_read_u32(np, "clock-id", &clk_id)) {
		pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
			__func__, clk_name);
		return;
	}
	parent_name = of_clk_get_parent_name(np, 0);
	hw = src_clk_register(NULL, clk_name, parent_name, clk_id);
	if (!IS_ERR(hw))
		of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
}
CLK_OF_DECLARE(nomadik_src_clk,
	"st,nomadik-src-clock", of_nomadik_src_clk_setup);
Commit	Line	Data
ef6eb322 LW	1	/*
	2	* Nomadik clock implementation
	3	* Copyright (C) 2013 ST-Ericsson AB
	4	* License terms: GNU General Public License (GPL) version 2
	5	* Author: Linus Walleij <[email protected]>
	6	*/
	7
	8	#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt
	9
	10	#include <linux/bitops.h>
aa1a7fc4	11	#include <linux/slab.h>
4a31bd28 LW	12	#include <linux/err.h>
	13	#include <linux/io.h>
	14	#include <linux/clk-provider.h>
6e2b07a1	15	#include <linux/of.h>
ef6eb322 LW	16	#include <linux/of_address.h>
	17	#include <linux/debugfs.h>
	18	#include <linux/seq_file.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/reboot.h>
4a31bd28 LW	21
	22	/*
	23	* The Nomadik clock tree is described in the STN8815A12 DB V4.2
	24	* reference manual for the chip, page 94 ff.
ef6eb322 LW	25	* Clock IDs are in the STn8815 Reference Manual table 3, page 27.
	26	*/
	27
	28	#define SRC_CR 0x00U
eb6b036d LW	29	#define SRC_CR_T0_ENSEL BIT(15)
	30	#define SRC_CR_T1_ENSEL BIT(17)
	31	#define SRC_CR_T2_ENSEL BIT(19)
	32	#define SRC_CR_T3_ENSEL BIT(21)
	33	#define SRC_CR_T4_ENSEL BIT(23)
	34	#define SRC_CR_T5_ENSEL BIT(25)
	35	#define SRC_CR_T6_ENSEL BIT(27)
	36	#define SRC_CR_T7_ENSEL BIT(29)
ef6eb322 LW	37	#define SRC_XTALCR 0x0CU
	38	#define SRC_XTALCR_XTALTIMEN BIT(20)
	39	#define SRC_XTALCR_SXTALDIS BIT(19)
	40	#define SRC_XTALCR_MXTALSTAT BIT(2)
	41	#define SRC_XTALCR_MXTALEN BIT(1)
	42	#define SRC_XTALCR_MXTALOVER BIT(0)
	43	#define SRC_PLLCR 0x10U
	44	#define SRC_PLLCR_PLLTIMEN BIT(29)
	45	#define SRC_PLLCR_PLL2EN BIT(28)
	46	#define SRC_PLLCR_PLL1STAT BIT(2)
	47	#define SRC_PLLCR_PLL1EN BIT(1)
	48	#define SRC_PLLCR_PLL1OVER BIT(0)
	49	#define SRC_PLLFR 0x14U
	50	#define SRC_PCKEN0 0x24U
	51	#define SRC_PCKDIS0 0x28U
	52	#define SRC_PCKENSR0 0x2CU
	53	#define SRC_PCKSR0 0x30U
	54	#define SRC_PCKEN1 0x34U
	55	#define SRC_PCKDIS1 0x38U
	56	#define SRC_PCKENSR1 0x3CU
	57	#define SRC_PCKSR1 0x40U
	58
	59	/* Lock protecting the SRC_CR register */
	60	static DEFINE_SPINLOCK(src_lock);
	61	/* Base address of the SRC */
	62	static void __iomem *src_base;
	63
ea25a900 SH	64	static int nomadik_clk_reboot_handler(struct notifier_block *this,
	65	unsigned long code,
	66	void *unused)
	67	{
	68	u32 val;
	69
	70	/* The main chrystal need to be enabled for reboot to work */
	71	val = readl(src_base + SRC_XTALCR);
	72	val &= ~SRC_XTALCR_MXTALOVER;
	73	val \|= SRC_XTALCR_MXTALEN;
	74	pr_crit("force-enabling MXTALO\n");
	75	writel(val, src_base + SRC_XTALCR);
	76	return NOTIFY_OK;
	77	}
	78
	79	static struct notifier_block nomadik_clk_reboot_notifier = {
	80	.notifier_call = nomadik_clk_reboot_handler,
	81	};
	82
	83	static const struct of_device_id nomadik_src_match[] __initconst = {
	84	{ .compatible = "stericsson,nomadik-src" },
	85	{ /* sentinel */ }
	86	};
	87
54bf93c4	88	static void __init nomadik_src_init(void)
ea25a900 SH	89	{
	90	struct device_node *np;
	91	u32 val;
	92
	93	np = of_find_matching_node(NULL, nomadik_src_match);
	94	if (!np) {
	95	pr_crit("no matching node for SRC, aborting clock init\n");
	96	return;
	97	}
	98	src_base = of_iomap(np, 0);
	99	if (!src_base) {
e665f029 RH	100	pr_err("%s: must have src parent node with REGS (%pOFn)\n",
e665f029 RH	101	__func__, np);
ea25a900 SH	102	return;
	103	}
	104
	105	/* Set all timers to use the 2.4 MHz TIMCLK */
	106	val = readl(src_base + SRC_CR);
	107	val \|= SRC_CR_T0_ENSEL;
	108	val \|= SRC_CR_T1_ENSEL;
	109	val \|= SRC_CR_T2_ENSEL;
	110	val \|= SRC_CR_T3_ENSEL;
	111	val \|= SRC_CR_T4_ENSEL;
	112	val \|= SRC_CR_T5_ENSEL;
	113	val \|= SRC_CR_T6_ENSEL;
	114	val \|= SRC_CR_T7_ENSEL;
	115	writel(val, src_base + SRC_CR);
	116
	117	val = readl(src_base + SRC_XTALCR);
	118	pr_info("SXTALO is %s\n",
	119	(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
	120	pr_info("MXTAL is %s\n",
	121	(val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
	122	if (of_property_read_bool(np, "disable-sxtalo")) {
	123	/* The machine uses an external oscillator circuit */
	124	val \|= SRC_XTALCR_SXTALDIS;
	125	pr_info("disabling SXTALO\n");
	126	}
	127	if (of_property_read_bool(np, "disable-mxtalo")) {
	128	/* Disable this too: also run by external oscillator */
	129	val \|= SRC_XTALCR_MXTALOVER;
	130	val &= ~SRC_XTALCR_MXTALEN;
	131	pr_info("disabling MXTALO\n");
	132	}
	133	writel(val, src_base + SRC_XTALCR);
	134	register_reboot_notifier(&nomadik_clk_reboot_notifier);
	135	}
	136
ef6eb322 LW	137	/**
	138	* struct clk_pll1 - Nomadik PLL1 clock
	139	* @hw: corresponding clock hardware entry
	140	* @id: PLL instance: 1 or 2
	141	*/
	142	struct clk_pll {
	143	struct clk_hw hw;
	144	int id;
	145	};
	146
	147	/**
	148	* struct clk_src - Nomadik src clock
	149	* @hw: corresponding clock hardware entry
	150	* @id: the clock ID
	151	* @group1: true if the clock is in group1, else it is in group0
	152	* @clkbit: bit 0...31 corresponding to the clock in each clock register
	153	*/
	154	struct clk_src {
	155	struct clk_hw hw;
	156	int id;
	157	bool group1;
	158	u32 clkbit;
	159	};
	160
	161	#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
	162	#define to_src(_hw) container_of(_hw, struct clk_src, hw)
	163
	164	static int pll_clk_enable(struct clk_hw *hw)
	165	{
	166	struct clk_pll *pll = to_pll(hw);
	167	u32 val;
	168
	169	spin_lock(&src_lock);
	170	val = readl(src_base + SRC_PLLCR);
	171	if (pll->id == 1) {
	172	if (val & SRC_PLLCR_PLL1OVER) {
	173	val \|= SRC_PLLCR_PLL1EN;
	174	writel(val, src_base + SRC_PLLCR);
	175	}
	176	} else if (pll->id == 2) {
	177	val \|= SRC_PLLCR_PLL2EN;
	178	writel(val, src_base + SRC_PLLCR);
	179	}
	180	spin_unlock(&src_lock);
	181	return 0;
	182	}
	183
	184	static void pll_clk_disable(struct clk_hw *hw)
	185	{
	186	struct clk_pll *pll = to_pll(hw);
	187	u32 val;
	188
	189	spin_lock(&src_lock);
	190	val = readl(src_base + SRC_PLLCR);
	191	if (pll->id == 1) {
	192	if (val & SRC_PLLCR_PLL1OVER) {
	193	val &= ~SRC_PLLCR_PLL1EN;
	194	writel(val, src_base + SRC_PLLCR);
	195	}
	196	} else if (pll->id == 2) {
	197	val &= ~SRC_PLLCR_PLL2EN;
	198	writel(val, src_base + SRC_PLLCR);
	199	}
	200	spin_unlock(&src_lock);
201	}
202
203	static int pll_clk_is_enabled(struct clk_hw *hw)
204	{
205	struct clk_pll *pll = to_pll(hw);
206	u32 val;
207
208	val = readl(src_base + SRC_PLLCR);
209	if (pll->id == 1) {
210	if (val & SRC_PLLCR_PLL1OVER)
211	return !!(val & SRC_PLLCR_PLL1EN);
212	} else if (pll->id == 2) {
213	return !!(val & SRC_PLLCR_PLL2EN);
214	}
215	return 1;
216	}
217
218	static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
219	unsigned long parent_rate)
220	{
221	struct clk_pll *pll = to_pll(hw);
222	u32 val;
223
224	val = readl(src_base + SRC_PLLFR);
225
226	if (pll->id == 1) {
227	u8 mul;
228	u8 div;
229
230	mul = (val >> 8) & 0x3FU;
231	mul += 2;
232	div = val & 0x07U;
233	return (parent_rate * mul) >> div;
234	}
235
236	if (pll->id == 2) {
237	u8 mul;
238
239	mul = (val >> 24) & 0x3FU;
240	mul += 2;
241	return (parent_rate * mul);
242	}
243
244	/* Unknown PLL */
245	return 0;
246	}
247
248
249	static const struct clk_ops pll_clk_ops = {
250	.enable = pll_clk_enable,
251	.disable = pll_clk_disable,
252	.is_enabled = pll_clk_is_enabled,
253	.recalc_rate = pll_clk_recalc_rate,
254	};
255
7b38d1b2	256	static struct clk_hw * __init
ef6eb322 LW	257	pll_clk_register(struct device dev, const char name,
	258	const char *parent_name, u32 id)
	259	{
7b38d1b2	260	int ret;
ef6eb322 LW	261	struct clk_pll *pll;
	262	struct clk_init_data init;
	263
	264	if (id != 1 && id != 2) {
	265	pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
	266	return ERR_PTR(-EINVAL);
	267	}
	268
	269	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
24f8186e	270	if (!pll)
ef6eb322	271	return ERR_PTR(-ENOMEM);
ef6eb322 LW	272
	273	init.name = name;
	274	init.ops = &pll_clk_ops;
	275	init.parent_names = (parent_name ? &parent_name : NULL);
	276	init.num_parents = (parent_name ? 1 : 0);
	277	pll->hw.init = &init;
	278	pll->id = id;
	279
	280	pr_debug("register PLL1 clock \"%s\"\n", name);
	281
7b38d1b2 SB	282	ret = clk_hw_register(dev, &pll->hw);
7b38d1b2 SB	283	if (ret) {
ef6eb322	284	kfree(pll);
7b38d1b2 SB	285	return ERR_PTR(ret);
7b38d1b2 SB	286	}
ef6eb322	287
7b38d1b2	288	return &pll->hw;
ef6eb322 LW	289	}
	290
	291	/*
	292	* The Nomadik SRC clocks are gated, but not in the sense that
	293	* you read-modify-write a register. Instead there are separate
	294	* clock enable and clock disable registers. Writing a '1' bit in
	295	* the enable register for a certain clock ungates that clock without
	296	* affecting the other clocks. The disable register works the opposite
	297	* way.
4a31bd28 LW	298	*/
4a31bd28 LW	299
ef6eb322 LW	300	static int src_clk_enable(struct clk_hw *hw)
	301	{
	302	struct clk_src *sclk = to_src(hw);
	303	u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
	304	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	305
	306	writel(sclk->clkbit, src_base + enreg);
	307	/* spin until enabled */
	308	while (!(readl(src_base + sreg) & sclk->clkbit))
	309	cpu_relax();
	310	return 0;
	311	}
	312
	313	static void src_clk_disable(struct clk_hw *hw)
	314	{
	315	struct clk_src *sclk = to_src(hw);
	316	u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
	317	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	318
	319	writel(sclk->clkbit, src_base + disreg);
	320	/* spin until disabled */
	321	while (readl(src_base + sreg) & sclk->clkbit)
	322	cpu_relax();
	323	}
	324
	325	static int src_clk_is_enabled(struct clk_hw *hw)
	326	{
	327	struct clk_src *sclk = to_src(hw);
	328	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	329	u32 val = readl(src_base + sreg);
	330
	331	return !!(val & sclk->clkbit);
	332	}
	333
	334	static unsigned long
	335	src_clk_recalc_rate(struct clk_hw *hw,
	336	unsigned long parent_rate)
	337	{
	338	return parent_rate;
	339	}
	340
	341	static const struct clk_ops src_clk_ops = {
	342	.enable = src_clk_enable,
	343	.disable = src_clk_disable,
	344	.is_enabled = src_clk_is_enabled,
	345	.recalc_rate = src_clk_recalc_rate,
	346	};
	347
7b38d1b2	348	static struct clk_hw * __init
ef6eb322 LW	349	src_clk_register(struct device dev, const char name,
	350	const char *parent_name, u8 id)
	351	{
7b38d1b2	352	int ret;
ef6eb322 LW	353	struct clk_src *sclk;
	354	struct clk_init_data init;
	355
	356	sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
24f8186e	357	if (!sclk)
ef6eb322	358	return ERR_PTR(-ENOMEM);
24f8186e	359
ef6eb322 LW	360	init.name = name;
	361	init.ops = &src_clk_ops;
	362	/* Do not force-disable the static SDRAM controller */
	363	if (id == 2)
	364	init.flags = CLK_IGNORE_UNUSED;
	365	else
	366	init.flags = 0;
	367	init.parent_names = (parent_name ? &parent_name : NULL);
	368	init.num_parents = (parent_name ? 1 : 0);
	369	sclk->hw.init = &init;
	370	sclk->id = id;
	371	sclk->group1 = (id > 31);
	372	sclk->clkbit = BIT(id & 0x1f);
	373
	374	pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
	375	name, id, sclk->group1, sclk->clkbit);
	376
7b38d1b2 SB	377	ret = clk_hw_register(dev, &sclk->hw);
7b38d1b2 SB	378	if (ret) {
ef6eb322	379	kfree(sclk);
7b38d1b2 SB	380	return ERR_PTR(ret);
7b38d1b2 SB	381	}
ef6eb322	382
7b38d1b2	383	return &sclk->hw;
ef6eb322 LW	384	}
	385
	386	#ifdef CONFIG_DEBUG_FS
	387
	388	static u32 src_pcksr0_boot;
	389	static u32 src_pcksr1_boot;
	390
	391	static const char * const src_clk_names[] = {
	392	"HCLKDMA0 ",
	393	"HCLKSMC ",
	394	"HCLKSDRAM ",
	395	"HCLKDMA1 ",
	396	"HCLKCLCD ",
	397	"PCLKIRDA ",
	398	"PCLKSSP ",
	399	"PCLKUART0 ",
	400	"PCLKSDI ",
	401	"PCLKI2C0 ",
	402	"PCLKI2C1 ",
	403	"PCLKUART1 ",
	404	"PCLMSP0 ",
	405	"HCLKUSB ",
	406	"HCLKDIF ",
	407	"HCLKSAA ",
	408	"HCLKSVA ",
	409	"PCLKHSI ",
	410	"PCLKXTI ",
	411	"PCLKUART2 ",
	412	"PCLKMSP1 ",
	413	"PCLKMSP2 ",
	414	"PCLKOWM ",
	415	"HCLKHPI ",
	416	"PCLKSKE ",
	417	"PCLKHSEM ",
	418	"HCLK3D ",
	419	"HCLKHASH ",
	420	"HCLKCRYP ",
	421	"PCLKMSHC ",
	422	"HCLKUSBM ",
	423	"HCLKRNG ",
	424	"RESERVED ",
	425	"RESERVED ",
	426	"RESERVED ",
	427	"RESERVED ",
	428	"CLDCLK ",
	429	"IRDACLK ",
	430	"SSPICLK ",
	431	"UART0CLK ",
	432	"SDICLK ",
	433	"I2C0CLK ",
	434	"I2C1CLK ",
	435	"UART1CLK ",
	436	"MSPCLK0 ",
	437	"USBCLK ",
	438	"DIFCLK ",
	439	"IPI2CCLK ",
	440	"IPBMCCLK ",
	441	"HSICLKRX ",
	442	"HSICLKTX ",
	443	"UART2CLK ",
	444	"MSPCLK1 ",
	445	"MSPCLK2 ",
	446	"OWMCLK ",
	447	"RESERVED ",
448	"SKECLK ",
449	"RESERVED ",
450	"3DCLK ",
451	"PCLKMSP3 ",
452	"MSPCLK3 ",
453	"MSHCCLK ",
454	"USBMCLK ",
455	"RNGCCLK ",
456	};
457
458	static int nomadik_src_clk_show(struct seq_file s, void what)
459	{
460	int i;
461	u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
462	u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
463	u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
464	u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);
465
add31511	466	seq_puts(s, "Clock: Boot: Now: Request: ASKED:\n");
ef6eb322 LW	467	for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
	468	u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
	469	u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
	470	u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
	471	u32 mask = BIT(i & 0x1f);
	472
	473	seq_printf(s, "%s %s %s %s\n",
	474	src_clk_names[i],
	475	(pcksrb & mask) ? "on " : "off",
	476	(pcksr & mask) ? "on " : "off",
	477	(pckreq & mask) ? "on " : "off");
	478	}
	479	return 0;
	480	}
	481
	482	static int nomadik_src_clk_open(struct inode inode, struct file file)
	483	{
	484	return single_open(file, nomadik_src_clk_show, NULL);
	485	}
	486
	487	static const struct file_operations nomadik_src_clk_debugfs_ops = {
	488	.open = nomadik_src_clk_open,
	489	.read = seq_read,
	490	.llseek = seq_lseek,
	491	.release = single_release,
	492	};
	493
	494	static int __init nomadik_src_clk_init_debugfs(void)
	495	{
ec6deea1 LW	496	/* Vital for multiplatform */
	497	if (!src_base)
	498	return -ENODEV;
ef6eb322 LW	499	src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
	500	src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
	501	debugfs_create_file("nomadik-src-clk", S_IFREG \| S_IRUGO,
	502	NULL, NULL, &nomadik_src_clk_debugfs_ops);
	503	return 0;
	504	}
791ed0bb	505	device_initcall(nomadik_src_clk_init_debugfs);
ef6eb322 LW	506
	507	#endif
	508
	509	static void __init of_nomadik_pll_setup(struct device_node *np)
	510	{
7b38d1b2	511	struct clk_hw *hw;
ef6eb322 LW	512	const char *clk_name = np->name;
	513	const char *parent_name;
	514	u32 pll_id;
	515
74227e65 SH	516	if (!src_base)
	517	nomadik_src_init();
	518
ef6eb322 LW	519	if (of_property_read_u32(np, "pll-id", &pll_id)) {
	520	pr_err("%s: PLL \"%s\" missing pll-id property\n",
	521	__func__, clk_name);
	522	return;
	523	}
	524	parent_name = of_clk_get_parent_name(np, 0);
7b38d1b2 SB	525	hw = pll_clk_register(NULL, clk_name, parent_name, pll_id);
	526	if (!IS_ERR(hw))
	527	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
ef6eb322	528	}
74227e65 SH	529	CLK_OF_DECLARE(nomadik_pll_clk,
74227e65 SH	530	"st,nomadik-pll-clock", of_nomadik_pll_setup);
ef6eb322 LW	531
	532	static void __init of_nomadik_hclk_setup(struct device_node *np)
	533	{
7b38d1b2	534	struct clk_hw *hw;
ef6eb322 LW	535	const char *clk_name = np->name;
	536	const char *parent_name;
	537
74227e65 SH	538	if (!src_base)
	539	nomadik_src_init();
	540
ef6eb322 LW	541	parent_name = of_clk_get_parent_name(np, 0);
	542	/*
	543	* The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
	544	*/
7b38d1b2	545	hw = clk_hw_register_divider(NULL, clk_name, parent_name,
ef6eb322 LW	546	0, src_base + SRC_CR,
	547	13, 2,
	548	CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO,
	549	&src_lock);
7b38d1b2 SB	550	if (!IS_ERR(hw))
7b38d1b2 SB	551	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
ef6eb322	552	}
74227e65 SH	553	CLK_OF_DECLARE(nomadik_hclk_clk,
74227e65 SH	554	"st,nomadik-hclk-clock", of_nomadik_hclk_setup);
ef6eb322 LW	555
	556	static void __init of_nomadik_src_clk_setup(struct device_node *np)
	557	{
7b38d1b2	558	struct clk_hw *hw;
ef6eb322 LW	559	const char *clk_name = np->name;
	560	const char *parent_name;
	561	u32 clk_id;
	562
74227e65 SH	563	if (!src_base)
	564	nomadik_src_init();
	565
ef6eb322 LW	566	if (of_property_read_u32(np, "clock-id", &clk_id)) {
	567	pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
	568	__func__, clk_name);
	569	return;
	570	}
	571	parent_name = of_clk_get_parent_name(np, 0);
7b38d1b2 SB	572	hw = src_clk_register(NULL, clk_name, parent_name, clk_id);
	573	if (!IS_ERR(hw))
	574	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
ef6eb322	575	}
74227e65 SH	576	CLK_OF_DECLARE(nomadik_src_clk,
74227e65 SH	577	"st,nomadik-src-clock", of_nomadik_src_clk_setup);