[linux.git] / drivers / clk / clk-max9485.c

// SPDX-License-Identifier: GPL-2.0

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/regulator/consumer.h>

#include <dt-bindings/clock/maxim,max9485.h>

#define MAX9485_NUM_CLKS 4

/* This chip has only one register of 8 bit width. */

#define MAX9485_FS_12KHZ	(0 << 0)
#define MAX9485_FS_32KHZ	(1 << 0)
#define MAX9485_FS_44_1KHZ	(2 << 0)
#define MAX9485_FS_48KHZ	(3 << 0)

#define MAX9485_SCALE_256	(0 << 2)
#define MAX9485_SCALE_384	(1 << 2)
#define MAX9485_SCALE_768	(2 << 2)

#define MAX9485_DOUBLE		BIT(4)
#define MAX9485_CLKOUT1_ENABLE	BIT(5)
#define MAX9485_CLKOUT2_ENABLE	BIT(6)
#define MAX9485_MCLK_ENABLE	BIT(7)
#define MAX9485_FREQ_MASK	0x1f

struct max9485_rate {
	unsigned long out;
	u8 reg_value;
};

/*
 * Ordered by frequency. For frequency the hardware can generate with
 * multiple settings, the one with lowest jitter is listed first.
 */
static const struct max9485_rate max9485_rates[] = {
	{  3072000, MAX9485_FS_12KHZ   | MAX9485_SCALE_256 },
	{  4608000, MAX9485_FS_12KHZ   | MAX9485_SCALE_384 },
	{  8192000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 },
	{  9126000, MAX9485_FS_12KHZ   | MAX9485_SCALE_768 },
	{ 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },
	{ 12288000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 },
	{ 12288000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 },
	{ 16384000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
	{ 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },
	{ 18384000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 },
	{ 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
	{ 24576000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
	{ 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
	{ 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 },
	{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
	{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },
	{ 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
	{ 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 },
	{ 49152000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
	{ 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
	{ 73728000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
	{ } /* sentinel */
};

struct max9485_driver_data;

struct max9485_clk_hw {
	struct clk_hw hw;
	struct clk_init_data init;
	u8 enable_bit;
	struct max9485_driver_data *drvdata;
};

struct max9485_driver_data {
	struct clk *xclk;
	struct i2c_client *client;
	u8 reg_value;
	struct regulator *supply;
	struct gpio_desc *reset_gpio;
	struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
};

static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)
{
	return container_of(hw, struct max9485_clk_hw, hw);
}

static int max9485_update_bits(struct max9485_driver_data *drvdata,
			       u8 mask, u8 value)
{
	int ret;

	drvdata->reg_value &= ~mask;
	drvdata->reg_value |= value;

	dev_dbg(&drvdata->client->dev,
		"updating mask 0x%02x value 0x%02x -> 0x%02x\n",
		mask, value, drvdata->reg_value);

	ret = i2c_master_send(drvdata->client,
			      &drvdata->reg_value,
			      sizeof(drvdata->reg_value));

	return ret < 0 ? ret : 0;
}

static int max9485_clk_prepare(struct clk_hw *hw)
{
	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);

	return max9485_update_bits(clk_hw->drvdata,
				   clk_hw->enable_bit,
				   clk_hw->enable_bit);
}

static void max9485_clk_unprepare(struct clk_hw *hw)
{
	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);

	max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);
}

/*
 * CLKOUT - configurable clock output
 */
static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{
	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
	const struct max9485_rate *entry;

	for (entry = max9485_rates; entry->out != 0; entry++)
		if (entry->out == rate)
			break;

	if (entry->out == 0)
		return -EINVAL;

	return max9485_update_bits(clk_hw->drvdata,
				   MAX9485_FREQ_MASK,
				   entry->reg_value);
}

static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
	struct max9485_driver_data *drvdata = clk_hw->drvdata;
	u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
	const struct max9485_rate *entry;

	for (entry = max9485_rates; entry->out != 0; entry++)
		if (val == entry->reg_value)
			return entry->out;

	return 0;
}

static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long *parent_rate)
{
	const struct max9485_rate *curr, *prev = NULL;

	for (curr = max9485_rates; curr->out != 0; curr++) {
		/* Exact matches */
		if (curr->out == rate)
			return rate;

		/*
		 * Find the first entry that has a frequency higher than the
		 * requested one.
		 */
		if (curr->out > rate) {
			unsigned int mid;

			/*
			 * If this is the first entry, clamp the value to the
			 * lowest possible frequency.
			 */
			if (!prev)
				return curr->out;

			/*
			 * Otherwise, determine whether the previous entry or
			 * current one is closer.
			 */
			mid = prev->out + ((curr->out - prev->out) / 2);

			return (mid > rate) ? prev->out : curr->out;
		}

		prev = curr;
	}

	/* If the last entry was still too high, clamp the value */
	return prev->out;
}

struct max9485_clk {
	const char *name;
	int parent_index;
	const struct clk_ops ops;
	u8 enable_bit;
};

static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {
	[MAX9485_MCLKOUT] = {
		.name = "mclkout",
		.parent_index = -1,
		.enable_bit = MAX9485_MCLK_ENABLE,
		.ops = {
			.prepare	= max9485_clk_prepare,
			.unprepare	= max9485_clk_unprepare,
		},
	},
	[MAX9485_CLKOUT] = {
		.name = "clkout",
		.parent_index = -1,
		.ops = {
			.set_rate	= max9485_clkout_set_rate,
			.round_rate	= max9485_clkout_round_rate,
			.recalc_rate	= max9485_clkout_recalc_rate,
		},
	},
	[MAX9485_CLKOUT1] = {
		.name = "clkout1",
		.parent_index = MAX9485_CLKOUT,
		.enable_bit = MAX9485_CLKOUT1_ENABLE,
		.ops = {
			.prepare	= max9485_clk_prepare,
			.unprepare	= max9485_clk_unprepare,
		},
	},
	[MAX9485_CLKOUT2] = {
		.name = "clkout2",
		.parent_index = MAX9485_CLKOUT,
		.enable_bit = MAX9485_CLKOUT2_ENABLE,
		.ops = {
			.prepare	= max9485_clk_prepare,
			.unprepare	= max9485_clk_unprepare,
		},
	},
};

static struct clk_hw *
max9485_of_clk_get(struct of_phandle_args *clkspec, void *data)
{
	struct max9485_driver_data *drvdata = data;
	unsigned int idx = clkspec->args[0];

	return &drvdata->hw[idx].hw;
}

static int max9485_i2c_probe(struct i2c_client *client,
			     const struct i2c_device_id *id)
{
	struct max9485_driver_data *drvdata;
	struct device *dev = &client->dev;
	const char *xclk_name;
	int i, ret;

	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;

	drvdata->xclk = devm_clk_get(dev, "xclk");
	if (IS_ERR(drvdata->xclk))
		return PTR_ERR(drvdata->xclk);

	xclk_name = __clk_get_name(drvdata->xclk);

	drvdata->supply = devm_regulator_get(dev, "vdd");
	if (IS_ERR(drvdata->supply))
		return PTR_ERR(drvdata->supply);

	ret = regulator_enable(drvdata->supply);
	if (ret < 0)
		return ret;

	drvdata->reset_gpio =
		devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
	if (IS_ERR(drvdata->reset_gpio))
		return PTR_ERR(drvdata->reset_gpio);

	i2c_set_clientdata(client, drvdata);
	drvdata->client = client;

	ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,
			      sizeof(drvdata->reg_value));
	if (ret < 0) {
		dev_warn(dev, "Unable to read device register: %d\n", ret);
		return ret;
	}

	for (i = 0; i < MAX9485_NUM_CLKS; i++) {
		int parent_index = max9485_clks[i].parent_index;
		const char *name;

		if (of_property_read_string_index(dev->of_node,
						  "clock-output-names",
						  i, &name) == 0) {
			drvdata->hw[i].init.name = name;
		} else {
			drvdata->hw[i].init.name = max9485_clks[i].name;
		}

		drvdata->hw[i].init.ops = &max9485_clks[i].ops;
		drvdata->hw[i].init.num_parents = 1;
		drvdata->hw[i].init.flags = 0;

		if (parent_index > 0) {
			drvdata->hw[i].init.parent_names =
				&drvdata->hw[parent_index].init.name;
			drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT;
		} else {
			drvdata->hw[i].init.parent_names = &xclk_name;
		}

		drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
		drvdata->hw[i].hw.init = &drvdata->hw[i].init;
		drvdata->hw[i].drvdata = drvdata;

		ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw);
		if (ret < 0)
			return ret;
	}

	return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata);
}

static int __maybe_unused max9485_suspend(struct device *dev)
{
	struct i2c_client *client = to_i2c_client(dev);
	struct max9485_driver_data *drvdata = i2c_get_clientdata(client);

	gpiod_set_value_cansleep(drvdata->reset_gpio, 0);

	return 0;
}

static int __maybe_unused max9485_resume(struct device *dev)
{
	struct i2c_client *client = to_i2c_client(dev);
	struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
	int ret;

	gpiod_set_value_cansleep(drvdata->reset_gpio, 1);

	ret = i2c_master_send(client, &drvdata->reg_value,
			      sizeof(drvdata->reg_value));

	return ret < 0 ? ret : 0;
}

static const struct dev_pm_ops max9485_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)
};

static const struct of_device_id max9485_dt_ids[] = {
	{ .compatible = "maxim,max9485", },
	{ }
};
MODULE_DEVICE_TABLE(of, max9485_dt_ids);

static const struct i2c_device_id max9485_i2c_ids[] = {
	{ .name = "max9485", },
	{ }
};
MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);

static struct i2c_driver max9485_driver = {
	.driver = {
		.name		= "max9485",
		.pm		= &max9485_pm_ops,
		.of_match_table	= max9485_dt_ids,
	},
	.probe = max9485_i2c_probe,
	.id_table = max9485_i2c_ids,
};
module_i2c_driver(max9485_driver);

MODULE_AUTHOR("Daniel Mack <[email protected]>");
MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
33f51046 DM	1	// SPDX-License-Identifier: GPL-2.0
	2
	3	#include <linux/module.h>
	4	#include <linux/kernel.h>
	5	#include <linux/clk.h>
	6	#include <linux/clk-provider.h>
	7	#include <linux/err.h>
	8	#include <linux/errno.h>
	9	#include <linux/gpio/consumer.h>
	10	#include <linux/i2c.h>
	11	#include <linux/regulator/consumer.h>
	12
	13	#include <dt-bindings/clock/maxim,max9485.h>
	14
	15	#define MAX9485_NUM_CLKS 4
	16
	17	/* This chip has only one register of 8 bit width. */
	18
	19	#define MAX9485_FS_12KHZ (0 << 0)
	20	#define MAX9485_FS_32KHZ (1 << 0)
	21	#define MAX9485_FS_44_1KHZ (2 << 0)
	22	#define MAX9485_FS_48KHZ (3 << 0)
	23
	24	#define MAX9485_SCALE_256 (0 << 2)
	25	#define MAX9485_SCALE_384 (1 << 2)
	26	#define MAX9485_SCALE_768 (2 << 2)
	27
	28	#define MAX9485_DOUBLE BIT(4)
	29	#define MAX9485_CLKOUT1_ENABLE BIT(5)
	30	#define MAX9485_CLKOUT2_ENABLE BIT(6)
	31	#define MAX9485_MCLK_ENABLE BIT(7)
	32	#define MAX9485_FREQ_MASK 0x1f
	33
	34	struct max9485_rate {
	35	unsigned long out;
	36	u8 reg_value;
	37	};
	38
	39	/*
	40	* Ordered by frequency. For frequency the hardware can generate with
	41	* multiple settings, the one with lowest jitter is listed first.
	42	*/
	43	static const struct max9485_rate max9485_rates[] = {
	44	{ 3072000, MAX9485_FS_12KHZ \| MAX9485_SCALE_256 },
	45	{ 4608000, MAX9485_FS_12KHZ \| MAX9485_SCALE_384 },
	46	{ 8192000, MAX9485_FS_32KHZ \| MAX9485_SCALE_256 },
	47	{ 9126000, MAX9485_FS_12KHZ \| MAX9485_SCALE_768 },
	48	{ 11289600, MAX9485_FS_44_1KHZ \| MAX9485_SCALE_256 },
	49	{ 12288000, MAX9485_FS_48KHZ \| MAX9485_SCALE_256 },
	50	{ 12288000, MAX9485_FS_32KHZ \| MAX9485_SCALE_384 },
	51	{ 16384000, MAX9485_FS_32KHZ \| MAX9485_SCALE_256 \| MAX9485_DOUBLE },
	52	{ 16934400, MAX9485_FS_44_1KHZ \| MAX9485_SCALE_384 },
	53	{ 18384000, MAX9485_FS_48KHZ \| MAX9485_SCALE_384 },
	54	{ 22579200, MAX9485_FS_44_1KHZ \| MAX9485_SCALE_256 \| MAX9485_DOUBLE },
	55	{ 24576000, MAX9485_FS_48KHZ \| MAX9485_SCALE_256 \| MAX9485_DOUBLE },
	56	{ 24576000, MAX9485_FS_32KHZ \| MAX9485_SCALE_384 \| MAX9485_DOUBLE },
	57	{ 24576000, MAX9485_FS_32KHZ \| MAX9485_SCALE_768 },
	58	{ 33868800, MAX9485_FS_44_1KHZ \| MAX9485_SCALE_384 \| MAX9485_DOUBLE },
	59	{ 33868800, MAX9485_FS_44_1KHZ \| MAX9485_SCALE_768 },
	60	{ 36864000, MAX9485_FS_48KHZ \| MAX9485_SCALE_384 \| MAX9485_DOUBLE },
	61	{ 36864000, MAX9485_FS_48KHZ \| MAX9485_SCALE_768 },
	62	{ 49152000, MAX9485_FS_32KHZ \| MAX9485_SCALE_768 \| MAX9485_DOUBLE },
	63	{ 67737600, MAX9485_FS_44_1KHZ \| MAX9485_SCALE_768 \| MAX9485_DOUBLE },
	64	{ 73728000, MAX9485_FS_48KHZ \| MAX9485_SCALE_768 \| MAX9485_DOUBLE },
65	{ } /* sentinel */
66	};
67
68	struct max9485_driver_data;
69
70	struct max9485_clk_hw {
71	struct clk_hw hw;
72	struct clk_init_data init;
73	u8 enable_bit;
74	struct max9485_driver_data *drvdata;
75	};
76
77	struct max9485_driver_data {
78	struct clk *xclk;
79	struct i2c_client *client;
80	u8 reg_value;
81	struct regulator *supply;
82	struct gpio_desc *reset_gpio;
83	struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
84	};
85
86	static inline struct max9485_clk_hw to_max9485_clk(struct clk_hw hw)
87	{
88	return container_of(hw, struct max9485_clk_hw, hw);
89	}
90
91	static int max9485_update_bits(struct max9485_driver_data *drvdata,
92	u8 mask, u8 value)
93	{
94	int ret;
95
96	drvdata->reg_value &= ~mask;
97	drvdata->reg_value \|= value;
98
99	dev_dbg(&drvdata->client->dev,
100	"updating mask 0x%02x value 0x%02x -> 0x%02x\n",
101	mask, value, drvdata->reg_value);
102
103	ret = i2c_master_send(drvdata->client,
104	&drvdata->reg_value,
105	sizeof(drvdata->reg_value));
106
107	return ret < 0 ? ret : 0;
108	}
109
110	static int max9485_clk_prepare(struct clk_hw *hw)
111	{
112	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
113
114	return max9485_update_bits(clk_hw->drvdata,
115	clk_hw->enable_bit,
116	clk_hw->enable_bit);
117	}
118
119	static void max9485_clk_unprepare(struct clk_hw *hw)
120	{
121	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
122
123	max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);
124	}
125
126	/*
127	* CLKOUT - configurable clock output
128	*/
129	static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
130	unsigned long parent_rate)
131	{
132	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
133	const struct max9485_rate *entry;
134
135	for (entry = max9485_rates; entry->out != 0; entry++)
136	if (entry->out == rate)
137	break;
138
139	if (entry->out == 0)
140	return -EINVAL;
141
142	return max9485_update_bits(clk_hw->drvdata,
143	MAX9485_FREQ_MASK,
144	entry->reg_value);
145	}
146
147	static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,
148	unsigned long parent_rate)
149	{
150	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
151	struct max9485_driver_data *drvdata = clk_hw->drvdata;
152	u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
153	const struct max9485_rate *entry;
154
155	for (entry = max9485_rates; entry->out != 0; entry++)
156	if (val == entry->reg_value)
157	return entry->out;
158
159	return 0;
160	}
161
162	static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
163	unsigned long *parent_rate)
164	{
165	const struct max9485_rate curr, prev = NULL;
166
167	for (curr = max9485_rates; curr->out != 0; curr++) {
168	/* Exact matches */
169	if (curr->out == rate)
170	return rate;
171
172	/*
173	* Find the first entry that has a frequency higher than the
174	* requested one.
175	*/
176	if (curr->out > rate) {
177	unsigned int mid;
178
179	/*
180	* If this is the first entry, clamp the value to the
181	* lowest possible frequency.
182	*/
183	if (!prev)
184	return curr->out;
185
186	/*
187	* Otherwise, determine whether the previous entry or
188	* current one is closer.
189	*/
190	mid = prev->out + ((curr->out - prev->out) / 2);
191
192	return (mid > rate) ? prev->out : curr->out;
193	}
194
195	prev = curr;
196	}
197
198	/* If the last entry was still too high, clamp the value */
199	return prev->out;
200	}
201
202	struct max9485_clk {
203	const char *name;
204	int parent_index;
205	const struct clk_ops ops;
206	u8 enable_bit;
207	};
208
209	static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {
210	[MAX9485_MCLKOUT] = {
211	.name = "mclkout",
212	.parent_index = -1,
213	.enable_bit = MAX9485_MCLK_ENABLE,
214	.ops = {
215	.prepare = max9485_clk_prepare,
216	.unprepare = max9485_clk_unprepare,
217	},
218	},
219	[MAX9485_CLKOUT] = {
220	.name = "clkout",
221	.parent_index = -1,
222	.ops = {
223	.set_rate = max9485_clkout_set_rate,
224	.round_rate = max9485_clkout_round_rate,
225	.recalc_rate = max9485_clkout_recalc_rate,
226	},
227	},
228	[MAX9485_CLKOUT1] = {
229	.name = "clkout1",
230	.parent_index = MAX9485_CLKOUT,
231	.enable_bit = MAX9485_CLKOUT1_ENABLE,
232	.ops = {
233	.prepare = max9485_clk_prepare,
234	.unprepare = max9485_clk_unprepare,
235	},
236	},
237	[MAX9485_CLKOUT2] = {
238	.name = "clkout2",
239	.parent_index = MAX9485_CLKOUT,
240	.enable_bit = MAX9485_CLKOUT2_ENABLE,
241	.ops = {
242	.prepare = max9485_clk_prepare,
243	.unprepare = max9485_clk_unprepare,
244	},
245	},
246	};
247
248	static struct clk_hw *
249	max9485_of_clk_get(struct of_phandle_args clkspec, void data)
250	{
251	struct max9485_driver_data *drvdata = data;
252	unsigned int idx = clkspec->args[0];
253
254	return &drvdata->hw[idx].hw;
255	}
256
257	static int max9485_i2c_probe(struct i2c_client *client,
258	const struct i2c_device_id *id)
259	{
260	struct max9485_driver_data *drvdata;
261	struct device *dev = &client->dev;
262	const char *xclk_name;
263	int i, ret;
264
265	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
266	if (!drvdata)
267	return -ENOMEM;
268
269	drvdata->xclk = devm_clk_get(dev, "xclk");
270	if (IS_ERR(drvdata->xclk))
271	return PTR_ERR(drvdata->xclk);
272
273	xclk_name = __clk_get_name(drvdata->xclk);
274
275	drvdata->supply = devm_regulator_get(dev, "vdd");
276	if (IS_ERR(drvdata->supply))
277	return PTR_ERR(drvdata->supply);
278
279	ret = regulator_enable(drvdata->supply);
280	if (ret < 0)
281	return ret;
282
283	drvdata->reset_gpio =
284	devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
285	if (IS_ERR(drvdata->reset_gpio))
286	return PTR_ERR(drvdata->reset_gpio);
287
288	i2c_set_clientdata(client, drvdata);
289	drvdata->client = client;
290
291	ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,
292	sizeof(drvdata->reg_value));
293	if (ret < 0) {
294	dev_warn(dev, "Unable to read device register: %d\n", ret);
295	return ret;
296	}
297
298	for (i = 0; i < MAX9485_NUM_CLKS; i++) {
299	int parent_index = max9485_clks[i].parent_index;
300	const char *name;
301
302	if (of_property_read_string_index(dev->of_node,
303	"clock-output-names",
304	i, &name) == 0) {
305	drvdata->hw[i].init.name = name;
306	} else {
307	drvdata->hw[i].init.name = max9485_clks[i].name;
308	}
309
310	drvdata->hw[i].init.ops = &max9485_clks[i].ops;
311	drvdata->hw[i].init.num_parents = 1;
312	drvdata->hw[i].init.flags = 0;
313
314	if (parent_index > 0) {
315	drvdata->hw[i].init.parent_names =
316	&drvdata->hw[parent_index].init.name;
317	drvdata->hw[i].init.flags \|= CLK_SET_RATE_PARENT;
318	} else {
319	drvdata->hw[i].init.parent_names = &xclk_name;
320	}
321
322	drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
323	drvdata->hw[i].hw.init = &drvdata->hw[i].init;
324	drvdata->hw[i].drvdata = drvdata;
325
326	ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw);
327	if (ret < 0)
328	return ret;
329	}
330
331	return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata);
332	}
333
334	static int __maybe_unused max9485_suspend(struct device *dev)
335	{
336	struct i2c_client *client = to_i2c_client(dev);
337	struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
338
339	gpiod_set_value_cansleep(drvdata->reset_gpio, 0);
340
341	return 0;
342	}
343
344	static int __maybe_unused max9485_resume(struct device *dev)
345	{
346	struct i2c_client *client = to_i2c_client(dev);
347	struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
348	int ret;
349
350	gpiod_set_value_cansleep(drvdata->reset_gpio, 1);
351
352	ret = i2c_master_send(client, &drvdata->reg_value,
353	sizeof(drvdata->reg_value));
354
355	return ret < 0 ? ret : 0;
356	}
357
358	static const struct dev_pm_ops max9485_pm_ops = {
359	SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)
360	};
361
362	static const struct of_device_id max9485_dt_ids[] = {
363	{ .compatible = "maxim,max9485", },
364	{ }
365	};
366	MODULE_DEVICE_TABLE(of, max9485_dt_ids);
367
368	static const struct i2c_device_id max9485_i2c_ids[] = {
369	{ .name = "max9485", },
370	{ }
371	};
372	MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);
373
374	static struct i2c_driver max9485_driver = {
375	.driver = {
376	.name = "max9485",
377	.pm = &max9485_pm_ops,
378	.of_match_table = max9485_dt_ids,
379	},
380	.probe = max9485_i2c_probe,
381	.id_table = max9485_i2c_ids,
382	};
383	module_i2c_driver(max9485_driver);
384
385	MODULE_AUTHOR("Daniel Mack <[email protected]>");
386	MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");
387	MODULE_LICENSE("GPL v2");