[linux.git] / drivers / net / mipsnet.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <asm/mips-boards/simint.h>

#define MIPSNET_VERSION "2007-11-17"

/*
 * Net status/control block as seen by sw in the core.
 */
struct mipsnet_regs {
	/*
	 * Device info for probing, reads as MIPSNET%d where %d is some
	 * form of version.
	 */
	u64 devId;		/*0x00 */

	/*
	 * read only busy flag.
	 * Set and cleared by the Net Device to indicate that an rx or a tx
	 * is in progress.
	 */
	u32 busy;		/*0x08 */

	/*
	 * Set by the Net Device.
	 * The device will set it once data has been received.
	 * The value is the number of bytes that should be read from
	 * rxDataBuffer.  The value will decrease till 0 until all the data
	 * from rxDataBuffer has been read.
	 */
	u32 rxDataCount;	/*0x0c */
#define MIPSNET_MAX_RXTX_DATACOUNT (1 << 16)

	/*
	 * Settable from the MIPS core, cleared by the Net Device.
	 * The core should set the number of bytes it wants to send,
	 * then it should write those bytes of data to txDataBuffer.
	 * The device will clear txDataCount has been processed (not
	 * necessarily sent).
	 */
	u32 txDataCount;	/*0x10 */

	/*
	 * Interrupt control
	 *
	 * Used to clear the interrupted generated by this dev.
	 * Write a 1 to clear the interrupt. (except bit31).
	 *
	 * Bit0 is set if it was a tx-done interrupt.
	 * Bit1 is set when new rx-data is available.
	 *    Until this bit is cleared there will be no other RXs.
	 *
	 * Bit31 is used for testing, it clears after a read.
	 *    Writing 1 to this bit will cause an interrupt to be generated.
	 *    To clear the test interrupt, write 0 to this register.
	 */
	u32 interruptControl;	/*0x14 */
#define MIPSNET_INTCTL_TXDONE     (1u << 0)
#define MIPSNET_INTCTL_RXDONE     (1u << 1)
#define MIPSNET_INTCTL_TESTBIT    (1u << 31)

	/*
	 * Readonly core-specific interrupt info for the device to signal
	 * the core. The meaning of the contents of this field might change.
	 */
	/* XXX: the whole memIntf interrupt scheme is messy: the device
	 * should have no control what so ever of what VPE/register set is
	 * being used.
	 * The MemIntf should only expose interrupt lines, and something in
	 * the config should be responsible for the line<->core/vpe bindings.
	 */
	u32 interruptInfo;	/*0x18 */

	/*
	 * This is where the received data is read out.
	 * There is more data to read until rxDataReady is 0.
	 * Only 1 byte at this regs offset is used.
	 */
	u32 rxDataBuffer;	/*0x1c */

	/*
	 * This is where the data to transmit is written.
	 * Data should be written for the amount specified in the
	 * txDataCount register.
	 * Only 1 byte at this regs offset is used.
	 */
	u32 txDataBuffer;	/*0x20 */
};

#define regaddr(dev, field) \
  (dev->base_addr + offsetof(struct mipsnet_regs, field))

static char mipsnet_string[] = "mipsnet";

/*
 * Copy data from the MIPSNET rx data port
 */
static int ioiocpy_frommipsnet(struct net_device *dev, unsigned char *kdata,
			int len)
{
	for (; len > 0; len--, kdata++)
		*kdata = inb(regaddr(dev, rxDataBuffer));

	return inl(regaddr(dev, rxDataCount));
}

static inline void mipsnet_put_todevice(struct net_device *dev,
	struct sk_buff *skb)
{
	int count_to_go = skb->len;
	char *buf_ptr = skb->data;

	outl(skb->len, regaddr(dev, txDataCount));

	for (; count_to_go; buf_ptr++, count_to_go--)
		outb(*buf_ptr, regaddr(dev, txDataBuffer));

	dev->stats.tx_packets++;
	dev->stats.tx_bytes += skb->len;

	dev_kfree_skb(skb);
}

static int mipsnet_xmit(struct sk_buff *skb, struct net_device *dev)
{
	/*
	 * Only one packet at a time. Once TXDONE interrupt is serviced, the
	 * queue will be restarted.
	 */
	netif_stop_queue(dev);
	mipsnet_put_todevice(dev, skb);

	return NETDEV_TX_OK;
}

static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t len)
{
	struct sk_buff *skb;

	if (!len)
		return len;

	skb = dev_alloc_skb(len + NET_IP_ALIGN);
	if (!skb) {
		dev->stats.rx_dropped++;
		return -ENOMEM;
	}

	skb_reserve(skb, NET_IP_ALIGN);
	if (ioiocpy_frommipsnet(dev, skb_put(skb, len), len))
		return -EFAULT;

	skb->protocol = eth_type_trans(skb, dev);
	skb->ip_summed = CHECKSUM_UNNECESSARY;

	netif_rx(skb);

	dev->stats.rx_packets++;
	dev->stats.rx_bytes += len;

	return len;
}

static irqreturn_t mipsnet_interrupt(int irq, void *dev_id)
{
	struct net_device *dev = dev_id;
	u32 int_flags;
	irqreturn_t ret = IRQ_NONE;

	if (irq != dev->irq)
		goto out_badirq;

	/* TESTBIT is cleared on read. */
	int_flags = inl(regaddr(dev, interruptControl));
	if (int_flags & MIPSNET_INTCTL_TESTBIT) {
		/* TESTBIT takes effect after a write with 0. */
		outl(0, regaddr(dev, interruptControl));
		ret = IRQ_HANDLED;
	} else if (int_flags & MIPSNET_INTCTL_TXDONE) {
		/* Only one packet at a time, we are done. */
		dev->stats.tx_packets++;
		netif_wake_queue(dev);
		outl(MIPSNET_INTCTL_TXDONE,
		     regaddr(dev, interruptControl));
		ret = IRQ_HANDLED;
	} else if (int_flags & MIPSNET_INTCTL_RXDONE) {
		mipsnet_get_fromdev(dev, inl(regaddr(dev, rxDataCount)));
		outl(MIPSNET_INTCTL_RXDONE, regaddr(dev, interruptControl));
		ret = IRQ_HANDLED;
	}
	return ret;

out_badirq:
	printk(KERN_INFO "%s: %s(): irq %d for unknown device\n",
	       dev->name, __func__, irq);
	return ret;
}

static int mipsnet_open(struct net_device *dev)
{
	int err;

	err = request_irq(dev->irq, mipsnet_interrupt,
			  IRQF_SHARED, dev->name, (void *) dev);
	if (err) {
		release_region(dev->base_addr, sizeof(struct mipsnet_regs));
		return err;
	}

	netif_start_queue(dev);

	/* test interrupt handler */
	outl(MIPSNET_INTCTL_TESTBIT, regaddr(dev, interruptControl));

	return 0;
}

static int mipsnet_close(struct net_device *dev)
{
	netif_stop_queue(dev);
	free_irq(dev->irq, dev);
	return 0;
}

static void mipsnet_set_mclist(struct net_device *dev)
{
}

static const struct net_device_ops mipsnet_netdev_ops = {
	.ndo_open		= mipsnet_open,
	.ndo_stop		= mipsnet_close,
	.ndo_start_xmit		= mipsnet_xmit,
	.ndo_set_multicast_list	= mipsnet_set_mclist,
	.ndo_change_mtu		= eth_change_mtu,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
};

static int __init mipsnet_probe(struct platform_device *dev)
{
	struct net_device *netdev;
	int err;

	netdev = alloc_etherdev(0);
	if (!netdev) {
		err = -ENOMEM;
		goto out;
	}

	platform_set_drvdata(dev, netdev);

	netdev->netdev_ops = &mipsnet_netdev_ops;

	/*
	 * TODO: probe for these or load them from PARAM
	 */
	netdev->base_addr = 0x4200;
	netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 +
		      inl(regaddr(netdev, interruptInfo));

	/* Get the io region now, get irq on open() */
	if (!request_region(netdev->base_addr, sizeof(struct mipsnet_regs),
			    "mipsnet")) {
		err = -EBUSY;
		goto out_free_netdev;
	}

	/*
	 * Lacking any better mechanism to allocate a MAC address we use a
	 * random one ...
	 */
	random_ether_addr(netdev->dev_addr);

	err = register_netdev(netdev);
	if (err) {
		printk(KERN_ERR "MIPSNet: failed to register netdev.\n");
		goto out_free_region;
	}

	return 0;

out_free_region:
	release_region(netdev->base_addr, sizeof(struct mipsnet_regs));

out_free_netdev:
	free_netdev(netdev);

out:
	return err;
}

static int __devexit mipsnet_device_remove(struct platform_device *device)
{
	struct net_device *dev = platform_get_drvdata(device);

	unregister_netdev(dev);
	release_region(dev->base_addr, sizeof(struct mipsnet_regs));
	free_netdev(dev);
	platform_set_drvdata(device, NULL);

	return 0;
}

static struct platform_driver mipsnet_driver = {
	.driver = {
		.name		= mipsnet_string,
		.owner		= THIS_MODULE,
	},
	.probe		= mipsnet_probe,
	.remove		= __devexit_p(mipsnet_device_remove),
};

static int __init mipsnet_init_module(void)
{
	int err;

	printk(KERN_INFO "MIPSNet Ethernet driver. Version: %s. "
	       "(c)2005 MIPS Technologies, Inc.\n", MIPSNET_VERSION);

	err = platform_driver_register(&mipsnet_driver);
	if (err)
		printk(KERN_ERR "Driver registration failed\n");

	return err;
}

static void __exit mipsnet_exit_module(void)
{
	platform_driver_unregister(&mipsnet_driver);
}

module_init(mipsnet_init_module);
module_exit(mipsnet_exit_module);
Commit	Line	Data
dcbf8477 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*/
	6
dcbf8477	7	#include <linux/init.h>
c2af68e5	8	#include <linux/io.h>
dcbf8477 RB	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/netdevice.h>
dcbf8477	12	#include <linux/etherdevice.h>
d052d1be	13	#include <linux/platform_device.h>
dcbf8477 RB	14	#include <asm/mips-boards/simint.h>
dcbf8477 RB	15
c800c5c9 RB	16	#define MIPSNET_VERSION "2007-11-17"
	17
	18	/*
	19	* Net status/control block as seen by sw in the core.
	20	*/
	21	struct mipsnet_regs {
	22	/*
	23	* Device info for probing, reads as MIPSNET%d where %d is some
	24	* form of version.
	25	*/
	26	u64 devId; /0x00 /
dcbf8477	27
c800c5c9 RB	28	/*
	29	* read only busy flag.
	30	* Set and cleared by the Net Device to indicate that an rx or a tx
	31	* is in progress.
	32	*/
	33	u32 busy; /0x08 /
dcbf8477	34
c800c5c9 RB	35	/*
	36	* Set by the Net Device.
	37	* The device will set it once data has been received.
	38	* The value is the number of bytes that should be read from
	39	* rxDataBuffer. The value will decrease till 0 until all the data
	40	* from rxDataBuffer has been read.
	41	*/
	42	u32 rxDataCount; /0x0c /
	43	#define MIPSNET_MAX_RXTX_DATACOUNT (1 << 16)
	44
	45	/*
	46	* Settable from the MIPS core, cleared by the Net Device.
	47	* The core should set the number of bytes it wants to send,
	48	* then it should write those bytes of data to txDataBuffer.
	49	* The device will clear txDataCount has been processed (not
	50	* necessarily sent).
	51	*/
	52	u32 txDataCount; /0x10 /
	53
	54	/*
	55	* Interrupt control
	56	*
	57	* Used to clear the interrupted generated by this dev.
	58	* Write a 1 to clear the interrupt. (except bit31).
	59	*
	60	* Bit0 is set if it was a tx-done interrupt.
	61	* Bit1 is set when new rx-data is available.
	62	* Until this bit is cleared there will be no other RXs.
	63	*
	64	* Bit31 is used for testing, it clears after a read.
	65	* Writing 1 to this bit will cause an interrupt to be generated.
	66	* To clear the test interrupt, write 0 to this register.
	67	*/
	68	u32 interruptControl; /0x14 /
	69	#define MIPSNET_INTCTL_TXDONE (1u << 0)
	70	#define MIPSNET_INTCTL_RXDONE (1u << 1)
	71	#define MIPSNET_INTCTL_TESTBIT (1u << 31)
	72
	73	/*
	74	* Readonly core-specific interrupt info for the device to signal
	75	* the core. The meaning of the contents of this field might change.
	76	*/
	77	/* XXX: the whole memIntf interrupt scheme is messy: the device
	78	* should have no control what so ever of what VPE/register set is
	79	* being used.
	80	* The MemIntf should only expose interrupt lines, and something in
	81	* the config should be responsible for the line<->core/vpe bindings.
	82	*/
	83	u32 interruptInfo; /0x18 /
	84
	85	/*
	86	* This is where the received data is read out.
	87	* There is more data to read until rxDataReady is 0.
	88	* Only 1 byte at this regs offset is used.
	89	*/
	90	u32 rxDataBuffer; /0x1c /
	91
	92	/*
	93	* This is where the data to transmit is written.
	94	* Data should be written for the amount specified in the
	95	* txDataCount register.
	96	* Only 1 byte at this regs offset is used.
	97	*/
	98	u32 txDataBuffer; /0x20 /
99	};
100
101	#define regaddr(dev, field) \
102	(dev->base_addr + offsetof(struct mipsnet_regs, field))
dcbf8477	103
dcbf8477 RB	104	static char mipsnet_string[] = "mipsnet";
	105
	106	/*
	107	* Copy data from the MIPSNET rx data port
	108	*/
	109	static int ioiocpy_frommipsnet(struct net_device dev, unsigned char kdata,
	110	int len)
	111	{
c2af68e5	112	for (; len > 0; len--, kdata++)
c800c5c9	113	*kdata = inb(regaddr(dev, rxDataBuffer));
dcbf8477	114
c800c5c9	115	return inl(regaddr(dev, rxDataCount));
dcbf8477 RB	116	}
dcbf8477 RB	117
c800c5c9	118	static inline void mipsnet_put_todevice(struct net_device *dev,
dcbf8477 RB	119	struct sk_buff *skb)
	120	{
	121	int count_to_go = skb->len;
	122	char *buf_ptr = skb->data;
dcbf8477	123
c800c5c9	124	outl(skb->len, regaddr(dev, txDataCount));
dcbf8477	125
c2af68e5	126	for (; count_to_go; buf_ptr++, count_to_go--)
c800c5c9	127	outb(*buf_ptr, regaddr(dev, txDataBuffer));
dcbf8477	128
09f75cd7 JG	129	dev->stats.tx_packets++;
09f75cd7 JG	130	dev->stats.tx_bytes += skb->len;
dcbf8477	131
c800c5c9	132	dev_kfree_skb(skb);
dcbf8477 RB	133	}
	134
	135	static int mipsnet_xmit(struct sk_buff skb, struct net_device dev)
	136	{
f5e42fba RB	137	/*
f5e42fba RB	138	* Only one packet at a time. Once TXDONE interrupt is serviced, the
dcbf8477 RB	139	* queue will be restarted.
	140	*/
	141	netif_stop_queue(dev);
	142	mipsnet_put_todevice(dev, skb);
	143
6ed10654	144	return NETDEV_TX_OK;
dcbf8477 RB	145	}
dcbf8477 RB	146
c800c5c9	147	static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t len)
dcbf8477 RB	148	{
dcbf8477 RB	149	struct sk_buff *skb;
dcbf8477	150
c800c5c9 RB	151	if (!len)
	152	return len;
	153
	154	skb = dev_alloc_skb(len + NET_IP_ALIGN);
c2af68e5	155	if (!skb) {
09f75cd7	156	dev->stats.rx_dropped++;
dcbf8477 RB	157	return -ENOMEM;
	158	}
	159
c800c5c9	160	skb_reserve(skb, NET_IP_ALIGN);
dcbf8477 RB	161	if (ioiocpy_frommipsnet(dev, skb_put(skb, len), len))
	162	return -EFAULT;
	163
dcbf8477 RB	164	skb->protocol = eth_type_trans(skb, dev);
	165	skb->ip_summed = CHECKSUM_UNNECESSARY;
	166
dcbf8477 RB	167	netif_rx(skb);
dcbf8477 RB	168
09f75cd7 JG	169	dev->stats.rx_packets++;
09f75cd7 JG	170	dev->stats.rx_bytes += len;
dcbf8477	171
c800c5c9	172	return len;
dcbf8477 RB	173	}
dcbf8477 RB	174
7d12e780	175	static irqreturn_t mipsnet_interrupt(int irq, void *dev_id)
dcbf8477 RB	176	{
dcbf8477 RB	177	struct net_device *dev = dev_id;
c800c5c9 RB	178	u32 int_flags;
	179	irqreturn_t ret = IRQ_NONE;
	180
	181	if (irq != dev->irq)
	182	goto out_badirq;
	183
	184	/* TESTBIT is cleared on read. */
	185	int_flags = inl(regaddr(dev, interruptControl));
	186	if (int_flags & MIPSNET_INTCTL_TESTBIT) {
	187	/* TESTBIT takes effect after a write with 0. */
	188	outl(0, regaddr(dev, interruptControl));
	189	ret = IRQ_HANDLED;
	190	} else if (int_flags & MIPSNET_INTCTL_TXDONE) {
	191	/* Only one packet at a time, we are done. */
	192	dev->stats.tx_packets++;
	193	netif_wake_queue(dev);
	194	outl(MIPSNET_INTCTL_TXDONE,
	195	regaddr(dev, interruptControl));
	196	ret = IRQ_HANDLED;
	197	} else if (int_flags & MIPSNET_INTCTL_RXDONE) {
	198	mipsnet_get_fromdev(dev, inl(regaddr(dev, rxDataCount)));
	199	outl(MIPSNET_INTCTL_RXDONE, regaddr(dev, interruptControl));
	200	ret = IRQ_HANDLED;
dcbf8477	201	}
c800c5c9 RB	202	return ret;
	203
	204	out_badirq:
	205	printk(KERN_INFO "%s: %s(): irq %d for unknown device\n",
b39d66a8	206	dev->name, __func__, irq);
c800c5c9	207	return ret;
c2af68e5	208	}
dcbf8477 RB	209
	210	static int mipsnet_open(struct net_device *dev)
	211	{
	212	int err;
dcbf8477	213
a0607fd3	214	err = request_irq(dev->irq, mipsnet_interrupt,
1fb9df5d	215	IRQF_SHARED, dev->name, (void *) dev);
dcbf8477	216	if (err) {
c800c5c9	217	release_region(dev->base_addr, sizeof(struct mipsnet_regs));
dcbf8477 RB	218	return err;
	219	}
	220
dcbf8477 RB	221	netif_start_queue(dev);
dcbf8477 RB	222
c2af68e5	223	/* test interrupt handler */
c800c5c9	224	outl(MIPSNET_INTCTL_TESTBIT, regaddr(dev, interruptControl));
dcbf8477 RB	225
	226	return 0;
	227	}
	228
	229	static int mipsnet_close(struct net_device *dev)
	230	{
dcbf8477	231	netif_stop_queue(dev);
c800c5c9	232	free_irq(dev->irq, dev);
dcbf8477 RB	233	return 0;
	234	}
	235
dcbf8477 RB	236	static void mipsnet_set_mclist(struct net_device *dev)
dcbf8477 RB	237	{
dcbf8477 RB	238	}
dcbf8477 RB	239
d6771e0b AB	240	static const struct net_device_ops mipsnet_netdev_ops = {
	241	.ndo_open = mipsnet_open,
	242	.ndo_stop = mipsnet_close,
	243	.ndo_start_xmit = mipsnet_xmit,
	244	.ndo_set_multicast_list = mipsnet_set_mclist,
	245	.ndo_change_mtu = eth_change_mtu,
	246	.ndo_validate_addr = eth_validate_addr,
	247	.ndo_set_mac_address = eth_mac_addr,
	248	};
	249
7a192ec3	250	static int __init mipsnet_probe(struct platform_device *dev)
dcbf8477 RB	251	{
	252	struct net_device *netdev;
	253	int err;
	254
09f75cd7	255	netdev = alloc_etherdev(0);
dcbf8477 RB	256	if (!netdev) {
	257	err = -ENOMEM;
	258	goto out;
	259	}
	260
7a192ec3	261	platform_set_drvdata(dev, netdev);
dcbf8477	262
d6771e0b	263	netdev->netdev_ops = &mipsnet_netdev_ops;
dcbf8477 RB	264
	265	/*
	266	* TODO: probe for these or load them from PARAM
	267	*/
	268	netdev->base_addr = 0x4200;
3b1d4ed5	269	netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 +
c800c5c9	270	inl(regaddr(netdev, interruptInfo));
dcbf8477	271
c2af68e5	272	/* Get the io region now, get irq on open() */
c800c5c9 RB	273	if (!request_region(netdev->base_addr, sizeof(struct mipsnet_regs),
c800c5c9 RB	274	"mipsnet")) {
dcbf8477 RB	275	err = -EBUSY;
	276	goto out_free_netdev;
	277	}
	278
	279	/*
	280	* Lacking any better mechanism to allocate a MAC address we use a
	281	* random one ...
	282	*/
	283	random_ether_addr(netdev->dev_addr);
	284
	285	err = register_netdev(netdev);
	286	if (err) {
	287	printk(KERN_ERR "MIPSNet: failed to register netdev.\n");
	288	goto out_free_region;
	289	}
	290
	291	return 0;
	292
	293	out_free_region:
c800c5c9	294	release_region(netdev->base_addr, sizeof(struct mipsnet_regs));
dcbf8477 RB	295
	296	out_free_netdev:
	297	free_netdev(netdev);
	298
	299	out:
	300	return err;
	301	}
	302
7a192ec3	303	static int __devexit mipsnet_device_remove(struct platform_device *device)
dcbf8477	304	{
7a192ec3	305	struct net_device *dev = platform_get_drvdata(device);
dcbf8477 RB	306
dcbf8477 RB	307	unregister_netdev(dev);
c800c5c9	308	release_region(dev->base_addr, sizeof(struct mipsnet_regs));
dcbf8477	309	free_netdev(dev);
7a192ec3	310	platform_set_drvdata(device, NULL);
dcbf8477 RB	311
	312	return 0;
	313	}
	314
7a192ec3 ML	315	static struct platform_driver mipsnet_driver = {
	316	.driver = {
	317	.name = mipsnet_string,
	318	.owner = THIS_MODULE,
	319	},
	320	.probe = mipsnet_probe,
	321	.remove = __devexit_p(mipsnet_device_remove),
dcbf8477 RB	322	};
dcbf8477 RB	323
dcbf8477 RB	324	static int __init mipsnet_init_module(void)
dcbf8477 RB	325	{
dcbf8477 RB	326	int err;
	327
	328	printk(KERN_INFO "MIPSNet Ethernet driver. Version: %s. "
	329	"(c)2005 MIPS Technologies, Inc.\n", MIPSNET_VERSION);
	330
7a192ec3	331	err = platform_driver_register(&mipsnet_driver);
1e2b980f	332	if (err)
dcbf8477	333	printk(KERN_ERR "Driver registration failed\n");
dcbf8477	334
dcbf8477 RB	335	return err;
	336	}
	337
	338	static void __exit mipsnet_exit_module(void)
	339	{
7a192ec3	340	platform_driver_unregister(&mipsnet_driver);
dcbf8477 RB	341	}
	342
	343	module_init(mipsnet_init_module);
	344	module_exit(mipsnet_exit_module);