[linux.git] / include / kvm / arm_vgic.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 */
#ifndef __KVM_ARM_VGIC_H
#define __KVM_ARM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/static_key.h>
#include <linux/types.h>
#include <kvm/iodev.h>
#include <linux/list.h>
#include <linux/jump_label.h>

#include <linux/irqchip/arm-gic-v4.h>

#define VGIC_V3_MAX_CPUS	512
#define VGIC_V2_MAX_CPUS	8
#define VGIC_NR_IRQS_LEGACY     256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
#define VGIC_MAX_SPI		1019
#define VGIC_MAX_RESERVED	1023
#define VGIC_MIN_LPI		8192
#define KVM_IRQCHIP_NUM_PINS	(1020 - 32)

#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
			 (irq) <= VGIC_MAX_SPI)

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
	/* type of the host GIC */
	enum vgic_type		type;

	/* Physical address of vgic virtual cpu interface */
	phys_addr_t		vcpu_base;

	/* GICV mapping, kernel VA */
	void __iomem		*vcpu_base_va;
	/* GICV mapping, HYP VA */
	void __iomem		*vcpu_hyp_va;

	/* virtual control interface mapping, kernel VA */
	void __iomem		*vctrl_base;
	/* virtual control interface mapping, HYP VA */
	void __iomem		*vctrl_hyp;

	/* Number of implemented list registers */
	int			nr_lr;

	/* Maintenance IRQ number */
	unsigned int		maint_irq;

	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	int			max_gic_vcpus;

	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool			can_emulate_gicv2;

	/* Hardware has GICv4? */
	bool			has_gicv4;
	bool			has_gicv4_1;

	/* GIC system register CPU interface */
	struct static_key_false gicv3_cpuif;

	u32			ich_vtr_el2;
};

extern struct vgic_global kvm_vgic_global_state;

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)

enum vgic_irq_config {
	VGIC_CONFIG_EDGE = 0,
	VGIC_CONFIG_LEVEL
};

struct vgic_irq {
	raw_spinlock_t irq_lock;	/* Protects the content of the struct */
	struct list_head lpi_list;	/* Used to link all LPIs together */
	struct list_head ap_list;

	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
					 * SPIs and LPIs: The VCPU whose ap_list
					 * this is queued on.
					 */

	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
					 * be sent to, as a result of the
					 * targets reg (v2) or the
					 * affinity reg (v3).
					 */

	u32 intid;			/* Guest visible INTID */
	bool line_level;		/* Level only */
	bool pending_latch;		/* The pending latch state used to calculate
					 * the pending state for both level
					 * and edge triggered IRQs. */
	bool active;			/* not used for LPIs */
	bool enabled;
	bool hw;			/* Tied to HW IRQ */
	struct kref refcount;		/* Used for LPIs */
	u32 hwintid;			/* HW INTID number */
	unsigned int host_irq;		/* linux irq corresponding to hwintid */
	union {
		u8 targets;			/* GICv2 target VCPUs mask */
		u32 mpidr;			/* GICv3 target VCPU */
	};
	u8 source;			/* GICv2 SGIs only */
	u8 active_source;		/* GICv2 SGIs only */
	u8 priority;
	u8 group;			/* 0 == group 0, 1 == group 1 */
	enum vgic_irq_config config;	/* Level or edge */

	/*
	 * Callback function pointer to in-kernel devices that can tell us the
	 * state of the input level of mapped level-triggered IRQ faster than
	 * peaking into the physical GIC.
	 *
	 * Always called in non-preemptible section and the functions can use
	 * kvm_arm_get_running_vcpu() to get the vcpu pointer for private
	 * IRQs.
	 */
	bool (*get_input_level)(int vintid);

	void *owner;			/* Opaque pointer to reserve an interrupt
					   for in-kernel devices. */
};

struct vgic_register_region;
struct vgic_its;

enum iodev_type {
	IODEV_CPUIF,
	IODEV_DIST,
	IODEV_REDIST,
	IODEV_ITS
};

struct vgic_io_device {
	gpa_t base_addr;
	union {
		struct kvm_vcpu *redist_vcpu;
		struct vgic_its *its;
	};
	const struct vgic_register_region *regions;
	enum iodev_type iodev_type;
	int nr_regions;
	struct kvm_io_device dev;
};

struct vgic_its {
	/* The base address of the ITS control register frame */
	gpa_t			vgic_its_base;

	bool			enabled;
	struct vgic_io_device	iodev;
	struct kvm_device	*dev;

	/* These registers correspond to GITS_BASER{0,1} */
	u64			baser_device_table;
	u64			baser_coll_table;

	/* Protects the command queue */
	struct mutex		cmd_lock;
	u64			cbaser;
	u32			creadr;
	u32			cwriter;

	/* migration ABI revision in use */
	u32			abi_rev;

	/* Protects the device and collection lists */
	struct mutex		its_lock;
	struct list_head	device_list;
	struct list_head	collection_list;
};

struct vgic_state_iter;

struct vgic_redist_region {
	u32 index;
	gpa_t base;
	u32 count; /* number of redistributors or 0 if single region */
	u32 free_index; /* index of the next free redistributor */
	struct list_head list;
};

struct vgic_dist {
	bool			in_kernel;
	bool			ready;
	bool			initialized;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	/* Implementation revision as reported in the GICD_IIDR */
	u32			implementation_rev;

	/* Userspace can write to GICv2 IGROUPR */
	bool			v2_groups_user_writable;

	/* Do injected MSIs require an additional device ID? */
	bool			msis_require_devid;

	int			nr_spis;

	/* base addresses in guest physical address space: */
	gpa_t			vgic_dist_base;		/* distributor */
	union {
		/* either a GICv2 CPU interface */
		gpa_t			vgic_cpu_base;
		/* or a number of GICv3 redistributor regions */
		struct list_head rd_regions;
	};

	/* distributor enabled */
	bool			enabled;

	/* Wants SGIs without active state */
	bool			nassgireq;

	struct vgic_irq		*spis;

	struct vgic_io_device	dist_iodev;

	bool			has_its;

	/*
	 * Contains the attributes and gpa of the LPI configuration table.
	 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	 * one address across all redistributors.
	 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables"
	 */
	u64			propbaser;

	/* Protects the lpi_list and the count value below. */
	raw_spinlock_t		lpi_list_lock;
	struct list_head	lpi_list_head;
	int			lpi_list_count;

	/* LPI translation cache */
	struct list_head	lpi_translation_cache;

	/* used by vgic-debug */
	struct vgic_state_iter *iter;

	/*
	 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
	 * array, the property table pointer as well as allocation
	 * data. This essentially ties the Linux IRQ core and ITS
	 * together, and avoids leaking KVM's data structures anywhere
	 * else.
	 */
	struct its_vm		its_vm;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];

	unsigned int used_lrs;
};

struct vgic_v3_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];

	/*
	 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
	 * pending table pointer, the its_vm pointer and a few other
	 * HW specific things. As for the its_vm structure, this is
	 * linking the Linux IRQ subsystem and the ITS together.
	 */
	struct its_vpe	its_vpe;

	unsigned int used_lrs;
};

struct vgic_cpu {
	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];

	raw_spinlock_t ap_list_lock;	/* Protects the ap_list */

	/*
	 * List of IRQs that this VCPU should consider because they are either
	 * Active or Pending (hence the name; AP list), or because they recently
	 * were one of the two and need to be migrated off this list to another
	 * VCPU.
	 */
	struct list_head ap_list_head;

	/*
	 * Members below are used with GICv3 emulation only and represent
	 * parts of the redistributor.
	 */
	struct vgic_io_device	rd_iodev;
	struct vgic_redist_region *rdreg;

	/* Contains the attributes and gpa of the LPI pending tables. */
	u64 pendbaser;

	bool lpis_enabled;

	/* Cache guest priority bits */
	u32 num_pri_bits;

	/* Cache guest interrupt ID bits */
	u32 num_id_bits;
};

extern struct static_key_false vgic_v2_cpuif_trap;
extern struct static_key_false vgic_v3_cpuif_trap;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_hyp_init(void);
void kvm_vgic_init_cpu_hardware(void);

int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			bool level, void *owner);
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
			  u32 vintid, bool (*get_input_level)(int vindid));
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);

int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);

void kvm_vgic_load(struct kvm_vcpu *vcpu);
void kvm_vgic_put(struct kvm_vcpu *vcpu);
void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.initialized)
#define vgic_ready(k)		((k)->arch.vgic.ready)
#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))

bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);

void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1);

/**
 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 *
 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 * can use.
 */
static inline int kvm_vgic_get_max_vcpus(void)
{
	return kvm_vgic_global_state.max_gic_vcpus;
}

/**
 * kvm_vgic_setup_default_irq_routing:
 * Setup a default flat gsi routing table mapping all SPIs
 */
int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);

int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);

struct kvm_kernel_irq_routing_entry;

int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
			       struct kvm_kernel_irq_routing_entry *irq_entry);

int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
				 struct kvm_kernel_irq_routing_entry *irq_entry);

int vgic_v4_load(struct kvm_vcpu *vcpu);
void vgic_v4_commit(struct kvm_vcpu *vcpu);
int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db);

#endif /* __KVM_ARM_VGIC_H */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
1a89dd91	2	/*
50926d82	3	* Copyright (C) 2015, 2016 ARM Ltd.
1a89dd91	4	*/
50926d82 MZ	5	#ifndef __KVM_ARM_VGIC_H
50926d82 MZ	6	#define __KVM_ARM_VGIC_H
b18b5778	7
b47ef92a MZ	8	#include <linux/kernel.h>
b47ef92a MZ	9	#include <linux/kvm.h>
b47ef92a MZ	10	#include <linux/irqreturn.h>
b47ef92a MZ	11	#include <linux/spinlock.h>
fb5ee369	12	#include <linux/static_key.h>
b47ef92a	13	#include <linux/types.h>
6777f77f	14	#include <kvm/iodev.h>
424c3383	15	#include <linux/list.h>
5a7a8426	16	#include <linux/jump_label.h>
1a89dd91	17
74fe55dc MZ	18	#include <linux/irqchip/arm-gic-v4.h>
74fe55dc MZ	19
e25028c8	20	#define VGIC_V3_MAX_CPUS 512
50926d82 MZ	21	#define VGIC_V2_MAX_CPUS 8
50926d82 MZ	22	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	23	#define VGIC_NR_SGIS 16
	24	#define VGIC_NR_PPIS 16
	25	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
50926d82 MZ	26	#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
	27	#define VGIC_MAX_SPI 1019
	28	#define VGIC_MAX_RESERVED 1023
	29	#define VGIC_MIN_LPI 8192
180ae7b1	30	#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
8f186d52	31
3cba4af3	32	#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
ebb127f2 CD	33	#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
ebb127f2 CD	34	(irq) <= VGIC_MAX_SPI)
3cba4af3	35
50926d82 MZ	36	enum vgic_type {
	37	VGIC_V2, /* Good ol' GICv2 */
	38	VGIC_V3, /* New fancy GICv3 */
	39	};
b47ef92a	40
50926d82 MZ	41	/* same for all guests, as depending only on the _host's_ GIC model */
	42	struct vgic_global {
	43	/* type of the host GIC */
	44	enum vgic_type type;
b47ef92a	45
50926d82 MZ	46	/* Physical address of vgic virtual cpu interface */
50926d82 MZ	47	phys_addr_t vcpu_base;
b47ef92a	48
1bb32a44	49	/* GICV mapping, kernel VA */
bf8feb39	50	void __iomem *vcpu_base_va;
1bb32a44 MZ	51	/* GICV mapping, HYP VA */
1bb32a44 MZ	52	void __iomem *vcpu_hyp_va;
bf8feb39	53
1bb32a44	54	/* virtual control interface mapping, kernel VA */
50926d82	55	void __iomem *vctrl_base;
1bb32a44 MZ	56	/* virtual control interface mapping, HYP VA */
1bb32a44 MZ	57	void __iomem *vctrl_hyp;
b47ef92a	58
50926d82 MZ	59	/* Number of implemented list registers */
50926d82 MZ	60	int nr_lr;
8d5c6b06	61
50926d82 MZ	62	/* Maintenance IRQ number */
50926d82 MZ	63	unsigned int maint_irq;
1a9b1305	64
50926d82 MZ	65	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
50926d82 MZ	66	int max_gic_vcpus;
8d5c6b06	67
50926d82 MZ	68	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
50926d82 MZ	69	bool can_emulate_gicv2;
5a7a8426	70
e7c48059 MZ	71	/* Hardware has GICv4? */
e7c48059 MZ	72	bool has_gicv4;
ae699ad3	73	bool has_gicv4_1;
e7c48059	74
5a7a8426 VM	75	/* GIC system register CPU interface */
5a7a8426 VM	76	struct static_key_false gicv3_cpuif;
d017d7b0 VK	77
d017d7b0 VK	78	u32 ich_vtr_el2;
8d5c6b06 MZ	79	};
8d5c6b06 MZ	80
50926d82	81	extern struct vgic_global kvm_vgic_global_state;
beee38b9	82
50926d82 MZ	83	#define VGIC_V2_MAX_LRS (1 << 6)
	84	#define VGIC_V3_MAX_LRS 16
	85	#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
8d5c6b06	86
50926d82 MZ	87	enum vgic_irq_config {
	88	VGIC_CONFIG_EDGE = 0,
	89	VGIC_CONFIG_LEVEL
ca85f623 MZ	90	};
ca85f623 MZ	91
50926d82	92	struct vgic_irq {
8fa3adb8	93	raw_spinlock_t irq_lock; /* Protects the content of the struct */
3802411d	94	struct list_head lpi_list; /* Used to link all LPIs together */
50926d82 MZ	95	struct list_head ap_list;
	96
	97	struct kvm_vcpu vcpu; / SGIs and PPIs: The VCPU
	98	* SPIs and LPIs: The VCPU whose ap_list
	99	* this is queued on.
	100	*/
	101
	102	struct kvm_vcpu target_vcpu; / The VCPU that this interrupt should
	103	* be sent to, as a result of the
	104	* targets reg (v2) or the
	105	* affinity reg (v3).
	106	*/
	107
	108	u32 intid; /* Guest visible INTID */
50926d82	109	bool line_level; /* Level only */
8694e4da CD	110	bool pending_latch; /* The pending latch state used to calculate
	111	* the pending state for both level
	112	* and edge triggered IRQs. */
50926d82 MZ	113	bool active; /* not used for LPIs */
	114	bool enabled;
	115	bool hw; /* Tied to HW IRQ */
5dd4b924	116	struct kref refcount; /* Used for LPIs */
50926d82	117	u32 hwintid; /* HW INTID number */
47bbd31f	118	unsigned int host_irq; /* linux irq corresponding to hwintid */
50926d82 MZ	119	union {
	120	u8 targets; /* GICv2 target VCPUs mask */
	121	u32 mpidr; /* GICv3 target VCPU */
	122	};
	123	u8 source; /* GICv2 SGIs only */
53692908	124	u8 active_source; /* GICv2 SGIs only */
50926d82	125	u8 priority;
8df3c8f3	126	u8 group; /* 0 == group 0, 1 == group 1 */
50926d82	127	enum vgic_irq_config config; /* Level or edge */
c6ccd30e	128
b6909a65 CD	129	/*
	130	* Callback function pointer to in-kernel devices that can tell us the
	131	* state of the input level of mapped level-triggered IRQ faster than
	132	* peaking into the physical GIC.
	133	*
	134	* Always called in non-preemptible section and the functions can use
	135	* kvm_arm_get_running_vcpu() to get the vcpu pointer for private
	136	* IRQs.
	137	*/
	138	bool (*get_input_level)(int vintid);
	139
c6ccd30e CD	140	void owner; / Opaque pointer to reserve an interrupt
c6ccd30e CD	141	for in-kernel devices. */
b26e5fda AP	142	};
b26e5fda AP	143
50926d82	144	struct vgic_register_region;
59c5ab40 AP	145	struct vgic_its;
	146
	147	enum iodev_type {
	148	IODEV_CPUIF,
	149	IODEV_DIST,
	150	IODEV_REDIST,
	151	IODEV_ITS
	152	};
50926d82	153
6777f77f	154	struct vgic_io_device {
50926d82	155	gpa_t base_addr;
59c5ab40 AP	156	union {
	157	struct kvm_vcpu *redist_vcpu;
	158	struct vgic_its *its;
	159	};
50926d82	160	const struct vgic_register_region *regions;
59c5ab40	161	enum iodev_type iodev_type;
50926d82	162	int nr_regions;
6777f77f AP	163	struct kvm_io_device dev;
	164	};
	165
59c5ab40 AP	166	struct vgic_its {
	167	/* The base address of the ITS control register frame */
	168	gpa_t vgic_its_base;
	169
	170	bool enabled;
	171	struct vgic_io_device iodev;
bb717644	172	struct kvm_device *dev;
424c3383 AP	173
	174	/* These registers correspond to GITS_BASER{0,1} */
	175	u64 baser_device_table;
	176	u64 baser_coll_table;
	177
	178	/* Protects the command queue */
	179	struct mutex cmd_lock;
	180	u64 cbaser;
	181	u32 creadr;
	182	u32 cwriter;
	183
71afe470 EA	184	/* migration ABI revision in use */
	185	u32 abi_rev;
	186
424c3383 AP	187	/* Protects the device and collection lists */
	188	struct mutex its_lock;
	189	struct list_head device_list;
	190	struct list_head collection_list;
59c5ab40 AP	191	};
59c5ab40 AP	192
10f92c4c CD	193	struct vgic_state_iter;
10f92c4c CD	194
dbd9733a EA	195	struct vgic_redist_region {
	196	u32 index;
	197	gpa_t base;
	198	u32 count; /* number of redistributors or 0 if single region */
	199	u32 free_index; /* index of the next free redistributor */
	200	struct list_head list;
	201	};
	202
1a89dd91	203	struct vgic_dist {
f982cf4e	204	bool in_kernel;
01ac5e34	205	bool ready;
50926d82	206	bool initialized;
b47ef92a	207
59892136 AP	208	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	209	u32 vgic_model;
	210
aa075b0f CD	211	/* Implementation revision as reported in the GICD_IIDR */
	212	u32 implementation_rev;
	213
32f8777e CD	214	/* Userspace can write to GICv2 IGROUPR */
	215	bool v2_groups_user_writable;
	216
0e4e82f1 AP	217	/* Do injected MSIs require an additional device ID? */
	218	bool msis_require_devid;
	219
50926d82	220	int nr_spis;
c1bfb577	221
50926d82 MZ	222	/* base addresses in guest physical address space: */
50926d82 MZ	223	gpa_t vgic_dist_base; /* distributor */
a0675c25	224	union {
50926d82 MZ	225	/* either a GICv2 CPU interface */
	226	gpa_t vgic_cpu_base;
	227	/* or a number of GICv3 redistributor regions */
dbd9733a	228	struct list_head rd_regions;
a0675c25	229	};
b47ef92a	230
50926d82 MZ	231	/* distributor enabled */
50926d82 MZ	232	bool enabled;
47a98b15	233
bacf2c60 MZ	234	/* Wants SGIs without active state */
	235	bool nassgireq;
	236
50926d82	237	struct vgic_irq *spis;
b47ef92a	238
a9cf86f6	239	struct vgic_io_device dist_iodev;
0aa1de57	240
1085fdc6 AP	241	bool has_its;
1085fdc6 AP	242
0aa1de57 AP	243	/*
	244	* Contains the attributes and gpa of the LPI configuration table.
	245	* Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	246	* one address across all redistributors.
bad36e4e	247	* GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables"
0aa1de57 AP	248	*/
0aa1de57 AP	249	u64 propbaser;
3802411d AP	250
3802411d AP	251	/* Protects the lpi_list and the count value below. */
fc3bc475	252	raw_spinlock_t lpi_list_lock;
3802411d AP	253	struct list_head lpi_list_head;
3802411d AP	254	int lpi_list_count;
10f92c4c	255
24cab82c MZ	256	/* LPI translation cache */
	257	struct list_head lpi_translation_cache;
	258
10f92c4c CD	259	/* used by vgic-debug */
10f92c4c CD	260	struct vgic_state_iter *iter;
74fe55dc MZ	261
	262	/*
	263	* GICv4 ITS per-VM data, containing the IRQ domain, the VPE
	264	* array, the property table pointer as well as allocation
	265	* data. This essentially ties the Linux IRQ core and ITS
	266	* together, and avoids leaking KVM's data structures anywhere
	267	* else.
	268	*/
	269	struct its_vm its_vm;
1a89dd91 MZ	270	};
1a89dd91 MZ	271
eede821d MZ	272	struct vgic_v2_cpu_if {
	273	u32 vgic_hcr;
	274	u32 vgic_vmcr;
eede821d	275	u32 vgic_apr;
8f186d52	276	u32 vgic_lr[VGIC_V2_MAX_LRS];
fc5d1f1a CD	277
fc5d1f1a CD	278	unsigned int used_lrs;
eede821d MZ	279	};
eede821d MZ	280
b2fb1c0d	281	struct vgic_v3_cpu_if {
b2fb1c0d MZ	282	u32 vgic_hcr;
b2fb1c0d MZ	283	u32 vgic_vmcr;
2f5fa41a	284	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	285	u32 vgic_ap0r[4];
	286	u32 vgic_ap1r[4];
	287	u64 vgic_lr[VGIC_V3_MAX_LRS];
74fe55dc MZ	288
	289	/*
	290	* GICv4 ITS per-VPE data, containing the doorbell IRQ, the
	291	* pending table pointer, the its_vm pointer and a few other
	292	* HW specific things. As for the its_vm structure, this is
	293	* linking the Linux IRQ subsystem and the ITS together.
	294	*/
	295	struct its_vpe its_vpe;
fc5d1f1a CD	296
fc5d1f1a CD	297	unsigned int used_lrs;
b2fb1c0d MZ	298	};
b2fb1c0d MZ	299
1a89dd91	300	struct vgic_cpu {
9d949dce	301	/* CPU vif control registers for world switch */
eede821d MZ	302	union {
eede821d MZ	303	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	304	struct vgic_v3_cpu_if vgic_v3;
eede821d	305	};
6c3d63c9	306
50926d82	307	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
1a89dd91	308
e08d8d29	309	raw_spinlock_t ap_list_lock; /* Protects the ap_list */
9d949dce	310
50926d82 MZ	311	/*
	312	* List of IRQs that this VCPU should consider because they are either
	313	* Active or Pending (hence the name; AP list), or because they recently
	314	* were one of the two and need to be migrated off this list to another
	315	* VCPU.
	316	*/
	317	struct list_head ap_list_head;
495dd859	318
8f6cdc1c AP	319	/*
	320	* Members below are used with GICv3 emulation only and represent
	321	* parts of the redistributor.
	322	*/
	323	struct vgic_io_device rd_iodev;
dbd9733a	324	struct vgic_redist_region *rdreg;
0aa1de57 AP	325
	326	/* Contains the attributes and gpa of the LPI pending tables. */
	327	u64 pendbaser;
	328
	329	bool lpis_enabled;
d017d7b0 VK	330
	331	/* Cache guest priority bits */
	332	u32 num_pri_bits;
	333
	334	/* Cache guest interrupt ID bits */
	335	u32 num_id_bits;
50926d82	336	};
1a89dd91	337
fb5ee369	338	extern struct static_key_false vgic_v2_cpuif_trap;
59da1cbf	339	extern struct static_key_false vgic_v3_cpuif_trap;
fb5ee369	340
ce01e4e8	341	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
6c3d63c9	342	void kvm_vgic_early_init(struct kvm *kvm);
1aab6f46	343	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
59892136	344	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	345	void kvm_vgic_destroy(struct kvm *kvm);
c1bfb577	346	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
50926d82 MZ	347	int kvm_vgic_map_resources(struct kvm *kvm);
50926d82 MZ	348	int kvm_vgic_hyp_init(void);
5b0d2cc2	349	void kvm_vgic_init_cpu_hardware(void);
50926d82 MZ	350
50926d82 MZ	351	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
cb3f0ad8	352	bool level, void *owner);
47bbd31f	353	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
b6909a65	354	u32 vintid, bool (*get_input_level)(int vindid));
47bbd31f EA	355	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
47bbd31f EA	356	bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
1a89dd91	357
50926d82 MZ	358	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
50926d82 MZ	359
328e5664 CD	360	void kvm_vgic_load(struct kvm_vcpu *vcpu);
328e5664 CD	361	void kvm_vgic_put(struct kvm_vcpu *vcpu);
5eeaf10e	362	void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu);
328e5664	363
f982cf4e	364	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
50926d82	365	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
c52edf5f	366	#define vgic_ready(k) ((k)->arch.vgic.ready)
2defaff4	367	#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
50926d82 MZ	368	((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	369
	370	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
	371	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
	372	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
413aa807	373	void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
9d949dce	374
6249f2a4	375	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1);
8f186d52	376
50926d82 MZ	377	/**
	378	* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
	379	*
	380	* The host's GIC naturally limits the maximum amount of VCPUs a guest
	381	* can use.
	382	*/
	383	static inline int kvm_vgic_get_max_vcpus(void)
	384	{
	385	return kvm_vgic_global_state.max_gic_vcpus;
	386	}
	387
180ae7b1 EA	388	/**
	389	* kvm_vgic_setup_default_irq_routing:
	390	* Setup a default flat gsi routing table mapping all SPIs
	391	*/
	392	int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
	393
c6ccd30e CD	394	int kvm_vgic_set_owner(struct kvm_vcpu vcpu, unsigned int intid, void owner);
c6ccd30e CD	395
196b1364 MZ	396	struct kvm_kernel_irq_routing_entry;
	397
	398	int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
	399	struct kvm_kernel_irq_routing_entry *irq_entry);
	400
	401	int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
	402	struct kvm_kernel_irq_routing_entry *irq_entry);
	403
8e01d9a3	404	int vgic_v4_load(struct kvm_vcpu *vcpu);
57e3cebd	405	void vgic_v4_commit(struct kvm_vcpu *vcpu);
8e01d9a3	406	int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db);
df9ba959	407
50926d82	408	#endif /* __KVM_ARM_VGIC_H */