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spi: davinci: enable GPIO lines to be used as chip selects
[linux.git] / drivers / spi / davinci_spi.c
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358934a6
SP		 1/*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/dma-mapping.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
5a0e3ad6 30#include <linux/slab.h>
358934a6
SP		 31
32#include <mach/spi.h>
33#include <mach/edma.h>
34
35#define SPI_NO_RESOURCE ((resource_size_t)-1)
36
37#define SPI_MAX_CHIPSELECT 2
38
39#define CS_DEFAULT 0xFF
40
41#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
42#define DAVINCI_DMA_DATA_TYPE_S8 0x01
43#define DAVINCI_DMA_DATA_TYPE_S16 0x02
44#define DAVINCI_DMA_DATA_TYPE_S32 0x04
45
46#define SPIFMT_PHASE_MASK BIT(16)
47#define SPIFMT_POLARITY_MASK BIT(17)
48#define SPIFMT_DISTIMER_MASK BIT(18)
49#define SPIFMT_SHIFTDIR_MASK BIT(20)
50#define SPIFMT_WAITENA_MASK BIT(21)
51#define SPIFMT_PARITYENA_MASK BIT(22)
52#define SPIFMT_ODD_PARITY_MASK BIT(23)
53#define SPIFMT_WDELAY_MASK 0x3f000000u
54#define SPIFMT_WDELAY_SHIFT 24
55#define SPIFMT_CHARLEN_MASK 0x0000001Fu
56
358934a6
SP		 57
58/* SPIPC0 */
59#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
60#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
61#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
62#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
358934a6
SP		 63
64#define SPIINT_MASKALL 0x0101035F
65#define SPI_INTLVL_1 0x000001FFu
66#define SPI_INTLVL_0 0x00000000u
67
cfbc5d1d
BN		 68/* SPIDAT1 (upper 16 bit defines) */
69#define SPIDAT1_CSHOLD_MASK BIT(12)
70
71/* SPIGCR1 */
358934a6
SP		 72#define SPIGCR1_CLKMOD_MASK BIT(1)
73#define SPIGCR1_MASTER_MASK BIT(0)
74#define SPIGCR1_LOOPBACK_MASK BIT(16)
8e206f1c 75#define SPIGCR1_SPIENA_MASK BIT(24)
358934a6
SP		 76
77/* SPIBUF */
78#define SPIBUF_TXFULL_MASK BIT(29)
79#define SPIBUF_RXEMPTY_MASK BIT(31)
80
81/* Error Masks */
82#define SPIFLG_DLEN_ERR_MASK BIT(0)
83#define SPIFLG_TIMEOUT_MASK BIT(1)
84#define SPIFLG_PARERR_MASK BIT(2)
85#define SPIFLG_DESYNC_MASK BIT(3)
86#define SPIFLG_BITERR_MASK BIT(4)
87#define SPIFLG_OVRRUN_MASK BIT(6)
88#define SPIFLG_RX_INTR_MASK BIT(8)
89#define SPIFLG_TX_INTR_MASK BIT(9)
90#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
8e206f1c 91
358934a6
SP		 92#define SPIINT_BITERR_INTR BIT(4)
93#define SPIINT_OVRRUN_INTR BIT(6)
94#define SPIINT_RX_INTR BIT(8)
95#define SPIINT_TX_INTR BIT(9)
96#define SPIINT_DMA_REQ_EN BIT(16)
358934a6
SP		 97
98#define SPI_T2CDELAY_SHIFT 16
99#define SPI_C2TDELAY_SHIFT 24
100
101/* SPI Controller registers */
102#define SPIGCR0 0x00
103#define SPIGCR1 0x04
104#define SPIINT 0x08
105#define SPILVL 0x0c
106#define SPIFLG 0x10
107#define SPIPC0 0x14
358934a6
SP		 108#define SPIDAT1 0x3c
109#define SPIBUF 0x40
358934a6
SP		 110#define SPIDELAY 0x48
111#define SPIDEF 0x4c
112#define SPIFMT0 0x50
358934a6
SP		 113
114struct davinci_spi_slave {
115 u32 cmd_to_write;
116 u32 clk_ctrl_to_write;
117 u32 bytes_per_word;
118 u8 active_cs;
119};
120
121/* We have 2 DMA channels per CS, one for RX and one for TX */
122struct davinci_spi_dma {
123 int dma_tx_channel;
124 int dma_rx_channel;
125 int dma_tx_sync_dev;
126 int dma_rx_sync_dev;
127 enum dma_event_q eventq;
128
129 struct completion dma_tx_completion;
130 struct completion dma_rx_completion;
131};
132
133/* SPI Controller driver's private data. */
134struct davinci_spi {
135 struct spi_bitbang bitbang;
136 struct clk *clk;
137
138 u8 version;
139 resource_size_t pbase;
140 void __iomem *base;
141 size_t region_size;
142 u32 irq;
143 struct completion done;
144
145 const void *tx;
146 void *rx;
147 u8 *tmp_buf;
148 int count;
149 struct davinci_spi_dma *dma_channels;
778e261e 150 struct davinci_spi_platform_data *pdata;
358934a6
SP		 151
152 void (*get_rx)(u32 rx_data, struct davinci_spi *);
153 u32 (*get_tx)(struct davinci_spi *);
154
155 struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
156};
157
158static unsigned use_dma;
159
160static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
161{
162 u8 *rx = davinci_spi->rx;
163
164 *rx++ = (u8)data;
165 davinci_spi->rx = rx;
166}
167
168static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
169{
170 u16 *rx = davinci_spi->rx;
171
172 *rx++ = (u16)data;
173 davinci_spi->rx = rx;
174}
175
176static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
177{
178 u32 data;
179 const u8 *tx = davinci_spi->tx;
180
181 data = *tx++;
182 davinci_spi->tx = tx;
183 return data;
184}
185
186static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
187{
188 u32 data;
189 const u16 *tx = davinci_spi->tx;
190
191 data = *tx++;
192 davinci_spi->tx = tx;
193 return data;
194}
195
196static inline void set_io_bits(void __iomem *addr, u32 bits)
197{
198 u32 v = ioread32(addr);
199
200 v |= bits;
201 iowrite32(v, addr);
202}
203
204static inline void clear_io_bits(void __iomem *addr, u32 bits)
205{
206 u32 v = ioread32(addr);
207
208 v &= ~bits;
209 iowrite32(v, addr);
210}
211
212static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
213{
214 set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
215}
216
217static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
218{
219 clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
220}
221
222static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
223{
224 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
225
226 if (enable)
227 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
228 else
229 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
230}
231
232/*
233 * Interface to control the chip select signal
234 */
235static void davinci_spi_chipselect(struct spi_device *spi, int value)
236{
237 struct davinci_spi *davinci_spi;
238 struct davinci_spi_platform_data *pdata;
7978b8c3 239 u8 chip_sel = spi->chip_select;
cfbc5d1d 240 u16 spidat1_cfg = CS_DEFAULT;
23853973 241 bool gpio_chipsel = false;
358934a6
SP		 242
243 davinci_spi = spi_master_get_devdata(spi->master);
244 pdata = davinci_spi->pdata;
245
23853973
BN		 246 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
247 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
248 gpio_chipsel = true;
249
358934a6
SP		 250 /*
251 * Board specific chip select logic decides the polarity and cs
252 * line for the controller
253 */
23853973
BN		 254 if (gpio_chipsel) {
255 if (value == BITBANG_CS_ACTIVE)
256 gpio_set_value(pdata->chip_sel[chip_sel], 0);
257 else
258 gpio_set_value(pdata->chip_sel[chip_sel], 1);
259 } else {
260 if (value == BITBANG_CS_ACTIVE) {
261 spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
262 spidat1_cfg &= ~(0x1 << chip_sel);
263 }
7978b8c3 264
23853973
BN		 265 iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
266 }
358934a6
SP		 267}
268
269/**
270 * davinci_spi_setup_transfer - This functions will determine transfer method
271 * @spi: spi device on which data transfer to be done
272 * @t: spi transfer in which transfer info is filled
273 *
274 * This function determines data transfer method (8/16/32 bit transfer).
275 * It will also set the SPI Clock Control register according to
276 * SPI slave device freq.
277 */
278static int davinci_spi_setup_transfer(struct spi_device *spi,
279 struct spi_transfer *t)
280{
281
282 struct davinci_spi *davinci_spi;
358934a6 283 u8 bits_per_word = 0;
0c2a2ae3 284 u32 hz = 0, prescale = 0, clkspeed;
358934a6
SP		 285
286 davinci_spi = spi_master_get_devdata(spi->master);
358934a6
SP		 287
288 if (t) {
289 bits_per_word = t->bits_per_word;
290 hz = t->speed_hz;
291 }
292
293 /* if bits_per_word is not set then set it default */
294 if (!bits_per_word)
295 bits_per_word = spi->bits_per_word;
296
297 /*
298 * Assign function pointer to appropriate transfer method
299 * 8bit, 16bit or 32bit transfer
300 */
301 if (bits_per_word <= 8 && bits_per_word >= 2) {
302 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
303 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
304 davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
305 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
306 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
307 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
308 davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
309 } else
310 return -EINVAL;
311
312 if (!hz)
313 hz = spi->max_speed_hz;
314
315 clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
316 spi->chip_select);
317 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
318 spi->chip_select);
319
0c2a2ae3
TK		 320 clkspeed = clk_get_rate(davinci_spi->clk);
321 if (hz > clkspeed / 2)
322 prescale = 1 << 8;
323 if (hz < clkspeed / 256)
324 prescale = 255 << 8;
325 if (!prescale)
326 prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
358934a6
SP		 327
328 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
0c2a2ae3 329 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
358934a6
SP		 330
331 return 0;
332}
333
334static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
335{
336 struct spi_device *spi = (struct spi_device *)data;
337 struct davinci_spi *davinci_spi;
338 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 339
340 davinci_spi = spi_master_get_devdata(spi->master);
341 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 342
343 if (ch_status == DMA_COMPLETE)
344 edma_stop(davinci_spi_dma->dma_rx_channel);
345 else
346 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
347
348 complete(&davinci_spi_dma->dma_rx_completion);
349 /* We must disable the DMA RX request */
350 davinci_spi_set_dma_req(spi, 0);
351}
352
353static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
354{
355 struct spi_device *spi = (struct spi_device *)data;
356 struct davinci_spi *davinci_spi;
357 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 358
359 davinci_spi = spi_master_get_devdata(spi->master);
360 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 361
362 if (ch_status == DMA_COMPLETE)
363 edma_stop(davinci_spi_dma->dma_tx_channel);
364 else
365 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
366
367 complete(&davinci_spi_dma->dma_tx_completion);
368 /* We must disable the DMA TX request */
369 davinci_spi_set_dma_req(spi, 0);
370}
371
372static int davinci_spi_request_dma(struct spi_device *spi)
373{
374 struct davinci_spi *davinci_spi;
375 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 376 struct device *sdev;
377 int r;
378
379 davinci_spi = spi_master_get_devdata(spi->master);
380 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
358934a6
SP		 381 sdev = davinci_spi->bitbang.master->dev.parent;
382
383 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
384 davinci_spi_dma_rx_callback, spi,
385 davinci_spi_dma->eventq);
386 if (r < 0) {
387 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
388 return -EAGAIN;
389 }
390 davinci_spi_dma->dma_rx_channel = r;
391 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
392 davinci_spi_dma_tx_callback, spi,
393 davinci_spi_dma->eventq);
394 if (r < 0) {
395 edma_free_channel(davinci_spi_dma->dma_rx_channel);
396 davinci_spi_dma->dma_rx_channel = -1;
397 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
398 return -EAGAIN;
399 }
400 davinci_spi_dma->dma_tx_channel = r;
401
402 return 0;
403}
404
405/**
406 * davinci_spi_setup - This functions will set default transfer method
407 * @spi: spi device on which data transfer to be done
408 *
409 * This functions sets the default transfer method.
410 */
358934a6
SP		 411static int davinci_spi_setup(struct spi_device *spi)
412{
413 int retval;
414 struct davinci_spi *davinci_spi;
415 struct davinci_spi_dma *davinci_spi_dma;
416 struct device *sdev;
417
418 davinci_spi = spi_master_get_devdata(spi->master);
419 sdev = davinci_spi->bitbang.master->dev.parent;
420
421 /* if bits per word length is zero then set it default 8 */
422 if (!spi->bits_per_word)
423 spi->bits_per_word = 8;
424
425 davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
426
427 if (use_dma && davinci_spi->dma_channels) {
428 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
429
430 if ((davinci_spi_dma->dma_rx_channel == -1)
431 || (davinci_spi_dma->dma_tx_channel == -1)) {
432 retval = davinci_spi_request_dma(spi);
433 if (retval < 0)
434 return retval;
435 }
436 }
437
438 /*
439 * SPI in DaVinci and DA8xx operate between
440 * 600 KHz and 50 MHz
441 */
442 if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
443 dev_dbg(sdev, "Operating frequency is not in acceptable "
444 "range\n");
445 return -EINVAL;
446 }
447
448 /*
449 * Set up SPIFMTn register, unique to this chipselect.
450 *
451 * NOTE: we could do all of these with one write. Also, some
452 * of the "version 2" features are found in chips that don't
453 * support all of them...
454 */
455 if (spi->mode & SPI_LSB_FIRST)
456 set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
457 spi->chip_select);
458 else
459 clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
460 spi->chip_select);
461
462 if (spi->mode & SPI_CPOL)
463 set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
464 spi->chip_select);
465 else
466 clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
467 spi->chip_select);
468
469 if (!(spi->mode & SPI_CPHA))
470 set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
471 spi->chip_select);
472 else
473 clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
474 spi->chip_select);
475
476 /*
477 * Version 1 hardware supports two basic SPI modes:
478 * - Standard SPI mode uses 4 pins, with chipselect
479 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
480 * (distinct from SPI_3WIRE, with just one data wire;
481 * or similar variants without MOSI or without MISO)
482 *
483 * Version 2 hardware supports an optional handshaking signal,
484 * so it can support two more modes:
485 * - 5 pin SPI variant is standard SPI plus SPI_READY
486 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
487 */
488
489 if (davinci_spi->version == SPI_VERSION_2) {
490 clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
491 spi->chip_select);
492 set_fmt_bits(davinci_spi->base,
493 (davinci_spi->pdata->wdelay
494 << SPIFMT_WDELAY_SHIFT)
495 & SPIFMT_WDELAY_MASK,
496 spi->chip_select);
497
498 if (davinci_spi->pdata->odd_parity)
499 set_fmt_bits(davinci_spi->base,
500 SPIFMT_ODD_PARITY_MASK,
501 spi->chip_select);
502 else
503 clear_fmt_bits(davinci_spi->base,
504 SPIFMT_ODD_PARITY_MASK,
505 spi->chip_select);
506
507 if (davinci_spi->pdata->parity_enable)
508 set_fmt_bits(davinci_spi->base,
509 SPIFMT_PARITYENA_MASK,
510 spi->chip_select);
511 else
512 clear_fmt_bits(davinci_spi->base,
513 SPIFMT_PARITYENA_MASK,
514 spi->chip_select);
515
516 if (davinci_spi->pdata->wait_enable)
517 set_fmt_bits(davinci_spi->base,
518 SPIFMT_WAITENA_MASK,
519 spi->chip_select);
520 else
521 clear_fmt_bits(davinci_spi->base,
522 SPIFMT_WAITENA_MASK,
523 spi->chip_select);
524
525 if (davinci_spi->pdata->timer_disable)
526 set_fmt_bits(davinci_spi->base,
527 SPIFMT_DISTIMER_MASK,
528 spi->chip_select);
529 else
530 clear_fmt_bits(davinci_spi->base,
531 SPIFMT_DISTIMER_MASK,
532 spi->chip_select);
533 }
534
535 retval = davinci_spi_setup_transfer(spi, NULL);
536
537 return retval;
538}
539
540static void davinci_spi_cleanup(struct spi_device *spi)
541{
542 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
543 struct davinci_spi_dma *davinci_spi_dma;
544
545 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
546
547 if (use_dma && davinci_spi->dma_channels) {
548 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
549
550 if ((davinci_spi_dma->dma_rx_channel != -1)
551 && (davinci_spi_dma->dma_tx_channel != -1)) {
552 edma_free_channel(davinci_spi_dma->dma_tx_channel);
553 edma_free_channel(davinci_spi_dma->dma_rx_channel);
554 }
555 }
556}
557
558static int davinci_spi_bufs_prep(struct spi_device *spi,
559 struct davinci_spi *davinci_spi)
560{
23853973 561 struct davinci_spi_platform_data *pdata;
358934a6
SP		 562 int op_mode = 0;
563
564 /*
565 * REVISIT unless devices disagree about SPI_LOOP or
566 * SPI_READY (SPI_NO_CS only allows one device!), this
567 * should not need to be done before each message...
568 * optimize for both flags staying cleared.
569 */
570
571 op_mode = SPIPC0_DIFUN_MASK
572 | SPIPC0_DOFUN_MASK
573 | SPIPC0_CLKFUN_MASK;
23853973
BN		 574 if (!(spi->mode & SPI_NO_CS)) {
575 pdata = davinci_spi->pdata;
576 if (!pdata->chip_sel ||
577 pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)
578 op_mode |= 1 << spi->chip_select;
579 }
358934a6
SP		 580 if (spi->mode & SPI_READY)
581 op_mode |= SPIPC0_SPIENA_MASK;
582
583 iowrite32(op_mode, davinci_spi->base + SPIPC0);
584
585 if (spi->mode & SPI_LOOP)
586 set_io_bits(davinci_spi->base + SPIGCR1,
587 SPIGCR1_LOOPBACK_MASK);
588 else
589 clear_io_bits(davinci_spi->base + SPIGCR1,
590 SPIGCR1_LOOPBACK_MASK);
591
592 return 0;
593}
594
595static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
596 int int_status)
597{
598 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
599
600 if (int_status & SPIFLG_TIMEOUT_MASK) {
601 dev_dbg(sdev, "SPI Time-out Error\n");
602 return -ETIMEDOUT;
603 }
604 if (int_status & SPIFLG_DESYNC_MASK) {
605 dev_dbg(sdev, "SPI Desynchronization Error\n");
606 return -EIO;
607 }
608 if (int_status & SPIFLG_BITERR_MASK) {
609 dev_dbg(sdev, "SPI Bit error\n");
610 return -EIO;
611 }
612
613 if (davinci_spi->version == SPI_VERSION_2) {
614 if (int_status & SPIFLG_DLEN_ERR_MASK) {
615 dev_dbg(sdev, "SPI Data Length Error\n");
616 return -EIO;
617 }
618 if (int_status & SPIFLG_PARERR_MASK) {
619 dev_dbg(sdev, "SPI Parity Error\n");
620 return -EIO;
621 }
622 if (int_status & SPIFLG_OVRRUN_MASK) {
623 dev_dbg(sdev, "SPI Data Overrun error\n");
624 return -EIO;
625 }
626 if (int_status & SPIFLG_TX_INTR_MASK) {
627 dev_dbg(sdev, "SPI TX intr bit set\n");
628 return -EIO;
629 }
630 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
631 dev_dbg(sdev, "SPI Buffer Init Active\n");
632 return -EBUSY;
633 }
634 }
635
636 return 0;
637}
638
639/**
640 * davinci_spi_bufs - functions which will handle transfer data
641 * @spi: spi device on which data transfer to be done
642 * @t: spi transfer in which transfer info is filled
643 *
644 * This function will put data to be transferred into data register
645 * of SPI controller and then wait until the completion will be marked
646 * by the IRQ Handler.
647 */
648static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
649{
650 struct davinci_spi *davinci_spi;
651 int int_status, count, ret;
7978b8c3 652 u8 conv;
358934a6
SP		 653 u32 tx_data, data1_reg_val;
654 u32 buf_val, flg_val;
655 struct davinci_spi_platform_data *pdata;
656
657 davinci_spi = spi_master_get_devdata(spi->master);
658 pdata = davinci_spi->pdata;
659
660 davinci_spi->tx = t->tx_buf;
661 davinci_spi->rx = t->rx_buf;
662
663 /* convert len to words based on bits_per_word */
664 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
665 davinci_spi->count = t->len / conv;
666
7978b8c3
BN		 667 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
668
358934a6
SP		 669 INIT_COMPLETION(davinci_spi->done);
670
671 ret = davinci_spi_bufs_prep(spi, davinci_spi);
672 if (ret)
673 return ret;
674
675 /* Enable SPI */
676 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
677
678 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
679 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
680 davinci_spi->base + SPIDELAY);
681
682 count = davinci_spi->count;
358934a6
SP		 683
684 /* Determine the command to execute READ or WRITE */
685 if (t->tx_buf) {
686 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
687
688 while (1) {
689 tx_data = davinci_spi->get_tx(davinci_spi);
690
691 data1_reg_val &= ~(0xFFFF);
692 data1_reg_val |= (0xFFFF & tx_data);
693
694 buf_val = ioread32(davinci_spi->base + SPIBUF);
695 if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
696 iowrite32(data1_reg_val,
697 davinci_spi->base + SPIDAT1);
698
699 count--;
700 }
701 while (ioread32(davinci_spi->base + SPIBUF)
702 & SPIBUF_RXEMPTY_MASK)
703 cpu_relax();
704
705 /* getting the returned byte */
706 if (t->rx_buf) {
707 buf_val = ioread32(davinci_spi->base + SPIBUF);
708 davinci_spi->get_rx(buf_val, davinci_spi);
709 }
710 if (count <= 0)
711 break;
712 }
713 } else {
714 if (pdata->poll_mode) {
715 while (1) {
716 /* keeps the serial clock going */
717 if ((ioread32(davinci_spi->base + SPIBUF)
718 & SPIBUF_TXFULL_MASK) == 0)
719 iowrite32(data1_reg_val,
720 davinci_spi->base + SPIDAT1);
721
722 while (ioread32(davinci_spi->base + SPIBUF) &
723 SPIBUF_RXEMPTY_MASK)
724 cpu_relax();
725
726 flg_val = ioread32(davinci_spi->base + SPIFLG);
727 buf_val = ioread32(davinci_spi->base + SPIBUF);
728
729 davinci_spi->get_rx(buf_val, davinci_spi);
730
731 count--;
732 if (count <= 0)
733 break;
734 }
735 } else { /* Receive in Interrupt mode */
736 int i;
737
738 for (i = 0; i < davinci_spi->count; i++) {
739 set_io_bits(davinci_spi->base + SPIINT,
740 SPIINT_BITERR_INTR
741 | SPIINT_OVRRUN_INTR
742 | SPIINT_RX_INTR);
743
744 iowrite32(data1_reg_val,
745 davinci_spi->base + SPIDAT1);
746
747 while (ioread32(davinci_spi->base + SPIINT) &
748 SPIINT_RX_INTR)
749 cpu_relax();
750 }
751 iowrite32((data1_reg_val & 0x0ffcffff),
752 davinci_spi->base + SPIDAT1);
753 }
754 }
755
756 /*
757 * Check for bit error, desync error,parity error,timeout error and
758 * receive overflow errors
759 */
760 int_status = ioread32(davinci_spi->base + SPIFLG);
761
762 ret = davinci_spi_check_error(davinci_spi, int_status);
763 if (ret != 0)
764 return ret;
765
766 /* SPI Framework maintains the count only in bytes so convert back */
767 davinci_spi->count *= conv;
768
769 return t->len;
770}
771
772#define DAVINCI_DMA_DATA_TYPE_S8 0x01
773#define DAVINCI_DMA_DATA_TYPE_S16 0x02
774#define DAVINCI_DMA_DATA_TYPE_S32 0x04
775
776static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
777{
778 struct davinci_spi *davinci_spi;
779 int int_status = 0;
780 int count, temp_count;
781 u8 conv = 1;
358934a6
SP		 782 u32 data1_reg_val;
783 struct davinci_spi_dma *davinci_spi_dma;
784 int word_len, data_type, ret;
785 unsigned long tx_reg, rx_reg;
786 struct davinci_spi_platform_data *pdata;
787 struct device *sdev;
788
789 davinci_spi = spi_master_get_devdata(spi->master);
790 pdata = davinci_spi->pdata;
791 sdev = davinci_spi->bitbang.master->dev.parent;
792
793 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
794
795 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
796 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
797
798 davinci_spi->tx = t->tx_buf;
799 davinci_spi->rx = t->rx_buf;
800
801 /* convert len to words based on bits_per_word */
802 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
803 davinci_spi->count = t->len / conv;
804
7978b8c3
BN		 805 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
806
358934a6
SP		 807 INIT_COMPLETION(davinci_spi->done);
808
809 init_completion(&davinci_spi_dma->dma_rx_completion);
810 init_completion(&davinci_spi_dma->dma_tx_completion);
811
812 word_len = conv * 8;
813
814 if (word_len <= 8)
815 data_type = DAVINCI_DMA_DATA_TYPE_S8;
816 else if (word_len <= 16)
817 data_type = DAVINCI_DMA_DATA_TYPE_S16;
818 else if (word_len <= 32)
819 data_type = DAVINCI_DMA_DATA_TYPE_S32;
820 else
821 return -EINVAL;
822
823 ret = davinci_spi_bufs_prep(spi, davinci_spi);
824 if (ret)
825 return ret;
826
827 /* Put delay val if required */
828 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
829 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
830 davinci_spi->base + SPIDELAY);
831
832 count = davinci_spi->count; /* the number of elements */
358934a6
SP		 833
834 /* disable all interrupts for dma transfers */
835 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
836 /* Disable SPI to write configuration bits in SPIDAT */
837 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
358934a6
SP		 838 /* Enable SPI */
839 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
840
358934a6
SP		 841 if (t->tx_buf) {
842 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
843 DMA_TO_DEVICE);
844 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
845 dev_dbg(sdev, "Unable to DMA map a %d bytes"
846 " TX buffer\n", count);
847 return -ENOMEM;
848 }
849 temp_count = count;
850 } else {
851 /* We need TX clocking for RX transaction */
852 t->tx_dma = dma_map_single(&spi->dev,
853 (void *)davinci_spi->tmp_buf, count + 1,
854 DMA_TO_DEVICE);
855 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
856 dev_dbg(sdev, "Unable to DMA map a %d bytes"
857 " TX tmp buffer\n", count);
858 return -ENOMEM;
859 }
860 temp_count = count + 1;
861 }
862
863 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
864 data_type, temp_count, 1, 0, ASYNC);
865 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
866 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
867 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
868 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
869
870 if (t->rx_buf) {
871 /* initiate transaction */
872 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
873
874 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
875 DMA_FROM_DEVICE);
876 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
877 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
878 count);
879 if (t->tx_buf != NULL)
880 dma_unmap_single(NULL, t->tx_dma,
881 count, DMA_TO_DEVICE);
882 return -ENOMEM;
883 }
884 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
885 data_type, count, 1, 0, ASYNC);
886 edma_set_src(davinci_spi_dma->dma_rx_channel,
887 rx_reg, INCR, W8BIT);
888 edma_set_dest(davinci_spi_dma->dma_rx_channel,
889 t->rx_dma, INCR, W8BIT);
890 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
891 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
892 data_type, 0);
893 }
894
895 if ((t->tx_buf) || (t->rx_buf))
896 edma_start(davinci_spi_dma->dma_tx_channel);
897
898 if (t->rx_buf)
899 edma_start(davinci_spi_dma->dma_rx_channel);
900
901 if ((t->rx_buf) || (t->tx_buf))
902 davinci_spi_set_dma_req(spi, 1);
903
904 if (t->tx_buf)
905 wait_for_completion_interruptible(
906 &davinci_spi_dma->dma_tx_completion);
907
908 if (t->rx_buf)
909 wait_for_completion_interruptible(
910 &davinci_spi_dma->dma_rx_completion);
911
912 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
913
914 if (t->rx_buf)
915 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
916
917 /*
918 * Check for bit error, desync error,parity error,timeout error and
919 * receive overflow errors
920 */
921 int_status = ioread32(davinci_spi->base + SPIFLG);
922
923 ret = davinci_spi_check_error(davinci_spi, int_status);
924 if (ret != 0)
925 return ret;
926
927 /* SPI Framework maintains the count only in bytes so convert back */
928 davinci_spi->count *= conv;
929
930 return t->len;
931}
932
933/**
934 * davinci_spi_irq - IRQ handler for DaVinci SPI
935 * @irq: IRQ number for this SPI Master
936 * @context_data: structure for SPI Master controller davinci_spi
937 */
938static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
939{
940 struct davinci_spi *davinci_spi = context_data;
941 u32 int_status, rx_data = 0;
942 irqreturn_t ret = IRQ_NONE;
943
944 int_status = ioread32(davinci_spi->base + SPIFLG);
945
946 while ((int_status & SPIFLG_RX_INTR_MASK)) {
947 if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
948 ret = IRQ_HANDLED;
949
950 rx_data = ioread32(davinci_spi->base + SPIBUF);
951 davinci_spi->get_rx(rx_data, davinci_spi);
952
953 /* Disable Receive Interrupt */
954 iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
955 davinci_spi->base + SPIINT);
956 } else
957 (void)davinci_spi_check_error(davinci_spi, int_status);
958
959 int_status = ioread32(davinci_spi->base + SPIFLG);
960 }
961
962 return ret;
963}
964
965/**
966 * davinci_spi_probe - probe function for SPI Master Controller
967 * @pdev: platform_device structure which contains plateform specific data
968 */
969static int davinci_spi_probe(struct platform_device *pdev)
970{
971 struct spi_master *master;
972 struct davinci_spi *davinci_spi;
973 struct davinci_spi_platform_data *pdata;
974 struct resource *r, *mem;
975 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
976 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
977 resource_size_t dma_eventq = SPI_NO_RESOURCE;
978 int i = 0, ret = 0;
979
980 pdata = pdev->dev.platform_data;
981 if (pdata == NULL) {
982 ret = -ENODEV;
983 goto err;
984 }
985
986 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
987 if (master == NULL) {
988 ret = -ENOMEM;
989 goto err;
990 }
991
992 dev_set_drvdata(&pdev->dev, master);
993
994 davinci_spi = spi_master_get_devdata(master);
995 if (davinci_spi == NULL) {
996 ret = -ENOENT;
997 goto free_master;
998 }
999
1000 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001 if (r == NULL) {
1002 ret = -ENOENT;
1003 goto free_master;
1004 }
1005
1006 davinci_spi->pbase = r->start;
1007 davinci_spi->region_size = resource_size(r);
1008 davinci_spi->pdata = pdata;
1009
1010 mem = request_mem_region(r->start, davinci_spi->region_size,
1011 pdev->name);
1012 if (mem == NULL) {
1013 ret = -EBUSY;
1014 goto free_master;
1015 }
1016
50356dd7 1017 davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
358934a6
SP		 1018 if (davinci_spi->base == NULL) {
1019 ret = -ENOMEM;
1020 goto release_region;
1021 }
1022
1023 davinci_spi->irq = platform_get_irq(pdev, 0);
1024 if (davinci_spi->irq <= 0) {
1025 ret = -EINVAL;
1026 goto unmap_io;
1027 }
1028
1029 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
1030 dev_name(&pdev->dev), davinci_spi);
1031 if (ret)
1032 goto unmap_io;
1033
1034 /* Allocate tmp_buf for tx_buf */
1035 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
1036 if (davinci_spi->tmp_buf == NULL) {
1037 ret = -ENOMEM;
1038 goto irq_free;
1039 }
1040
1041 davinci_spi->bitbang.master = spi_master_get(master);
1042 if (davinci_spi->bitbang.master == NULL) {
1043 ret = -ENODEV;
1044 goto free_tmp_buf;
1045 }
1046
1047 davinci_spi->clk = clk_get(&pdev->dev, NULL);
1048 if (IS_ERR(davinci_spi->clk)) {
1049 ret = -ENODEV;
1050 goto put_master;
1051 }
1052 clk_enable(davinci_spi->clk);
1053
358934a6
SP		 1054 master->bus_num = pdev->id;
1055 master->num_chipselect = pdata->num_chipselect;
1056 master->setup = davinci_spi_setup;
1057 master->cleanup = davinci_spi_cleanup;
1058
1059 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
1060 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1061
1062 davinci_spi->version = pdata->version;
1063 use_dma = pdata->use_dma;
1064
1065 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1066 if (davinci_spi->version == SPI_VERSION_2)
1067 davinci_spi->bitbang.flags |= SPI_READY;
1068
1069 if (use_dma) {
778e261e
BN		 1070 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1071 if (r)
1072 dma_rx_chan = r->start;
1073 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1074 if (r)
1075 dma_tx_chan = r->start;
1076 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1077 if (r)
1078 dma_eventq = r->start;
358934a6
SP		 1079 }
1080
1081 if (!use_dma ||
1082 dma_rx_chan == SPI_NO_RESOURCE ||
1083 dma_tx_chan == SPI_NO_RESOURCE ||
1084 dma_eventq == SPI_NO_RESOURCE) {
1085 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1086 use_dma = 0;
1087 } else {
1088 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1089 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1090 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
1091 if (davinci_spi->dma_channels == NULL) {
1092 ret = -ENOMEM;
1093 goto free_clk;
1094 }
1095
1096 for (i = 0; i < master->num_chipselect; i++) {
1097 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1098 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1099 dma_rx_chan;
1100 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1101 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1102 dma_tx_chan;
1103 davinci_spi->dma_channels[i].eventq = dma_eventq;
1104 }
1105 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1106 "Using RX channel = %d , TX channel = %d and "
1107 "event queue = %d", dma_rx_chan, dma_tx_chan,
1108 dma_eventq);
1109 }
1110
1111 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1112 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1113
1114 init_completion(&davinci_spi->done);
1115
1116 /* Reset In/OUT SPI module */
1117 iowrite32(0, davinci_spi->base + SPIGCR0);
1118 udelay(100);
1119 iowrite32(1, davinci_spi->base + SPIGCR0);
1120
23853973
BN		 1121 /* initialize chip selects */
1122 if (pdata->chip_sel) {
1123 for (i = 0; i < pdata->num_chipselect; i++) {
1124 if (pdata->chip_sel[i] != SPI_INTERN_CS)
1125 gpio_direction_output(pdata->chip_sel[i], 1);
1126 }
1127 }
1128
358934a6
SP		 1129 /* Clock internal */
1130 if (davinci_spi->pdata->clk_internal)
1131 set_io_bits(davinci_spi->base + SPIGCR1,
1132 SPIGCR1_CLKMOD_MASK);
1133 else
1134 clear_io_bits(davinci_spi->base + SPIGCR1,
1135 SPIGCR1_CLKMOD_MASK);
1136
843a713b
BN		 1137 iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
1138
358934a6
SP		 1139 /* master mode default */
1140 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1141
1142 if (davinci_spi->pdata->intr_level)
1143 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1144 else
1145 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1146
1147 ret = spi_bitbang_start(&davinci_spi->bitbang);
1148 if (ret)
1149 goto free_clk;
1150
3b740b10 1151 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
358934a6
SP		 1152
1153 if (!pdata->poll_mode)
1154 dev_info(&pdev->dev, "Operating in interrupt mode"
1155 " using IRQ %d\n", davinci_spi->irq);
1156
1157 return ret;
1158
1159free_clk:
1160 clk_disable(davinci_spi->clk);
1161 clk_put(davinci_spi->clk);
1162put_master:
1163 spi_master_put(master);
1164free_tmp_buf:
1165 kfree(davinci_spi->tmp_buf);
1166irq_free:
1167 free_irq(davinci_spi->irq, davinci_spi);
1168unmap_io:
1169 iounmap(davinci_spi->base);
1170release_region:
1171 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1172free_master:
1173 kfree(master);
1174err:
1175 return ret;
1176}
1177
1178/**
1179 * davinci_spi_remove - remove function for SPI Master Controller
1180 * @pdev: platform_device structure which contains plateform specific data
1181 *
1182 * This function will do the reverse action of davinci_spi_probe function
1183 * It will free the IRQ and SPI controller's memory region.
1184 * It will also call spi_bitbang_stop to destroy the work queue which was
1185 * created by spi_bitbang_start.
1186 */
1187static int __exit davinci_spi_remove(struct platform_device *pdev)
1188{
1189 struct davinci_spi *davinci_spi;
1190 struct spi_master *master;
1191
1192 master = dev_get_drvdata(&pdev->dev);
1193 davinci_spi = spi_master_get_devdata(master);
1194
1195 spi_bitbang_stop(&davinci_spi->bitbang);
1196
1197 clk_disable(davinci_spi->clk);
1198 clk_put(davinci_spi->clk);
1199 spi_master_put(master);
1200 kfree(davinci_spi->tmp_buf);
1201 free_irq(davinci_spi->irq, davinci_spi);
1202 iounmap(davinci_spi->base);
1203 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1204
1205 return 0;
1206}
1207
1208static struct platform_driver davinci_spi_driver = {
1209 .driver.name = "spi_davinci",
1210 .remove = __exit_p(davinci_spi_remove),
1211};
1212
1213static int __init davinci_spi_init(void)
1214{
1215 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1216}
1217module_init(davinci_spi_init);
1218
1219static void __exit davinci_spi_exit(void)
1220{
1221 platform_driver_unregister(&davinci_spi_driver);
1222}
1223module_exit(davinci_spi_exit);
1224
1225MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1226MODULE_LICENSE("GPL");
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