[linux.git] / drivers / clk / clk-clps711x.c

/*
 *  Cirrus Logic CLPS711X CLK driver
 *
 *  Copyright (C) 2014 Alexander Shiyan <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon/clps711x.h>

#include <dt-bindings/clock/clps711x-clock.h>

#define CLPS711X_SYSCON1	(0x0100)
#define CLPS711X_SYSCON2	(0x1100)
#define CLPS711X_SYSFLG2	(CLPS711X_SYSCON2 + SYSFLG_OFFSET)
#define CLPS711X_PLLR		(0xa5a8)

#define CLPS711X_EXT_FREQ	(13000000)
#define CLPS711X_OSC_FREQ	(3686400)

static const struct clk_div_table spi_div_table[] = {
	{ .val = 0, .div = 32, },
	{ .val = 1, .div = 8, },
	{ .val = 2, .div = 2, },
	{ .val = 3, .div = 1, },
};

static const struct clk_div_table timer_div_table[] = {
	{ .val = 0, .div = 256, },
	{ .val = 1, .div = 1, },
};

struct clps711x_clk {
	spinlock_t			lock;
	struct clk_hw_onecell_data	clk_data;
};

static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,
						       u32 fref)
{
	u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi;
	struct clps711x_clk *clps711x_clk;
	unsigned i;

	if (!base)
		return ERR_PTR(-ENOMEM);

	clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
					   CLPS711X_CLK_MAX),
			       GFP_KERNEL);
	if (!clps711x_clk)
		return ERR_PTR(-ENOMEM);

	spin_lock_init(&clps711x_clk->lock);

	/* Read PLL multiplier value and sanity check */
	tmp = readl(base + CLPS711X_PLLR) >> 24;
	if (((tmp >= 10) && (tmp <= 50)) || !fref)
		f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
	else
		f_pll = fref;

	tmp = readl(base + CLPS711X_SYSFLG2);
	if (tmp & SYSFLG2_CKMODE) {
		f_cpu = CLPS711X_EXT_FREQ;
		f_bus = CLPS711X_EXT_FREQ;
		f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
		f_pll = 0;
		f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
	} else {
		f_cpu = f_pll;
		if (f_cpu > 36864000)
			f_bus = DIV_ROUND_UP(f_cpu, 2);
		else
			f_bus = 36864000 / 2;
		f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
		f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
	}

	if (tmp & SYSFLG2_CKMODE) {
		if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
			f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
		else
			f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
	} else
		f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);

	tmp = readl(base + CLPS711X_SYSCON1);
	/* Timer1 in free running mode.
	 * Counter will wrap around to 0xffff when it underflows
	 * and will continue to count down.
	 */
	tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
	/* Timer2 in prescale mode.
	 * Value writen is automatically re-loaded when
	 * the counter underflows.
	 */
	tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
	writel(tmp, base + CLPS711X_SYSCON1);

	clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
		clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
		clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
		clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
		clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
		clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
		clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
					   base + CLPS711X_SYSCON1, 5, 1, 0,
					   timer_div_table, &clps711x_clk->lock);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
		clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
					   base + CLPS711X_SYSCON1, 7, 1, 0,
					   timer_div_table, &clps711x_clk->lock);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
		clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
		clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
		clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
					   base + CLPS711X_SYSCON1, 16, 2, 0,
					   spi_div_table, &clps711x_clk->lock);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
		clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
	clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
		clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
	for (i = 0; i < CLPS711X_CLK_MAX; i++)
		if (IS_ERR(clps711x_clk->clk_data.hws[i]))
			pr_err("clk %i: register failed with %ld\n",
			       i, PTR_ERR(clps711x_clk->clk_data.hws[i]));

	return clps711x_clk;
}

void __init clps711x_clk_init(void __iomem *base)
{
	struct clps711x_clk *clps711x_clk;

	clps711x_clk = _clps711x_clk_init(base, 73728000);

	BUG_ON(IS_ERR(clps711x_clk));

	/* Clocksource */
	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1],
			    NULL, "clps711x-timer.0");
	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2],
			    NULL, "clps711x-timer.1");

	/* Drivers */
	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM],
			    NULL, "clps711x-pwm");
	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
			    NULL, "clps711x-uart.0");
	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
			    NULL, "clps711x-uart.1");
}

#ifdef CONFIG_OF
static void __init clps711x_clk_init_dt(struct device_node *np)
{
	void __iomem *base = of_iomap(np, 0);
	struct clps711x_clk *clps711x_clk;
	u32 fref = 0;

	WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));

	clps711x_clk = _clps711x_clk_init(base, fref);
	BUG_ON(IS_ERR(clps711x_clk));

	clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
	of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
			       &clps711x_clk->clk_data);
}
CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
#endif
Commit	Line	Data
631c5347 AS	1	/*
	2	* Cirrus Logic CLPS711X CLK driver
	3	*
	4	* Copyright (C) 2014 Alexander Shiyan <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
631c5347 AS	12	#include <linux/clk-provider.h>
	13	#include <linux/clkdev.h>
	14	#include <linux/io.h>
	15	#include <linux/ioport.h>
	16	#include <linux/of_address.h>
	17	#include <linux/slab.h>
	18	#include <linux/mfd/syscon/clps711x.h>
	19
	20	#include <dt-bindings/clock/clps711x-clock.h>
	21
	22	#define CLPS711X_SYSCON1 (0x0100)
	23	#define CLPS711X_SYSCON2 (0x1100)
	24	#define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
	25	#define CLPS711X_PLLR (0xa5a8)
	26
	27	#define CLPS711X_EXT_FREQ (13000000)
	28	#define CLPS711X_OSC_FREQ (3686400)
	29
	30	static const struct clk_div_table spi_div_table[] = {
	31	{ .val = 0, .div = 32, },
	32	{ .val = 1, .div = 8, },
	33	{ .val = 2, .div = 2, },
	34	{ .val = 3, .div = 1, },
	35	};
	36
	37	static const struct clk_div_table timer_div_table[] = {
	38	{ .val = 0, .div = 256, },
	39	{ .val = 1, .div = 1, },
	40	};
	41
	42	struct clps711x_clk {
f48d947a SB	43	spinlock_t lock;
f48d947a SB	44	struct clk_hw_onecell_data clk_data;
631c5347 AS	45	};
	46
	47	static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,
	48	u32 fref)
	49	{
	50	u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi;
	51	struct clps711x_clk *clps711x_clk;
	52	unsigned i;
	53
	54	if (!base)
	55	return ERR_PTR(-ENOMEM);
	56
acafe7e3 KC	57	clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
	58	CLPS711X_CLK_MAX),
	59	GFP_KERNEL);
631c5347 AS	60	if (!clps711x_clk)
	61	return ERR_PTR(-ENOMEM);
	62
	63	spin_lock_init(&clps711x_clk->lock);
	64
	65	/* Read PLL multiplier value and sanity check */
	66	tmp = readl(base + CLPS711X_PLLR) >> 24;
	67	if (((tmp >= 10) && (tmp <= 50)) \|\| !fref)
	68	f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
	69	else
	70	f_pll = fref;
	71
	72	tmp = readl(base + CLPS711X_SYSFLG2);
	73	if (tmp & SYSFLG2_CKMODE) {
	74	f_cpu = CLPS711X_EXT_FREQ;
	75	f_bus = CLPS711X_EXT_FREQ;
	76	f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
	77	f_pll = 0;
	78	f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
	79	} else {
	80	f_cpu = f_pll;
	81	if (f_cpu > 36864000)
	82	f_bus = DIV_ROUND_UP(f_cpu, 2);
	83	else
	84	f_bus = 36864000 / 2;
	85	f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
	86	f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
	87	}
	88
	89	if (tmp & SYSFLG2_CKMODE) {
	90	if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
	91	f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
	92	else
	93	f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
	94	} else
	95	f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
	96
	97	tmp = readl(base + CLPS711X_SYSCON1);
	98	/* Timer1 in free running mode.
	99	* Counter will wrap around to 0xffff when it underflows
	100	* and will continue to count down.
	101	*/
	102	tmp &= ~(SYSCON1_TC1M \| SYSCON1_TC1S);
	103	/* Timer2 in prescale mode.
	104	* Value writen is automatically re-loaded when
	105	* the counter underflows.
	106	*/
	107	tmp \|= SYSCON1_TC2M \| SYSCON1_TC2S;
	108	writel(tmp, base + CLPS711X_SYSCON1);
	109
f48d947a SB	110	clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
	111	clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
	112	clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
	113	clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
	114	clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
	115	clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
	116	clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
	117	clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
	118	clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
	119	clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
	120	clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
	121	clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
631c5347 AS	122	base + CLPS711X_SYSCON1, 5, 1, 0,
631c5347 AS	123	timer_div_table, &clps711x_clk->lock);
f48d947a SB	124	clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
f48d947a SB	125	clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
631c5347 AS	126	base + CLPS711X_SYSCON1, 7, 1, 0,
631c5347 AS	127	timer_div_table, &clps711x_clk->lock);
f48d947a SB	128	clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
	129	clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
	130	clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
	131	clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
	132	clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
	133	clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
631c5347 AS	134	base + CLPS711X_SYSCON1, 16, 2, 0,
631c5347 AS	135	spi_div_table, &clps711x_clk->lock);
f48d947a SB	136	clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
	137	clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
	138	clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
	139	clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
631c5347	140	for (i = 0; i < CLPS711X_CLK_MAX; i++)
f48d947a	141	if (IS_ERR(clps711x_clk->clk_data.hws[i]))
631c5347	142	pr_err("clk %i: register failed with %ld\n",
f48d947a	143	i, PTR_ERR(clps711x_clk->clk_data.hws[i]));
631c5347 AS	144
	145	return clps711x_clk;
	146	}
	147
	148	void __init clps711x_clk_init(void __iomem *base)
	149	{
	150	struct clps711x_clk *clps711x_clk;
	151
	152	clps711x_clk = _clps711x_clk_init(base, 73728000);
	153
	154	BUG_ON(IS_ERR(clps711x_clk));
	155
	156	/* Clocksource */
f48d947a	157	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1],
631c5347	158	NULL, "clps711x-timer.0");
f48d947a	159	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2],
631c5347 AS	160	NULL, "clps711x-timer.1");
	161
	162	/* Drivers */
f48d947a	163	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM],
631c5347	164	NULL, "clps711x-pwm");
f48d947a	165	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
631c5347	166	NULL, "clps711x-uart.0");
f48d947a	167	clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
631c5347 AS	168	NULL, "clps711x-uart.1");
	169	}
	170
	171	#ifdef CONFIG_OF
	172	static void __init clps711x_clk_init_dt(struct device_node *np)
	173	{
	174	void __iomem *base = of_iomap(np, 0);
	175	struct clps711x_clk *clps711x_clk;
	176	u32 fref = 0;
	177
	178	WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
	179
	180	clps711x_clk = _clps711x_clk_init(base, fref);
	181	BUG_ON(IS_ERR(clps711x_clk));
	182
f48d947a SB	183	clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
	184	of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
	185	&clps711x_clk->clk_data);
631c5347	186	}
893b7798	187	CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
631c5347	188	#endif