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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux.git] / include / asm-powerpc / immap_qe.h
CommitLineData
98658538
LY		 1/*
2 * include/asm-powerpc/immap_qe.h
3 *
4 * QUICC Engine (QE) Internal Memory Map.
5 * The Internal Memory Map for devices with QE on them. This
6 * is the superset of all QE devices (8360, etc.).
7
8 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
9 *
10 * Authors: Shlomi Gridish <[email protected]>
11 * Li Yang <[email protected]>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _ASM_POWERPC_IMMAP_QE_H
19#define _ASM_POWERPC_IMMAP_QE_H
20#ifdef __KERNEL__
21
22#include <linux/kernel.h>
23
24#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
25
26/* QE I-RAM */
27struct qe_iram {
28 __be32 iadd; /* I-RAM Address Register */
29 __be32 idata; /* I-RAM Data Register */
30 u8 res0[0x78];
31} __attribute__ ((packed));
32
33/* QE Interrupt Controller */
34struct qe_ic_regs {
35 __be32 qicr;
36 __be32 qivec;
37 __be32 qripnr;
38 __be32 qipnr;
39 __be32 qipxcc;
40 __be32 qipycc;
41 __be32 qipwcc;
42 __be32 qipzcc;
43 __be32 qimr;
44 __be32 qrimr;
45 __be32 qicnr;
46 u8 res0[0x4];
47 __be32 qiprta;
48 __be32 qiprtb;
49 u8 res1[0x4];
50 __be32 qricr;
51 u8 res2[0x20];
52 __be32 qhivec;
53 u8 res3[0x1C];
54} __attribute__ ((packed));
55
56/* Communications Processor */
57struct cp_qe {
58 __be32 cecr; /* QE command register */
59 __be32 ceccr; /* QE controller configuration register */
60 __be32 cecdr; /* QE command data register */
61 u8 res0[0xA];
62 __be16 ceter; /* QE timer event register */
63 u8 res1[0x2];
64 __be16 cetmr; /* QE timers mask register */
65 __be32 cetscr; /* QE time-stamp timer control register */
66 __be32 cetsr1; /* QE time-stamp register 1 */
67 __be32 cetsr2; /* QE time-stamp register 2 */
68 u8 res2[0x8];
69 __be32 cevter; /* QE virtual tasks event register */
70 __be32 cevtmr; /* QE virtual tasks mask register */
71 __be16 cercr; /* QE RAM control register */
72 u8 res3[0x2];
73 u8 res4[0x24];
74 __be16 ceexe1; /* QE external request 1 event register */
75 u8 res5[0x2];
76 __be16 ceexm1; /* QE external request 1 mask register */
77 u8 res6[0x2];
78 __be16 ceexe2; /* QE external request 2 event register */
79 u8 res7[0x2];
80 __be16 ceexm2; /* QE external request 2 mask register */
81 u8 res8[0x2];
82 __be16 ceexe3; /* QE external request 3 event register */
83 u8 res9[0x2];
84 __be16 ceexm3; /* QE external request 3 mask register */
85 u8 res10[0x2];
86 __be16 ceexe4; /* QE external request 4 event register */
87 u8 res11[0x2];
88 __be16 ceexm4; /* QE external request 4 mask register */
89 u8 res12[0x2];
90 u8 res13[0x280];
91} __attribute__ ((packed));
92
93/* QE Multiplexer */
94struct qe_mux {
95 __be32 cmxgcr; /* CMX general clock route register */
96 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
97 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
98 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
99 __be32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
100 __be32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
101 __be32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
102 __be32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
103 __be32 cmxupcr; /* CMX UPC clock route register */
104 u8 res0[0x1C];
105} __attribute__ ((packed));
106
107/* QE Timers */
108struct qe_timers {
109 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
110 u8 res0[0x3];
111 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
112 u8 res1[0xB];
113 __be16 gtmdr1; /* Timer 1 mode register */
114 __be16 gtmdr2; /* Timer 2 mode register */
115 __be16 gtrfr1; /* Timer 1 reference register */
116 __be16 gtrfr2; /* Timer 2 reference register */
117 __be16 gtcpr1; /* Timer 1 capture register */
118 __be16 gtcpr2; /* Timer 2 capture register */
119 __be16 gtcnr1; /* Timer 1 counter */
120 __be16 gtcnr2; /* Timer 2 counter */
121 __be16 gtmdr3; /* Timer 3 mode register */
122 __be16 gtmdr4; /* Timer 4 mode register */
123 __be16 gtrfr3; /* Timer 3 reference register */
124 __be16 gtrfr4; /* Timer 4 reference register */
125 __be16 gtcpr3; /* Timer 3 capture register */
126 __be16 gtcpr4; /* Timer 4 capture register */
127 __be16 gtcnr3; /* Timer 3 counter */
128 __be16 gtcnr4; /* Timer 4 counter */
129 __be16 gtevr1; /* Timer 1 event register */
130 __be16 gtevr2; /* Timer 2 event register */
131 __be16 gtevr3; /* Timer 3 event register */
132 __be16 gtevr4; /* Timer 4 event register */
133 __be16 gtps; /* Timer 1 prescale register */
134 u8 res2[0x46];
135} __attribute__ ((packed));
136
137/* BRG */
138struct qe_brg {
fc9e8b4e 139 __be32 brgc[16]; /* BRG configuration registers */
98658538
LY		 140 u8 res0[0x40];
141} __attribute__ ((packed));
142
143/* SPI */
144struct spi {
145 u8 res0[0x20];
146 __be32 spmode; /* SPI mode register */
147 u8 res1[0x2];
148 u8 spie; /* SPI event register */
149 u8 res2[0x1];
150 u8 res3[0x2];
151 u8 spim; /* SPI mask register */
152 u8 res4[0x1];
153 u8 res5[0x1];
154 u8 spcom; /* SPI command register */
155 u8 res6[0x2];
156 __be32 spitd; /* SPI transmit data register (cpu mode) */
157 __be32 spird; /* SPI receive data register (cpu mode) */
158 u8 res7[0x8];
159} __attribute__ ((packed));
160
161/* SI */
162struct si1 {
163 __be16 siamr1; /* SI1 TDMA mode register */
164 __be16 sibmr1; /* SI1 TDMB mode register */
165 __be16 sicmr1; /* SI1 TDMC mode register */
166 __be16 sidmr1; /* SI1 TDMD mode register */
167 u8 siglmr1_h; /* SI1 global mode register high */
168 u8 res0[0x1];
169 u8 sicmdr1_h; /* SI1 command register high */
170 u8 res2[0x1];
171 u8 sistr1_h; /* SI1 status register high */
172 u8 res3[0x1];
173 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
174 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
175 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
176 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
177 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
178 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
179 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
180 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
181 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
182 u8 res4[0x8];
183 __be16 siemr1; /* SI1 TDME mode register 16 bits */
184 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
185 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
186 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
187 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
188 u8 res5[0x1];
189 u8 sicmdr1_l; /* SI1 command register low 8 bits */
190 u8 res6[0x1];
191 u8 sistr1_l; /* SI1 status register low 8 bits */
192 u8 res7[0x1];
193 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
194 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
195 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
196 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
197 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
198 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
199 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
200 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
201 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
202 u8 res8[0x8];
203 __be32 siml1; /* SI1 multiframe limit register */
204 u8 siedm1; /* SI1 extended diagnostic mode register */
205 u8 res9[0xBB];
206} __attribute__ ((packed));
207
208/* SI Routing Tables */
209struct sir {
210 u8 tx[0x400];
211 u8 rx[0x400];
212 u8 res0[0x800];
213} __attribute__ ((packed));
214
215/* USB Controller */
216struct usb_ctlr {
217 u8 usb_usmod;
218 u8 usb_usadr;
219 u8 usb_uscom;
220 u8 res1[1];
221 __be16 usb_usep1;
222 __be16 usb_usep2;
223 __be16 usb_usep3;
224 __be16 usb_usep4;
225 u8 res2[4];
226 __be16 usb_usber;
227 u8 res3[2];
228 __be16 usb_usbmr;
229 u8 res4[1];
230 u8 usb_usbs;
231 __be16 usb_ussft;
232 u8 res5[2];
233 __be16 usb_usfrn;
234 u8 res6[0x22];
235} __attribute__ ((packed));
236
237/* MCC */
238struct mcc {
239 __be32 mcce; /* MCC event register */
240 __be32 mccm; /* MCC mask register */
241 __be32 mccf; /* MCC configuration register */
242 __be32 merl; /* MCC emergency request level register */
243 u8 res0[0xF0];
244} __attribute__ ((packed));
245
246/* QE UCC Slow */
247struct ucc_slow {
248 __be32 gumr_l; /* UCCx general mode register (low) */
249 __be32 gumr_h; /* UCCx general mode register (high) */
250 __be16 upsmr; /* UCCx protocol-specific mode register */
251 u8 res0[0x2];
252 __be16 utodr; /* UCCx transmit on demand register */
253 __be16 udsr; /* UCCx data synchronization register */
254 __be16 ucce; /* UCCx event register */
255 u8 res1[0x2];
256 __be16 uccm; /* UCCx mask register */
257 u8 res2[0x1];
258 u8 uccs; /* UCCx status register */
259 u8 res3[0x24];
260 __be16 utpt;
297640e8 261 u8 res4[0x52];
98658538 262 u8 guemr; /* UCC general extended mode register */
297640e8 263 u8 res5[0x200 - 0x091];
98658538
LY		 264} __attribute__ ((packed));
265
266/* QE UCC Fast */
267struct ucc_fast {
268 __be32 gumr; /* UCCx general mode register */
269 __be32 upsmr; /* UCCx protocol-specific mode register */
270 __be16 utodr; /* UCCx transmit on demand register */
271 u8 res0[0x2];
272 __be16 udsr; /* UCCx data synchronization register */
273 u8 res1[0x2];
274 __be32 ucce; /* UCCx event register */
275 __be32 uccm; /* UCCx mask register */
276 u8 uccs; /* UCCx status register */
277 u8 res2[0x7];
278 __be32 urfb; /* UCC receive FIFO base */
279 __be16 urfs; /* UCC receive FIFO size */
280 u8 res3[0x2];
281 __be16 urfet; /* UCC receive FIFO emergency threshold */
282 __be16 urfset; /* UCC receive FIFO special emergency
283 threshold */
284 __be32 utfb; /* UCC transmit FIFO base */
285 __be16 utfs; /* UCC transmit FIFO size */
286 u8 res4[0x2];
287 __be16 utfet; /* UCC transmit FIFO emergency threshold */
288 u8 res5[0x2];
289 __be16 utftt; /* UCC transmit FIFO transmit threshold */
290 u8 res6[0x2];
291 __be16 utpt; /* UCC transmit polling timer */
292 u8 res7[0x2];
293 __be32 urtry; /* UCC retry counter register */
294 u8 res8[0x4C];
295 u8 guemr; /* UCC general extended mode register */
296 u8 res9[0x100 - 0x091];
297} __attribute__ ((packed));
298
299/* QE UCC */
300struct ucc_common {
301 u8 res1[0x90];
302 u8 guemr;
303 u8 res2[0x200 - 0x091];
304} __attribute__ ((packed));
305
306struct ucc {
307 union {
308 struct ucc_slow slow;
309 struct ucc_fast fast;
310 struct ucc_common common;
311 };
312} __attribute__ ((packed));
313
314/* MultiPHY UTOPIA POS Controllers (UPC) */
315struct upc {
316 __be32 upgcr; /* UTOPIA/POS general configuration register */
317 __be32 uplpa; /* UTOPIA/POS last PHY address */
318 __be32 uphec; /* ATM HEC register */
319 __be32 upuc; /* UTOPIA/POS UCC configuration */
320 __be32 updc1; /* UTOPIA/POS device 1 configuration */
321 __be32 updc2; /* UTOPIA/POS device 2 configuration */
322 __be32 updc3; /* UTOPIA/POS device 3 configuration */
323 __be32 updc4; /* UTOPIA/POS device 4 configuration */
324 __be32 upstpa; /* UTOPIA/POS STPA threshold */
325 u8 res0[0xC];
326 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
327 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
328 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
329 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
330 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
331 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
332 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
333 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
334 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
335 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
336 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
337 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
338 __be32 upde1; /* UTOPIA/POS device 1 event */
339 __be32 upde2; /* UTOPIA/POS device 2 event */
340 __be32 upde3; /* UTOPIA/POS device 3 event */
341 __be32 upde4; /* UTOPIA/POS device 4 event */
342 __be16 uprp1;
343 __be16 uprp2;
344 __be16 uprp3;
345 __be16 uprp4;
346 u8 res1[0x8];
347 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
348 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
349 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
350 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
351 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
352 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
353 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
354 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
355 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
356 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
357 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
358 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
359 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
360 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
361 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
362 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
363 __be32 uper1; /* Device 1 port enable register */
364 __be32 uper2; /* Device 2 port enable register */
365 __be32 uper3; /* Device 3 port enable register */
366 __be32 uper4; /* Device 4 port enable register */
367 u8 res2[0x150];
368} __attribute__ ((packed));
369
370/* SDMA */
371struct sdma {
372 __be32 sdsr; /* Serial DMA status register */
373 __be32 sdmr; /* Serial DMA mode register */
374 __be32 sdtr1; /* SDMA system bus threshold register */
375 __be32 sdtr2; /* SDMA secondary bus threshold register */
376 __be32 sdhy1; /* SDMA system bus hysteresis register */
377 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
378 __be32 sdta1; /* SDMA system bus address register */
379 __be32 sdta2; /* SDMA secondary bus address register */
380 __be32 sdtm1; /* SDMA system bus MSNUM register */
381 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
382 u8 res0[0x10];
383 __be32 sdaqr; /* SDMA address bus qualify register */
384 __be32 sdaqmr; /* SDMA address bus qualify mask register */
385 u8 res1[0x4];
386 __be32 sdebcr; /* SDMA CAM entries base register */
387 u8 res2[0x38];
388} __attribute__ ((packed));
389
390/* Debug Space */
391struct dbg {
392 __be32 bpdcr; /* Breakpoint debug command register */
393 __be32 bpdsr; /* Breakpoint debug status register */
394 __be32 bpdmr; /* Breakpoint debug mask register */
395 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
396 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
397 u8 res0[0x8];
398 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
399 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
400 u8 res1[0x8];
401 __be32 bprmir; /* Breakpoint request mode immediate register */
402 __be32 bprmsr; /* Breakpoint request mode serial register */
403 __be32 bpemr; /* Breakpoint exit mode register */
404 u8 res2[0x48];
405} __attribute__ ((packed));
406
407/* RISC Special Registers (Trap and Breakpoint) */
408struct rsp {
409 u8 fixme[0x100];
410} __attribute__ ((packed));
411
412struct qe_immap {
413 struct qe_iram iram; /* I-RAM */
414 struct qe_ic_regs ic; /* Interrupt Controller */
415 struct cp_qe cp; /* Communications Processor */
416 struct qe_mux qmx; /* QE Multiplexer */
417 struct qe_timers qet; /* QE Timers */
418 struct spi spi[0x2]; /* spi */
419 struct mcc mcc; /* mcc */
420 struct qe_brg brg; /* brg */
421 struct usb_ctlr usb; /* USB */
422 struct si1 si1; /* SI */
423 u8 res11[0x800];
424 struct sir sir; /* SI Routing Tables */
425 struct ucc ucc1; /* ucc1 */
426 struct ucc ucc3; /* ucc3 */
427 struct ucc ucc5; /* ucc5 */
428 struct ucc ucc7; /* ucc7 */
429 u8 res12[0x600];
430 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
431 struct ucc ucc2; /* ucc2 */
432 struct ucc ucc4; /* ucc4 */
433 struct ucc ucc6; /* ucc6 */
434 struct ucc ucc8; /* ucc8 */
435 u8 res13[0x600];
436 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
437 struct sdma sdma; /* SDMA */
438 struct dbg dbg; /* Debug Space */
439 struct rsp rsp[0x2]; /* RISC Special Registers
440 (Trap and Breakpoint) */
441 u8 res14[0x300];
442 u8 res15[0x3A00];
443 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
444 u8 muram[0xC000]; /* 0x110000 - 0x11C000
445 Multi-user RAM */
446 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
447 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
448} __attribute__ ((packed));
449
450extern struct qe_immap *qe_immr;
451extern phys_addr_t get_qe_base(void);
452
453static inline unsigned long immrbar_virt_to_phys(volatile void * address)
454{
455 if ( ((u32)address >= (u32)qe_immr) &&
456 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
457 return (unsigned long)(address - (u32)qe_immr +
458 (u32)get_qe_base());
459 return (unsigned long)virt_to_phys(address);
460}
461
462#endif /* __KERNEL__ */
463#endif /* _ASM_POWERPC_IMMAP_QE_H */
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