[linux.git] / include / acpi / actbl1.h

/******************************************************************************
 *
 * Name: actbl1.h - ACPI 1.0 tables
 *
 *****************************************************************************/

/*
 * Copyright (C) 2000 - 2006, R. Byron Moore
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    substantially similar to the "NO WARRANTY" disclaimer below
 *    ("Disclaimer") and any redistribution must be conditioned upon
 *    including a substantially similar Disclaimer requirement for further
 *    binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES.
 */

#ifndef __ACTBL1_H__
#define __ACTBL1_H__

#pragma pack(1)

/*
 * ACPI 1.0 Root System Description Table (RSDT)
 */
struct rsdt_descriptor_rev1 {
	ACPI_TABLE_HEADER_DEF	/* ACPI common table header */
	u32 table_offset_entry[1];	/* Array of pointers to ACPI tables */
};

/*
 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
 */
struct facs_descriptor_rev1 {
	char signature[4];	/* ASCII table signature */
	u32 length;		/* Length of structure in bytes */
	u32 hardware_signature;	/* Hardware configuration signature */
	u32 firmware_waking_vector;	/* ACPI OS waking vector */
	u32 global_lock;	/* Global Lock */

	/* Flags (32 bits) */

	u8 S4bios_f:1;		/* 00:    S4BIOS support is present */
	 u8:7;			/* 01-07: Reserved, must be zero */
	u8 reserved1[3];	/* 08-31: Reserved, must be zero */

	u8 reserved2[40];	/* Reserved, must be zero */
};

/*
 * ACPI 1.0 Fixed ACPI Description Table (FADT)
 */
struct fadt_descriptor_rev1 {
	ACPI_TABLE_HEADER_DEF	/* ACPI common table header */
	u32 firmware_ctrl;	/* Physical address of FACS */
	u32 dsdt;		/* Physical address of DSDT */
	u8 model;		/* System Interrupt Model */
	u8 reserved1;		/* Reserved, must be zero */
	u16 sci_int;		/* System vector of SCI interrupt */
	u32 smi_cmd;		/* Port address of SMI command port */
	u8 acpi_enable;		/* Value to write to smi_cmd to enable ACPI */
	u8 acpi_disable;	/* Value to write to smi_cmd to disable ACPI */
	u8 S4bios_req;		/* Value to write to SMI CMD to enter S4BIOS state */
	u8 reserved2;		/* Reserved, must be zero */
	u32 pm1a_evt_blk;	/* Port address of Power Mgt 1a acpi_event Reg Blk */
	u32 pm1b_evt_blk;	/* Port address of Power Mgt 1b acpi_event Reg Blk */
	u32 pm1a_cnt_blk;	/* Port address of Power Mgt 1a Control Reg Blk */
	u32 pm1b_cnt_blk;	/* Port address of Power Mgt 1b Control Reg Blk */
	u32 pm2_cnt_blk;	/* Port address of Power Mgt 2 Control Reg Blk */
	u32 pm_tmr_blk;		/* Port address of Power Mgt Timer Ctrl Reg Blk */
	u32 gpe0_blk;		/* Port addr of General Purpose acpi_event 0 Reg Blk */
	u32 gpe1_blk;		/* Port addr of General Purpose acpi_event 1 Reg Blk */
	u8 pm1_evt_len;		/* Byte length of ports at pm1_x_evt_blk */
	u8 pm1_cnt_len;		/* Byte length of ports at pm1_x_cnt_blk */
	u8 pm2_cnt_len;		/* Byte Length of ports at pm2_cnt_blk */
	u8 pm_tm_len;		/* Byte Length of ports at pm_tm_blk */
	u8 gpe0_blk_len;	/* Byte Length of ports at gpe0_blk */
	u8 gpe1_blk_len;	/* Byte Length of ports at gpe1_blk */
	u8 gpe1_base;		/* Offset in gpe model where gpe1 events start */
	u8 reserved3;		/* Reserved, must be zero */
	u16 plvl2_lat;		/* Worst case HW latency to enter/exit C2 state */
	u16 plvl3_lat;		/* Worst case HW latency to enter/exit C3 state */
	u16 flush_size;		/* Size of area read to flush caches */
	u16 flush_stride;	/* Stride used in flushing caches */
	u8 duty_offset;		/* Bit location of duty cycle field in p_cnt reg */
	u8 duty_width;		/* Bit width of duty cycle field in p_cnt reg */
	u8 day_alrm;		/* Index to day-of-month alarm in RTC CMOS RAM */
	u8 mon_alrm;		/* Index to month-of-year alarm in RTC CMOS RAM */
	u8 century;		/* Index to century in RTC CMOS RAM */
	u8 reserved4[3];	/* Reserved, must be zero */

	/* Flags (32 bits) */

	u8 wb_invd:1;		/* 00:    The wbinvd instruction works properly */
	u8 wb_invd_flush:1;	/* 01:    The wbinvd flushes but does not invalidate */
	u8 proc_c1:1;		/* 02:    All processors support C1 state */
	u8 plvl2_up:1;		/* 03:    C2 state works on MP system */
	u8 pwr_button:1;	/* 04:    Power button is handled as a generic feature */
	u8 sleep_button:1;	/* 05:    Sleep button is handled as a generic feature, or not present */
	u8 fixed_rTC:1;		/* 06:    RTC wakeup stat not in fixed register space */
	u8 rtcs4:1;		/* 07:    RTC wakeup stat not possible from S4 */
	u8 tmr_val_ext:1;	/* 08:    tmr_val width is 32 bits (0 = 24 bits) */
	 u8:7;			/* 09-15: Reserved, must be zero */
	u8 reserved5[2];	/* 16-31: Reserved, must be zero */
};

#pragma pack()

#endif				/* __ACTBL1_H__ */
Commit	Line	Data
1da177e4 LT	1	/******************************************************************************
	2	*
	3	* Name: actbl1.h - ACPI 1.0 tables
	4	*
	5	*****************************************************************************/
	6
	7	/*
4a90c7e8	8	* Copyright (C) 2000 - 2006, R. Byron Moore
1da177e4 LT	9	* All rights reserved.
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	* 1. Redistributions of source code must retain the above copyright
	15	* notice, this list of conditions, and the following disclaimer,
	16	* without modification.
	17	* 2. Redistributions in binary form must reproduce at minimum a disclaimer
	18	* substantially similar to the "NO WARRANTY" disclaimer below
	19	* ("Disclaimer") and any redistribution must be conditioned upon
	20	* including a substantially similar Disclaimer requirement for further
	21	* binary redistribution.
	22	* 3. Neither the names of the above-listed copyright holders nor the names
	23	* of any contributors may be used to endorse or promote products derived
	24	* from this software without specific prior written permission.
	25	*
	26	* Alternatively, this software may be distributed under the terms of the
	27	* GNU General Public License ("GPL") version 2 as published by the Free
	28	* Software Foundation.
	29	*
	30	* NO WARRANTY
	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	32	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	33	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
	34	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	35	* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	37	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	38	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	39	* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	40	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	41	* POSSIBILITY OF SUCH DAMAGES.
	42	*/
	43
	44	#ifndef __ACTBL1_H__
	45	#define __ACTBL1_H__
	46
	47	#pragma pack(1)
	48
	49	/*
	50	* ACPI 1.0 Root System Description Table (RSDT)
	51	*/
4be44fcd LB	52	struct rsdt_descriptor_rev1 {
	53	ACPI_TABLE_HEADER_DEF /* ACPI common table header */
	54	u32 table_offset_entry[1]; /* Array of pointers to ACPI tables */
1da177e4 LT	55	};
1da177e4 LT	56
1da177e4 LT	57	/*
	58	* ACPI 1.0 Firmware ACPI Control Structure (FACS)
	59	*/
4be44fcd LB	60	struct facs_descriptor_rev1 {
	61	char signature[4]; /* ASCII table signature */
	62	u32 length; /* Length of structure in bytes */
	63	u32 hardware_signature; /* Hardware configuration signature */
	64	u32 firmware_waking_vector; /* ACPI OS waking vector */
	65	u32 global_lock; /* Global Lock */
f9f4601f RM	66
	67	/* Flags (32 bits) */
	68
4be44fcd LB	69	u8 S4bios_f:1; /* 00: S4BIOS support is present */
	70	u8:7; /* 01-07: Reserved, must be zero */
	71	u8 reserved1[3]; /* 08-31: Reserved, must be zero */
f9f4601f	72
4be44fcd	73	u8 reserved2[40]; /* Reserved, must be zero */
1da177e4 LT	74	};
1da177e4 LT	75
1da177e4 LT	76	/*
	77	* ACPI 1.0 Fixed ACPI Description Table (FADT)
	78	*/
4be44fcd LB	79	struct fadt_descriptor_rev1 {
	80	ACPI_TABLE_HEADER_DEF /* ACPI common table header */
	81	u32 firmware_ctrl; /* Physical address of FACS */
	82	u32 dsdt; /* Physical address of DSDT */
	83	u8 model; /* System Interrupt Model */
	84	u8 reserved1; /* Reserved, must be zero */
	85	u16 sci_int; /* System vector of SCI interrupt */
	86	u32 smi_cmd; /* Port address of SMI command port */
	87	u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
	88	u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
	89	u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
	90	u8 reserved2; /* Reserved, must be zero */
	91	u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
	92	u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
	93	u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
	94	u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
	95	u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
	96	u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
	97	u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
	98	u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
	99	u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
	100	u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
	101	u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
	102	u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
	103	u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
	104	u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
	105	u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
	106	u8 reserved3; /* Reserved, must be zero */
	107	u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
	108	u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
	109	u16 flush_size; /* Size of area read to flush caches */
	110	u16 flush_stride; /* Stride used in flushing caches */
	111	u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
	112	u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
	113	u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
	114	u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
	115	u8 century; /* Index to century in RTC CMOS RAM */
	116	u8 reserved4[3]; /* Reserved, must be zero */
f9f4601f RM	117
	118	/* Flags (32 bits) */
	119
4be44fcd LB	120	u8 wb_invd:1; /* 00: The wbinvd instruction works properly */
	121	u8 wb_invd_flush:1; /* 01: The wbinvd flushes but does not invalidate */
	122	u8 proc_c1:1; /* 02: All processors support C1 state */
	123	u8 plvl2_up:1; /* 03: C2 state works on MP system */
	124	u8 pwr_button:1; /* 04: Power button is handled as a generic feature */
	125	u8 sleep_button:1; /* 05: Sleep button is handled as a generic feature, or not present */
	126	u8 fixed_rTC:1; /* 06: RTC wakeup stat not in fixed register space */
	127	u8 rtcs4:1; /* 07: RTC wakeup stat not possible from S4 */
	128	u8 tmr_val_ext:1; /* 08: tmr_val width is 32 bits (0 = 24 bits) */
	129	u8:7; /* 09-15: Reserved, must be zero */
	130	u8 reserved5[2]; /* 16-31: Reserved, must be zero */
1da177e4 LT	131	};
	132
	133	#pragma pack()
	134
4be44fcd	135	#endif /* __ACTBL1_H__ */