projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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2 | #ifndef _ASM_X86_CPUFEATURES_H |
| 3 | #define _ASM_X86_CPUFEATURES_H | |
| 4 | ||
| 5 | #ifndef _ASM_X86_REQUIRED_FEATURES_H | |
| 6 | #include <asm/required-features.h> | |
| 7 | #endif | |
| 8 | ||
| 9 | #ifndef _ASM_X86_DISABLED_FEATURES_H | |
| 10 | #include <asm/disabled-features.h> | |
| 11 | #endif | |
| 12 | ||
| 13 | /* | |
| 14 | * Defines x86 CPU feature bits | |
| 15 | */ | |
| 4053717a | 16 | #define NCAPINTS 19 /* N 32-bit words worth of info */ |
| 0b44cfb8 | 17 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
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18 | |
| 19 | /* | |
| 20 | * Note: If the comment begins with a quoted string, that string is used | |
| 21 | * in /proc/cpuinfo instead of the macro name. If the string is "", | |
| 22 | * this feature bit is not displayed in /proc/cpuinfo at all. | |
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23 | * |
| 24 | * When adding new features here that depend on other features, | |
| 25 | * please update the table in kernel/cpu/cpuid-deps.c as well. | |
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26 | */ |
| 27 | ||
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28 | /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ |
| 29 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | |
| 30 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | |
| 31 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | |
| 32 | #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ | |
| 33 | #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ | |
| 34 | #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ | |
| 35 | #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ | |
| 36 | #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ | |
| 37 | #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ | |
| 38 | #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ | |
| 39 | #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ | |
| 40 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | |
| 41 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | |
| 42 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | |
| 43 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ | |
| 44 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | |
| 45 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | |
| 46 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | |
| 47 | #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ | |
| 48 | #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ | |
| 49 | #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ | |
| 50 | #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ | |
| 51 | #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | |
| 52 | #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ | |
| 53 | #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ | |
| 54 | #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ | |
| 55 | #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ | |
| 56 | #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ | |
| 57 | #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ | |
| 58 | #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ | |
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59 | |
| 60 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
| 61 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
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62 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ |
| 63 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ | |
| 64 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | |
| 65 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | |
| 66 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | |
| 67 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | |
| 68 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | |
| 69 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ | |
| 70 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ | |
| 71 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ | |
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72 | |
| 73 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
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74 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ |
| 75 | #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ | |
| 76 | #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ | |
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77 | |
| 78 | /* Other features, Linux-defined mapping, word 3 */ | |
| 79 | /* This range is used for feature bits which conflict or are synthesized */ | |
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80 | #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ |
| 81 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
| 82 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
| 83 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
| 84 | ||
| 85 | /* CPU types for specific tunings: */ | |
| 86 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | |
| 87 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | |
| 88 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | |
| 89 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | |
| 90 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | |
| 91 | #define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ | |
| 92 | #define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ | |
| 93 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ | |
| 94 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | |
| 95 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | |
| 96 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ | |
| 97 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ | |
| 98 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ | |
| 99 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ | |
| 100 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ | |
| 101 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ | |
| 102 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ | |
| 103 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | |
| 104 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ | |
| 105 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | |
| 106 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | |
| 107 | #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ | |
| 108 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ | |
| 109 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ | |
| 110 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ | |
| 111 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | |
| 112 | #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ | |
| 7d7d1bf1 | 113 | |
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114 | /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ |
| 115 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | |
| 116 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | |
| 117 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | |
| 118 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ | |
| 119 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ | |
| 120 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | |
| 121 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ | |
| 122 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | |
| 123 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | |
| 124 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | |
| 125 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | |
| 126 | #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | |
| 127 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | |
| 128 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ | |
| 129 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | |
| 130 | #define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ | |
| 131 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | |
| 132 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | |
| 133 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | |
| 134 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | |
| 135 | #define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ | |
| 136 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | |
| 137 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | |
| 138 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ | |
| 139 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | |
| 140 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ | |
| 141 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ | |
| 142 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | |
| 143 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ | |
| 144 | #define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ | |
| 145 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | |
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146 | |
| 147 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
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148 | #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ |
| 149 | #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ | |
| 150 | #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | |
| 151 | #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | |
| 152 | #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ | |
| 153 | #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ | |
| 154 | #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ | |
| 155 | #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ | |
| 156 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | |
| 157 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | |
| 7d7d1bf1 | 158 | |
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159 | /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ |
| 160 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | |
| 161 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | |
| 162 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ | |
| 163 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | |
| 164 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | |
| 165 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | |
| 166 | #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ | |
| 167 | #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ | |
| 168 | #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ | |
| 169 | #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ | |
| 170 | #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ | |
| 171 | #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ | |
| 172 | #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ | |
| 173 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | |
| 174 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | |
| 175 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | |
| 176 | #define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ | |
| 177 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | |
| 178 | #define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ | |
| 179 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ | |
| 180 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ | |
| 181 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | |
| 182 | #define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ | |
| 183 | #define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ | |
| 184 | #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ | |
| 185 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ | |
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186 | |
| 187 | /* | |
| 188 | * Auxiliary flags: Linux defined - For features scattered in various | |
| 189 | * CPUID levels like 0x6, 0xA etc, word 7. | |
| 190 | * | |
| 191 | * Reuse free bits when adding new feature flags! | |
| 192 | */ | |
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193 | #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ |
| 194 | #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ | |
| 195 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | |
| 196 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | |
| 197 | #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ | |
| 198 | #define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ | |
| 199 | #define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ | |
| 5d64db29 | 200 | #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */ |
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201 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
| 202 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | |
| 203 | #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ | |
| 5d64db29 | 204 | #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ |
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205 | #define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ |
| 206 | #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */ | |
| 0b44cfb8 | 207 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ |
| 4053717a | 208 | #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */ |
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209 | #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */ |
| 210 | #define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */ | |
| 0b44cfb8 | 211 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ |
| 4053717a | 212 | #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ |
| f091f1d6 | 213 | #define X86_FEATURE_SEV ( 7*32+20) /* AMD Secure Encrypted Virtualization */ |
| 4053717a | 214 | #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */ |
| 4caea057 | 215 | #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */ |
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216 | #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */ |
| 217 | #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */ | |
| 218 | #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ | |
| 219 | #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ | |
| 220 | #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ | |
| 221 | #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ | |
| e24f14b0 | 222 | #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ |
| d207ea8e | 223 | #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ |
| 6e30437b | 224 | |
| 7d7d1bf1 | 225 | /* Virtualization flags: Linux defined, word 8 */ |
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226 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
| 227 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ | |
| 228 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ | |
| 229 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | |
| 230 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | |
| 7d7d1bf1 | 231 | |
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232 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ |
| 233 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | |
| 252df177 | 234 | #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */ |
| 7d7d1bf1 | 235 | |
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236 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ |
| 237 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ | |
| 238 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ | |
| 239 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | |
| 240 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | |
| 241 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | |
| 242 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | |
| 243 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | |
| 244 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ | |
| 245 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | |
| 246 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | |
| 247 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | |
| 248 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ | |
| 249 | #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ | |
| 250 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | |
| 251 | #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ | |
| 252 | #define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ | |
| 253 | #define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ | |
| 254 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | |
| 255 | #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | |
| 256 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | |
| 257 | #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ | |
| 4053717a | 258 | #define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */ |
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259 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ |
| 260 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | |
| 261 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | |
| 262 | #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ | |
| 263 | #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ | |
| 264 | #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | |
| 7d7d1bf1 | 265 | |
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266 | /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ |
| 267 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ | |
| 268 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ | |
| 269 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ | |
| 270 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ | |
| 7d7d1bf1 | 271 | |
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272 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ |
| 273 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | |
| 7d7d1bf1 | 274 | |
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275 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ |
| 276 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */ | |
| 277 | #define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ | |
| 278 | #define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | |
| 7d7d1bf1 | 279 | |
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280 | /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ |
| 281 | #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ | |
| 282 | #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ | |
| 643e345c | 283 | #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ |
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284 | #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ |
| 285 | #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ | |
| 286 | #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ | |
| 32fdbd90 | 287 | #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ |
| a20d23bb | 288 | #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ |
| 32fdbd90 | 289 | #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ |
| 7d7d1bf1 | 290 | |
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291 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |
| 292 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | |
| 293 | #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | |
| 294 | #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | |
| 295 | #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ | |
| 296 | #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ | |
| 297 | #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ | |
| 298 | #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ | |
| 299 | #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ | |
| 300 | #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | |
| 301 | #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | |
| 7d7d1bf1 | 302 | |
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303 | /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ |
| 304 | #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | |
| 305 | #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | |
| 306 | #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | |
| 307 | #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ | |
| 308 | #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ | |
| 309 | #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ | |
| 310 | #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ | |
| 311 | #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ | |
| 312 | #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ | |
| 313 | #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ | |
| 314 | #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ | |
| 315 | #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ | |
| 316 | #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ | |
| 7d7d1bf1 | 317 | |
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318 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ |
| 319 | #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ | |
| 320 | #define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ | |
| 321 | #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ | |
| 322 | #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | |
| 323 | #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ | |
| 324 | #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ | |
| 325 | #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ | |
| 326 | #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ | |
| 327 | #define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ | |
| 328 | #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ | |
| 5e2a146b | 329 | #define X86_FEATURE_TME (16*32+13) /* Intel Total Memory Encryption */ |
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330 | #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ |
| 331 | #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ | |
| 332 | #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | |
| 605e71cd | 333 | #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */ |
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334 | #define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */ |
| 335 | #define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */ | |
| 7d7d1bf1 | 336 | |
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337 | /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ |
| 338 | #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ | |
| 339 | #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ | |
| 340 | #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ | |
| 7d7d1bf1 | 341 | |
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342 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ |
| 343 | #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ | |
| 344 | #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ | |
| 5e2a146b | 345 | #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ |
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346 | #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ |
| 347 | #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ | |
| e24f14b0 | 348 | #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ |
| 4053717a | 349 | #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ |
| a20d23bb | 350 | #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ |
| 4053717a | 351 | |
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352 | /* |
| 353 | * BUG word(s) | |
| 354 | */ | |
| 0b44cfb8 | 355 | #define X86_BUG(x) (NCAPINTS*32 + (x)) |
| 7d7d1bf1 | 356 | |
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357 | #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ |
| 358 | #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ | |
| 359 | #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ | |
| 360 | #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ | |
| 361 | #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ | |
| 362 | #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ | |
| 363 | #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ | |
| 364 | #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ | |
| 365 | #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ | |
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366 | #ifdef CONFIG_X86_32 |
| 367 | /* | |
| 368 | * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional | |
| 369 | * to avoid confusion. | |
| 370 | */ | |
| 0b44cfb8 | 371 | #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ |
| 7d7d1bf1 | 372 | #endif |
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373 | #define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ |
| 374 | #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | |
| 375 | #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | |
| 376 | #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | |
| 5d64db29 | 377 | #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ |
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378 | #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ |
| 379 | #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ | |
| a20d23bb | 380 | #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */ |
| e24f14b0 | 381 | #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ |
| 0b44cfb8 | 382 | |
| 7d7d1bf1 | 383 | #endif /* _ASM_X86_CPUFEATURES_H */ |