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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <[email protected]>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
d9b84a15 34#include <asm/io.h>
95c6e9cb 35#include <sound/core.h>
be57bfff 36#include <sound/hda_codec.h>
95c6e9cb 37#include "hda_local.h"
128bc4ba 38#include "hda_auto_parser.h"
5aaca44d 39#include "hda_jack.h"
95c6e9cb 40
bcd109c0
IM		 41#include "ca0132_regs.h"
42
ef6b2ead
IM		 43/* Enable this to see controls for tuning purpose. */
44/*#define ENABLE_TUNING_CONTROLS*/
45
8e142e9e
TS		 46#ifdef ENABLE_TUNING_CONTROLS
47#include <sound/tlv.h>
48#endif
49
ef6b2ead
IM		 50#define FLOAT_ZERO 0x00000000
51#define FLOAT_ONE 0x3f800000
52#define FLOAT_TWO 0x40000000
38ba69ff 53#define FLOAT_THREE 0x40400000
7cb9d94c 54#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 55#define FLOAT_MINUS_5 0xc0a00000
56
ef6b2ead
IM		 57#define UNSOL_TAG_DSP 0x16
58
4aa3bb0c
IM		 59#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
60#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
61
62#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
63#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
64#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
65
66#define MASTERCONTROL 0x80
ef6b2ead
IM		 67#define MASTERCONTROL_ALLOC_DMA_CHAN 10
68#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 69
95c6e9cb
IM		 70#define WIDGET_CHIP_CTRL 0x15
71#define WIDGET_DSP_CTRL 0x16
72
4aa3bb0c
IM		 73#define MEM_CONNID_MICIN1 3
74#define MEM_CONNID_MICIN2 5
75#define MEM_CONNID_MICOUT1 12
76#define MEM_CONNID_MICOUT2 14
77#define MEM_CONNID_WUH 10
78#define MEM_CONNID_DSP 16
79#define MEM_CONNID_DMIC 100
80
81#define SCP_SET 0
82#define SCP_GET 1
83
01ef7dbf 84#define EFX_FILE "ctefx.bin"
7a928186 85#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 86#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 87
24f3cede 88#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 89MODULE_FIRMWARE(EFX_FILE);
7a928186 90MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 91MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 92#endif
01ef7dbf 93
3a03f83b 94static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 95
7cb9d94c 96#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 97enum {
98 SPEAKER_OUT,
7cb9d94c
CM		 99 HEADPHONE_OUT,
100 SURROUND_OUT
ef6b2ead
IM		 101};
102
103enum {
104 DIGITAL_MIC,
105 LINE_MIC_IN
106};
107
7cb9d94c 108/* Strings for Input Source Enum Control */
3a03f83b 109static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 110#define IN_SRC_NUM_OF_INPUTS 3
111enum {
112 REAR_MIC,
113 REAR_LINE_IN,
114 FRONT_MIC,
115};
116
ef6b2ead
IM		 117enum {
118#define VNODE_START_NID 0x80
119 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
120 VNID_MIC,
121 VNID_HP_SEL,
122 VNID_AMIC1_SEL,
123 VNID_HP_ASEL,
124 VNID_AMIC1_ASEL,
125 VNODE_END_NID,
126#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
127
128#define EFFECT_START_NID 0x90
129#define OUT_EFFECT_START_NID EFFECT_START_NID
130 SURROUND = OUT_EFFECT_START_NID,
131 CRYSTALIZER,
132 DIALOG_PLUS,
133 SMART_VOLUME,
134 X_BASS,
135 EQUALIZER,
136 OUT_EFFECT_END_NID,
137#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
138
139#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
140 ECHO_CANCELLATION = IN_EFFECT_START_NID,
141 VOICE_FOCUS,
142 MIC_SVM,
143 NOISE_REDUCTION,
144 IN_EFFECT_END_NID,
145#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
146
147 VOICEFX = IN_EFFECT_END_NID,
148 PLAY_ENHANCEMENT,
149 CRYSTAL_VOICE,
7cb9d94c
CM		 150 EFFECT_END_NID,
151 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 152 INPUT_SOURCE_ENUM,
153 XBASS_XOVER,
154 EQ_PRESET_ENUM,
155 SMART_VOLUME_ENUM,
212de2e7
CM		 156 MIC_BOOST_ENUM,
157 AE5_HEADPHONE_GAIN_ENUM,
d51434d4
CM		 158 AE5_SOUND_FILTER_ENUM,
159 ZXR_HEADPHONE_GAIN
ef6b2ead
IM		 160#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
161};
162
163/* Effects values size*/
164#define EFFECT_VALS_MAX_COUNT 12
165
47cdf76e
CM		 166/*
167 * Default values for the effect slider controls, they are in order of their
168 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
169 * X-bass.
170 */
171static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
172/* Amount of effect level sliders for ca0132_alt controls. */
173#define EFFECT_LEVEL_SLIDERS 5
174
e8412ca4
DR		 175/* Latency introduced by DSP blocks in milliseconds. */
176#define DSP_CAPTURE_INIT_LATENCY 0
177#define DSP_CRYSTAL_VOICE_LATENCY 124
178#define DSP_PLAYBACK_INIT_LATENCY 13
179#define DSP_PLAY_ENHANCEMENT_LATENCY 30
180#define DSP_SPEAKER_OUT_LATENCY 7
181
ef6b2ead 182struct ct_effect {
975cc02a 183 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 184 hda_nid_t nid;
185 int mid; /*effect module ID*/
186 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
187 int direct; /* 0:output; 1:input*/
188 int params; /* number of default non-on/off params */
189 /*effect default values, 1st is on/off. */
190 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
191};
192
193#define EFX_DIR_OUT 0
194#define EFX_DIR_IN 1
195
862154bb 196static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 197 { .name = "Surround",
198 .nid = SURROUND,
199 .mid = 0x96,
200 .reqs = {0, 1},
201 .direct = EFX_DIR_OUT,
202 .params = 1,
203 .def_vals = {0x3F800000, 0x3F2B851F}
204 },
205 { .name = "Crystalizer",
206 .nid = CRYSTALIZER,
207 .mid = 0x96,
208 .reqs = {7, 8},
209 .direct = EFX_DIR_OUT,
210 .params = 1,
211 .def_vals = {0x3F800000, 0x3F266666}
212 },
213 { .name = "Dialog Plus",
214 .nid = DIALOG_PLUS,
215 .mid = 0x96,
216 .reqs = {2, 3},
217 .direct = EFX_DIR_OUT,
218 .params = 1,
219 .def_vals = {0x00000000, 0x3F000000}
220 },
221 { .name = "Smart Volume",
222 .nid = SMART_VOLUME,
223 .mid = 0x96,
224 .reqs = {4, 5, 6},
225 .direct = EFX_DIR_OUT,
226 .params = 2,
227 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
228 },
229 { .name = "X-Bass",
230 .nid = X_BASS,
231 .mid = 0x96,
232 .reqs = {24, 23, 25},
233 .direct = EFX_DIR_OUT,
234 .params = 2,
235 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
236 },
237 { .name = "Equalizer",
238 .nid = EQUALIZER,
239 .mid = 0x96,
240 .reqs = {9, 10, 11, 12, 13, 14,
241 15, 16, 17, 18, 19, 20},
242 .direct = EFX_DIR_OUT,
243 .params = 11,
244 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
245 0x00000000, 0x00000000, 0x00000000, 0x00000000,
246 0x00000000, 0x00000000, 0x00000000, 0x00000000}
247 },
248 { .name = "Echo Cancellation",
249 .nid = ECHO_CANCELLATION,
250 .mid = 0x95,
251 .reqs = {0, 1, 2, 3},
252 .direct = EFX_DIR_IN,
253 .params = 3,
254 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
255 },
256 { .name = "Voice Focus",
257 .nid = VOICE_FOCUS,
258 .mid = 0x95,
259 .reqs = {6, 7, 8, 9},
260 .direct = EFX_DIR_IN,
261 .params = 3,
262 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
263 },
264 { .name = "Mic SVM",
265 .nid = MIC_SVM,
266 .mid = 0x95,
267 .reqs = {44, 45},
268 .direct = EFX_DIR_IN,
269 .params = 1,
270 .def_vals = {0x00000000, 0x3F3D70A4}
271 },
272 { .name = "Noise Reduction",
273 .nid = NOISE_REDUCTION,
274 .mid = 0x95,
275 .reqs = {4, 5},
276 .direct = EFX_DIR_IN,
277 .params = 1,
278 .def_vals = {0x3F800000, 0x3F000000}
279 },
280 { .name = "VoiceFX",
281 .nid = VOICEFX,
282 .mid = 0x95,
283 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
284 .direct = EFX_DIR_IN,
285 .params = 8,
286 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
287 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
288 0x00000000}
289 }
290};
291
292/* Tuning controls */
293#ifdef ENABLE_TUNING_CONTROLS
294
295enum {
296#define TUNING_CTL_START_NID 0xC0
297 WEDGE_ANGLE = TUNING_CTL_START_NID,
298 SVM_LEVEL,
299 EQUALIZER_BAND_0,
300 EQUALIZER_BAND_1,
301 EQUALIZER_BAND_2,
302 EQUALIZER_BAND_3,
303 EQUALIZER_BAND_4,
304 EQUALIZER_BAND_5,
305 EQUALIZER_BAND_6,
306 EQUALIZER_BAND_7,
307 EQUALIZER_BAND_8,
308 EQUALIZER_BAND_9,
309 TUNING_CTL_END_NID
310#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
311};
312
313struct ct_tuning_ctl {
975cc02a 314 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 315 hda_nid_t parent_nid;
316 hda_nid_t nid;
317 int mid; /*effect module ID*/
318 int req; /*effect module request*/
319 int direct; /* 0:output; 1:input*/
320 unsigned int def_val;/*effect default values*/
321};
322
862154bb 323static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 324 { .name = "Wedge Angle",
325 .parent_nid = VOICE_FOCUS,
326 .nid = WEDGE_ANGLE,
327 .mid = 0x95,
328 .req = 8,
329 .direct = EFX_DIR_IN,
330 .def_val = 0x41F00000
331 },
332 { .name = "SVM Level",
333 .parent_nid = MIC_SVM,
334 .nid = SVM_LEVEL,
335 .mid = 0x95,
336 .req = 45,
337 .direct = EFX_DIR_IN,
338 .def_val = 0x3F3D70A4
339 },
340 { .name = "EQ Band0",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_0,
343 .mid = 0x96,
344 .req = 11,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
347 },
348 { .name = "EQ Band1",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_1,
351 .mid = 0x96,
352 .req = 12,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
355 },
356 { .name = "EQ Band2",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_2,
359 .mid = 0x96,
360 .req = 13,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
363 },
364 { .name = "EQ Band3",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_3,
367 .mid = 0x96,
368 .req = 14,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
371 },
372 { .name = "EQ Band4",
373 .parent_nid = EQUALIZER,
374 .nid = EQUALIZER_BAND_4,
375 .mid = 0x96,
376 .req = 15,
377 .direct = EFX_DIR_OUT,
378 .def_val = 0x00000000
379 },
380 { .name = "EQ Band5",
381 .parent_nid = EQUALIZER,
382 .nid = EQUALIZER_BAND_5,
383 .mid = 0x96,
384 .req = 16,
385 .direct = EFX_DIR_OUT,
386 .def_val = 0x00000000
387 },
388 { .name = "EQ Band6",
389 .parent_nid = EQUALIZER,
390 .nid = EQUALIZER_BAND_6,
391 .mid = 0x96,
392 .req = 17,
393 .direct = EFX_DIR_OUT,
394 .def_val = 0x00000000
395 },
396 { .name = "EQ Band7",
397 .parent_nid = EQUALIZER,
398 .nid = EQUALIZER_BAND_7,
399 .mid = 0x96,
400 .req = 18,
401 .direct = EFX_DIR_OUT,
402 .def_val = 0x00000000
403 },
404 { .name = "EQ Band8",
405 .parent_nid = EQUALIZER,
406 .nid = EQUALIZER_BAND_8,
407 .mid = 0x96,
408 .req = 19,
409 .direct = EFX_DIR_OUT,
410 .def_val = 0x00000000
411 },
412 { .name = "EQ Band9",
413 .parent_nid = EQUALIZER,
414 .nid = EQUALIZER_BAND_9,
415 .mid = 0x96,
416 .req = 20,
417 .direct = EFX_DIR_OUT,
418 .def_val = 0x00000000
419 }
420};
421#endif
422
423/* Voice FX Presets */
424#define VOICEFX_MAX_PARAM_COUNT 9
425
426struct ct_voicefx {
427 char *name;
428 hda_nid_t nid;
429 int mid;
430 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
431};
432
433struct ct_voicefx_preset {
434 char *name; /*preset name*/
435 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
436};
437
862154bb 438static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 439 .name = "VoiceFX Capture Switch",
440 .nid = VOICEFX,
441 .mid = 0x95,
442 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
443};
444
862154bb 445static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 446 { .name = "Neutral",
447 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
448 0x44FA0000, 0x3F800000, 0x3F800000,
449 0x3F800000, 0x00000000, 0x00000000 }
450 },
451 { .name = "Female2Male",
452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
453 0x44FA0000, 0x3F19999A, 0x3F866666,
454 0x3F800000, 0x00000000, 0x00000000 }
455 },
456 { .name = "Male2Female",
457 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
458 0x450AC000, 0x4017AE14, 0x3F6B851F,
459 0x3F800000, 0x00000000, 0x00000000 }
460 },
461 { .name = "ScrappyKid",
462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
463 0x44FA0000, 0x40400000, 0x3F28F5C3,
464 0x3F800000, 0x00000000, 0x00000000 }
465 },
466 { .name = "Elderly",
467 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
468 0x44E10000, 0x3FB33333, 0x3FB9999A,
469 0x3F800000, 0x3E3A2E43, 0x00000000 }
470 },
471 { .name = "Orc",
472 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
473 0x45098000, 0x3F266666, 0x3FC00000,
474 0x3F800000, 0x00000000, 0x00000000 }
475 },
476 { .name = "Elf",
477 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
478 0x45193000, 0x3F8E147B, 0x3F75C28F,
479 0x3F800000, 0x00000000, 0x00000000 }
480 },
481 { .name = "Dwarf",
482 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
483 0x45007000, 0x3F451EB8, 0x3F7851EC,
484 0x3F800000, 0x00000000, 0x00000000 }
485 },
486 { .name = "AlienBrute",
487 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
488 0x451F6000, 0x3F266666, 0x3FA7D945,
489 0x3F800000, 0x3CF5C28F, 0x00000000 }
490 },
491 { .name = "Robot",
492 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
493 0x44FA0000, 0x3FB2718B, 0x3F800000,
494 0xBC07010E, 0x00000000, 0x00000000 }
495 },
496 { .name = "Marine",
497 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
498 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
499 0x3F0A3D71, 0x00000000, 0x00000000 }
500 },
501 { .name = "Emo",
502 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
503 0x44FA0000, 0x3F800000, 0x3F800000,
504 0x3E4CCCCD, 0x00000000, 0x00000000 }
505 },
506 { .name = "DeepVoice",
507 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
508 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
509 0x3F800000, 0x00000000, 0x00000000 }
510 },
511 { .name = "Munchkin",
512 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
513 0x44FA0000, 0x3F800000, 0x3F1A043C,
514 0x3F800000, 0x00000000, 0x00000000 }
515 }
516};
517
47cdf76e
CM		 518/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
519
520#define EQ_PRESET_MAX_PARAM_COUNT 11
521
522struct ct_eq {
523 char *name;
524 hda_nid_t nid;
525 int mid;
526 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
527};
528
529struct ct_eq_preset {
530 char *name; /*preset name*/
531 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
532};
533
862154bb 534static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 535 .name = "FX: Equalizer Preset Switch",
536 .nid = EQ_PRESET_ENUM,
537 .mid = 0x96,
538 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
539};
540
541
862154bb 542static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 543 { .name = "Flat",
544 .vals = { 0x00000000, 0x00000000, 0x00000000,
545 0x00000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x00000000,
547 0x00000000, 0x00000000 }
548 },
549 { .name = "Acoustic",
550 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
551 0x40000000, 0x00000000, 0x00000000,
552 0x00000000, 0x00000000, 0x40000000,
553 0x40000000, 0x40000000 }
554 },
555 { .name = "Classical",
556 .vals = { 0x00000000, 0x00000000, 0x40C00000,
557 0x40C00000, 0x40466666, 0x00000000,
558 0x00000000, 0x00000000, 0x00000000,
559 0x40466666, 0x40466666 }
560 },
561 { .name = "Country",
562 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
563 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
564 0x00000000, 0x00000000, 0x40000000,
565 0x40466666, 0x40800000 }
566 },
567 { .name = "Dance",
568 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
569 0x40466666, 0x40866666, 0xBF99999A,
570 0xBF99999A, 0x00000000, 0x00000000,
571 0x40800000, 0x40800000 }
572 },
573 { .name = "Jazz",
574 .vals = { 0x00000000, 0x00000000, 0x00000000,
575 0x3F8CCCCD, 0x40800000, 0x40800000,
576 0x40800000, 0x00000000, 0x3F8CCCCD,
577 0x40466666, 0x40466666 }
578 },
579 { .name = "New Age",
580 .vals = { 0x00000000, 0x00000000, 0x40000000,
581 0x40000000, 0x00000000, 0x00000000,
582 0x00000000, 0x3F8CCCCD, 0x40000000,
583 0x40000000, 0x40000000 }
584 },
585 { .name = "Pop",
586 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
587 0x40000000, 0x40000000, 0x00000000,
588 0xBF99999A, 0xBF99999A, 0x00000000,
589 0x40466666, 0x40C00000 }
590 },
591 { .name = "Rock",
592 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
593 0x3F8CCCCD, 0x40000000, 0xBF99999A,
594 0xBF99999A, 0x00000000, 0x00000000,
595 0x40800000, 0x40800000 }
596 },
597 { .name = "Vocal",
598 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
599 0xBF99999A, 0x00000000, 0x40466666,
600 0x40800000, 0x40466666, 0x00000000,
601 0x00000000, 0x3F8CCCCD }
602 }
603};
604
7cb9d94c
CM		 605/* DSP command sequences for ca0132_alt_select_out */
606#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
607struct ca0132_alt_out_set {
608 char *name; /*preset name*/
609 unsigned char commands;
610 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
611 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
612 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
613};
614
615static const struct ca0132_alt_out_set alt_out_presets[] = {
616 { .name = "Line Out",
617 .commands = 7,
618 .mids = { 0x96, 0x96, 0x96, 0x8F,
619 0x96, 0x96, 0x96 },
620 .reqs = { 0x19, 0x17, 0x18, 0x01,
621 0x1F, 0x15, 0x3A },
622 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
623 0x00000000, 0x00000000, 0x00000000,
624 0x00000000 }
625 },
626 { .name = "Headphone",
627 .commands = 7,
628 .mids = { 0x96, 0x96, 0x96, 0x8F,
629 0x96, 0x96, 0x96 },
630 .reqs = { 0x19, 0x17, 0x18, 0x01,
631 0x1F, 0x15, 0x3A },
632 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
633 0x00000000, 0x00000000, 0x00000000,
634 0x00000000 }
635 },
636 { .name = "Surround",
637 .commands = 8,
638 .mids = { 0x96, 0x8F, 0x96, 0x96,
639 0x96, 0x96, 0x96, 0x96 },
640 .reqs = { 0x18, 0x01, 0x1F, 0x15,
641 0x3A, 0x1A, 0x1B, 0x1C },
642 .vals = { 0x00000000, 0x00000000, 0x00000000,
643 0x00000000, 0x00000000, 0x00000000,
644 0x00000000, 0x00000000 }
645 }
646};
647
017310fb
CM		 648/*
649 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
650 * and I don't know what the third req is, but it's always zero. I assume it's
651 * some sort of update or set command to tell the DSP there's new volume info.
652 */
653#define DSP_VOL_OUT 0
654#define DSP_VOL_IN 1
655
656struct ct_dsp_volume_ctl {
657 hda_nid_t vnid;
658 int mid; /* module ID*/
659 unsigned int reqs[3]; /* scp req ID */
660};
661
862154bb 662static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 663 { .vnid = VNID_SPK,
664 .mid = 0x32,
665 .reqs = {3, 4, 2}
666 },
667 { .vnid = VNID_MIC,
668 .mid = 0x37,
669 .reqs = {2, 3, 1}
670 }
671};
672
2283c85b
CM		 673/* Values for ca0113_mmio_command_set for selecting output. */
674#define AE5_CA0113_OUT_SET_COMMANDS 6
675struct ae5_ca0113_output_set {
676 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
677 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
678 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
679};
680
681static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
682 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
683 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
684 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
685 },
686 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
687 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
688 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
689 },
690 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
691 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
692 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
693 }
694};
695
212de2e7
CM		 696/* ae5 ca0113 command sequences to set headphone gain levels. */
697#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
698struct ae5_headphone_gain_set {
699 char *name;
700 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
701};
702
703static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
704 { .name = "Low (16-31",
705 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
706 },
707 { .name = "Medium (32-149",
708 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
709 },
710 { .name = "High (150-600",
711 .vals = { 0xff, 0xff, 0xff, 0x7f }
712 }
713};
714
715struct ae5_filter_set {
716 char *name;
717 unsigned int val;
718};
719
720static const struct ae5_filter_set ae5_filter_presets[] = {
721 { .name = "Slow Roll Off",
722 .val = 0xa0
723 },
724 { .name = "Minimum Phase",
725 .val = 0xc0
726 },
727 { .name = "Fast Roll Off",
728 .val = 0x80
729 }
730};
731
95c6e9cb
IM		 732enum hda_cmd_vendor_io {
733 /* for DspIO node */
734 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
735 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
736
737 VENDOR_DSPIO_STATUS = 0xF01,
738 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
739 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
740 VENDOR_DSPIO_DSP_INIT = 0x703,
741 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
742 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
743
744 /* for ChipIO node */
745 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
746 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
747 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
748 VENDOR_CHIPIO_DATA_LOW = 0x300,
749 VENDOR_CHIPIO_DATA_HIGH = 0x400,
750
bf85a91c
CM		 751 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
752 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
753
95c6e9cb
IM		 754 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
755 VENDOR_CHIPIO_STATUS = 0xF01,
756 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
757 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
758
4aa3bb0c
IM		 759 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
760 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 761 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
762 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
763 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 764
95c6e9cb 765 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 766 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 767
768 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
769 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
770 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
771 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
772 VENDOR_CHIPIO_FLAG_SET = 0x70F,
773 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 774 VENDOR_CHIPIO_PARAM_SET = 0x710,
775 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 776
777 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
778 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
779 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
780 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
781
4aa3bb0c
IM		 782 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
783 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
784 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
785 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
786
787 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
788 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
789 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
790 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
791 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
792 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
793
794 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 795};
796
797/*
798 * Control flag IDs
799 */
800enum control_flag_id {
801 /* Connection manager stream setup is bypassed/enabled */
802 CONTROL_FLAG_C_MGR = 0,
803 /* DSP DMA is bypassed/enabled */
804 CONTROL_FLAG_DMA = 1,
805 /* 8051 'idle' mode is disabled/enabled */
806 CONTROL_FLAG_IDLE_ENABLE = 2,
807 /* Tracker for the SPDIF-in path is bypassed/enabled */
808 CONTROL_FLAG_TRACKER = 3,
809 /* DigitalOut to Spdif2Out connection is disabled/enabled */
810 CONTROL_FLAG_SPDIF2OUT = 4,
811 /* Digital Microphone is disabled/enabled */
812 CONTROL_FLAG_DMIC = 5,
813 /* ADC_B rate is 48 kHz/96 kHz */
814 CONTROL_FLAG_ADC_B_96KHZ = 6,
815 /* ADC_C rate is 48 kHz/96 kHz */
816 CONTROL_FLAG_ADC_C_96KHZ = 7,
817 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
818 CONTROL_FLAG_DAC_96KHZ = 8,
819 /* DSP rate is 48 kHz/96 kHz */
820 CONTROL_FLAG_DSP_96KHZ = 9,
821 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
822 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
823 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
824 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
825 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
826 CONTROL_FLAG_DECODE_LOOP = 12,
827 /* De-emphasis filter on DAC-1 disabled/enabled */
828 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
829 /* De-emphasis filter on DAC-2 disabled/enabled */
830 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
831 /* De-emphasis filter on DAC-3 disabled/enabled */
832 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
833 /* High-pass filter on ADC_B disabled/enabled */
834 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
835 /* High-pass filter on ADC_C disabled/enabled */
836 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
837 /* Common mode on Port_A disabled/enabled */
838 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
839 /* Common mode on Port_D disabled/enabled */
840 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
841 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
842 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
843 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 844 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 845 /* ASI rate is 48kHz/96kHz */
846 CONTROL_FLAG_ASI_96KHZ = 22,
847 /* DAC power settings able to control attached ports no/yes */
848 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
849 /* Clock Stop OK reporting is disabled/enabled */
850 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
851 /* Number of control flags */
852 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
853};
854
855/*
856 * Control parameter IDs
857 */
4aa3bb0c 858enum control_param_id {
ef6b2ead
IM		 859 /* 0: None, 1: Mic1In*/
860 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 861 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
862 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 863 /* Port A output stage gain setting to use when 16 Ohm output
864 * impedance is selected*/
865 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
866 /* Port D output stage gain setting to use when 16 Ohm output
867 * impedance is selected*/
868 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 869
bf85a91c
CM		 870 /*
871 * This control param name was found in the 8051 memory, and makes
872 * sense given the fact the AE-5 uses it and has the ASI flag set.
873 */
874 CONTROL_PARAM_ASI = 23,
875
95c6e9cb
IM		 876 /* Stream Control */
877
878 /* Select stream with the given ID */
879 CONTROL_PARAM_STREAM_ID = 24,
880 /* Source connection point for the selected stream */
881 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
882 /* Destination connection point for the selected stream */
883 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
884 /* Number of audio channels in the selected stream */
885 CONTROL_PARAM_STREAMS_CHANNELS = 27,
886 /*Enable control for the selected stream */
887 CONTROL_PARAM_STREAM_CONTROL = 28,
888
889 /* Connection Point Control */
890
891 /* Select connection point with the given ID */
892 CONTROL_PARAM_CONN_POINT_ID = 29,
893 /* Connection point sample rate */
894 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
895
896 /* Node Control */
897
898 /* Select HDA node with the given ID */
899 CONTROL_PARAM_NODE_ID = 31
900};
901
902/*
903 * Dsp Io Status codes
904 */
905enum hda_vendor_status_dspio {
906 /* Success */
907 VENDOR_STATUS_DSPIO_OK = 0x00,
908 /* Busy, unable to accept new command, the host must retry */
909 VENDOR_STATUS_DSPIO_BUSY = 0x01,
910 /* SCP command queue is full */
911 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
912 /* SCP response queue is empty */
913 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
914};
915
916/*
917 * Chip Io Status codes
918 */
919enum hda_vendor_status_chipio {
920 /* Success */
921 VENDOR_STATUS_CHIPIO_OK = 0x00,
922 /* Busy, unable to accept new command, the host must retry */
923 VENDOR_STATUS_CHIPIO_BUSY = 0x01
924};
925
926/*
927 * CA0132 sample rate
928 */
929enum ca0132_sample_rate {
930 SR_6_000 = 0x00,
931 SR_8_000 = 0x01,
932 SR_9_600 = 0x02,
933 SR_11_025 = 0x03,
934 SR_16_000 = 0x04,
935 SR_22_050 = 0x05,
936 SR_24_000 = 0x06,
937 SR_32_000 = 0x07,
938 SR_44_100 = 0x08,
939 SR_48_000 = 0x09,
940 SR_88_200 = 0x0A,
941 SR_96_000 = 0x0B,
942 SR_144_000 = 0x0C,
943 SR_176_400 = 0x0D,
944 SR_192_000 = 0x0E,
945 SR_384_000 = 0x0F,
946
947 SR_COUNT = 0x10,
948
949 SR_RATE_UNKNOWN = 0x1F
950};
951
01ef7dbf
IM		 952enum dsp_download_state {
953 DSP_DOWNLOAD_FAILED = -1,
954 DSP_DOWNLOAD_INIT = 0,
955 DSP_DOWNLOADING = 1,
956 DSP_DOWNLOADED = 2
957};
958
01ef7dbf
IM		 959/* retrieve parameters from hda format */
960#define get_hdafmt_chs(fmt) (fmt & 0xf)
961#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
962#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
963#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
964
965/*
966 * CA0132 specific
967 */
968
969struct ca0132_spec {
b0eaa072 970 const struct snd_kcontrol_new *mixers[5];
a7e76271 971 unsigned int num_mixers;
5aaca44d
IM		 972 const struct hda_verb *base_init_verbs;
973 const struct hda_verb *base_exit_verbs;
d5c016b5 974 const struct hda_verb *chip_init_verbs;
e42c7c73 975 const struct hda_verb *desktop_init_verbs;
d5c016b5 976 struct hda_verb *spec_init_verbs;
01ef7dbf 977 struct auto_pin_cfg autocfg;
5aaca44d
IM		 978
979 /* Nodes configurations */
01ef7dbf
IM		 980 struct hda_multi_out multiout;
981 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
982 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 983 unsigned int num_outputs;
01ef7dbf
IM		 984 hda_nid_t input_pins[AUTO_PIN_LAST];
985 hda_nid_t adcs[AUTO_PIN_LAST];
986 hda_nid_t dig_out;
987 hda_nid_t dig_in;
988 unsigned int num_inputs;
a7e76271
IM		 989 hda_nid_t shared_mic_nid;
990 hda_nid_t shared_out_nid;
d5c016b5 991 hda_nid_t unsol_tag_hp;
63177afc 992 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 993 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 994
995 /* chip access */
996 struct mutex chipio_mutex; /* chip access mutex */
997 u32 curr_chip_addx;
998
999 /* DSP download related */
1000 enum dsp_download_state dsp_state;
1001 unsigned int dsp_stream_id;
1002 unsigned int wait_scp;
1003 unsigned int wait_scp_header;
1004 unsigned int wait_num_data;
1005 unsigned int scp_resp_header;
1006 unsigned int scp_resp_data[4];
1007 unsigned int scp_resp_count;
8a19bcee 1008 bool alt_firmware_present;
38ba69ff 1009 bool startup_check_entered;
e93ac30a 1010 bool dsp_reload;
5aaca44d
IM		 1011
1012 /* mixer and effects related */
1013 unsigned char dmic_ctl;
1014 int cur_out_type;
1015 int cur_mic_type;
1016 long vnode_lvol[VNODES_COUNT];
1017 long vnode_rvol[VNODES_COUNT];
1018 long vnode_lswitch[VNODES_COUNT];
1019 long vnode_rswitch[VNODES_COUNT];
1020 long effects_switch[EFFECTS_COUNT];
1021 long voicefx_val;
1022 long cur_mic_boost;
7cb9d94c
CM		 1023 /* ca0132_alt control related values */
1024 unsigned char in_enum_val;
1025 unsigned char out_enum_val;
47cdf76e
CM		 1026 unsigned char mic_boost_enum_val;
1027 unsigned char smart_volume_setting;
1028 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1029 long xbass_xover_freq;
1030 long eq_preset_val;
1031 unsigned int tlv[4];
1032 struct hda_vmaster_mute_hook vmaster_mute;
212de2e7
CM		 1033 /* AE-5 Control values */
1034 unsigned char ae5_headphone_gain_val;
1035 unsigned char ae5_filter_val;
d51434d4
CM		 1036 /* ZxR Control Values */
1037 unsigned char zxr_gain_set;
44f0c978 1038
993884f6
CCC		 1039 struct hda_codec *codec;
1040 struct delayed_work unsol_hp_work;
d5c016b5 1041 int quirk;
993884f6 1042
44f0c978
IM		 1043#ifdef ENABLE_TUNING_CONTROLS
1044 long cur_ctl_vals[TUNING_CTLS_COUNT];
1045#endif
aa31704f 1046 /*
08eca6b1
CM		 1047 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1048 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1049 * things.
aa31704f 1050 */
08eca6b1 1051 bool use_pci_mmio;
aa31704f 1052 void __iomem *mem_base;
009b8f97
CM		 1053
1054 /*
1055 * Whether or not to use the alt functions like alt_select_out,
1056 * alt_select_in, etc. Only used on desktop codecs for now, because of
1057 * surround sound support.
1058 */
1059 bool use_alt_functions;
47cdf76e
CM		 1060
1061 /*
1062 * Whether or not to use alt controls: volume effect sliders, EQ
1063 * presets, smart volume presets, and new control names with FX prefix.
1064 * Renames PlayEnhancement and CrystalVoice too.
1065 */
1066 bool use_alt_controls;
01ef7dbf
IM		 1067};
1068
d5c016b5
GM		 1069/*
1070 * CA0132 quirks table
1071 */
1072enum {
1073 QUIRK_NONE,
1074 QUIRK_ALIENWARE,
a57a46b9 1075 QUIRK_ALIENWARE_M17XR4,
8a19bcee 1076 QUIRK_SBZ,
b29733db
CM		 1077 QUIRK_ZXR,
1078 QUIRK_ZXR_DBPRO,
8a19bcee 1079 QUIRK_R3DI,
8f8c523c 1080 QUIRK_R3D,
f6276463 1081 QUIRK_AE5,
d5c016b5
GM		 1082};
1083
fe14f39e
TI		 1084static const struct hda_pintbl alienware_pincfgs[] = {
1085 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1086 { 0x0c, 0x411111f0 }, /* N/A */
1087 { 0x0d, 0x411111f0 }, /* N/A */
1088 { 0x0e, 0x411111f0 }, /* N/A */
1089 { 0x0f, 0x0321101f }, /* HP */
1090 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1091 { 0x11, 0x03a11021 }, /* Mic */
1092 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1093 { 0x13, 0x411111f0 }, /* N/A */
1094 { 0x18, 0x411111f0 }, /* N/A */
1095 {}
1096};
1097
63177afc
CM		 1098/* Sound Blaster Z pin configs taken from Windows Driver */
1099static const struct hda_pintbl sbz_pincfgs[] = {
1100 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1101 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1102 { 0x0d, 0x014510f0 }, /* Digital Out */
1103 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1104 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1105 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1106 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1107 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1108 { 0x13, 0x908700f0 }, /* What U Hear In*/
1109 { 0x18, 0x50d000f0 }, /* N/A */
1110 {}
1111};
1112
6dcd7244
CM		 1113/* Sound Blaster ZxR pin configs taken from Windows Driver */
1114static const struct hda_pintbl zxr_pincfgs[] = {
1115 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1116 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1117 { 0x0d, 0x014510f0 }, /* Digital Out */
1118 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1119 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1120 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1121 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1122 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1123 { 0x13, 0x908700f0 }, /* What U Hear In*/
1124 { 0x18, 0x50d000f0 }, /* N/A */
1125 {}
1126};
1127
7f73df95
CM		 1128/* Recon3D pin configs taken from Windows Driver */
1129static const struct hda_pintbl r3d_pincfgs[] = {
1130 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1131 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1132 { 0x0d, 0x014510f0 }, /* Digital Out */
1133 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1134 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1135 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1136 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1137 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1138 { 0x13, 0x908700f0 }, /* What U Hear In*/
1139 { 0x18, 0x50d000f0 }, /* N/A */
1140 {}
1141};
1142
d06feaf0
CM		 1143/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1144static const struct hda_pintbl ae5_pincfgs[] = {
1145 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1146 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1147 { 0x0d, 0x014510f0 }, /* Digital Out */
1148 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1149 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1150 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1151 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1152 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1153 { 0x13, 0x908700f0 }, /* What U Hear In*/
1154 { 0x18, 0x50d000f0 }, /* N/A */
1155 {}
1156};
1157
63177afc
CM		 1158/* Recon3D integrated pin configs taken from Windows Driver */
1159static const struct hda_pintbl r3di_pincfgs[] = {
1160 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1161 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1162 { 0x0d, 0x014510f0 }, /* Digital Out */
1163 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1164 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1165 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1166 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1167 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1168 { 0x13, 0x908700f0 }, /* What U Hear In*/
1169 { 0x18, 0x500000f0 }, /* N/A */
1170 {}
1171};
1172
d5c016b5 1173static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1174 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1175 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1176 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1177 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1178 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1179 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
cce99729 1180 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
8a19bcee 1181 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1182 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1183 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1184 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1185 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1186 {}
1187};
1188
01ef7dbf
IM		 1189/*
1190 * CA0132 codec access
1191 */
399ae725 1192static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1193 unsigned int verb, unsigned int parm, unsigned int *res)
1194{
1195 unsigned int response;
1196 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1197 *res = response;
1198
1199 return ((response == -1) ? -1 : 0);
1200}
1201
1202static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1203 unsigned short converter_format, unsigned int *res)
1204{
1205 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1206 converter_format & 0xffff, res);
1207}
1208
1209static int codec_set_converter_stream_channel(struct hda_codec *codec,
1210 hda_nid_t nid, unsigned char stream,
1211 unsigned char channel, unsigned int *res)
1212{
1213 unsigned char converter_stream_channel = 0;
1214
1215 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1216 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1217 converter_stream_channel, res);
1218}
1219
1220/* Chip access helper function */
1221static int chipio_send(struct hda_codec *codec,
1222 unsigned int reg,
1223 unsigned int data)
1224{
1225 unsigned int res;
6d67530e 1226 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1227
1228 /* send bits of data specified by reg */
1229 do {
1230 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1231 reg, data);
1232 if (res == VENDOR_STATUS_CHIPIO_OK)
1233 return 0;
6d67530e
IM		 1234 msleep(20);
1235 } while (time_before(jiffies, timeout));
1236
01ef7dbf
IM		 1237 return -EIO;
1238}
1239
1240/*
1241 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1242 */
1243static int chipio_write_address(struct hda_codec *codec,
1244 unsigned int chip_addx)
1245{
4861af80 1246 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1247 int res;
1248
4861af80
IM		 1249 if (spec->curr_chip_addx == chip_addx)
1250 return 0;
1251
01ef7dbf
IM		 1252 /* send low 16 bits of the address */
1253 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1254 chip_addx & 0xffff);
1255
1256 if (res != -EIO) {
1257 /* send high 16 bits of the address */
1258 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1259 chip_addx >> 16);
1260 }
1261
d1600401 1262 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1263
4861af80 1264 return res;
01ef7dbf
IM		 1265}
1266
1267/*
1268 * Write data through the vendor widget -- NOT protected by the Mutex!
1269 */
01ef7dbf
IM		 1270static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1271{
5aaca44d 1272 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1273 int res;
1274
1275 /* send low 16 bits of the data */
1276 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1277
1278 if (res != -EIO) {
1279 /* send high 16 bits of the data */
1280 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1281 data >> 16);
1282 }
1283
5aaca44d
IM		 1284 /*If no error encountered, automatically increment the address
1285 as per chip behaviour*/
1286 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1287 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1288 return res;
1289}
1290
d5c21b88
IM		 1291/*
1292 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1293 */
01ef7dbf
IM		 1294static int chipio_write_data_multiple(struct hda_codec *codec,
1295 const u32 *data,
1296 unsigned int count)
1297{
1298 int status = 0;
1299
1300 if (data == NULL) {
4e76a883 1301 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1302 return -EINVAL;
1303 }
1304
1305 while ((count-- != 0) && (status == 0))
1306 status = chipio_write_data(codec, *data++);
1307
1308 return status;
1309}
1310
1311
1312/*
1313 * Read data through the vendor widget -- NOT protected by the Mutex!
1314 */
1315static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1316{
5aaca44d 1317 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1318 int res;
1319
1320 /* post read */
1321 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1322
1323 if (res != -EIO) {
1324 /* read status */
1325 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1326 }
1327
1328 if (res != -EIO) {
1329 /* read data */
1330 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1331 VENDOR_CHIPIO_HIC_READ_DATA,
1332 0);
1333 }
1334
5aaca44d
IM		 1335 /*If no error encountered, automatically increment the address
1336 as per chip behaviour*/
1337 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1338 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1339 return res;
1340}
1341
1342/*
1343 * Write given value to the given address through the chip I/O widget.
1344 * protected by the Mutex
1345 */
1346static int chipio_write(struct hda_codec *codec,
1347 unsigned int chip_addx, const unsigned int data)
1348{
1349 struct ca0132_spec *spec = codec->spec;
1350 int err;
1351
1352 mutex_lock(&spec->chipio_mutex);
1353
1354 /* write the address, and if successful proceed to write data */
1355 err = chipio_write_address(codec, chip_addx);
1356 if (err < 0)
1357 goto exit;
1358
1359 err = chipio_write_data(codec, data);
1360 if (err < 0)
1361 goto exit;
1362
1363exit:
1364 mutex_unlock(&spec->chipio_mutex);
1365 return err;
1366}
1367
38ba69ff
CM		 1368/*
1369 * Write given value to the given address through the chip I/O widget.
1370 * not protected by the Mutex
1371 */
1372static int chipio_write_no_mutex(struct hda_codec *codec,
1373 unsigned int chip_addx, const unsigned int data)
1374{
1375 int err;
1376
1377
1378 /* write the address, and if successful proceed to write data */
1379 err = chipio_write_address(codec, chip_addx);
1380 if (err < 0)
1381 goto exit;
1382
1383 err = chipio_write_data(codec, data);
1384 if (err < 0)
1385 goto exit;
1386
1387exit:
1388 return err;
1389}
1390
d5c21b88
IM		 1391/*
1392 * Write multiple values to the given address through the chip I/O widget.
1393 * protected by the Mutex
1394 */
01ef7dbf
IM		 1395static int chipio_write_multiple(struct hda_codec *codec,
1396 u32 chip_addx,
1397 const u32 *data,
1398 unsigned int count)
1399{
1400 struct ca0132_spec *spec = codec->spec;
1401 int status;
1402
1403 mutex_lock(&spec->chipio_mutex);
4861af80 1404 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1405 if (status < 0)
1406 goto error;
1407
1408 status = chipio_write_data_multiple(codec, data, count);
1409error:
1410 mutex_unlock(&spec->chipio_mutex);
1411
1412 return status;
1413}
1414
1415/*
1416 * Read the given address through the chip I/O widget
1417 * protected by the Mutex
1418 */
1419static int chipio_read(struct hda_codec *codec,
1420 unsigned int chip_addx, unsigned int *data)
1421{
1422 struct ca0132_spec *spec = codec->spec;
1423 int err;
1424
1425 mutex_lock(&spec->chipio_mutex);
1426
1427 /* write the address, and if successful proceed to write data */
1428 err = chipio_write_address(codec, chip_addx);
1429 if (err < 0)
1430 goto exit;
1431
1432 err = chipio_read_data(codec, data);
1433 if (err < 0)
1434 goto exit;
1435
1436exit:
1437 mutex_unlock(&spec->chipio_mutex);
1438 return err;
1439}
1440
d5c21b88
IM		 1441/*
1442 * Set chip control flags through the chip I/O widget.
1443 */
01ef7dbf
IM		 1444static void chipio_set_control_flag(struct hda_codec *codec,
1445 enum control_flag_id flag_id,
1446 bool flag_state)
1447{
1448 unsigned int val;
1449 unsigned int flag_bit;
1450
1451 flag_bit = (flag_state ? 1 : 0);
1452 val = (flag_bit << 7) | (flag_id);
1453 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1454 VENDOR_CHIPIO_FLAG_SET, val);
1455}
1456
d5c21b88
IM		 1457/*
1458 * Set chip parameters through the chip I/O widget.
1459 */
01ef7dbf
IM		 1460static void chipio_set_control_param(struct hda_codec *codec,
1461 enum control_param_id param_id, int param_val)
1462{
1463 struct ca0132_spec *spec = codec->spec;
1464 int val;
1465
1466 if ((param_id < 32) && (param_val < 8)) {
1467 val = (param_val << 5) | (param_id);
1468 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1469 VENDOR_CHIPIO_PARAM_SET, val);
1470 } else {
1471 mutex_lock(&spec->chipio_mutex);
1472 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1473 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1474 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1475 param_id);
1476 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1477 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1478 param_val);
1479 }
1480 mutex_unlock(&spec->chipio_mutex);
1481 }
1482}
1483
009b8f97
CM		 1484/*
1485 * Set chip parameters through the chip I/O widget. NO MUTEX.
1486 */
1487static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1488 enum control_param_id param_id, int param_val)
1489{
1490 int val;
1491
1492 if ((param_id < 32) && (param_val < 8)) {
1493 val = (param_val << 5) | (param_id);
1494 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1495 VENDOR_CHIPIO_PARAM_SET, val);
1496 } else {
1497 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1498 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1499 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1500 param_id);
1501 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1502 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1503 param_val);
1504 }
1505 }
1506}
38ba69ff
CM		 1507/*
1508 * Connect stream to a source point, and then connect
1509 * that source point to a destination point.
1510 */
1511static void chipio_set_stream_source_dest(struct hda_codec *codec,
1512 int streamid, int source_point, int dest_point)
1513{
1514 chipio_set_control_param_no_mutex(codec,
1515 CONTROL_PARAM_STREAM_ID, streamid);
1516 chipio_set_control_param_no_mutex(codec,
1517 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1518 chipio_set_control_param_no_mutex(codec,
1519 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1520}
1521
1522/*
1523 * Set number of channels in the selected stream.
1524 */
1525static void chipio_set_stream_channels(struct hda_codec *codec,
1526 int streamid, unsigned int channels)
1527{
1528 chipio_set_control_param_no_mutex(codec,
1529 CONTROL_PARAM_STREAM_ID, streamid);
1530 chipio_set_control_param_no_mutex(codec,
1531 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1532}
009b8f97
CM		 1533
1534/*
1535 * Enable/Disable audio stream.
1536 */
1537static void chipio_set_stream_control(struct hda_codec *codec,
1538 int streamid, int enable)
1539{
1540 chipio_set_control_param_no_mutex(codec,
1541 CONTROL_PARAM_STREAM_ID, streamid);
1542 chipio_set_control_param_no_mutex(codec,
1543 CONTROL_PARAM_STREAM_CONTROL, enable);
1544}
1545
38ba69ff
CM		 1546
1547/*
1548 * Set sampling rate of the connection point. NO MUTEX.
1549 */
1550static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1551 int connid, enum ca0132_sample_rate rate)
1552{
1553 chipio_set_control_param_no_mutex(codec,
1554 CONTROL_PARAM_CONN_POINT_ID, connid);
1555 chipio_set_control_param_no_mutex(codec,
1556 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1557}
1558
d5c21b88
IM		 1559/*
1560 * Set sampling rate of the connection point.
1561 */
01ef7dbf
IM		 1562static void chipio_set_conn_rate(struct hda_codec *codec,
1563 int connid, enum ca0132_sample_rate rate)
1564{
1565 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1566 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1567 rate);
1568}
1569
b9b41345
CM		 1570/*
1571 * Writes to the 8051's internal address space directly instead of indirectly,
1572 * giving access to the special function registers located at addresses
1573 * 0x80-0xFF.
1574 */
1575static void chipio_8051_write_direct(struct hda_codec *codec,
1576 unsigned int addr, unsigned int data)
1577{
1578 unsigned int verb;
1579
1580 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1581 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1582}
1583
d5c21b88
IM		 1584/*
1585 * Enable clocks.
1586 */
01ef7dbf
IM		 1587static void chipio_enable_clocks(struct hda_codec *codec)
1588{
1589 struct ca0132_spec *spec = codec->spec;
1590
1591 mutex_lock(&spec->chipio_mutex);
1592 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1593 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1594 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1595 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1596 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1597 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1598 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1599 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1601 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1602 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1603 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1604 mutex_unlock(&spec->chipio_mutex);
1605}
1606
1607/*
1608 * CA0132 DSP IO stuffs
1609 */
1610static int dspio_send(struct hda_codec *codec, unsigned int reg,
1611 unsigned int data)
1612{
b645d796 1613 int res;
6d67530e 1614 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1615
1616 /* send bits of data specified by reg to dsp */
1617 do {
1618 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1619 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1620 return res;
6d67530e
IM		 1621 msleep(20);
1622 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1623
1624 return -EIO;
1625}
1626
d5c21b88
IM		 1627/*
1628 * Wait for DSP to be ready for commands
1629 */
01ef7dbf
IM		 1630static void dspio_write_wait(struct hda_codec *codec)
1631{
4861af80
IM		 1632 int status;
1633 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1634
01ef7dbf 1635 do {
4861af80
IM		 1636 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1637 VENDOR_DSPIO_STATUS, 0);
1638 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1639 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1640 break;
1641 msleep(1);
1642 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1643}
1644
d5c21b88
IM		 1645/*
1646 * Write SCP data to DSP
1647 */
01ef7dbf
IM		 1648static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1649{
1650 struct ca0132_spec *spec = codec->spec;
1651 int status;
1652
1653 dspio_write_wait(codec);
1654
1655 mutex_lock(&spec->chipio_mutex);
1656 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1657 scp_data & 0xffff);
1658 if (status < 0)
1659 goto error;
1660
1661 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1662 scp_data >> 16);
1663 if (status < 0)
1664 goto error;
1665
1666 /* OK, now check if the write itself has executed*/
1667 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1668 VENDOR_DSPIO_STATUS, 0);
1669error:
1670 mutex_unlock(&spec->chipio_mutex);
1671
1672 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1673 -EIO : 0;
1674}
1675
d5c21b88
IM		 1676/*
1677 * Write multiple SCP data to DSP
1678 */
01ef7dbf
IM		 1679static int dspio_write_multiple(struct hda_codec *codec,
1680 unsigned int *buffer, unsigned int size)
1681{
1682 int status = 0;
1683 unsigned int count;
1684
a16fbb85 1685 if (buffer == NULL)
01ef7dbf
IM		 1686 return -EINVAL;
1687
1688 count = 0;
1689 while (count < size) {
1690 status = dspio_write(codec, *buffer++);
1691 if (status != 0)
1692 break;
1693 count++;
1694 }
1695
1696 return status;
1697}
1698
a73d511c
IM		 1699static int dspio_read(struct hda_codec *codec, unsigned int *data)
1700{
1701 int status;
1702
1703 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1704 if (status == -EIO)
1705 return status;
1706
1707 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1708 if (status == -EIO ||
1709 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1710 return -EIO;
1711
1712 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1713 VENDOR_DSPIO_SCP_READ_DATA, 0);
1714
1715 return 0;
1716}
1717
1718static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1719 unsigned int *buf_size, unsigned int size_count)
1720{
1721 int status = 0;
1722 unsigned int size = *buf_size;
1723 unsigned int count;
1724 unsigned int skip_count;
1725 unsigned int dummy;
1726
a16fbb85 1727 if (buffer == NULL)
a73d511c
IM		 1728 return -1;
1729
1730 count = 0;
1731 while (count < size && count < size_count) {
1732 status = dspio_read(codec, buffer++);
1733 if (status != 0)
1734 break;
1735 count++;
1736 }
1737
1738 skip_count = count;
1739 if (status == 0) {
1740 while (skip_count < size) {
1741 status = dspio_read(codec, &dummy);
1742 if (status != 0)
1743 break;
1744 skip_count++;
1745 }
1746 }
1747 *buf_size = count;
1748
1749 return status;
1750}
1751
d5c21b88
IM		 1752/*
1753 * Construct the SCP header using corresponding fields
1754 */
01ef7dbf
IM		 1755static inline unsigned int
1756make_scp_header(unsigned int target_id, unsigned int source_id,
1757 unsigned int get_flag, unsigned int req,
1758 unsigned int device_flag, unsigned int resp_flag,
1759 unsigned int error_flag, unsigned int data_size)
1760{
1761 unsigned int header = 0;
1762
1763 header = (data_size & 0x1f) << 27;
1764 header |= (error_flag & 0x01) << 26;
1765 header |= (resp_flag & 0x01) << 25;
1766 header |= (device_flag & 0x01) << 24;
1767 header |= (req & 0x7f) << 17;
1768 header |= (get_flag & 0x01) << 16;
1769 header |= (source_id & 0xff) << 8;
1770 header |= target_id & 0xff;
1771
1772 return header;
1773}
1774
d5c21b88
IM		 1775/*
1776 * Extract corresponding fields from SCP header
1777 */
01ef7dbf
IM		 1778static inline void
1779extract_scp_header(unsigned int header,
1780 unsigned int *target_id, unsigned int *source_id,
1781 unsigned int *get_flag, unsigned int *req,
1782 unsigned int *device_flag, unsigned int *resp_flag,
1783 unsigned int *error_flag, unsigned int *data_size)
1784{
1785 if (data_size)
1786 *data_size = (header >> 27) & 0x1f;
1787 if (error_flag)
1788 *error_flag = (header >> 26) & 0x01;
1789 if (resp_flag)
1790 *resp_flag = (header >> 25) & 0x01;
1791 if (device_flag)
1792 *device_flag = (header >> 24) & 0x01;
1793 if (req)
1794 *req = (header >> 17) & 0x7f;
1795 if (get_flag)
1796 *get_flag = (header >> 16) & 0x01;
1797 if (source_id)
1798 *source_id = (header >> 8) & 0xff;
1799 if (target_id)
1800 *target_id = header & 0xff;
1801}
1802
1803#define SCP_MAX_DATA_WORDS (16)
1804
1805/* Structure to contain any SCP message */
1806struct scp_msg {
1807 unsigned int hdr;
1808 unsigned int data[SCP_MAX_DATA_WORDS];
1809};
1810
a73d511c
IM		 1811static void dspio_clear_response_queue(struct hda_codec *codec)
1812{
1813 unsigned int dummy = 0;
1814 int status = -1;
1815
1816 /* clear all from the response queue */
1817 do {
1818 status = dspio_read(codec, &dummy);
1819 } while (status == 0);
1820}
1821
1822static int dspio_get_response_data(struct hda_codec *codec)
1823{
1824 struct ca0132_spec *spec = codec->spec;
1825 unsigned int data = 0;
1826 unsigned int count;
1827
1828 if (dspio_read(codec, &data) < 0)
1829 return -EIO;
1830
1831 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1832 spec->scp_resp_header = data;
1833 spec->scp_resp_count = data >> 27;
1834 count = spec->wait_num_data;
1835 dspio_read_multiple(codec, spec->scp_resp_data,
1836 &spec->scp_resp_count, count);
1837 return 0;
1838 }
1839
1840 return -EIO;
1841}
1842
d5c21b88
IM		 1843/*
1844 * Send SCP message to DSP
1845 */
01ef7dbf
IM		 1846static int dspio_send_scp_message(struct hda_codec *codec,
1847 unsigned char *send_buf,
1848 unsigned int send_buf_size,
1849 unsigned char *return_buf,
1850 unsigned int return_buf_size,
1851 unsigned int *bytes_returned)
1852{
1853 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1854 int status = -1;
1855 unsigned int scp_send_size = 0;
1856 unsigned int total_size;
1857 bool waiting_for_resp = false;
1858 unsigned int header;
1859 struct scp_msg *ret_msg;
1860 unsigned int resp_src_id, resp_target_id;
1861 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1862
1863 if (bytes_returned)
1864 *bytes_returned = 0;
1865
1866 /* get scp header from buffer */
1867 header = *((unsigned int *)send_buf);
1868 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1869 &device_flag, NULL, NULL, &data_size);
1870 scp_send_size = data_size + 1;
1871 total_size = (scp_send_size * 4);
1872
1873 if (send_buf_size < total_size)
1874 return -EINVAL;
1875
1876 if (get_flag || device_flag) {
1877 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1878 return -EINVAL;
1879
1880 spec->wait_scp_header = *((unsigned int *)send_buf);
1881
1882 /* swap source id with target id */
1883 resp_target_id = src_id;
1884 resp_src_id = target_id;
1885 spec->wait_scp_header &= 0xffff0000;
1886 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1887 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1888 spec->wait_scp = 1;
1889 waiting_for_resp = true;
1890 }
1891
1892 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1893 scp_send_size);
1894 if (status < 0) {
1895 spec->wait_scp = 0;
1896 return status;
1897 }
1898
1899 if (waiting_for_resp) {
6d67530e 1900 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1901 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1902 do {
1903 msleep(20);
6d67530e 1904 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1905 waiting_for_resp = false;
6d67530e 1906 if (!spec->wait_scp) {
01ef7dbf
IM		 1907 ret_msg = (struct scp_msg *)return_buf;
1908 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1909 memcpy(&ret_msg->data, spec->scp_resp_data,
1910 spec->wait_num_data);
1911 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1912 status = 0;
1913 } else {
1914 status = -EIO;
1915 }
1916 spec->wait_scp = 0;
1917 }
1918
1919 return status;
1920}
1921
d5c21b88
IM		 1922/**
1923 * Prepare and send the SCP message to DSP
1924 * @codec: the HDA codec
1925 * @mod_id: ID of the DSP module to send the command
1926 * @req: ID of request to send to the DSP module
1927 * @dir: SET or GET
1928 * @data: pointer to the data to send with the request, request specific
1929 * @len: length of the data, in bytes
1930 * @reply: point to the buffer to hold data returned for a reply
1931 * @reply_len: length of the reply buffer returned from GET
1932 *
1933 * Returns zero or a negative error code.
1934 */
01ef7dbf 1935static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1936 int mod_id, int src_id, int req, int dir, const void *data,
1937 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1938{
1939 int status = 0;
1940 struct scp_msg scp_send, scp_reply;
1941 unsigned int ret_bytes, send_size, ret_size;
1942 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1943 unsigned int reply_data_size;
1944
1945 memset(&scp_send, 0, sizeof(scp_send));
1946 memset(&scp_reply, 0, sizeof(scp_reply));
1947
1948 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1949 return -EINVAL;
1950
1951 if (dir == SCP_GET && reply == NULL) {
4e76a883 1952 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1953 return -EINVAL;
1954 }
1955
1956 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1957 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1958 return -EINVAL;
1959 }
1960
447fd8e9 1961 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1962 0, 0, 0, len/sizeof(unsigned int));
1963 if (data != NULL && len > 0) {
1964 len = min((unsigned int)(sizeof(scp_send.data)), len);
1965 memcpy(scp_send.data, data, len);
1966 }
1967
1968 ret_bytes = 0;
1969 send_size = sizeof(unsigned int) + len;
1970 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1971 send_size, (unsigned char *)&scp_reply,
1972 sizeof(scp_reply), &ret_bytes);
1973
1974 if (status < 0) {
4e76a883 1975 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1976 return status;
1977 }
1978
1979 /* extract send and reply headers members */
1980 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1981 NULL, NULL, NULL, NULL, NULL);
1982 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1983 &reply_resp_flag, &reply_error_flag,
1984 &reply_data_size);
1985
1986 if (!send_get_flag)
1987 return 0;
1988
1989 if (reply_resp_flag && !reply_error_flag) {
1990 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1991 / sizeof(unsigned int);
1992
1993 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1994 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1995 return -EINVAL;
1996 } else if (ret_size != reply_data_size) {
4e76a883 1997 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1998 return -EINVAL;
46a049da
AB		 1999 } else if (!reply) {
2000 codec_dbg(codec, "NULL reply\n");
2001 return -EINVAL;
01ef7dbf
IM		 2002 } else {
2003 *reply_len = ret_size*sizeof(unsigned int);
2004 memcpy(reply, scp_reply.data, *reply_len);
2005 }
2006 } else {
4e76a883 2007 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 2008 return -EIO;
2009 }
2010
2011 return status;
2012}
2013
5aaca44d
IM		 2014/*
2015 * Set DSP parameters
2016 */
2017static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 2018 int src_id, int req, const void *data, unsigned int len)
5aaca44d 2019{
447fd8e9
CM		 2020 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2021 NULL);
5aaca44d
IM		 2022}
2023
2024static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 2025 int req, const unsigned int data)
5aaca44d 2026{
447fd8e9
CM		 2027 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2028 sizeof(unsigned int));
2029}
2030
2031static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2032 int req, const unsigned int data)
2033{
2034 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2035 sizeof(unsigned int));
5aaca44d
IM		 2036}
2037
d5c21b88
IM		 2038/*
2039 * Allocate a DSP DMA channel via an SCP message
2040 */
01ef7dbf
IM		 2041static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2042{
2043 int status = 0;
2044 unsigned int size = sizeof(dma_chan);
2045
4e76a883 2046 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 2047 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2048 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2049 dma_chan, &size);
01ef7dbf
IM		 2050
2051 if (status < 0) {
4e76a883 2052 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2053 return status;
2054 }
2055
2056 if ((*dma_chan + 1) == 0) {
4e76a883 2057 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 2058 return -EBUSY;
2059 }
2060
4e76a883
TI		 2061 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2062 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 2063
2064 return status;
2065}
2066
d5c21b88
IM		 2067/*
2068 * Free a DSP DMA via an SCP message
2069 */
01ef7dbf
IM		 2070static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2071{
2072 int status = 0;
2073 unsigned int dummy = 0;
2074
4e76a883
TI		 2075 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2076 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 2077
447fd8e9
CM		 2078 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2079 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2080 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 2081
2082 if (status < 0) {
4e76a883 2083 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2084 return status;
2085 }
2086
4e76a883 2087 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2088
2089 return status;
2090}
2091
2092/*
d5c21b88 2093 * (Re)start the DSP
01ef7dbf
IM		 2094 */
2095static int dsp_set_run_state(struct hda_codec *codec)
2096{
2097 unsigned int dbg_ctrl_reg;
2098 unsigned int halt_state;
2099 int err;
2100
2101 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2102 if (err < 0)
2103 return err;
2104
2105 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2106 DSP_DBGCNTL_STATE_LOBIT;
2107
2108 if (halt_state != 0) {
2109 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2110 DSP_DBGCNTL_SS_MASK);
2111 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2112 dbg_ctrl_reg);
2113 if (err < 0)
2114 return err;
2115
2116 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2117 DSP_DBGCNTL_EXEC_MASK;
2118 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2119 dbg_ctrl_reg);
2120 if (err < 0)
2121 return err;
2122 }
2123
2124 return 0;
2125}
2126
d5c21b88
IM		 2127/*
2128 * Reset the DSP
2129 */
01ef7dbf
IM		 2130static int dsp_reset(struct hda_codec *codec)
2131{
2132 unsigned int res;
2133 int retry = 20;
2134
4e76a883 2135 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2136 do {
2137 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2138 retry--;
2139 } while (res == -EIO && retry);
2140
2141 if (!retry) {
4e76a883 2142 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2143 return -EIO;
2144 }
2145
2146 return 0;
2147}
2148
d5c21b88
IM		 2149/*
2150 * Convert chip address to DSP address
2151 */
01ef7dbf
IM		 2152static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2153 bool *code, bool *yram)
2154{
2155 *code = *yram = false;
2156
2157 if (UC_RANGE(chip_addx, 1)) {
2158 *code = true;
2159 return UC_OFF(chip_addx);
2160 } else if (X_RANGE_ALL(chip_addx, 1)) {
2161 return X_OFF(chip_addx);
2162 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2163 *yram = true;
2164 return Y_OFF(chip_addx);
2165 }
2166
4a8b89f9 2167 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2168}
2169
d5c21b88
IM		 2170/*
2171 * Check if the DSP DMA is active
2172 */
01ef7dbf
IM		 2173static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2174{
2175 unsigned int dma_chnlstart_reg;
2176
2177 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2178
2179 return ((dma_chnlstart_reg & (1 <<
2180 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2181}
2182
2183static int dsp_dma_setup_common(struct hda_codec *codec,
2184 unsigned int chip_addx,
2185 unsigned int dma_chan,
2186 unsigned int port_map_mask,
2187 bool ovly)
2188{
2189 int status = 0;
2190 unsigned int chnl_prop;
2191 unsigned int dsp_addx;
2192 unsigned int active;
2193 bool code, yram;
2194
4e76a883 2195 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2196
2197 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2198 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2199 return -EINVAL;
2200 }
2201
2202 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2203 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2204 return -EBUSY;
2205 }
2206
2207 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2208
2209 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2210 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2211 return -ENXIO;
2212 }
2213
2214 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2215 active = 0;
2216
4e76a883 2217 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2218
2219 if (ovly) {
2220 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2221 &chnl_prop);
2222
2223 if (status < 0) {
4e76a883 2224 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2225 return status;
2226 }
4e76a883 2227 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2228 }
2229
2230 if (!code)
2231 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2232 else
2233 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2234
2235 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2236
2237 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2238 if (status < 0) {
4e76a883 2239 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2240 return status;
2241 }
4e76a883 2242 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2243
2244 if (ovly) {
2245 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2246 &active);
2247
2248 if (status < 0) {
4e76a883 2249 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2250 return status;
2251 }
4e76a883 2252 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2253 }
2254
2255 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2256 DSPDMAC_ACTIVE_AAR_MASK;
2257
2258 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2259 if (status < 0) {
4e76a883 2260 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2261 return status;
2262 }
2263
4e76a883 2264 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2265
2266 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2267 port_map_mask);
2268 if (status < 0) {
4e76a883 2269 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2270 return status;
2271 }
4e76a883 2272 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2273
2274 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2275 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2276 if (status < 0) {
4e76a883 2277 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2278 return status;
2279 }
4e76a883 2280 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2281
4e76a883 2282 codec_dbg(codec,
01ef7dbf
IM		 2283 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2284 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2285 chip_addx, dsp_addx, dma_chan,
2286 port_map_mask, chnl_prop, active);
2287
4e76a883 2288 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2289
2290 return 0;
2291}
2292
d5c21b88
IM		 2293/*
2294 * Setup the DSP DMA per-transfer-specific registers
2295 */
01ef7dbf
IM		 2296static int dsp_dma_setup(struct hda_codec *codec,
2297 unsigned int chip_addx,
2298 unsigned int count,
2299 unsigned int dma_chan)
2300{
2301 int status = 0;
2302 bool code, yram;
2303 unsigned int dsp_addx;
2304 unsigned int addr_field;
2305 unsigned int incr_field;
2306 unsigned int base_cnt;
2307 unsigned int cur_cnt;
2308 unsigned int dma_cfg = 0;
2309 unsigned int adr_ofs = 0;
2310 unsigned int xfr_cnt = 0;
2311 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2312 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2313
4e76a883 2314 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2315
2316 if (count > max_dma_count) {
4e76a883 2317 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2318 return -EINVAL;
2319 }
2320
2321 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2322 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2323 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2324 return -ENXIO;
2325 }
2326
4e76a883 2327 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2328
2329 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2330 incr_field = 0;
2331
2332 if (!code) {
2333 addr_field <<= 1;
2334 if (yram)
2335 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2336
2337 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2338 }
2339
2340 dma_cfg = addr_field + incr_field;
2341 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2342 dma_cfg);
2343 if (status < 0) {
4e76a883 2344 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2345 return status;
2346 }
4e76a883 2347 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2348
2349 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2350 (code ? 0 : 1));
2351
2352 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2353 adr_ofs);
2354 if (status < 0) {
4e76a883 2355 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2356 return status;
2357 }
4e76a883 2358 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2359
2360 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2361
2362 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2363
2364 xfr_cnt = base_cnt | cur_cnt;
2365
2366 status = chipio_write(codec,
2367 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2368 if (status < 0) {
4e76a883 2369 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2370 return status;
2371 }
4e76a883 2372 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2373
4e76a883 2374 codec_dbg(codec,
01ef7dbf
IM		 2375 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2376 "ADROFS=0x%x, XFRCNT=0x%x\n",
2377 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2378
4e76a883 2379 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2380
2381 return 0;
2382}
2383
d5c21b88
IM		 2384/*
2385 * Start the DSP DMA
2386 */
01ef7dbf
IM		 2387static int dsp_dma_start(struct hda_codec *codec,
2388 unsigned int dma_chan, bool ovly)
2389{
2390 unsigned int reg = 0;
2391 int status = 0;
2392
4e76a883 2393 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2394
2395 if (ovly) {
2396 status = chipio_read(codec,
2397 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2398
2399 if (status < 0) {
4e76a883 2400 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2401 return status;
2402 }
4e76a883 2403 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2404
2405 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2406 DSPDMAC_CHNLSTART_DIS_MASK);
2407 }
2408
2409 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2410 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2411 if (status < 0) {
4e76a883 2412 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2413 return status;
2414 }
4e76a883 2415 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2416
2417 return status;
2418}
2419
d5c21b88
IM		 2420/*
2421 * Stop the DSP DMA
2422 */
01ef7dbf
IM		 2423static int dsp_dma_stop(struct hda_codec *codec,
2424 unsigned int dma_chan, bool ovly)
2425{
2426 unsigned int reg = 0;
2427 int status = 0;
2428
4e76a883 2429 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2430
2431 if (ovly) {
2432 status = chipio_read(codec,
2433 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2434
2435 if (status < 0) {
4e76a883 2436 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2437 return status;
2438 }
4e76a883 2439 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2440 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2441 DSPDMAC_CHNLSTART_DIS_MASK);
2442 }
2443
2444 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2445 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2446 if (status < 0) {
4e76a883 2447 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2448 return status;
2449 }
4e76a883 2450 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2451
2452 return status;
2453}
2454
d5c21b88
IM		 2455/**
2456 * Allocate router ports
2457 *
2458 * @codec: the HDA codec
2459 * @num_chans: number of channels in the stream
2460 * @ports_per_channel: number of ports per channel
2461 * @start_device: start device
2462 * @port_map: pointer to the port list to hold the allocated ports
2463 *
2464 * Returns zero or a negative error code.
2465 */
01ef7dbf
IM		 2466static int dsp_allocate_router_ports(struct hda_codec *codec,
2467 unsigned int num_chans,
2468 unsigned int ports_per_channel,
2469 unsigned int start_device,
2470 unsigned int *port_map)
2471{
2472 int status = 0;
2473 int res;
2474 u8 val;
2475
2476 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2477 if (status < 0)
2478 return status;
2479
2480 val = start_device << 6;
2481 val |= (ports_per_channel - 1) << 4;
2482 val |= num_chans - 1;
2483
2484 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2485 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2486 val);
2487
2488 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2489 VENDOR_CHIPIO_PORT_ALLOC_SET,
2490 MEM_CONNID_DSP);
2491
2492 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2493 if (status < 0)
2494 return status;
2495
2496 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2497 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2498
2499 *port_map = res;
2500
2501 return (res < 0) ? res : 0;
2502}
2503
d5c21b88
IM		 2504/*
2505 * Free router ports
2506 */
01ef7dbf
IM		 2507static int dsp_free_router_ports(struct hda_codec *codec)
2508{
2509 int status = 0;
2510
2511 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2512 if (status < 0)
2513 return status;
2514
2515 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2516 VENDOR_CHIPIO_PORT_FREE_SET,
2517 MEM_CONNID_DSP);
2518
2519 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2520
2521 return status;
2522}
2523
d5c21b88
IM		 2524/*
2525 * Allocate DSP ports for the download stream
2526 */
01ef7dbf
IM		 2527static int dsp_allocate_ports(struct hda_codec *codec,
2528 unsigned int num_chans,
2529 unsigned int rate_multi, unsigned int *port_map)
2530{
2531 int status;
2532
4e76a883 2533 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2534
2535 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2536 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2537 return -EINVAL;
2538 }
2539
2540 status = dsp_allocate_router_ports(codec, num_chans,
2541 rate_multi, 0, port_map);
2542
4e76a883 2543 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2544
2545 return status;
2546}
2547
01ef7dbf
IM		 2548static int dsp_allocate_ports_format(struct hda_codec *codec,
2549 const unsigned short fmt,
2550 unsigned int *port_map)
2551{
2552 int status;
2553 unsigned int num_chans;
2554
2555 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2556 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2557 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2558
2559 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2560 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2561 return -EINVAL;
2562 }
2563
2564 num_chans = get_hdafmt_chs(fmt) + 1;
2565
2566 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2567
2568 return status;
2569}
2570
d5c21b88
IM		 2571/*
2572 * free DSP ports
2573 */
2574static int dsp_free_ports(struct hda_codec *codec)
2575{
2576 int status;
2577
4e76a883 2578 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2579
2580 status = dsp_free_router_ports(codec);
2581 if (status < 0) {
4e76a883 2582 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2583 return status;
2584 }
4e76a883 2585 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2586
2587 return status;
2588}
2589
01ef7dbf
IM		 2590/*
2591 * HDA DMA engine stuffs for DSP code download
2592 */
2593struct dma_engine {
2594 struct hda_codec *codec;
2595 unsigned short m_converter_format;
2596 struct snd_dma_buffer *dmab;
2597 unsigned int buf_size;
2598};
2599
2600
2601enum dma_state {
2602 DMA_STATE_STOP = 0,
2603 DMA_STATE_RUN = 1
2604};
2605
6194b99d 2606static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2607 unsigned int sample_rate,
2608 unsigned short channels,
01ef7dbf
IM		 2609 unsigned short *hda_format)
2610{
2611 unsigned int format_val;
2612
b7d023e1
TI		 2613 format_val = snd_hdac_calc_stream_format(sample_rate,
2614 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2615
2616 if (hda_format)
2617 *hda_format = (unsigned short)format_val;
2618
2619 return 0;
2620}
2621
d5c21b88
IM		 2622/*
2623 * Reset DMA for DSP download
2624 */
01ef7dbf
IM		 2625static int dma_reset(struct dma_engine *dma)
2626{
2627 struct hda_codec *codec = dma->codec;
2628 struct ca0132_spec *spec = codec->spec;
2629 int status;
2630
b3667bd7 2631 if (dma->dmab->area)
01ef7dbf
IM		 2632 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2633
2634 status = snd_hda_codec_load_dsp_prepare(codec,
2635 dma->m_converter_format,
2636 dma->buf_size,
2637 dma->dmab);
2638 if (status < 0)
2639 return status;
2640 spec->dsp_stream_id = status;
2641 return 0;
2642}
2643
2644static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2645{
01ef7dbf
IM		 2646 bool cmd;
2647
01ef7dbf
IM		 2648 switch (state) {
2649 case DMA_STATE_STOP:
2650 cmd = false;
2651 break;
2652 case DMA_STATE_RUN:
2653 cmd = true;
2654 break;
2655 default:
c41999a2
DH		 2656 return 0;
2657 }
01ef7dbf
IM		 2658
2659 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2660 return 0;
95c6e9cb
IM		 2661}
2662
01ef7dbf
IM		 2663static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2664{
2665 return dma->dmab->bytes;
2666}
95c6e9cb 2667
01ef7dbf
IM		 2668static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2669{
2670 return dma->dmab->area;
2671}
95c6e9cb 2672
01ef7dbf
IM		 2673static int dma_xfer(struct dma_engine *dma,
2674 const unsigned int *data,
2675 unsigned int count)
2676{
2677 memcpy(dma->dmab->area, data, count);
2678 return 0;
2679}
95c6e9cb 2680
01ef7dbf
IM		 2681static void dma_get_converter_format(
2682 struct dma_engine *dma,
2683 unsigned short *format)
2684{
2685 if (format)
2686 *format = dma->m_converter_format;
2687}
95c6e9cb 2688
01ef7dbf 2689static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2690{
01ef7dbf 2691 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2692
01ef7dbf 2693 return spec->dsp_stream_id;
95c6e9cb
IM		 2694}
2695
01ef7dbf
IM		 2696struct dsp_image_seg {
2697 u32 magic;
2698 u32 chip_addr;
2699 u32 count;
2700 u32 data[0];
2701};
2702
2703static const u32 g_magic_value = 0x4c46584d;
2704static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2705
2706static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2707{
01ef7dbf
IM		 2708 return p->magic == g_magic_value;
2709}
95c6e9cb 2710
01ef7dbf
IM		 2711static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2712{
2713 return g_chip_addr_magic_value == p->chip_addr;
2714}
95c6e9cb 2715
01ef7dbf
IM		 2716static bool is_last(const struct dsp_image_seg *p)
2717{
2718 return p->count == 0;
2719}
95c6e9cb 2720
01ef7dbf
IM		 2721static size_t dsp_sizeof(const struct dsp_image_seg *p)
2722{
2723 return sizeof(*p) + p->count*sizeof(u32);
2724}
2725
2726static const struct dsp_image_seg *get_next_seg_ptr(
2727 const struct dsp_image_seg *p)
2728{
2729 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2730}
2731
2732/*
01ef7dbf 2733 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2734 */
8ae3124b 2735#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2736
d5c21b88
IM		 2737/*
2738 * Program a list of address/data pairs via the ChipIO widget.
2739 * The segment data is in the format of successive pairs of words.
2740 * These are repeated as indicated by the segment's count field.
2741 */
01ef7dbf
IM		 2742static int dspxfr_hci_write(struct hda_codec *codec,
2743 const struct dsp_image_seg *fls)
95c6e9cb 2744{
01ef7dbf
IM		 2745 int status;
2746 const u32 *data;
2747 unsigned int count;
95c6e9cb 2748
01ef7dbf 2749 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2750 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2751 return -EINVAL;
95c6e9cb
IM		 2752 }
2753
01ef7dbf
IM		 2754 count = fls->count;
2755 data = (u32 *)(fls->data);
2756 while (count >= 2) {
2757 status = chipio_write(codec, data[0], data[1]);
2758 if (status < 0) {
4e76a883 2759 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2760 return status;
2761 }
2762 count -= 2;
2763 data += 2;
2764 }
2765 return 0;
95c6e9cb
IM		 2766}
2767
d5c21b88
IM		 2768/**
2769 * Write a block of data into DSP code or data RAM using pre-allocated
2770 * DMA engine.
2771 *
2772 * @codec: the HDA codec
2773 * @fls: pointer to a fast load image
2774 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2775 * no relocation
2776 * @dma_engine: pointer to DMA engine to be used for DSP download
2777 * @dma_chan: The number of DMA channels used for DSP download
2778 * @port_map_mask: port mapping
2779 * @ovly: TRUE if overlay format is required
2780 *
2781 * Returns zero or a negative error code.
2782 */
01ef7dbf
IM		 2783static int dspxfr_one_seg(struct hda_codec *codec,
2784 const struct dsp_image_seg *fls,
2785 unsigned int reloc,
2786 struct dma_engine *dma_engine,
2787 unsigned int dma_chan,
2788 unsigned int port_map_mask,
2789 bool ovly)
95c6e9cb 2790{
406261ce 2791 int status = 0;
01ef7dbf
IM		 2792 bool comm_dma_setup_done = false;
2793 const unsigned int *data;
2794 unsigned int chip_addx;
2795 unsigned int words_to_write;
2796 unsigned int buffer_size_words;
2797 unsigned char *buffer_addx;
2798 unsigned short hda_format;
2799 unsigned int sample_rate_div;
2800 unsigned int sample_rate_mul;
2801 unsigned int num_chans;
2802 unsigned int hda_frame_size_words;
2803 unsigned int remainder_words;
2804 const u32 *data_remainder;
2805 u32 chip_addx_remainder;
2806 unsigned int run_size_words;
2807 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2808 unsigned long timeout;
2809 bool dma_active;
01ef7dbf
IM		 2810
2811 if (fls == NULL)
2812 return -EINVAL;
2813 if (is_hci_prog_list_seg(fls)) {
2814 hci_write = fls;
2815 fls = get_next_seg_ptr(fls);
2816 }
95c6e9cb 2817
01ef7dbf 2818 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2819 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2820 return dspxfr_hci_write(codec, hci_write);
2821 }
95c6e9cb 2822
01ef7dbf 2823 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2824 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2825 return -EINVAL;
95c6e9cb
IM		 2826 }
2827
01ef7dbf
IM		 2828 data = fls->data;
2829 chip_addx = fls->chip_addr,
2830 words_to_write = fls->count;
2831
2832 if (!words_to_write)
2833 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2834 if (reloc)
2835 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2836
2837 if (!UC_RANGE(chip_addx, words_to_write) &&
2838 !X_RANGE_ALL(chip_addx, words_to_write) &&
2839 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2840 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2841 return -EINVAL;
95c6e9cb
IM		 2842 }
2843
01ef7dbf
IM		 2844 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2845 sizeof(u32);
2846
2847 buffer_addx = dma_get_buffer_addr(dma_engine);
2848
2849 if (buffer_addx == NULL) {
4e76a883 2850 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2851 return -EINVAL;
2852 }
2853
2854 dma_get_converter_format(dma_engine, &hda_format);
2855 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2856 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2857 num_chans = get_hdafmt_chs(hda_format) + 1;
2858
2859 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2860 (num_chans * sample_rate_mul / sample_rate_div));
2861
3bc085a1 2862 if (hda_frame_size_words == 0) {
4e76a883 2863 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2864 return -EINVAL;
2865 }
2866
01ef7dbf
IM		 2867 buffer_size_words = min(buffer_size_words,
2868 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2869 65536 : 32768));
2870 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2871 codec_dbg(codec,
01ef7dbf
IM		 2872 "chpadr=0x%08x frmsz=%u nchan=%u "
2873 "rate_mul=%u div=%u bufsz=%u\n",
2874 chip_addx, hda_frame_size_words, num_chans,
2875 sample_rate_mul, sample_rate_div, buffer_size_words);
2876
3bc085a1 2877 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2878 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2879 return -EINVAL;
2880 }
2881
2882 remainder_words = words_to_write % hda_frame_size_words;
2883 data_remainder = data;
2884 chip_addx_remainder = chip_addx;
2885
2886 data += remainder_words;
2887 chip_addx += remainder_words*sizeof(u32);
2888 words_to_write -= remainder_words;
2889
2890 while (words_to_write != 0) {
2891 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2892 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2893 words_to_write, run_size_words, remainder_words);
2894 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2895 if (!comm_dma_setup_done) {
2896 status = dsp_dma_stop(codec, dma_chan, ovly);
2897 if (status < 0)
425a7880 2898 return status;
01ef7dbf
IM		 2899 status = dsp_dma_setup_common(codec, chip_addx,
2900 dma_chan, port_map_mask, ovly);
2901 if (status < 0)
2902 return status;
2903 comm_dma_setup_done = true;
2904 }
2905
2906 status = dsp_dma_setup(codec, chip_addx,
2907 run_size_words, dma_chan);
2908 if (status < 0)
2909 return status;
2910 status = dsp_dma_start(codec, dma_chan, ovly);
2911 if (status < 0)
2912 return status;
2913 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2914 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2915 return -EIO;
2916 }
2917 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2918 if (status < 0)
2919 return status;
2920 if (remainder_words != 0) {
2921 status = chipio_write_multiple(codec,
2922 chip_addx_remainder,
2923 data_remainder,
2924 remainder_words);
b3667bd7
TI		 2925 if (status < 0)
2926 return status;
01ef7dbf
IM		 2927 remainder_words = 0;
2928 }
2929 if (hci_write) {
2930 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2931 if (status < 0)
2932 return status;
01ef7dbf
IM		 2933 hci_write = NULL;
2934 }
6d67530e
IM		 2935
2936 timeout = jiffies + msecs_to_jiffies(2000);
2937 do {
2938 dma_active = dsp_is_dma_active(codec, dma_chan);
2939 if (!dma_active)
01ef7dbf 2940 break;
6d67530e
IM		 2941 msleep(20);
2942 } while (time_before(jiffies, timeout));
2943 if (dma_active)
2944 break;
2945
4e76a883 2946 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2947 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2948 status = dma_reset(dma_engine);
01ef7dbf
IM		 2949
2950 if (status < 0)
2951 return status;
2952
2953 data += run_size_words;
2954 chip_addx += run_size_words*sizeof(u32);
2955 words_to_write -= run_size_words;
2956 }
2957
2958 if (remainder_words != 0) {
2959 status = chipio_write_multiple(codec, chip_addx_remainder,
2960 data_remainder, remainder_words);
2961 }
2962
2963 return status;
95c6e9cb
IM		 2964}
2965
d5c21b88
IM		 2966/**
2967 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2968 *
2969 * @codec: the HDA codec
2970 * @fls_data: pointer to a fast load image
2971 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2972 * no relocation
e97249dd 2973 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2974 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2975 * @ovly: TRUE if overlay format is required
2976 *
2977 * Returns zero or a negative error code.
2978 */
01ef7dbf
IM		 2979static int dspxfr_image(struct hda_codec *codec,
2980 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2981 unsigned int reloc,
2982 unsigned int sample_rate,
2983 unsigned short channels,
01ef7dbf 2984 bool ovly)
95c6e9cb
IM		 2985{
2986 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2987 int status;
2988 unsigned short hda_format = 0;
2989 unsigned int response;
2990 unsigned char stream_id = 0;
2991 struct dma_engine *dma_engine;
2992 unsigned int dma_chan;
2993 unsigned int port_map_mask;
2994
2995 if (fls_data == NULL)
2996 return -EINVAL;
2997
2998 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2999 if (!dma_engine)
3000 return -ENOMEM;
95c6e9cb 3001
01ef7dbf
IM		 3002 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3003 if (!dma_engine->dmab) {
549e8292
TI		 3004 kfree(dma_engine);
3005 return -ENOMEM;
01ef7dbf 3006 }
95c6e9cb 3007
01ef7dbf 3008 dma_engine->codec = codec;
6194b99d 3009 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 3010 dma_engine->m_converter_format = hda_format;
3011 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3012 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3013
8ae3124b 3014 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 3015
3016 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3017 hda_format, &response);
3018
3019 if (status < 0) {
4e76a883 3020 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 3021 goto exit;
3022 }
3023
3024 status = snd_hda_codec_load_dsp_prepare(codec,
3025 dma_engine->m_converter_format,
3026 dma_engine->buf_size,
3027 dma_engine->dmab);
3028 if (status < 0)
95c6e9cb 3029 goto exit;
01ef7dbf
IM		 3030 spec->dsp_stream_id = status;
3031
3032 if (ovly) {
3033 status = dspio_alloc_dma_chan(codec, &dma_chan);
3034 if (status < 0) {
4e76a883 3035 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 3036 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 3037 goto exit;
3038 }
3039 }
95c6e9cb 3040
01ef7dbf
IM		 3041 port_map_mask = 0;
3042 status = dsp_allocate_ports_format(codec, hda_format,
3043 &port_map_mask);
3044 if (status < 0) {
4e76a883 3045 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 3046 goto exit;
3047 }
3048
3049 stream_id = dma_get_stream_id(dma_engine);
3050 status = codec_set_converter_stream_channel(codec,
3051 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3052 if (status < 0) {
4e76a883 3053 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 3054 goto exit;
3055 }
3056
3057 while ((fls_data != NULL) && !is_last(fls_data)) {
3058 if (!is_valid(fls_data)) {
4e76a883 3059 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 3060 status = -EINVAL;
3061 goto exit;
3062 }
3063 status = dspxfr_one_seg(codec, fls_data, reloc,
3064 dma_engine, dma_chan,
3065 port_map_mask, ovly);
3066 if (status < 0)
3067 break;
3068
3069 if (is_hci_prog_list_seg(fls_data))
3070 fls_data = get_next_seg_ptr(fls_data);
3071
3072 if ((fls_data != NULL) && !is_last(fls_data))
3073 fls_data = get_next_seg_ptr(fls_data);
3074 }
3075
3076 if (port_map_mask != 0)
3077 status = dsp_free_ports(codec);
3078
3079 if (status < 0)
95c6e9cb
IM		 3080 goto exit;
3081
01ef7dbf
IM		 3082 status = codec_set_converter_stream_channel(codec,
3083 WIDGET_CHIP_CTRL, 0, 0, &response);
3084
95c6e9cb 3085exit:
01ef7dbf
IM		 3086 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3087 dspio_free_dma_chan(codec, dma_chan);
3088
b3667bd7 3089 if (dma_engine->dmab->area)
01ef7dbf
IM		 3090 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3091 kfree(dma_engine->dmab);
3092 kfree(dma_engine);
3093
3094 return status;
95c6e9cb
IM		 3095}
3096
3097/*
01ef7dbf 3098 * CA0132 DSP download stuffs.
95c6e9cb 3099 */
01ef7dbf 3100static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3101{
009b8f97 3102 struct ca0132_spec *spec = codec->spec;
4e76a883 3103 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 3104 if (!spec->use_alt_functions) {
3105 /*set DSP speaker to 2.0 configuration*/
3106 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3107 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3108
009b8f97
CM		 3109 /*update write pointer*/
3110 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3111 }
01ef7dbf 3112}
95c6e9cb 3113
d5c21b88 3114/**
e60b2c7f 3115 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3116 *
3117 * @codec: the HDA codec
3118 * @fls: pointer to a fast load image
3119 * @ovly: TRUE if overlay format is required
3120 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3121 * no relocation
3122 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3123 * @router_chans: number of audio router channels to be allocated (0 means use
3124 * internal defaults; max is 32)
3125 *
e60b2c7f
TI		 3126 * Download DSP from a DSP Image Fast Load structure. This structure is a
3127 * linear, non-constant sized element array of structures, each of which
3128 * contain the count of the data to be loaded, the data itself, and the
3129 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3130 * Returns zero or a negative error code.
3131 */
01ef7dbf
IM		 3132static int dspload_image(struct hda_codec *codec,
3133 const struct dsp_image_seg *fls,
3134 bool ovly,
3135 unsigned int reloc,
3136 bool autostart,
3137 int router_chans)
3138{
3139 int status = 0;
e97249dd
IM		 3140 unsigned int sample_rate;
3141 unsigned short channels;
01ef7dbf 3142
4e76a883 3143 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3144 if (router_chans == 0) {
3145 if (!ovly)
3146 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3147 else
3148 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3149 }
95c6e9cb 3150
e97249dd
IM		 3151 sample_rate = 48000;
3152 channels = (unsigned short)router_chans;
01ef7dbf 3153
e97249dd
IM		 3154 while (channels > 16) {
3155 sample_rate *= 2;
3156 channels /= 2;
01ef7dbf
IM		 3157 }
3158
01ef7dbf 3159 do {
4e76a883 3160 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3161 if (!ovly)
3162 status = dsp_reset(codec);
3163
3164 if (status < 0)
3165 break;
3166
4e76a883 3167 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3168 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3169 ovly);
01ef7dbf
IM		 3170
3171 if (status < 0)
3172 break;
3173
4e76a883 3174 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3175 if (autostart && !ovly) {
3176 dspload_post_setup(codec);
3177 status = dsp_set_run_state(codec);
3178 }
3179
4e76a883 3180 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3181 } while (0);
3182
3183 return status;
3184}
3185
f664417e 3186#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3187static bool dspload_is_loaded(struct hda_codec *codec)
3188{
3189 unsigned int data = 0;
3190 int status = 0;
3191
3192 status = chipio_read(codec, 0x40004, &data);
3193 if ((status < 0) || (data != 1))
3194 return false;
3195
3196 return true;
3197}
f664417e
TI		 3198#else
3199#define dspload_is_loaded(codec) false
3200#endif
01ef7dbf
IM		 3201
3202static bool dspload_wait_loaded(struct hda_codec *codec)
3203{
6d67530e 3204 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3205
3206 do {
01ef7dbf 3207 if (dspload_is_loaded(codec)) {
d9684bb5 3208 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3209 return true;
3210 }
6d67530e
IM		 3211 msleep(20);
3212 } while (time_before(jiffies, timeout));
01ef7dbf 3213
d9684bb5 3214 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3215 return false;
95c6e9cb
IM		 3216}
3217
e93ac30a 3218/*
b9b41345
CM		 3219 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3220 * based cards, and has a second mmio region, region2, that's used for special
3221 * commands.
e93ac30a
CM		 3222 */
3223
a62e4739
CM		 3224/*
3225 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3226 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3227 * The first eight bits are just the number of the pin. So far, I've only seen
3228 * this number go to 7.
b9b41345
CM		 3229 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3230 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3231 * then off to send that bit.
a62e4739 3232 */
b9b41345 3233static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3234 bool enable)
3235{
3236 struct ca0132_spec *spec = codec->spec;
3237 unsigned short gpio_data;
3238
3239 gpio_data = gpio_pin & 0xF;
3240 gpio_data |= ((enable << 8) & 0x100);
3241
3242 writew(gpio_data, spec->mem_base + 0x320);
3243}
3244
b9b41345
CM		 3245/*
3246 * Special pci region2 commands that are only used by the AE-5. They follow
3247 * a set format, and require reads at certain points to seemingly 'clear'
3248 * the response data. My first tests didn't do these reads, and would cause
3249 * the card to get locked up until the memory was read. These commands
3250 * seem to work with three distinct values that I've taken to calling group,
3251 * target-id, and value.
3252 */
3253static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3254 unsigned int target, unsigned int value)
3255{
3256 struct ca0132_spec *spec = codec->spec;
3257 unsigned int write_val;
3258
3259 writel(0x0000007e, spec->mem_base + 0x210);
3260 readl(spec->mem_base + 0x210);
3261 writel(0x0000005a, spec->mem_base + 0x210);
3262 readl(spec->mem_base + 0x210);
3263 readl(spec->mem_base + 0x210);
3264
3265 writel(0x00800005, spec->mem_base + 0x20c);
3266 writel(group, spec->mem_base + 0x804);
3267
3268 writel(0x00800005, spec->mem_base + 0x20c);
3269 write_val = (target & 0xff);
3270 write_val |= (value << 8);
3271
3272
3273 writel(write_val, spec->mem_base + 0x204);
3274 /*
3275 * Need delay here or else it goes too fast and works inconsistently.
3276 */
3277 msleep(20);
3278
3279 readl(spec->mem_base + 0x860);
3280 readl(spec->mem_base + 0x854);
3281 readl(spec->mem_base + 0x840);
3282
3283 writel(0x00800004, spec->mem_base + 0x20c);
3284 writel(0x00000000, spec->mem_base + 0x210);
3285 readl(spec->mem_base + 0x210);
3286 readl(spec->mem_base + 0x210);
3287}
3288
212de2e7
CM		 3289/*
3290 * This second type of command is used for setting the sound filter type.
3291 */
3292static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3293 unsigned int group, unsigned int target, unsigned int value)
3294{
3295 struct ca0132_spec *spec = codec->spec;
3296 unsigned int write_val;
3297
3298 writel(0x0000007e, spec->mem_base + 0x210);
3299 readl(spec->mem_base + 0x210);
3300 writel(0x0000005a, spec->mem_base + 0x210);
3301 readl(spec->mem_base + 0x210);
3302 readl(spec->mem_base + 0x210);
3303
3304 writel(0x00800003, spec->mem_base + 0x20c);
3305 writel(group, spec->mem_base + 0x804);
3306
3307 writel(0x00800005, spec->mem_base + 0x20c);
3308 write_val = (target & 0xff);
3309 write_val |= (value << 8);
3310
3311
3312 writel(write_val, spec->mem_base + 0x204);
3313 msleep(20);
3314 readl(spec->mem_base + 0x860);
3315 readl(spec->mem_base + 0x854);
3316 readl(spec->mem_base + 0x840);
3317
3318 writel(0x00800004, spec->mem_base + 0x20c);
3319 writel(0x00000000, spec->mem_base + 0x210);
3320 readl(spec->mem_base + 0x210);
3321 readl(spec->mem_base + 0x210);
3322}
3323
b9b41345
CM		 3324/*
3325 * Setup GPIO for the other variants of Core3D.
3326 */
3327
e93ac30a
CM		 3328/*
3329 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3330 * the card shows as having no GPIO pins.
3331 */
3332static void ca0132_gpio_init(struct hda_codec *codec)
3333{
3334 struct ca0132_spec *spec = codec->spec;
3335
3336 switch (spec->quirk) {
3337 case QUIRK_SBZ:
03c9b6b1 3338 case QUIRK_AE5:
e93ac30a
CM		 3339 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3340 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3341 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3342 break;
3343 case QUIRK_R3DI:
3344 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3345 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3346 break;
3347 }
3348
3349}
3350
3351/* Sets the GPIO for audio output. */
3352static void ca0132_gpio_setup(struct hda_codec *codec)
3353{
3354 struct ca0132_spec *spec = codec->spec;
3355
3356 switch (spec->quirk) {
3357 case QUIRK_SBZ:
3358 snd_hda_codec_write(codec, 0x01, 0,
3359 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3360 snd_hda_codec_write(codec, 0x01, 0,
3361 AC_VERB_SET_GPIO_MASK, 0x07);
3362 snd_hda_codec_write(codec, 0x01, 0,
3363 AC_VERB_SET_GPIO_DATA, 0x04);
3364 snd_hda_codec_write(codec, 0x01, 0,
3365 AC_VERB_SET_GPIO_DATA, 0x06);
3366 break;
3367 case QUIRK_R3DI:
3368 snd_hda_codec_write(codec, 0x01, 0,
3369 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3370 snd_hda_codec_write(codec, 0x01, 0,
3371 AC_VERB_SET_GPIO_MASK, 0x1F);
3372 snd_hda_codec_write(codec, 0x01, 0,
3373 AC_VERB_SET_GPIO_DATA, 0x0C);
3374 break;
3375 }
3376}
3377
7e6ed62e
CM		 3378/*
3379 * GPIO control functions for the Recon3D integrated.
3380 */
3381
3382enum r3di_gpio_bit {
3383 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3384 R3DI_MIC_SELECT_BIT = 1,
3385 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3386 R3DI_OUT_SELECT_BIT = 2,
3387 /*
3388 * I dunno what this actually does, but it stays on until the dsp
3389 * is downloaded.
3390 */
3391 R3DI_GPIO_DSP_DOWNLOADING = 3,
3392 /*
3393 * Same as above, no clue what it does, but it comes on after the dsp
3394 * is downloaded.
3395 */
3396 R3DI_GPIO_DSP_DOWNLOADED = 4
3397};
3398
3399enum r3di_mic_select {
3400 /* Set GPIO bit 1 to 0 for rear mic */
3401 R3DI_REAR_MIC = 0,
3402 /* Set GPIO bit 1 to 1 for front microphone*/
3403 R3DI_FRONT_MIC = 1
3404};
3405
3406enum r3di_out_select {
3407 /* Set GPIO bit 2 to 0 for headphone */
3408 R3DI_HEADPHONE_OUT = 0,
3409 /* Set GPIO bit 2 to 1 for speaker */
3410 R3DI_LINE_OUT = 1
3411};
3412enum r3di_dsp_status {
3413 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3414 R3DI_DSP_DOWNLOADING = 0,
3415 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3416 R3DI_DSP_DOWNLOADED = 1
3417};
3418
7cb9d94c
CM		 3419
3420static void r3di_gpio_mic_set(struct hda_codec *codec,
3421 enum r3di_mic_select cur_mic)
3422{
3423 unsigned int cur_gpio;
3424
3425 /* Get the current GPIO Data setup */
3426 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3427
3428 switch (cur_mic) {
3429 case R3DI_REAR_MIC:
3430 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3431 break;
3432 case R3DI_FRONT_MIC:
3433 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3434 break;
3435 }
3436 snd_hda_codec_write(codec, codec->core.afg, 0,
3437 AC_VERB_SET_GPIO_DATA, cur_gpio);
3438}
3439
3440static void r3di_gpio_out_set(struct hda_codec *codec,
3441 enum r3di_out_select cur_out)
3442{
3443 unsigned int cur_gpio;
3444
3445 /* Get the current GPIO Data setup */
3446 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3447
3448 switch (cur_out) {
3449 case R3DI_HEADPHONE_OUT:
3450 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3451 break;
3452 case R3DI_LINE_OUT:
3453 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3454 break;
3455 }
3456 snd_hda_codec_write(codec, codec->core.afg, 0,
3457 AC_VERB_SET_GPIO_DATA, cur_gpio);
3458}
3459
7e6ed62e
CM		 3460static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3461 enum r3di_dsp_status dsp_status)
3462{
3463 unsigned int cur_gpio;
3464
3465 /* Get the current GPIO Data setup */
3466 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3467
3468 switch (dsp_status) {
3469 case R3DI_DSP_DOWNLOADING:
3470 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3471 snd_hda_codec_write(codec, codec->core.afg, 0,
3472 AC_VERB_SET_GPIO_DATA, cur_gpio);
3473 break;
3474 case R3DI_DSP_DOWNLOADED:
3475 /* Set DOWNLOADING bit to 0. */
3476 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3477
3478 snd_hda_codec_write(codec, codec->core.afg, 0,
3479 AC_VERB_SET_GPIO_DATA, cur_gpio);
3480
3481 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3482 break;
3483 }
3484
3485 snd_hda_codec_write(codec, codec->core.afg, 0,
3486 AC_VERB_SET_GPIO_DATA, cur_gpio);
3487}
3488
825315bc
IM		 3489/*
3490 * PCM callbacks
3491 */
95c6e9cb
IM		 3492static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3493 struct hda_codec *codec,
3494 unsigned int stream_tag,
3495 unsigned int format,
3496 struct snd_pcm_substream *substream)
3497{
3498 struct ca0132_spec *spec = codec->spec;
825315bc 3499
28fba950 3500 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3501
3502 return 0;
95c6e9cb
IM		 3503}
3504
3505static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3506 struct hda_codec *codec,
3507 struct snd_pcm_substream *substream)
3508{
3509 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3510
3511 if (spec->dsp_state == DSP_DOWNLOADING)
3512 return 0;
3513
3514 /*If Playback effects are on, allow stream some time to flush
3515 *effects tail*/
3516 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3517 msleep(50);
3518
28fba950 3519 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3520
3521 return 0;
95c6e9cb
IM		 3522}
3523
e8412ca4
DR		 3524static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3525 struct hda_codec *codec,
3526 struct snd_pcm_substream *substream)
3527{
3528 struct ca0132_spec *spec = codec->spec;
3529 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3530 struct snd_pcm_runtime *runtime = substream->runtime;
3531
3532 if (spec->dsp_state != DSP_DOWNLOADED)
3533 return 0;
3534
3535 /* Add latency if playback enhancement and either effect is enabled. */
3536 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3537 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3538 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3539 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3540 }
3541
3542 /* Applying Speaker EQ adds latency as well. */
3543 if (spec->cur_out_type == SPEAKER_OUT)
3544 latency += DSP_SPEAKER_OUT_LATENCY;
3545
3546 return (latency * runtime->rate) / 1000;
3547}
3548
95c6e9cb
IM		 3549/*
3550 * Digital out
3551 */
27ebeb0b
TI		 3552static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3553 struct hda_codec *codec,
3554 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3555{
3556 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3557 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3558}
3559
27ebeb0b 3560static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3561 struct hda_codec *codec,
3562 unsigned int stream_tag,
3563 unsigned int format,
3564 struct snd_pcm_substream *substream)
3565{
3566 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3567 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3568 stream_tag, format, substream);
95c6e9cb
IM		 3569}
3570
27ebeb0b 3571static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3572 struct hda_codec *codec,
95c6e9cb
IM		 3573 struct snd_pcm_substream *substream)
3574{
3575 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3576 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3577}
3578
27ebeb0b
TI		 3579static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3580 struct hda_codec *codec,
3581 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3582{
3583 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3584 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3585}
3586
825315bc
IM		 3587/*
3588 * Analog capture
3589 */
3590static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3591 struct hda_codec *codec,
3592 unsigned int stream_tag,
3593 unsigned int format,
3594 struct snd_pcm_substream *substream)
3595{
13c12dbe 3596 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3597 stream_tag, 0, format);
825315bc
IM		 3598
3599 return 0;
3600}
3601
3602static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3603 struct hda_codec *codec,
3604 struct snd_pcm_substream *substream)
3605{
3606 struct ca0132_spec *spec = codec->spec;
3607
3608 if (spec->dsp_state == DSP_DOWNLOADING)
3609 return 0;
3610
28fba950 3611 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3612 return 0;
3613}
3614
e8412ca4
DR		 3615static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3616 struct hda_codec *codec,
3617 struct snd_pcm_substream *substream)
3618{
3619 struct ca0132_spec *spec = codec->spec;
3620 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3621 struct snd_pcm_runtime *runtime = substream->runtime;
3622
3623 if (spec->dsp_state != DSP_DOWNLOADED)
3624 return 0;
3625
3626 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3627 latency += DSP_CRYSTAL_VOICE_LATENCY;
3628
3629 return (latency * runtime->rate) / 1000;
3630}
3631
e90f29e4
IM		 3632/*
3633 * Controls stuffs.
3634 */
3635
3636/*
3637 * Mixer controls helpers.
3638 */
3639#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3640 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3641 .name = xname, \
3642 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3643 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3644 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3645 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3646 .info = ca0132_volume_info, \
3647 .get = ca0132_volume_get, \
3648 .put = ca0132_volume_put, \
3649 .tlv = { .c = ca0132_volume_tlv }, \
3650 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3651
017310fb
CM		 3652/*
3653 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3654 * volume put, which is used for setting the DSP volume. This was done because
3655 * the ca0132 functions were taking too much time and causing lag.
3656 */
3657#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3658 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3659 .name = xname, \
3660 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3661 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3662 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3663 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3664 .info = snd_hda_mixer_amp_volume_info, \
3665 .get = snd_hda_mixer_amp_volume_get, \
3666 .put = ca0132_alt_volume_put, \
3667 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3668 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3669
e90f29e4
IM		 3670#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3671 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3672 .name = xname, \
3673 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3674 .info = snd_hda_mixer_amp_switch_info, \
3675 .get = ca0132_switch_get, \
3676 .put = ca0132_switch_put, \
3677 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3678
3679/* stereo */
3680#define CA0132_CODEC_VOL(xname, nid, dir) \
3681 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3682#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3683 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3684#define CA0132_CODEC_MUTE(xname, nid, dir) \
3685 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3686
017310fb
CM		 3687/* lookup tables */
3688/*
3689 * Lookup table with decibel values for the DSP. When volume is changed in
3690 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3691 * these values have decimal points, probably because the Windows driver
3692 * actually uses floating point. We can't here, so I made a lookup table of
3693 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3694 * DAC's, and 9 is the maximum.
3695 */
3696static const unsigned int float_vol_db_lookup[] = {
36970xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
36980xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
36990xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
37000xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
37010xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
37020xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
37030xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
37040xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
37050xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
37060xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
37070xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
37080xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
37090xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37100xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
37110xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
37120x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
37130x40C00000, 0x40E00000, 0x41000000, 0x41100000
3714};
3715
47cdf76e
CM		 3716/*
3717 * This table counts from float 0 to 1 in increments of .01, which is
3718 * useful for a few different sliders.
3719 */
3720static const unsigned int float_zero_to_one_lookup[] = {
37210x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37220x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37230x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37240x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37250x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37260x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37270x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37280x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37290x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37300x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37310x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37320x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37330x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37340x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37350x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37360x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37370x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3738};
3739
3740/*
3741 * This table counts from float 10 to 1000, which is the range of the x-bass
3742 * crossover slider in Windows.
3743 */
3744static const unsigned int float_xbass_xover_lookup[] = {
37450x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
37460x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
37470x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
37480x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
37490x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
37500x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
37510x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
37520x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
37530x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
37540x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
37550x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
37560x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
37570x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
37580x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
37590x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
37600x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
37610x44728000, 0x44750000, 0x44778000, 0x447A0000
3762};
3763
4091fb95 3764/* The following are for tuning of products */
44f0c978
IM		 3765#ifdef ENABLE_TUNING_CONTROLS
3766
3767static unsigned int voice_focus_vals_lookup[] = {
37680x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
37690x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
37700x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
37710x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
37720x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
37730x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
37740x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
37750x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
37760x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
37770x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
37780x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
37790x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
37800x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
37810x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
37820x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
37830x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
37840x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
37850x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
37860x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
37870x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
37880x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
37890x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
37900x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
37910x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
37920x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
37930x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
37940x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3795};
3796
3797static unsigned int mic_svm_vals_lookup[] = {
37980x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37990x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
38000x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
38010x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
38020x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
38030x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
38040x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
38050x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
38060x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
38070x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
38080x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
38090x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
38100x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
38110x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
38120x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
38130x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
38140x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3815};
3816
3817static unsigned int equalizer_vals_lookup[] = {
38180xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
38190xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
38200xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
38210xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
38220x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
38230x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
38240x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
38250x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
38260x41C00000
3827};
3828
3829static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3830 unsigned int *lookup, int idx)
3831{
3832 int i = 0;
3833
3834 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3835 if (nid == ca0132_tuning_ctls[i].nid)
3836 break;
3837
3838 snd_hda_power_up(codec);
447fd8e9 3839 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3840 ca0132_tuning_ctls[i].req,
3841 &(lookup[idx]), sizeof(unsigned int));
3842 snd_hda_power_down(codec);
3843
3844 return 1;
3845}
3846
3847static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3848 struct snd_ctl_elem_value *ucontrol)
3849{
3850 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3851 struct ca0132_spec *spec = codec->spec;
3852 hda_nid_t nid = get_amp_nid(kcontrol);
3853 long *valp = ucontrol->value.integer.value;
3854 int idx = nid - TUNING_CTL_START_NID;
3855
3856 *valp = spec->cur_ctl_vals[idx];
3857 return 0;
3858}
3859
3860static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3861 struct snd_ctl_elem_info *uinfo)
3862{
3863 int chs = get_amp_channels(kcontrol);
3864 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3865 uinfo->count = chs == 3 ? 2 : 1;
3866 uinfo->value.integer.min = 20;
3867 uinfo->value.integer.max = 180;
3868 uinfo->value.integer.step = 1;
3869
3870 return 0;
3871}
3872
3873static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3874 struct snd_ctl_elem_value *ucontrol)
3875{
3876 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3877 struct ca0132_spec *spec = codec->spec;
3878 hda_nid_t nid = get_amp_nid(kcontrol);
3879 long *valp = ucontrol->value.integer.value;
3880 int idx;
3881
3882 idx = nid - TUNING_CTL_START_NID;
3883 /* any change? */
3884 if (spec->cur_ctl_vals[idx] == *valp)
3885 return 0;
3886
3887 spec->cur_ctl_vals[idx] = *valp;
3888
3889 idx = *valp - 20;
3890 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3891
3892 return 1;
3893}
3894
3895static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3896 struct snd_ctl_elem_info *uinfo)
3897{
3898 int chs = get_amp_channels(kcontrol);
3899 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3900 uinfo->count = chs == 3 ? 2 : 1;
3901 uinfo->value.integer.min = 0;
3902 uinfo->value.integer.max = 100;
3903 uinfo->value.integer.step = 1;
3904
3905 return 0;
3906}
3907
3908static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3909 struct snd_ctl_elem_value *ucontrol)
3910{
3911 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3912 struct ca0132_spec *spec = codec->spec;
3913 hda_nid_t nid = get_amp_nid(kcontrol);
3914 long *valp = ucontrol->value.integer.value;
3915 int idx;
3916
3917 idx = nid - TUNING_CTL_START_NID;
3918 /* any change? */
3919 if (spec->cur_ctl_vals[idx] == *valp)
3920 return 0;
3921
3922 spec->cur_ctl_vals[idx] = *valp;
3923
3924 idx = *valp;
3925 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3926
3927 return 0;
3928}
3929
3930static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3931 struct snd_ctl_elem_info *uinfo)
3932{
3933 int chs = get_amp_channels(kcontrol);
3934 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3935 uinfo->count = chs == 3 ? 2 : 1;
3936 uinfo->value.integer.min = 0;
3937 uinfo->value.integer.max = 48;
3938 uinfo->value.integer.step = 1;
3939
3940 return 0;
3941}
3942
3943static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3944 struct snd_ctl_elem_value *ucontrol)
3945{
3946 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3947 struct ca0132_spec *spec = codec->spec;
3948 hda_nid_t nid = get_amp_nid(kcontrol);
3949 long *valp = ucontrol->value.integer.value;
3950 int idx;
3951
3952 idx = nid - TUNING_CTL_START_NID;
3953 /* any change? */
3954 if (spec->cur_ctl_vals[idx] == *valp)
3955 return 0;
3956
3957 spec->cur_ctl_vals[idx] = *valp;
3958
3959 idx = *valp;
3960 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3961
3962 return 1;
3963}
3964
8e142e9e
TS		 3965static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3966static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3967
3968static int add_tuning_control(struct hda_codec *codec,
3969 hda_nid_t pnid, hda_nid_t nid,
3970 const char *name, int dir)
3971{
975cc02a 3972 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3973 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3974 struct snd_kcontrol_new knew =
3975 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3976
3977 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3978 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3979 knew.tlv.c = 0;
3980 knew.tlv.p = 0;
3981 switch (pnid) {
3982 case VOICE_FOCUS:
3983 knew.info = voice_focus_ctl_info;
3984 knew.get = tuning_ctl_get;
3985 knew.put = voice_focus_ctl_put;
3986 knew.tlv.p = voice_focus_db_scale;
3987 break;
3988 case MIC_SVM:
3989 knew.info = mic_svm_ctl_info;
3990 knew.get = tuning_ctl_get;
3991 knew.put = mic_svm_ctl_put;
3992 break;
3993 case EQUALIZER:
3994 knew.info = equalizer_ctl_info;
3995 knew.get = tuning_ctl_get;
3996 knew.put = equalizer_ctl_put;
3997 knew.tlv.p = eq_db_scale;
3998 break;
3999 default:
4000 return 0;
4001 }
4002 knew.private_value =
4003 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4004 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4005 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4006}
4007
4008static int add_tuning_ctls(struct hda_codec *codec)
4009{
4010 int i;
4011 int err;
4012
4013 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4014 err = add_tuning_control(codec,
4015 ca0132_tuning_ctls[i].parent_nid,
4016 ca0132_tuning_ctls[i].nid,
4017 ca0132_tuning_ctls[i].name,
4018 ca0132_tuning_ctls[i].direct);
4019 if (err < 0)
4020 return err;
4021 }
4022
4023 return 0;
4024}
4025
4026static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4027{
4028 struct ca0132_spec *spec = codec->spec;
4029 int i;
4030
4031 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4032 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4033 /* SVM level defaults to 0.74. */
4034 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4035
4036 /* EQ defaults to 0dB. */
4037 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4038 spec->cur_ctl_vals[i] = 24;
4039}
4040#endif /*ENABLE_TUNING_CONTROLS*/
4041
5aaca44d
IM		 4042/*
4043 * Select the active output.
4044 * If autodetect is enabled, output will be selected based on jack detection.
4045 * If jack inserted, headphone will be selected, else built-in speakers
4046 * If autodetect is disabled, output will be selected based on selection.
4047 */
4048static int ca0132_select_out(struct hda_codec *codec)
4049{
4050 struct ca0132_spec *spec = codec->spec;
4051 unsigned int pin_ctl;
4052 int jack_present;
4053 int auto_jack;
4054 unsigned int tmp;
4055 int err;
4056
4e76a883 4057 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 4058
664c7155 4059 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4060
4061 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4062
4063 if (auto_jack)
fe14f39e 4064 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 4065 else
4066 jack_present =
4067 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4068
4069 if (jack_present)
4070 spec->cur_out_type = HEADPHONE_OUT;
4071 else
4072 spec->cur_out_type = SPEAKER_OUT;
4073
4074 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 4075 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 4076 /*speaker out config*/
4077 tmp = FLOAT_ONE;
4078 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4079 if (err < 0)
4080 goto exit;
4081 /*enable speaker EQ*/
4082 tmp = FLOAT_ONE;
4083 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4084 if (err < 0)
4085 goto exit;
4086
4087 /* Setup EAPD */
4088 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4089 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4090 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4091 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4092 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4093 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4094 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4095 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4096
4097 /* disable headphone node */
4098 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4099 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4100 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4101 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4102 /* enable speaker node */
4103 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 4104 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4105 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4106 pin_ctl | PIN_OUT);
5aaca44d 4107 } else {
4e76a883 4108 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 4109 /*headphone out config*/
4110 tmp = FLOAT_ZERO;
4111 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4112 if (err < 0)
4113 goto exit;
4114 /*disable speaker EQ*/
4115 tmp = FLOAT_ZERO;
4116 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4117 if (err < 0)
4118 goto exit;
4119
4120 /* Setup EAPD */
4121 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4122 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4123 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4124 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4125 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4126 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4127 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4128 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4129
4130 /* disable speaker*/
4131 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4132 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4133 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4134 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4135 /* enable headphone*/
4136 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4137 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4138 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4139 pin_ctl | PIN_HP);
5aaca44d
IM		 4140 }
4141
4142exit:
664c7155 4143 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4144
4145 return err < 0 ? err : 0;
4146}
4147
212de2e7 4148static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
d51434d4 4149static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
8e6bc6b3 4150static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
212de2e7 4151
2283c85b
CM		 4152static void ae5_mmio_select_out(struct hda_codec *codec)
4153{
4154 struct ca0132_spec *spec = codec->spec;
4155 unsigned int i;
4156
4157 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4158 ca0113_mmio_command_set(codec,
4159 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4160 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4161 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4162}
4163
746fc9de
CM		 4164/*
4165 * These are the commands needed to setup output on each of the different card
4166 * types.
4167 */
4168static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4169{
4170 struct ca0132_spec *spec = codec->spec;
2283c85b 4171 unsigned int tmp;
746fc9de
CM		 4172
4173 switch (spec->cur_out_type) {
4174 case SPEAKER_OUT:
4175 switch (spec->quirk) {
4176 case QUIRK_SBZ:
4177 ca0113_mmio_gpio_set(codec, 7, false);
4178 ca0113_mmio_gpio_set(codec, 4, true);
4179 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4180 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4181 break;
55845949
CM		 4182 case QUIRK_ZXR:
4183 ca0113_mmio_gpio_set(codec, 2, true);
4184 ca0113_mmio_gpio_set(codec, 3, true);
4185 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4186 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4187 chipio_set_control_param(codec, 0x0d, 0x24);
4188 break;
746fc9de 4189 case QUIRK_R3DI:
2283c85b 4190 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4191 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4192 break;
4193 case QUIRK_R3D:
2283c85b 4194 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4195 ca0113_mmio_gpio_set(codec, 1, true);
4196 break;
2283c85b
CM		 4197 case QUIRK_AE5:
4198 ae5_mmio_select_out(codec);
212de2e7 4199 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4200 tmp = FLOAT_ZERO;
4201 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4202 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4203 chipio_set_control_param(codec, 0x0d, 0xa4);
4204 chipio_write(codec, 0x18b03c, 0x00000012);
4205 break;
746fc9de
CM		 4206 }
4207 break;
4208 case HEADPHONE_OUT:
4209 switch (spec->quirk) {
4210 case QUIRK_SBZ:
4211 ca0113_mmio_gpio_set(codec, 7, true);
4212 ca0113_mmio_gpio_set(codec, 4, true);
4213 ca0113_mmio_gpio_set(codec, 1, false);
2283c85b 4214 chipio_set_control_param(codec, 0x0d, 0x12);
746fc9de 4215 break;
55845949
CM		 4216 case QUIRK_ZXR:
4217 ca0113_mmio_gpio_set(codec, 2, false);
4218 ca0113_mmio_gpio_set(codec, 3, false);
4219 ca0113_mmio_gpio_set(codec, 5, true);
d51434d4 4220 zxr_headphone_gain_set(codec, spec->zxr_gain_set);
55845949
CM		 4221 chipio_set_control_param(codec, 0x0d, 0x21);
4222 break;
746fc9de 4223 case QUIRK_R3DI:
2283c85b 4224 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4225 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4226 break;
4227 case QUIRK_R3D:
2283c85b 4228 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4229 ca0113_mmio_gpio_set(codec, 0x1, false);
4230 break;
2283c85b
CM		 4231 case QUIRK_AE5:
4232 ae5_mmio_select_out(codec);
212de2e7
CM		 4233 ae5_headphone_gain_set(codec,
4234 spec->ae5_headphone_gain_val);
2283c85b
CM		 4235 tmp = FLOAT_ONE;
4236 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4237 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4238 chipio_set_control_param(codec, 0x0d, 0xa1);
4239 chipio_write(codec, 0x18b03c, 0x00000012);
4240 break;
746fc9de
CM		 4241 }
4242 break;
4243 case SURROUND_OUT:
4244 switch (spec->quirk) {
4245 case QUIRK_SBZ:
4246 ca0113_mmio_gpio_set(codec, 7, false);
4247 ca0113_mmio_gpio_set(codec, 4, true);
4248 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4249 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4250 break;
55845949
CM		 4251 case QUIRK_ZXR:
4252 ca0113_mmio_gpio_set(codec, 2, true);
4253 ca0113_mmio_gpio_set(codec, 3, true);
4254 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4255 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4256 chipio_set_control_param(codec, 0x0d, 0x24);
4257 break;
746fc9de 4258 case QUIRK_R3DI:
2283c85b 4259 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4260 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4261 break;
4262 case QUIRK_R3D:
4263 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b
CM		 4264 chipio_set_control_param(codec, 0x0d, 0x24);
4265 break;
4266 case QUIRK_AE5:
4267 ae5_mmio_select_out(codec);
212de2e7 4268 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4269 tmp = FLOAT_ZERO;
4270 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4271 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4272 chipio_set_control_param(codec, 0x0d, 0xa4);
4273 chipio_write(codec, 0x18b03c, 0x00000012);
746fc9de
CM		 4274 break;
4275 }
4276 break;
4277 }
4278}
4279
7cb9d94c
CM		 4280/*
4281 * This function behaves similarly to the ca0132_select_out funciton above,
4282 * except with a few differences. It adds the ability to select the current
4283 * output with an enumerated control "output source" if the auto detect
4284 * mute switch is set to off. If the auto detect mute switch is enabled, it
4285 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4286 * It also adds the ability to auto-detect the front headphone port. The only
4287 * way to select surround is to disable auto detect, and set Surround with the
4288 * enumerated control.
4289 */
4290static int ca0132_alt_select_out(struct hda_codec *codec)
4291{
4292 struct ca0132_spec *spec = codec->spec;
4293 unsigned int pin_ctl;
4294 int jack_present;
4295 int auto_jack;
4296 unsigned int i;
4297 unsigned int tmp;
4298 int err;
4299 /* Default Headphone is rear headphone */
4300 hda_nid_t headphone_nid = spec->out_pins[1];
4301
4302 codec_dbg(codec, "%s\n", __func__);
4303
4304 snd_hda_power_up_pm(codec);
4305
4306 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4307
4308 /*
4309 * If headphone rear or front is plugged in, set to headphone.
4310 * If neither is plugged in, set to rear line out. Only if
4311 * hp/speaker auto detect is enabled.
4312 */
4313 if (auto_jack) {
4314 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4315 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4316
4317 if (jack_present)
4318 spec->cur_out_type = HEADPHONE_OUT;
4319 else
4320 spec->cur_out_type = SPEAKER_OUT;
4321 } else
4322 spec->cur_out_type = spec->out_enum_val;
4323
4324 /* Begin DSP output switch */
4325 tmp = FLOAT_ONE;
4326 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4327 if (err < 0)
4328 goto exit;
4329
746fc9de
CM		 4330 ca0132_alt_select_out_quirk_handler(codec);
4331
7cb9d94c
CM		 4332 switch (spec->cur_out_type) {
4333 case SPEAKER_OUT:
4334 codec_dbg(codec, "%s speaker\n", __func__);
7cb9d94c
CM		 4335
4336 /* disable headphone node */
4337 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4338 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4339 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4340 pin_ctl & ~PIN_HP);
4341 /* enable line-out node */
4342 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4343 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4344 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4345 pin_ctl | PIN_OUT);
4346 /* Enable EAPD */
4347 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4348 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4349
4350 /* If PlayEnhancement is enabled, set different source */
4351 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4352 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4353 else
4354 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4355 break;
4356 case HEADPHONE_OUT:
4357 codec_dbg(codec, "%s hp\n", __func__);
7cb9d94c
CM		 4358
4359 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4360 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4361
4362 /* disable speaker*/
4363 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4364 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4365 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4366 pin_ctl & ~PIN_HP);
4367
4368 /* enable headphone, either front or rear */
4369
4370 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4371 headphone_nid = spec->out_pins[2];
4372 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4373 headphone_nid = spec->out_pins[1];
4374
4375 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4376 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4377 snd_hda_set_pin_ctl(codec, headphone_nid,
4378 pin_ctl | PIN_HP);
4379
4380 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4381 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4382 else
4383 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4384 break;
4385 case SURROUND_OUT:
4386 codec_dbg(codec, "%s surround\n", __func__);
746fc9de 4387
7cb9d94c
CM		 4388 /* enable line out node */
4389 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4390 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4391 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4392 pin_ctl | PIN_OUT);
4393 /* Disable headphone out */
4394 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4395 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4396 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4397 pin_ctl & ~PIN_HP);
4398 /* Enable EAPD on line out */
4399 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4400 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4401 /* enable center/lfe out node */
4402 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4403 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4404 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4405 pin_ctl | PIN_OUT);
4406 /* Now set rear surround node as out. */
4407 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4408 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4409 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4410 pin_ctl | PIN_OUT);
4411
8e6bc6b3 4412 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
7cb9d94c
CM		 4413 break;
4414 }
8e6bc6b3
CM		 4415 /*
4416 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT.
4417 * With this set though, X_BASS cannot be enabled. So, if we have OutFX
4418 * enabled, we need to make sure X_BASS is off, otherwise everything
4419 * sounds all muffled. Running ca0132_effects_set with X_BASS as the
4420 * effect should sort this out.
4421 */
4422 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4423 ca0132_effects_set(codec, X_BASS,
4424 spec->effects_switch[X_BASS - EFFECT_START_NID]);
7cb9d94c 4425
2283c85b 4426 /* run through the output dsp commands for the selected output. */
7cb9d94c
CM		 4427 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4428 err = dspio_set_uint_param(codec,
4429 alt_out_presets[spec->cur_out_type].mids[i],
4430 alt_out_presets[spec->cur_out_type].reqs[i],
4431 alt_out_presets[spec->cur_out_type].vals[i]);
4432
4433 if (err < 0)
4434 goto exit;
4435 }
4436
4437exit:
4438 snd_hda_power_down_pm(codec);
4439
4440 return err < 0 ? err : 0;
4441}
4442
993884f6
CCC		 4443static void ca0132_unsol_hp_delayed(struct work_struct *work)
4444{
4445 struct ca0132_spec *spec = container_of(
4446 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4447 struct hda_jack_tbl *jack;
4448
7cb9d94c
CM		 4449 if (spec->use_alt_functions)
4450 ca0132_alt_select_out(spec->codec);
4451 else
4452 ca0132_select_out(spec->codec);
4453
d5c016b5 4454 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4455 if (jack) {
4456 jack->block_report = 0;
4457 snd_hda_jack_report_sync(spec->codec);
4458 }
993884f6
CCC		 4459}
4460
5aaca44d
IM		 4461static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4462static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
e0026d03
CM		 4463static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4464static int stop_mic1(struct hda_codec *codec);
4465static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4466static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4467
4468/*
4469 * Select the active VIP source
4470 */
4471static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4472{
4473 struct ca0132_spec *spec = codec->spec;
4474 unsigned int tmp;
4475
e8f1bd5d 4476 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4477 return 0;
4478
4479 /* if CrystalVoice if off, vipsource should be 0 */
4480 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4481 (val == 0)) {
4482 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4483 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4484 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4485 if (spec->cur_mic_type == DIGITAL_MIC)
4486 tmp = FLOAT_TWO;
4487 else
4488 tmp = FLOAT_ONE;
4489 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4490 tmp = FLOAT_ZERO;
4491 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4492 } else {
4493 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4494 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4495 if (spec->cur_mic_type == DIGITAL_MIC)
4496 tmp = FLOAT_TWO;
4497 else
4498 tmp = FLOAT_ONE;
4499 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4500 tmp = FLOAT_ONE;
4501 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4502 msleep(20);
4503 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4504 }
4505
4506 return 1;
4507}
4508
e0026d03
CM		 4509static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4510{
4511 struct ca0132_spec *spec = codec->spec;
4512 unsigned int tmp;
4513
4514 if (spec->dsp_state != DSP_DOWNLOADED)
4515 return 0;
4516
4517 codec_dbg(codec, "%s\n", __func__);
4518
4519 chipio_set_stream_control(codec, 0x03, 0);
4520 chipio_set_stream_control(codec, 0x04, 0);
4521
4522 /* if CrystalVoice is off, vipsource should be 0 */
4523 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4524 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4525 codec_dbg(codec, "%s: off.", __func__);
4526 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4527
4528 tmp = FLOAT_ZERO;
4529 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4530
4531 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4532 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4533 if (spec->quirk == QUIRK_R3DI)
4534 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4535
4536
4537 if (spec->in_enum_val == REAR_LINE_IN)
4538 tmp = FLOAT_ZERO;
4539 else {
4540 if (spec->quirk == QUIRK_SBZ)
4541 tmp = FLOAT_THREE;
4542 else
4543 tmp = FLOAT_ONE;
4544 }
4545
4546 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4547
4548 } else {
4549 codec_dbg(codec, "%s: on.", __func__);
4550 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4551 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4552 if (spec->quirk == QUIRK_R3DI)
4553 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4554
4555 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4556 tmp = FLOAT_TWO;
4557 else
4558 tmp = FLOAT_ONE;
4559 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4560
4561 tmp = FLOAT_ONE;
4562 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4563
4564 msleep(20);
4565 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4566 }
4567
4568 chipio_set_stream_control(codec, 0x03, 1);
4569 chipio_set_stream_control(codec, 0x04, 1);
4570
4571 return 1;
4572}
4573
5aaca44d
IM		 4574/*
4575 * Select the active microphone.
4576 * If autodetect is enabled, mic will be selected based on jack detection.
4577 * If jack inserted, ext.mic will be selected, else built-in mic
4578 * If autodetect is disabled, mic will be selected based on selection.
4579 */
4580static int ca0132_select_mic(struct hda_codec *codec)
4581{
4582 struct ca0132_spec *spec = codec->spec;
4583 int jack_present;
4584 int auto_jack;
4585
4e76a883 4586 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4587
664c7155 4588 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4589
4590 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4591
4592 if (auto_jack)
fe14f39e 4593 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4594 else
4595 jack_present =
4596 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4597
4598 if (jack_present)
4599 spec->cur_mic_type = LINE_MIC_IN;
4600 else
4601 spec->cur_mic_type = DIGITAL_MIC;
4602
4603 if (spec->cur_mic_type == DIGITAL_MIC) {
4604 /* enable digital Mic */
4605 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4606 ca0132_set_dmic(codec, 1);
4607 ca0132_mic_boost_set(codec, 0);
4608 /* set voice focus */
4609 ca0132_effects_set(codec, VOICE_FOCUS,
4610 spec->effects_switch
4611 [VOICE_FOCUS - EFFECT_START_NID]);
4612 } else {
4613 /* disable digital Mic */
4614 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4615 ca0132_set_dmic(codec, 0);
4616 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4617 /* disable voice focus */
4618 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4619 }
4620
664c7155 4621 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4622
4623 return 0;
4624}
4625
7cb9d94c
CM		 4626/*
4627 * Select the active input.
4628 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4629 * The front mic has no jack-detection, so the only way to switch to it
4630 * is to do it manually in alsamixer.
4631 */
4632static int ca0132_alt_select_in(struct hda_codec *codec)
4633{
4634 struct ca0132_spec *spec = codec->spec;
4635 unsigned int tmp;
4636
4637 codec_dbg(codec, "%s\n", __func__);
4638
4639 snd_hda_power_up_pm(codec);
4640
4641 chipio_set_stream_control(codec, 0x03, 0);
4642 chipio_set_stream_control(codec, 0x04, 0);
4643
4644 spec->cur_mic_type = spec->in_enum_val;
4645
4646 switch (spec->cur_mic_type) {
4647 case REAR_MIC:
4648 switch (spec->quirk) {
4649 case QUIRK_SBZ:
42aa3a16 4650 case QUIRK_R3D:
b9b41345 4651 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4652 tmp = FLOAT_THREE;
4653 break;
55845949
CM		 4654 case QUIRK_ZXR:
4655 tmp = FLOAT_THREE;
4656 break;
7cb9d94c
CM		 4657 case QUIRK_R3DI:
4658 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4659 tmp = FLOAT_ONE;
4660 break;
f231daaf
CM		 4661 case QUIRK_AE5:
4662 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4663 tmp = FLOAT_THREE;
4664 break;
7cb9d94c
CM		 4665 default:
4666 tmp = FLOAT_ONE;
4667 break;
4668 }
4669
4670 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4671 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4672 if (spec->quirk == QUIRK_R3DI)
4673 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4674
4675 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4676
4677 chipio_set_stream_control(codec, 0x03, 1);
4678 chipio_set_stream_control(codec, 0x04, 1);
f231daaf
CM		 4679 switch (spec->quirk) {
4680 case QUIRK_SBZ:
7cb9d94c
CM		 4681 chipio_write(codec, 0x18B098, 0x0000000C);
4682 chipio_write(codec, 0x18B09C, 0x0000000C);
f231daaf 4683 break;
55845949
CM		 4684 case QUIRK_ZXR:
4685 chipio_write(codec, 0x18B098, 0x0000000C);
4686 chipio_write(codec, 0x18B09C, 0x000000CC);
4687 break;
f231daaf
CM		 4688 case QUIRK_AE5:
4689 chipio_write(codec, 0x18B098, 0x0000000C);
4690 chipio_write(codec, 0x18B09C, 0x0000004C);
4691 break;
7cb9d94c 4692 }
47cdf76e 4693 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4694 break;
4695 case REAR_LINE_IN:
4696 ca0132_mic_boost_set(codec, 0);
4697 switch (spec->quirk) {
4698 case QUIRK_SBZ:
42aa3a16 4699 case QUIRK_R3D:
b9b41345 4700 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4701 break;
4702 case QUIRK_R3DI:
4703 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4704 break;
f231daaf
CM		 4705 case QUIRK_AE5:
4706 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4707 break;
7cb9d94c
CM		 4708 }
4709
4710 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4711 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4712 if (spec->quirk == QUIRK_R3DI)
4713 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4714
4715 tmp = FLOAT_ZERO;
4716 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4717
f231daaf
CM		 4718 switch (spec->quirk) {
4719 case QUIRK_SBZ:
4720 case QUIRK_AE5:
7cb9d94c
CM		 4721 chipio_write(codec, 0x18B098, 0x00000000);
4722 chipio_write(codec, 0x18B09C, 0x00000000);
f231daaf 4723 break;
7cb9d94c 4724 }
7cb9d94c
CM		 4725 chipio_set_stream_control(codec, 0x03, 1);
4726 chipio_set_stream_control(codec, 0x04, 1);
4727 break;
4728 case FRONT_MIC:
4729 switch (spec->quirk) {
4730 case QUIRK_SBZ:
42aa3a16 4731 case QUIRK_R3D:
b9b41345
CM		 4732 ca0113_mmio_gpio_set(codec, 0, true);
4733 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4734 tmp = FLOAT_THREE;
4735 break;
4736 case QUIRK_R3DI:
4737 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4738 tmp = FLOAT_ONE;
4739 break;
f231daaf
CM		 4740 case QUIRK_AE5:
4741 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f);
4742 tmp = FLOAT_THREE;
4743 break;
7cb9d94c
CM		 4744 default:
4745 tmp = FLOAT_ONE;
4746 break;
4747 }
4748
4749 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4750 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4751 if (spec->quirk == QUIRK_R3DI)
4752 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4753
4754 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4755
4756 chipio_set_stream_control(codec, 0x03, 1);
4757 chipio_set_stream_control(codec, 0x04, 1);
4758
f231daaf
CM		 4759 switch (spec->quirk) {
4760 case QUIRK_SBZ:
7cb9d94c
CM		 4761 chipio_write(codec, 0x18B098, 0x0000000C);
4762 chipio_write(codec, 0x18B09C, 0x000000CC);
f231daaf
CM		 4763 break;
4764 case QUIRK_AE5:
4765 chipio_write(codec, 0x18B098, 0x0000000C);
4766 chipio_write(codec, 0x18B09C, 0x0000004C);
4767 break;
7cb9d94c 4768 }
47cdf76e 4769 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4770 break;
4771 }
e0026d03 4772 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4773
4774 snd_hda_power_down_pm(codec);
4775 return 0;
7cb9d94c
CM		 4776}
4777
a7e76271
IM		 4778/*
4779 * Check if VNODE settings take effect immediately.
4780 */
4781static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4782 hda_nid_t vnid,
4783 hda_nid_t *shared_nid)
4784{
4785 struct ca0132_spec *spec = codec->spec;
4786 hda_nid_t nid;
a7e76271
IM		 4787
4788 switch (vnid) {
4789 case VNID_SPK:
4790 nid = spec->shared_out_nid;
a7e76271
IM		 4791 break;
4792 case VNID_MIC:
4793 nid = spec->shared_mic_nid;
a7e76271
IM		 4794 break;
4795 default:
9a0869f4 4796 return false;
a7e76271
IM		 4797 }
4798
9a0869f4 4799 if (shared_nid)
a7e76271
IM		 4800 *shared_nid = nid;
4801
9a0869f4 4802 return true;
a7e76271
IM		 4803}
4804
4805/*
4806* The following functions are control change helpers.
4807* They return 0 if no changed. Return 1 if changed.
4808*/
4809static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4810{
4811 struct ca0132_spec *spec = codec->spec;
4812 unsigned int tmp;
4813
4814 /* based on CrystalVoice state to enable VoiceFX. */
4815 if (enable) {
4816 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4817 FLOAT_ONE : FLOAT_ZERO;
4818 } else {
4819 tmp = FLOAT_ZERO;
4820 }
4821
4822 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4823 ca0132_voicefx.reqs[0], tmp);
4824
4825 return 1;
4826}
4827
5aaca44d
IM		 4828/*
4829 * Set the effects parameters
4830 */
4831static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4832{
4833 struct ca0132_spec *spec = codec->spec;
009b8f97 4834 unsigned int on, tmp;
5aaca44d
IM		 4835 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4836 int err = 0;
4837 int idx = nid - EFFECT_START_NID;
4838
4839 if ((idx < 0) || (idx >= num_fx))
4840 return 0; /* no changed */
4841
4842 /* for out effect, qualify with PE */
4843 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4844 /* if PE if off, turn off out effects. */
4845 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4846 val = 0;
8e6bc6b3
CM		 4847 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS)
4848 val = 0;
5aaca44d
IM		 4849 }
4850
4851 /* for in effect, qualify with CrystalVoice */
4852 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4853 /* if CrystalVoice if off, turn off in effects. */
4854 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4855 val = 0;
4856
4857 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4858 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4859 val = 0;
009b8f97
CM		 4860
4861 /* If Voice Focus on SBZ, set to two channel. */
7a2dc84f 4862 if ((nid == VOICE_FOCUS) && (spec->use_pci_mmio)
7cb9d94c 4863 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4864 if (spec->effects_switch[CRYSTAL_VOICE -
4865 EFFECT_START_NID]) {
4866
4867 if (spec->effects_switch[VOICE_FOCUS -
4868 EFFECT_START_NID]) {
4869 tmp = FLOAT_TWO;
4870 val = 1;
4871 } else
4872 tmp = FLOAT_ONE;
4873
4874 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4875 }
4876 }
4877 /*
4878 * For SBZ noise reduction, there's an extra command
4879 * to module ID 0x47. No clue why.
4880 */
7a2dc84f 4881 if ((nid == NOISE_REDUCTION) && (spec->use_pci_mmio)
7cb9d94c 4882 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4883 if (spec->effects_switch[CRYSTAL_VOICE -
4884 EFFECT_START_NID]) {
4885 if (spec->effects_switch[NOISE_REDUCTION -
4886 EFFECT_START_NID])
4887 tmp = FLOAT_ONE;
4888 else
4889 tmp = FLOAT_ZERO;
4890 } else
4891 tmp = FLOAT_ZERO;
4892
4893 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4894 }
7cb9d94c
CM		 4895
4896 /* If rear line in disable effects. */
4897 if (spec->use_alt_functions &&
4898 spec->in_enum_val == REAR_LINE_IN)
4899 val = 0;
5aaca44d
IM		 4900 }
4901
4e76a883 4902 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4903 nid, val);
4904
4905 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4906 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4907 ca0132_effects[idx].reqs[0], on);
4908
4909 if (err < 0)
4910 return 0; /* no changed */
4911
4912 return 1;
4913}
4914
a7e76271
IM		 4915/*
4916 * Turn on/off Playback Enhancements
4917 */
4918static int ca0132_pe_switch_set(struct hda_codec *codec)
4919{
4920 struct ca0132_spec *spec = codec->spec;
4921 hda_nid_t nid;
4922 int i, ret = 0;
4923
4e76a883 4924 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4925 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4926
7cb9d94c
CM		 4927 if (spec->use_alt_functions)
4928 ca0132_alt_select_out(codec);
4929
a7e76271
IM		 4930 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4931 nid = OUT_EFFECT_START_NID;
4932 /* PE affects all out effects */
4933 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4934 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4935
4936 return ret;
4937}
4938
5aaca44d
IM		 4939/* Check if Mic1 is streaming, if so, stop streaming */
4940static int stop_mic1(struct hda_codec *codec)
4941{
4942 struct ca0132_spec *spec = codec->spec;
4943 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4944 AC_VERB_GET_CONV, 0);
4945 if (oldval != 0)
4946 snd_hda_codec_write(codec, spec->adcs[0], 0,
4947 AC_VERB_SET_CHANNEL_STREAMID,
4948 0);
4949 return oldval;
4950}
4951
4952/* Resume Mic1 streaming if it was stopped. */
4953static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4954{
4955 struct ca0132_spec *spec = codec->spec;
4956 /* Restore the previous stream and channel */
4957 if (oldval != 0)
4958 snd_hda_codec_write(codec, spec->adcs[0], 0,
4959 AC_VERB_SET_CHANNEL_STREAMID,
4960 oldval);
4961}
4962
4963/*
a7e76271 4964 * Turn on/off CrystalVoice
5aaca44d 4965 */
a7e76271
IM		 4966static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4967{
4968 struct ca0132_spec *spec = codec->spec;
4969 hda_nid_t nid;
4970 int i, ret = 0;
4971 unsigned int oldval;
4972
4e76a883 4973 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4974 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4975
4976 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4977 nid = IN_EFFECT_START_NID;
4978 /* CrystalVoice affects all in effects */
4979 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4980 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4981
4982 /* including VoiceFX */
4983 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4984
4985 /* set correct vipsource */
4986 oldval = stop_mic1(codec);
e0026d03
CM		 4987 if (spec->use_alt_functions)
4988 ret |= ca0132_alt_set_vipsource(codec, 1);
4989 else
4990 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4991 resume_mic1(codec, oldval);
4992 return ret;
4993}
4994
5aaca44d
IM		 4995static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4996{
4997 struct ca0132_spec *spec = codec->spec;
4998 int ret = 0;
4999
5000 if (val) /* on */
5001 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5002 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5003 else /* off */
5004 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5005 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5006
5007 return ret;
5008}
5009
47cdf76e
CM		 5010static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5011{
5012 struct ca0132_spec *spec = codec->spec;
5013 int ret = 0;
5014
5015 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5016 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5017 return ret;
5018}
5019
212de2e7
CM		 5020static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5021{
5022 unsigned int i;
5023
5024 for (i = 0; i < 4; i++)
5025 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5026 ae5_headphone_gain_presets[val].vals[i]);
5027 return 0;
5028}
5029
d51434d4
CM		 5030/*
5031 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5032 * amplifier to handle a 600 ohm load.
5033 */
5034static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5035{
5036 ca0113_mmio_gpio_set(codec, 1, val);
5037
5038 return 0;
5039}
5040
a7e76271
IM		 5041static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5042 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 5043{
a7e76271
IM		 5044 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5045 hda_nid_t nid = get_amp_nid(kcontrol);
5046 hda_nid_t shared_nid = 0;
5047 bool effective;
5048 int ret = 0;
95c6e9cb 5049 struct ca0132_spec *spec = codec->spec;
a7e76271 5050 int auto_jack;
95c6e9cb 5051
a7e76271
IM		 5052 if (nid == VNID_HP_SEL) {
5053 auto_jack =
5054 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 5055 if (!auto_jack) {
5056 if (spec->use_alt_functions)
5057 ca0132_alt_select_out(codec);
5058 else
5059 ca0132_select_out(codec);
5060 }
a7e76271
IM		 5061 return 1;
5062 }
95c6e9cb 5063
a7e76271
IM		 5064 if (nid == VNID_AMIC1_SEL) {
5065 auto_jack =
5066 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5067 if (!auto_jack)
5068 ca0132_select_mic(codec);
5069 return 1;
5070 }
95c6e9cb 5071
a7e76271 5072 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 5073 if (spec->use_alt_functions)
5074 ca0132_alt_select_out(codec);
5075 else
5076 ca0132_select_out(codec);
a7e76271
IM		 5077 return 1;
5078 }
95c6e9cb 5079
a7e76271
IM		 5080 if (nid == VNID_AMIC1_ASEL) {
5081 ca0132_select_mic(codec);
5082 return 1;
95c6e9cb 5083 }
a7e76271
IM		 5084
5085 /* if effective conditions, then update hw immediately. */
5086 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5087 if (effective) {
5088 int dir = get_amp_direction(kcontrol);
5089 int ch = get_amp_channels(kcontrol);
5090 unsigned long pval;
5091
5092 mutex_lock(&codec->control_mutex);
5093 pval = kcontrol->private_value;
5094 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5095 0, dir);
5096 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5097 kcontrol->private_value = pval;
5098 mutex_unlock(&codec->control_mutex);
95c6e9cb 5099 }
95c6e9cb 5100
a7e76271 5101 return ret;
95c6e9cb 5102}
a7e76271 5103/* End of control change helpers. */
47cdf76e
CM		 5104/*
5105 * Below I've added controls to mess with the effect levels, I've only enabled
5106 * them on the Sound Blaster Z, but they would probably also work on the
5107 * Chromebook. I figured they were probably tuned specifically for it, and left
5108 * out for a reason.
5109 */
5110
5111/* Sets DSP effect level from the sliders above the controls */
5112static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5113 const unsigned int *lookup, int idx)
5114{
5115 int i = 0;
5116 unsigned int y;
5117 /*
5118 * For X_BASS, req 2 is actually crossover freq instead of
5119 * effect level
5120 */
5121 if (nid == X_BASS)
5122 y = 2;
5123 else
5124 y = 1;
5125
5126 snd_hda_power_up(codec);
5127 if (nid == XBASS_XOVER) {
5128 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5129 if (ca0132_effects[i].nid == X_BASS)
5130 break;
5131
5132 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5133 ca0132_effects[i].reqs[1],
5134 &(lookup[idx - 1]), sizeof(unsigned int));
5135 } else {
5136 /* Find the actual effect structure */
5137 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5138 if (nid == ca0132_effects[i].nid)
5139 break;
5140
5141 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5142 ca0132_effects[i].reqs[y],
5143 &(lookup[idx]), sizeof(unsigned int));
5144 }
5145
5146 snd_hda_power_down(codec);
5147
5148 return 0;
5149}
5150
5151static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5152 struct snd_ctl_elem_value *ucontrol)
5153{
5154 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5155 struct ca0132_spec *spec = codec->spec;
5156 long *valp = ucontrol->value.integer.value;
5157
5158 *valp = spec->xbass_xover_freq;
5159 return 0;
5160}
5161
5162static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5163 struct snd_ctl_elem_value *ucontrol)
5164{
5165 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5166 struct ca0132_spec *spec = codec->spec;
5167 hda_nid_t nid = get_amp_nid(kcontrol);
5168 long *valp = ucontrol->value.integer.value;
5169 int idx = nid - OUT_EFFECT_START_NID;
5170
5171 *valp = spec->fx_ctl_val[idx];
5172 return 0;
5173}
5174
5175/*
5176 * The X-bass crossover starts at 10hz, so the min is 1. The
5177 * frequency is set in multiples of 10.
5178 */
5179static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5180 struct snd_ctl_elem_info *uinfo)
5181{
5182 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5183 uinfo->count = 1;
5184 uinfo->value.integer.min = 1;
5185 uinfo->value.integer.max = 100;
5186 uinfo->value.integer.step = 1;
5187
5188 return 0;
5189}
5190
5191static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5192 struct snd_ctl_elem_info *uinfo)
5193{
5194 int chs = get_amp_channels(kcontrol);
5195
5196 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5197 uinfo->count = chs == 3 ? 2 : 1;
5198 uinfo->value.integer.min = 0;
5199 uinfo->value.integer.max = 100;
5200 uinfo->value.integer.step = 1;
5201
5202 return 0;
5203}
5204
5205static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5206 struct snd_ctl_elem_value *ucontrol)
5207{
5208 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5209 struct ca0132_spec *spec = codec->spec;
5210 hda_nid_t nid = get_amp_nid(kcontrol);
5211 long *valp = ucontrol->value.integer.value;
5212 int idx;
5213
5214 /* any change? */
5215 if (spec->xbass_xover_freq == *valp)
5216 return 0;
5217
5218 spec->xbass_xover_freq = *valp;
5219
5220 idx = *valp;
5221 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5222
5223 return 0;
5224}
5225
5226static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5227 struct snd_ctl_elem_value *ucontrol)
5228{
5229 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5230 struct ca0132_spec *spec = codec->spec;
5231 hda_nid_t nid = get_amp_nid(kcontrol);
5232 long *valp = ucontrol->value.integer.value;
5233 int idx;
5234
5235 idx = nid - EFFECT_START_NID;
5236 /* any change? */
5237 if (spec->fx_ctl_val[idx] == *valp)
5238 return 0;
5239
5240 spec->fx_ctl_val[idx] = *valp;
5241
5242 idx = *valp;
5243 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5244
5245 return 0;
5246}
5247
5248
5249/*
5250 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5251 * only has off or full 30 dB, and didn't like making a volume slider that has
5252 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5253 */
5254#define MIC_BOOST_NUM_OF_STEPS 4
5255#define MIC_BOOST_ENUM_MAX_STRLEN 10
5256
5257static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5258 struct snd_ctl_elem_info *uinfo)
5259{
5260 char *sfx = "dB";
5261 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5262
5263 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5264 uinfo->count = 1;
5265 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5266 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5267 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5268 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5269 strcpy(uinfo->value.enumerated.name, namestr);
5270 return 0;
5271}
5272
5273static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5274 struct snd_ctl_elem_value *ucontrol)
5275{
5276 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5277 struct ca0132_spec *spec = codec->spec;
5278
5279 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5280 return 0;
5281}
5282
5283static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5284 struct snd_ctl_elem_value *ucontrol)
5285{
5286 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5287 struct ca0132_spec *spec = codec->spec;
5288 int sel = ucontrol->value.enumerated.item[0];
5289 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5290
5291 if (sel >= items)
5292 return 0;
5293
5294 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5295 sel);
5296
5297 spec->mic_boost_enum_val = sel;
5298
5299 if (spec->in_enum_val != REAR_LINE_IN)
5300 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5301
5302 return 1;
5303}
5304
212de2e7
CM		 5305/*
5306 * Sound BlasterX AE-5 Headphone Gain Controls.
5307 */
5308#define AE5_HEADPHONE_GAIN_MAX 3
5309static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5310 struct snd_ctl_elem_info *uinfo)
5311{
5312 char *sfx = " Ohms)";
5313 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5314
5315 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5316 uinfo->count = 1;
5317 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5318 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5319 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5320 sprintf(namestr, "%s %s",
5321 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5322 sfx);
5323 strcpy(uinfo->value.enumerated.name, namestr);
5324 return 0;
5325}
5326
5327static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5328 struct snd_ctl_elem_value *ucontrol)
5329{
5330 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5331 struct ca0132_spec *spec = codec->spec;
5332
5333 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5334 return 0;
5335}
5336
5337static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5338 struct snd_ctl_elem_value *ucontrol)
5339{
5340 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5341 struct ca0132_spec *spec = codec->spec;
5342 int sel = ucontrol->value.enumerated.item[0];
5343 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5344
5345 if (sel >= items)
5346 return 0;
5347
5348 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5349 sel);
5350
5351 spec->ae5_headphone_gain_val = sel;
5352
5353 if (spec->out_enum_val == HEADPHONE_OUT)
5354 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5355
5356 return 1;
5357}
5358
5359/*
5360 * Sound BlasterX AE-5 sound filter enumerated control.
5361 */
5362#define AE5_SOUND_FILTER_MAX 3
5363
5364static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5365 struct snd_ctl_elem_info *uinfo)
5366{
5367 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5368
5369 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5370 uinfo->count = 1;
5371 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5372 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5373 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5374 sprintf(namestr, "%s",
5375 ae5_filter_presets[uinfo->value.enumerated.item].name);
5376 strcpy(uinfo->value.enumerated.name, namestr);
5377 return 0;
5378}
5379
5380static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5381 struct snd_ctl_elem_value *ucontrol)
5382{
5383 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5384 struct ca0132_spec *spec = codec->spec;
5385
5386 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5387 return 0;
5388}
5389
5390static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5391 struct snd_ctl_elem_value *ucontrol)
5392{
5393 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5394 struct ca0132_spec *spec = codec->spec;
5395 int sel = ucontrol->value.enumerated.item[0];
5396 unsigned int items = AE5_SOUND_FILTER_MAX;
5397
5398 if (sel >= items)
5399 return 0;
5400
5401 codec_dbg(codec, "ae5_sound_filter: %s\n",
5402 ae5_filter_presets[sel].name);
5403
5404 spec->ae5_filter_val = sel;
5405
5406 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5407 ae5_filter_presets[sel].val);
5408
5409 return 1;
5410}
95c6e9cb 5411
7cb9d94c
CM		 5412/*
5413 * Input Select Control for alternative ca0132 codecs. This exists because
5414 * front microphone has no auto-detect, and we need a way to set the rear
5415 * as line-in
5416 */
5417static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5418 struct snd_ctl_elem_info *uinfo)
5419{
5420 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5421 uinfo->count = 1;
5422 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5423 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5424 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5425 strcpy(uinfo->value.enumerated.name,
5426 in_src_str[uinfo->value.enumerated.item]);
5427 return 0;
5428}
5429
5430static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5431 struct snd_ctl_elem_value *ucontrol)
5432{
5433 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5434 struct ca0132_spec *spec = codec->spec;
5435
5436 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5437 return 0;
5438}
5439
5440static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5441 struct snd_ctl_elem_value *ucontrol)
5442{
5443 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5444 struct ca0132_spec *spec = codec->spec;
5445 int sel = ucontrol->value.enumerated.item[0];
5446 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5447
5448 if (sel >= items)
5449 return 0;
5450
5451 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5452 sel, in_src_str[sel]);
5453
5454 spec->in_enum_val = sel;
5455
5456 ca0132_alt_select_in(codec);
5457
5458 return 1;
5459}
5460
5461/* Sound Blaster Z Output Select Control */
5462static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5463 struct snd_ctl_elem_info *uinfo)
5464{
5465 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5466 uinfo->count = 1;
5467 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5468 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5469 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5470 strcpy(uinfo->value.enumerated.name,
5471 alt_out_presets[uinfo->value.enumerated.item].name);
5472 return 0;
5473}
5474
5475static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5476 struct snd_ctl_elem_value *ucontrol)
5477{
5478 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5479 struct ca0132_spec *spec = codec->spec;
5480
5481 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5482 return 0;
5483}
5484
5485static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5486 struct snd_ctl_elem_value *ucontrol)
5487{
5488 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5489 struct ca0132_spec *spec = codec->spec;
5490 int sel = ucontrol->value.enumerated.item[0];
5491 unsigned int items = NUM_OF_OUTPUTS;
5492 unsigned int auto_jack;
5493
5494 if (sel >= items)
5495 return 0;
5496
5497 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5498 sel, alt_out_presets[sel].name);
5499
5500 spec->out_enum_val = sel;
5501
5502 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5503
5504 if (!auto_jack)
5505 ca0132_alt_select_out(codec);
5506
5507 return 1;
5508}
5509
47cdf76e
CM		 5510/*
5511 * Smart Volume output setting control. Three different settings, Normal,
5512 * which takes the value from the smart volume slider. The two others, loud
5513 * and night, disregard the slider value and have uneditable values.
5514 */
5515#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5516static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5517
5518static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5519 struct snd_ctl_elem_info *uinfo)
5520{
5521 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5522 uinfo->count = 1;
5523 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5524 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5525 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5526 strcpy(uinfo->value.enumerated.name,
5527 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5528 return 0;
5529}
5530
5531static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5532 struct snd_ctl_elem_value *ucontrol)
5533{
5534 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5535 struct ca0132_spec *spec = codec->spec;
5536
5537 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5538 return 0;
5539}
5540
5541static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5542 struct snd_ctl_elem_value *ucontrol)
5543{
5544 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5545 struct ca0132_spec *spec = codec->spec;
5546 int sel = ucontrol->value.enumerated.item[0];
5547 unsigned int items = NUM_OF_SVM_SETTINGS;
5548 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5549 unsigned int tmp;
5550
5551 if (sel >= items)
5552 return 0;
5553
5554 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5555 sel, out_svm_set_enum_str[sel]);
5556
5557 spec->smart_volume_setting = sel;
5558
5559 switch (sel) {
5560 case 0:
5561 tmp = FLOAT_ZERO;
5562 break;
5563 case 1:
5564 tmp = FLOAT_ONE;
5565 break;
5566 case 2:
5567 tmp = FLOAT_TWO;
5568 break;
5569 default:
5570 tmp = FLOAT_ZERO;
5571 break;
5572 }
5573 /* Req 2 is the Smart Volume Setting req. */
5574 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5575 ca0132_effects[idx].reqs[2], tmp);
5576 return 1;
5577}
5578
5579/* Sound Blaster Z EQ preset controls */
5580static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5581 struct snd_ctl_elem_info *uinfo)
5582{
c5f13d75 5583 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5584
5585 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5586 uinfo->count = 1;
5587 uinfo->value.enumerated.items = items;
5588 if (uinfo->value.enumerated.item >= items)
5589 uinfo->value.enumerated.item = items - 1;
5590 strcpy(uinfo->value.enumerated.name,
5591 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5592 return 0;
5593}
5594
5595static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5596 struct snd_ctl_elem_value *ucontrol)
5597{
5598 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5599 struct ca0132_spec *spec = codec->spec;
5600
5601 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5602 return 0;
5603}
5604
5605static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5606 struct snd_ctl_elem_value *ucontrol)
5607{
5608 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5609 struct ca0132_spec *spec = codec->spec;
5610 int i, err = 0;
5611 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5612 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5613
5614 if (sel >= items)
5615 return 0;
5616
5617 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5618 ca0132_alt_eq_presets[sel].name);
5619 /*
5620 * Idx 0 is default.
5621 * Default needs to qualify with CrystalVoice state.
5622 */
5623 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5624 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5625 ca0132_alt_eq_enum.reqs[i],
5626 ca0132_alt_eq_presets[sel].vals[i]);
5627 if (err < 0)
5628 break;
5629 }
5630
5631 if (err >= 0)
5632 spec->eq_preset_val = sel;
5633
5634 return 1;
5635}
5636
a7e76271
IM		 5637static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5638 struct snd_ctl_elem_info *uinfo)
5639{
a9291f46 5640 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5641
5642 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5643 uinfo->count = 1;
5644 uinfo->value.enumerated.items = items;
5645 if (uinfo->value.enumerated.item >= items)
5646 uinfo->value.enumerated.item = items - 1;
5647 strcpy(uinfo->value.enumerated.name,
5648 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5649 return 0;
5650}
95c6e9cb 5651
a7e76271 5652static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5653 struct snd_ctl_elem_value *ucontrol)
5654{
5655 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5656 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5657
a7e76271 5658 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5659 return 0;
5660}
5661
a7e76271 5662static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5663 struct snd_ctl_elem_value *ucontrol)
5664{
5665 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5666 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5667 int i, err = 0;
5668 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5669
a9291f46 5670 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5671 return 0;
5672
4e76a883 5673 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5674 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5675
a7e76271
IM		 5676 /*
5677 * Idx 0 is default.
5678 * Default needs to qualify with CrystalVoice state.
5679 */
5680 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5681 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5682 ca0132_voicefx.reqs[i],
5683 ca0132_voicefx_presets[sel].vals[i]);
5684 if (err < 0)
5685 break;
5686 }
95c6e9cb 5687
a7e76271
IM		 5688 if (err >= 0) {
5689 spec->voicefx_val = sel;
5690 /* enable voice fx */
5691 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5692 }
95c6e9cb 5693
a7e76271 5694 return 1;
95c6e9cb
IM		 5695}
5696
a7e76271
IM		 5697static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5698 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5699{
5700 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5701 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5702 hda_nid_t nid = get_amp_nid(kcontrol);
5703 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5704 long *valp = ucontrol->value.integer.value;
5705
a7e76271
IM		 5706 /* vnode */
5707 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5708 if (ch & 1) {
5709 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5710 valp++;
5711 }
5712 if (ch & 2) {
5713 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5714 valp++;
5715 }
5716 return 0;
5717 }
5718
5719 /* effects, include PE and CrystalVoice */
5720 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5721 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5722 return 0;
5723 }
5724
5725 /* mic boost */
5726 if (nid == spec->input_pins[0]) {
5727 *valp = spec->cur_mic_boost;
5728 return 0;
5729 }
5730
95c6e9cb
IM		 5731 return 0;
5732}
5733
a7e76271
IM		 5734static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5735 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5736{
5737 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5738 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5739 hda_nid_t nid = get_amp_nid(kcontrol);
5740 int ch = get_amp_channels(kcontrol);
95c6e9cb 5741 long *valp = ucontrol->value.integer.value;
a7e76271 5742 int changed = 1;
95c6e9cb 5743
4e76a883 5744 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5745 nid, *valp);
95c6e9cb
IM		 5746
5747 snd_hda_power_up(codec);
a7e76271
IM		 5748 /* vnode */
5749 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5750 if (ch & 1) {
5751 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5752 valp++;
5753 }
5754 if (ch & 2) {
5755 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5756 valp++;
5757 }
5758 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5759 goto exit;
5760 }
95c6e9cb 5761
a7e76271
IM		 5762 /* PE */
5763 if (nid == PLAY_ENHANCEMENT) {
5764 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5765 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5766 goto exit;
a7e76271 5767 }
95c6e9cb 5768
a7e76271
IM		 5769 /* CrystalVoice */
5770 if (nid == CRYSTAL_VOICE) {
5771 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5772 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5773 goto exit;
a7e76271 5774 }
95c6e9cb 5775
a7e76271
IM		 5776 /* out and in effects */
5777 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5778 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5779 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5780 changed = ca0132_effects_set(codec, nid, *valp);
5781 goto exit;
5782 }
5783
5784 /* mic boost */
5785 if (nid == spec->input_pins[0]) {
5786 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5787 if (spec->use_alt_functions) {
5788 if (spec->in_enum_val != REAR_LINE_IN)
5789 changed = ca0132_mic_boost_set(codec, *valp);
5790 } else {
5791 /* Mic boost does not apply to Digital Mic */
5792 if (spec->cur_mic_type != DIGITAL_MIC)
5793 changed = ca0132_mic_boost_set(codec, *valp);
5794 }
a7e76271 5795
a7e76271
IM		 5796 goto exit;
5797 }
95c6e9cb 5798
d51434d4
CM		 5799 if (nid == ZXR_HEADPHONE_GAIN) {
5800 spec->zxr_gain_set = *valp;
5801 if (spec->cur_out_type == HEADPHONE_OUT)
5802 changed = zxr_headphone_gain_set(codec, *valp);
5803 else
5804 changed = 0;
5805
5806 goto exit;
5807 }
5808
a7e76271 5809exit:
95c6e9cb 5810 snd_hda_power_down(codec);
a7e76271 5811 return changed;
95c6e9cb
IM		 5812}
5813
a7e76271
IM		 5814/*
5815 * Volume related
5816 */
017310fb
CM		 5817/*
5818 * Sets the internal DSP decibel level to match the DAC for output, and the
5819 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5820 * all alternative codecs set DSP playback volume.
5821 */
5822static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5823{
5824 struct ca0132_spec *spec = codec->spec;
5825 unsigned int dsp_dir;
5826 unsigned int lookup_val;
5827
5828 if (nid == VNID_SPK)
5829 dsp_dir = DSP_VOL_OUT;
5830 else
5831 dsp_dir = DSP_VOL_IN;
5832
5833 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5834
5835 dspio_set_uint_param(codec,
5836 ca0132_alt_vol_ctls[dsp_dir].mid,
5837 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5838 float_vol_db_lookup[lookup_val]);
5839
5840 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5841
5842 dspio_set_uint_param(codec,
5843 ca0132_alt_vol_ctls[dsp_dir].mid,
5844 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5845 float_vol_db_lookup[lookup_val]);
5846
5847 dspio_set_uint_param(codec,
5848 ca0132_alt_vol_ctls[dsp_dir].mid,
5849 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5850}
5851
a7e76271
IM		 5852static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5853 struct snd_ctl_elem_info *uinfo)
5854{
5855 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5856 struct ca0132_spec *spec = codec->spec;
5857 hda_nid_t nid = get_amp_nid(kcontrol);
5858 int ch = get_amp_channels(kcontrol);
5859 int dir = get_amp_direction(kcontrol);
5860 unsigned long pval;
5861 int err;
5862
5863 switch (nid) {
5864 case VNID_SPK:
5865 /* follow shared_out info */
5866 nid = spec->shared_out_nid;
5867 mutex_lock(&codec->control_mutex);
5868 pval = kcontrol->private_value;
5869 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5870 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5871 kcontrol->private_value = pval;
5872 mutex_unlock(&codec->control_mutex);
5873 break;
5874 case VNID_MIC:
5875 /* follow shared_mic info */
5876 nid = spec->shared_mic_nid;
5877 mutex_lock(&codec->control_mutex);
5878 pval = kcontrol->private_value;
5879 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5880 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5881 kcontrol->private_value = pval;
5882 mutex_unlock(&codec->control_mutex);
5883 break;
5884 default:
5885 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5886 }
5887 return err;
5888}
5889
5890static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5891 struct snd_ctl_elem_value *ucontrol)
5892{
5893 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5894 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5895 hda_nid_t nid = get_amp_nid(kcontrol);
5896 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5897 long *valp = ucontrol->value.integer.value;
5898
a7e76271
IM		 5899 /* store the left and right volume */
5900 if (ch & 1) {
5901 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5902 valp++;
5903 }
5904 if (ch & 2) {
5905 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5906 valp++;
5907 }
95c6e9cb
IM		 5908 return 0;
5909}
5910
a7e76271 5911static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5912 struct snd_ctl_elem_value *ucontrol)
5913{
5914 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5915 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5916 hda_nid_t nid = get_amp_nid(kcontrol);
5917 int ch = get_amp_channels(kcontrol);
95c6e9cb 5918 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5919 hda_nid_t shared_nid = 0;
5920 bool effective;
5921 int changed = 1;
5922
5923 /* store the left and right volume */
5924 if (ch & 1) {
5925 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5926 valp++;
5927 }
5928 if (ch & 2) {
5929 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5930 valp++;
5931 }
95c6e9cb 5932
a7e76271
IM		 5933 /* if effective conditions, then update hw immediately. */
5934 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5935 if (effective) {
5936 int dir = get_amp_direction(kcontrol);
5937 unsigned long pval;
5938
5939 snd_hda_power_up(codec);
5940 mutex_lock(&codec->control_mutex);
5941 pval = kcontrol->private_value;
5942 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5943 0, dir);
5944 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5945 kcontrol->private_value = pval;
5946 mutex_unlock(&codec->control_mutex);
5947 snd_hda_power_down(codec);
5948 }
95c6e9cb 5949
a7e76271 5950 return changed;
95c6e9cb
IM		 5951}
5952
017310fb
CM		 5953/*
5954 * This function is the same as the one above, because using an if statement
5955 * inside of the above volume control for the DSP volume would cause too much
5956 * lag. This is a lot more smooth.
5957 */
5958static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5959 struct snd_ctl_elem_value *ucontrol)
5960{
5961 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5962 struct ca0132_spec *spec = codec->spec;
5963 hda_nid_t nid = get_amp_nid(kcontrol);
5964 int ch = get_amp_channels(kcontrol);
5965 long *valp = ucontrol->value.integer.value;
5966 hda_nid_t vnid = 0;
5967 int changed = 1;
5968
5969 switch (nid) {
5970 case 0x02:
5971 vnid = VNID_SPK;
5972 break;
5973 case 0x07:
5974 vnid = VNID_MIC;
5975 break;
5976 }
5977
5978 /* store the left and right volume */
5979 if (ch & 1) {
5980 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5981 valp++;
5982 }
5983 if (ch & 2) {
5984 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5985 valp++;
5986 }
5987
5988 snd_hda_power_up(codec);
5989 ca0132_alt_dsp_volume_put(codec, vnid);
5990 mutex_lock(&codec->control_mutex);
5991 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5992 mutex_unlock(&codec->control_mutex);
5993 snd_hda_power_down(codec);
5994
5995 return changed;
5996}
5997
a7e76271
IM		 5998static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5999 unsigned int size, unsigned int __user *tlv)
95c6e9cb 6000{
a7e76271
IM		 6001 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6002 struct ca0132_spec *spec = codec->spec;
6003 hda_nid_t nid = get_amp_nid(kcontrol);
6004 int ch = get_amp_channels(kcontrol);
6005 int dir = get_amp_direction(kcontrol);
6006 unsigned long pval;
6007 int err;
6008
6009 switch (nid) {
6010 case VNID_SPK:
6011 /* follow shared_out tlv */
6012 nid = spec->shared_out_nid;
6013 mutex_lock(&codec->control_mutex);
6014 pval = kcontrol->private_value;
6015 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6016 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6017 kcontrol->private_value = pval;
6018 mutex_unlock(&codec->control_mutex);
6019 break;
6020 case VNID_MIC:
6021 /* follow shared_mic tlv */
6022 nid = spec->shared_mic_nid;
6023 mutex_lock(&codec->control_mutex);
6024 pval = kcontrol->private_value;
6025 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6026 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6027 kcontrol->private_value = pval;
6028 mutex_unlock(&codec->control_mutex);
6029 break;
6030 default:
6031 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6032 }
6033 return err;
95c6e9cb
IM		 6034}
6035
47cdf76e
CM		 6036/* Add volume slider control for effect level */
6037static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6038 const char *pfx, int dir)
6039{
47cdf76e
CM		 6040 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6041 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6042 struct snd_kcontrol_new knew =
6043 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6044
0cc1aa71 6045 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 6046
bb86124c 6047 knew.tlv.c = NULL;
47cdf76e
CM		 6048
6049 switch (nid) {
6050 case XBASS_XOVER:
6051 knew.info = ca0132_alt_xbass_xover_slider_info;
6052 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6053 knew.put = ca0132_alt_xbass_xover_slider_put;
6054 break;
6055 default:
6056 knew.info = ca0132_alt_effect_slider_info;
6057 knew.get = ca0132_alt_slider_ctl_get;
6058 knew.put = ca0132_alt_effect_slider_put;
6059 knew.private_value =
6060 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6061 break;
6062 }
6063
6064 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6065}
6066
6067/*
6068 * Added FX: prefix for the alternative codecs, because otherwise the surround
6069 * effect would conflict with the Surround sound volume control. Also seems more
6070 * clear as to what the switches do. Left alone for others.
6071 */
a7e76271
IM		 6072static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6073 const char *pfx, int dir)
95c6e9cb 6074{
47cdf76e 6075 struct ca0132_spec *spec = codec->spec;
975cc02a 6076 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 6077 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 6078 struct snd_kcontrol_new knew =
a7e76271 6079 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 6080 /* If using alt_controls, add FX: prefix. But, don't add FX:
6081 * prefix to OutFX or InFX enable controls.
6082 */
6083 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 6084 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 6085 else
6086 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6087
95c6e9cb
IM		 6088 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6089}
6090
a7e76271 6091static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 6092{
6093 struct snd_kcontrol_new knew =
a7e76271
IM		 6094 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6095 VOICEFX, 1, 0, HDA_INPUT);
6096 knew.info = ca0132_voicefx_info;
6097 knew.get = ca0132_voicefx_get;
6098 knew.put = ca0132_voicefx_put;
6099 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 6100}
6101
47cdf76e
CM		 6102/* Create the EQ Preset control */
6103static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6104{
6105 struct snd_kcontrol_new knew =
6106 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6107 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6108 knew.info = ca0132_alt_eq_preset_info;
6109 knew.get = ca0132_alt_eq_preset_get;
6110 knew.put = ca0132_alt_eq_preset_put;
6111 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6112 snd_ctl_new1(&knew, codec));
6113}
6114
6115/*
6116 * Add enumerated control for the three different settings of the smart volume
6117 * output effect. Normal just uses the slider value, and loud and night are
6118 * their own things that ignore that value.
6119 */
6120static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6121{
6122 struct snd_kcontrol_new knew =
6123 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6124 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6125 knew.info = ca0132_alt_svm_setting_info;
6126 knew.get = ca0132_alt_svm_setting_get;
6127 knew.put = ca0132_alt_svm_setting_put;
6128 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6129 snd_ctl_new1(&knew, codec));
6130
6131}
6132
7cb9d94c
CM		 6133/*
6134 * Create an Output Select enumerated control for codecs with surround
6135 * out capabilities.
6136 */
6137static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6138{
6139 struct snd_kcontrol_new knew =
6140 HDA_CODEC_MUTE_MONO("Output Select",
6141 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6142 knew.info = ca0132_alt_output_select_get_info;
6143 knew.get = ca0132_alt_output_select_get;
6144 knew.put = ca0132_alt_output_select_put;
6145 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6146 snd_ctl_new1(&knew, codec));
6147}
6148
6149/*
6150 * Create an Input Source enumerated control for the alternate ca0132 codecs
6151 * because the front microphone has no auto-detect, and Line-in has to be set
6152 * somehow.
6153 */
6154static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6155{
6156 struct snd_kcontrol_new knew =
6157 HDA_CODEC_MUTE_MONO("Input Source",
6158 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6159 knew.info = ca0132_alt_input_source_info;
6160 knew.get = ca0132_alt_input_source_get;
6161 knew.put = ca0132_alt_input_source_put;
6162 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6163 snd_ctl_new1(&knew, codec));
6164}
6165
47cdf76e
CM		 6166/*
6167 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6168 * more control than the original mic boost, which is either full 30dB or off.
6169 */
6170static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6171{
6172 struct snd_kcontrol_new knew =
6173 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6174 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6175 knew.info = ca0132_alt_mic_boost_info;
6176 knew.get = ca0132_alt_mic_boost_get;
6177 knew.put = ca0132_alt_mic_boost_put;
6178 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6179 snd_ctl_new1(&knew, codec));
6180
6181}
6182
212de2e7
CM		 6183/*
6184 * Add headphone gain enumerated control for the AE-5. This switches between
6185 * three modes, low, medium, and high. When non-headphone outputs are selected,
6186 * it is automatically set to high. This is the same behavior as Windows.
6187 */
6188static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6189{
6190 struct snd_kcontrol_new knew =
6191 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
4b432ad4 6192 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6193 knew.info = ae5_headphone_gain_info;
6194 knew.get = ae5_headphone_gain_get;
6195 knew.put = ae5_headphone_gain_put;
6196 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6197 snd_ctl_new1(&knew, codec));
6198}
6199
6200/*
6201 * Add sound filter enumerated control for the AE-5. This adds three different
6202 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6203 * read into it, it changes the DAC's interpolation filter.
6204 */
6205static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6206{
6207 struct snd_kcontrol_new knew =
6208 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
4b432ad4 6209 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6210 knew.info = ae5_sound_filter_info;
6211 knew.get = ae5_sound_filter_get;
6212 knew.put = ae5_sound_filter_put;
6213 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6214 snd_ctl_new1(&knew, codec));
6215}
6216
d51434d4
CM		 6217static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6218{
6219 struct snd_kcontrol_new knew =
6220 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6221 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6222
6223 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6224 snd_ctl_new1(&knew, codec));
6225}
6226
47cdf76e
CM		 6227/*
6228 * Need to create slave controls for the alternate codecs that have surround
6229 * capabilities.
6230 */
6231static const char * const ca0132_alt_slave_pfxs[] = {
6232 "Front", "Surround", "Center", "LFE", NULL,
6233};
6234
6235/*
6236 * Also need special channel map, because the default one is incorrect.
6237 * I think this has to do with the pin for rear surround being 0x11,
6238 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6239 */
9c4a665e 6240static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 6241 { .channels = 2,
6242 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6243 { .channels = 4,
6244 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6245 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6246 { .channels = 6,
6247 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6248 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6249 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6250 { }
6251};
6252
6253/* Add the correct chmap for streams with 6 channels. */
6254static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6255{
6256 int err = 0;
6257 struct hda_pcm *pcm;
6258
6259 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6260 struct hda_pcm_stream *hinfo =
6261 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6262 struct snd_pcm_chmap *chmap;
6263 const struct snd_pcm_chmap_elem *elem;
6264
6265 elem = ca0132_alt_chmaps;
6266 if (hinfo->channels_max == 6) {
6267 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6268 SNDRV_PCM_STREAM_PLAYBACK,
6269 elem, hinfo->channels_max, 0, &chmap);
6270 if (err < 0)
6271 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6272 }
6273 }
6274}
6275
a7e76271
IM		 6276/*
6277 * When changing Node IDs for Mixer Controls below, make sure to update
6278 * Node IDs in ca0132_config() as well.
6279 */
b0eaa072 6280static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 6281 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6282 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6283 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6284 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6285 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6286 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6287 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6288 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6289 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6290 0x12, 1, HDA_INPUT),
6291 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6292 VNID_HP_SEL, 1, HDA_OUTPUT),
6293 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6294 VNID_AMIC1_SEL, 1, HDA_INPUT),
6295 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6296 VNID_HP_ASEL, 1, HDA_OUTPUT),
6297 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6298 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6299 { } /* end */
6300};
6301
017310fb 6302/*
e25e3445
CM		 6303 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6304 * surround controls. Also sets both the Front Playback and Capture Volume
6305 * controls to alt so they set the DSP's decibel level.
017310fb 6306 */
e25e3445 6307static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 6308 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6309 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6310 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6311 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6312 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6313 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6314 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6315 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6316 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6317 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6318 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6319 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6320 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6321 VNID_HP_ASEL, 1, HDA_OUTPUT),
6322 { } /* end */
6323};
6324
6325/*
6326 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6327 * because it doesn't set decibel levels for the DSP for capture.
6328 */
b0eaa072 6329static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 6330 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6331 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6332 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6333 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6334 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6335 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6336 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6337 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6338 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6339 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6340 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6341 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6342 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6343 VNID_HP_ASEL, 1, HDA_OUTPUT),
6344 { } /* end */
6345};
6346
e90f29e4
IM		 6347static int ca0132_build_controls(struct hda_codec *codec)
6348{
6349 struct ca0132_spec *spec = codec->spec;
47cdf76e 6350 int i, num_fx, num_sliders;
e90f29e4
IM		 6351 int err = 0;
6352
6353 /* Add Mixer controls */
6354 for (i = 0; i < spec->num_mixers; i++) {
6355 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6356 if (err < 0)
6357 return err;
6358 }
47cdf76e
CM		 6359 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6360 if (spec->use_alt_functions) {
6361 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6362 spec->tlv);
6363 snd_hda_add_vmaster(codec, "Master Playback Volume",
6364 spec->tlv, ca0132_alt_slave_pfxs,
6365 "Playback Volume");
6366 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6367 NULL, ca0132_alt_slave_pfxs,
6368 "Playback Switch",
6369 true, &spec->vmaster_mute.sw_kctl);
1502b432
CM		 6370 if (err < 0)
6371 return err;
47cdf76e 6372 }
e90f29e4
IM		 6373
6374 /* Add in and out effects controls.
6375 * VoiceFX, PE and CrystalVoice are added separately.
6376 */
6377 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6378 for (i = 0; i < num_fx; i++) {
7a2dc84f
CM		 6379 /* Desktop cards break if Echo Cancellation is used. */
6380 if (spec->use_pci_mmio) {
47cdf76e
CM		 6381 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6382 OUT_EFFECTS_COUNT))
6383 continue;
6384 }
6385
e90f29e4
IM		 6386 err = add_fx_switch(codec, ca0132_effects[i].nid,
6387 ca0132_effects[i].name,
6388 ca0132_effects[i].direct);
6389 if (err < 0)
6390 return err;
6391 }
47cdf76e
CM		 6392 /*
6393 * If codec has use_alt_controls set to true, add effect level sliders,
6394 * EQ presets, and Smart Volume presets. Also, change names to add FX
6395 * prefix, and change PlayEnhancement and CrystalVoice to match.
6396 */
6397 if (spec->use_alt_controls) {
1502b432
CM		 6398 err = ca0132_alt_add_svm_enum(codec);
6399 if (err < 0)
6400 return err;
6401
6402 err = add_ca0132_alt_eq_presets(codec);
6403 if (err < 0)
6404 return err;
6405
47cdf76e
CM		 6406 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6407 "Enable OutFX", 0);
6408 if (err < 0)
6409 return err;
e90f29e4 6410
47cdf76e
CM		 6411 err = add_fx_switch(codec, CRYSTAL_VOICE,
6412 "Enable InFX", 1);
6413 if (err < 0)
6414 return err;
e90f29e4 6415
47cdf76e
CM		 6416 num_sliders = OUT_EFFECTS_COUNT - 1;
6417 for (i = 0; i < num_sliders; i++) {
6418 err = ca0132_alt_add_effect_slider(codec,
6419 ca0132_effects[i].nid,
6420 ca0132_effects[i].name,
6421 ca0132_effects[i].direct);
6422 if (err < 0)
6423 return err;
6424 }
6425
6426 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6427 "X-Bass Crossover", EFX_DIR_OUT);
6428
6429 if (err < 0)
6430 return err;
6431 } else {
6432 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6433 "PlayEnhancement", 0);
6434 if (err < 0)
6435 return err;
e90f29e4 6436
47cdf76e
CM		 6437 err = add_fx_switch(codec, CRYSTAL_VOICE,
6438 "CrystalVoice", 1);
6439 if (err < 0)
6440 return err;
6441 }
1502b432
CM		 6442 err = add_voicefx(codec);
6443 if (err < 0)
6444 return err;
e90f29e4 6445
7cb9d94c
CM		 6446 /*
6447 * If the codec uses alt_functions, you need the enumerated controls
6448 * to select the new outputs and inputs, plus add the new mic boost
6449 * setting control.
6450 */
6451 if (spec->use_alt_functions) {
1502b432
CM		 6452 err = ca0132_alt_add_output_enum(codec);
6453 if (err < 0)
6454 return err;
6455 err = ca0132_alt_add_mic_boost_enum(codec);
6456 if (err < 0)
6457 return err;
76dea4db
CM		 6458 /*
6459 * ZxR only has microphone input, there is no front panel
6460 * header on the card, and aux-in is handled by the DBPro board.
6461 */
1502b432
CM		 6462 if (spec->quirk != QUIRK_ZXR) {
6463 err = ca0132_alt_add_input_enum(codec);
6464 if (err < 0)
6465 return err;
6466 }
7cb9d94c 6467 }
212de2e7
CM		 6468
6469 if (spec->quirk == QUIRK_AE5) {
1502b432
CM		 6470 err = ae5_add_headphone_gain_enum(codec);
6471 if (err < 0)
6472 return err;
6473 err = ae5_add_sound_filter_enum(codec);
6474 if (err < 0)
6475 return err;
212de2e7 6476 }
d51434d4 6477
1502b432
CM		 6478 if (spec->quirk == QUIRK_ZXR) {
6479 err = zxr_add_headphone_gain_switch(codec);
6480 if (err < 0)
6481 return err;
6482 }
e90f29e4
IM		 6483#ifdef ENABLE_TUNING_CONTROLS
6484 add_tuning_ctls(codec);
6485#endif
6486
6487 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6488 if (err < 0)
6489 return err;
6490
6491 if (spec->dig_out) {
6492 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6493 spec->dig_out);
6494 if (err < 0)
6495 return err;
6496 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6497 if (err < 0)
6498 return err;
6499 /* spec->multiout.share_spdif = 1; */
6500 }
6501
6502 if (spec->dig_in) {
6503 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6504 if (err < 0)
6505 return err;
6506 }
47cdf76e
CM		 6507
6508 if (spec->use_alt_functions)
6509 ca0132_alt_add_chmap_ctls(codec);
6510
e90f29e4
IM		 6511 return 0;
6512}
6513
7675a2a9
CM		 6514static int dbpro_build_controls(struct hda_codec *codec)
6515{
6516 struct ca0132_spec *spec = codec->spec;
6517 int err = 0;
6518
6519 if (spec->dig_out) {
6520 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6521 spec->dig_out);
6522 if (err < 0)
6523 return err;
6524 }
6525
6526 if (spec->dig_in) {
6527 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6528 if (err < 0)
6529 return err;
6530 }
6531
6532 return 0;
6533}
6534
a7e76271 6535/*
e90f29e4 6536 * PCM
a7e76271 6537 */
071f1344 6538static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6539 .substreams = 1,
6540 .channels_min = 2,
825315bc 6541 .channels_max = 6,
a7e76271 6542 .ops = {
a7e76271 6543 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6544 .cleanup = ca0132_playback_pcm_cleanup,
6545 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6546 },
6547};
6548
071f1344 6549static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6550 .substreams = 1,
6551 .channels_min = 2,
6552 .channels_max = 2,
825315bc
IM		 6553 .ops = {
6554 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6555 .cleanup = ca0132_capture_pcm_cleanup,
6556 .get_delay = ca0132_capture_pcm_delay,
825315bc 6557 },
a7e76271
IM		 6558};
6559
071f1344 6560static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6561 .substreams = 1,
6562 .channels_min = 2,
6563 .channels_max = 2,
6564 .ops = {
6565 .open = ca0132_dig_playback_pcm_open,
6566 .close = ca0132_dig_playback_pcm_close,
6567 .prepare = ca0132_dig_playback_pcm_prepare,
6568 .cleanup = ca0132_dig_playback_pcm_cleanup
6569 },
6570};
6571
071f1344 6572static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6573 .substreams = 1,
6574 .channels_min = 2,
6575 .channels_max = 2,
6576};
6577
6578static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6579{
6580 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6581 struct hda_pcm *info;
a7e76271 6582
bbbc7e85
TI		 6583 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6584 if (!info)
6585 return -ENOMEM;
47cdf76e
CM		 6586 if (spec->use_alt_functions) {
6587 info->own_chmap = true;
6588 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6589 = ca0132_alt_chmaps;
6590 }
a7e76271
IM		 6591 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6592 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6593 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6594 spec->multiout.max_channels;
6595 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6596 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6597 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6598
009b8f97 6599 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 6600 if (!spec->use_alt_functions) {
009b8f97
CM		 6601 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6602 if (!info)
6603 return -ENOMEM;
6604 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6605 ca0132_pcm_analog_capture;
6606 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6607 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6608 }
825315bc 6609
bbbc7e85
TI		 6610 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6611 if (!info)
6612 return -ENOMEM;
825315bc
IM		 6613 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6614 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6615 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6616
a7e76271
IM		 6617 if (!spec->dig_out && !spec->dig_in)
6618 return 0;
6619
bbbc7e85
TI		 6620 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6621 if (!info)
6622 return -ENOMEM;
a7e76271
IM		 6623 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6624 if (spec->dig_out) {
6625 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6626 ca0132_pcm_digital_playback;
6627 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6628 }
6629 if (spec->dig_in) {
6630 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6631 ca0132_pcm_digital_capture;
6632 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6633 }
95c6e9cb 6634
a7e76271 6635 return 0;
95c6e9cb
IM		 6636}
6637
7675a2a9
CM		 6638static int dbpro_build_pcms(struct hda_codec *codec)
6639{
6640 struct ca0132_spec *spec = codec->spec;
6641 struct hda_pcm *info;
6642
6643 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
6644 if (!info)
6645 return -ENOMEM;
6646 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6647 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6648 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6649
6650
6651 if (!spec->dig_out && !spec->dig_in)
6652 return 0;
6653
6654 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6655 if (!info)
6656 return -ENOMEM;
6657 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6658 if (spec->dig_out) {
6659 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6660 ca0132_pcm_digital_playback;
6661 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6662 }
6663 if (spec->dig_in) {
6664 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6665 ca0132_pcm_digital_capture;
6666 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6667 }
6668
6669 return 0;
6670}
6671
441aa6a0
IM		 6672static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6673{
6674 if (pin) {
a0c041cb 6675 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6676 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6677 snd_hda_codec_write(codec, pin, 0,
6678 AC_VERB_SET_AMP_GAIN_MUTE,
6679 AMP_OUT_UNMUTE);
6680 }
6681 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6682 snd_hda_codec_write(codec, dac, 0,
6683 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6684}
6685
6686static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6687{
6688 if (pin) {
a0c041cb 6689 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6690 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6691 snd_hda_codec_write(codec, pin, 0,
6692 AC_VERB_SET_AMP_GAIN_MUTE,
6693 AMP_IN_UNMUTE(0));
6694 }
6695 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6696 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6697 AMP_IN_UNMUTE(0));
6698
6699 /* init to 0 dB and unmute. */
6700 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6701 HDA_AMP_VOLMASK, 0x5a);
6702 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6703 HDA_AMP_MUTE, 0);
6704 }
6705}
6706
5aaca44d
IM		 6707static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6708{
6709 unsigned int caps;
6710
6711 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6712 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6713 snd_hda_override_amp_caps(codec, nid, dir, caps);
6714}
6715
6716/*
6717 * Switch between Digital built-in mic and analog mic.
6718 */
6719static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6720{
6721 struct ca0132_spec *spec = codec->spec;
6722 unsigned int tmp;
6723 u8 val;
6724 unsigned int oldval;
6725
4e76a883 6726 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6727
6728 oldval = stop_mic1(codec);
6729 ca0132_set_vipsource(codec, 0);
6730 if (enable) {
6731 /* set DMic input as 2-ch */
6732 tmp = FLOAT_TWO;
6733 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6734
6735 val = spec->dmic_ctl;
6736 val |= 0x80;
6737 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6738 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6739
6740 if (!(spec->dmic_ctl & 0x20))
6741 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6742 } else {
6743 /* set AMic input as mono */
6744 tmp = FLOAT_ONE;
6745 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6746
6747 val = spec->dmic_ctl;
6748 /* clear bit7 and bit5 to disable dmic */
6749 val &= 0x5f;
6750 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6751 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6752
6753 if (!(spec->dmic_ctl & 0x20))
6754 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6755 }
6756 ca0132_set_vipsource(codec, 1);
6757 resume_mic1(codec, oldval);
6758}
6759
6760/*
6761 * Initialization for Digital Mic.
6762 */
6763static void ca0132_init_dmic(struct hda_codec *codec)
6764{
6765 struct ca0132_spec *spec = codec->spec;
6766 u8 val;
6767
6768 /* Setup Digital Mic here, but don't enable.
6769 * Enable based on jack detect.
6770 */
6771
6772 /* MCLK uses MPIO1, set to enable.
6773 * Bit 2-0: MPIO select
6774 * Bit 3: set to disable
6775 * Bit 7-4: reserved
6776 */
6777 val = 0x01;
6778 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6779 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6780
6781 /* Data1 uses MPIO3. Data2 not use
6782 * Bit 2-0: Data1 MPIO select
6783 * Bit 3: set disable Data1
6784 * Bit 6-4: Data2 MPIO select
6785 * Bit 7: set disable Data2
6786 */
6787 val = 0x83;
6788 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6789 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6790
6791 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6792 * Bit 3-0: Channel mask
6793 * Bit 4: set for 48KHz, clear for 32KHz
6794 * Bit 5: mode
6795 * Bit 6: set to select Data2, clear for Data1
6796 * Bit 7: set to enable DMic, clear for AMic
6797 */
a57a46b9
AB		 6798 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6799 val = 0x33;
6800 else
6801 val = 0x23;
5aaca44d
IM		 6802 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6803 spec->dmic_ctl = val;
6804 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6805 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6806}
6807
6808/*
6809 * Initialization for Analog Mic 2
6810 */
6811static void ca0132_init_analog_mic2(struct hda_codec *codec)
6812{
6813 struct ca0132_spec *spec = codec->spec;
6814
6815 mutex_lock(&spec->chipio_mutex);
6816 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6817 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6818 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6819 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6820 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6821 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6822 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6823 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6824 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6825 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6826 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6827 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6828 mutex_unlock(&spec->chipio_mutex);
6829}
6830
6831static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6832{
6833 struct ca0132_spec *spec = codec->spec;
6834 int i;
5aaca44d 6835
4e76a883 6836 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6837 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6838
6839 for (i = 0; i < spec->multiout.num_dacs; i++)
6840 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6841
6842 for (i = 0; i < spec->num_outputs; i++)
6843 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6844
6845 for (i = 0; i < spec->num_inputs; i++) {
6846 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6847 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6848 }
6849}
6850
7e6ed62e 6851/*
6ef0e91e
CM		 6852 * Creates a dummy stream to bind the output to. This seems to have to be done
6853 * after changing the main outputs source and destination streams.
7e6ed62e 6854 */
6ef0e91e 6855static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6856{
6ef0e91e
CM		 6857 struct ca0132_spec *spec = codec->spec;
6858 unsigned int stream_format;
447fd8e9 6859
6ef0e91e
CM		 6860 stream_format = snd_hdac_calc_stream_format(48000, 2,
6861 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6862
6ef0e91e
CM		 6863 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6864 0, stream_format);
7e6ed62e 6865
6ef0e91e 6866 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6867}
6868
38ba69ff 6869/*
6ef0e91e 6870 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6871 */
6ef0e91e 6872static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6873{
6ef0e91e 6874 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6875 unsigned int tmp;
6876
6877 /* Mic 1 Setup */
6878 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6879 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6ef0e91e
CM		 6880 if (spec->quirk == QUIRK_R3DI) {
6881 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6882 tmp = FLOAT_ONE;
6883 } else
6884 tmp = FLOAT_THREE;
38ba69ff
CM		 6885 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6886
6ef0e91e 6887 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6888 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6889 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6ef0e91e
CM		 6890 if (spec->quirk == QUIRK_R3DI)
6891 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6892 tmp = FLOAT_ZERO;
6893 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6894}
6895
6896/*
6897 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6898 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6899 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6900 * having an updated DAC, which changes the destination to that DAC.
6901 */
6902static void sbz_connect_streams(struct hda_codec *codec)
6903{
6904 struct ca0132_spec *spec = codec->spec;
6905
6906 mutex_lock(&spec->chipio_mutex);
6907
6908 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6909
6910 chipio_set_stream_channels(codec, 0x0C, 6);
6911 chipio_set_stream_control(codec, 0x0C, 1);
6912
6913 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6914 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6915
6916 /* Setup stream 0x14 with it's source and destination points */
6917 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6918 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6919 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6920 chipio_set_stream_channels(codec, 0x14, 2);
6921 chipio_set_stream_control(codec, 0x14, 1);
6922
6923 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6924
6925 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6926}
6927
6928/*
6929 * Write data through ChipIO to setup proper stream destinations.
6930 * Not sure how it exactly works, but it seems to direct data
6931 * to different destinations. Example is f8 to c0, e0 to c0.
6932 * All I know is, if you don't set these, you get no sound.
6933 */
6934static void sbz_chipio_startup_data(struct hda_codec *codec)
6935{
6936 struct ca0132_spec *spec = codec->spec;
6937
6938 mutex_lock(&spec->chipio_mutex);
6939 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6940
6941 /* These control audio output */
6942 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6943 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6944 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6945 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6946 /* Signal to update I think */
6947 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6948
6949 chipio_set_stream_channels(codec, 0x0C, 6);
6950 chipio_set_stream_control(codec, 0x0C, 1);
6951 /* No clue what these control */
c25c73e0
CM		 6952 if (spec->quirk == QUIRK_SBZ) {
6953 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6954 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6955 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6956 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6957 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6958 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6959 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6960 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6961 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6962 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6963 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6964 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6965 } else if (spec->quirk == QUIRK_ZXR) {
6966 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
6967 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
6968 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
6969 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
6970 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
6971 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
6972 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
6973 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
6974 }
38ba69ff
CM		 6975 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6976
6977 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6978 mutex_unlock(&spec->chipio_mutex);
6979}
6980
447fd8e9 6981/*
6ef0e91e
CM		 6982 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
6983 * done after the DSP is loaded.
447fd8e9 6984 */
6ef0e91e 6985static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 6986{
6ef0e91e 6987 struct ca0132_spec *spec = codec->spec;
b5a22935 6988 unsigned int tmp, i;
447fd8e9 6989
b5a22935
CM		 6990 /*
6991 * Gotta run these twice, or else mic works inconsistently. Not clear
6992 * why this is, but multiple tests have confirmed it.
6993 */
6994 for (i = 0; i < 2; i++) {
6995 switch (spec->quirk) {
6996 case QUIRK_SBZ:
6997 case QUIRK_AE5:
6998 tmp = 0x00000003;
6999 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7000 tmp = 0x00000000;
7001 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7002 tmp = 0x00000001;
7003 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7004 tmp = 0x00000004;
7005 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7006 tmp = 0x00000005;
7007 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7008 tmp = 0x00000000;
7009 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7010 break;
7011 case QUIRK_R3D:
7012 case QUIRK_R3DI:
7013 tmp = 0x00000000;
7014 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7015 tmp = 0x00000001;
7016 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7017 tmp = 0x00000004;
7018 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7019 tmp = 0x00000005;
7020 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7021 tmp = 0x00000000;
7022 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7023 break;
7024 }
7025 msleep(100);
6ef0e91e 7026 }
447fd8e9
CM		 7027}
7028
6ef0e91e 7029static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 7030{
6ef0e91e 7031 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 7032 unsigned int tmp;
7033
7034 chipio_set_stream_control(codec, 0x03, 0);
7035 chipio_set_stream_control(codec, 0x04, 0);
7036
7037 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7038 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7039
7040 tmp = FLOAT_THREE;
7041 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7042
7043 chipio_set_stream_control(codec, 0x03, 1);
7044 chipio_set_stream_control(codec, 0x04, 1);
7045
6ef0e91e
CM		 7046 switch (spec->quirk) {
7047 case QUIRK_SBZ:
7048 chipio_write(codec, 0x18b098, 0x0000000c);
7049 chipio_write(codec, 0x18b09C, 0x0000000c);
7050 break;
7051 case QUIRK_AE5:
7052 chipio_write(codec, 0x18b098, 0x0000000c);
7053 chipio_write(codec, 0x18b09c, 0x0000004c);
7054 break;
7055 }
38ba69ff
CM		 7056}
7057
415cd844
CM		 7058static void ae5_post_dsp_register_set(struct hda_codec *codec)
7059{
7060 struct ca0132_spec *spec = codec->spec;
7061
7062 chipio_8051_write_direct(codec, 0x93, 0x10);
7063 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7064 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7065 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7066 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7067
7068 writeb(0xff, spec->mem_base + 0x304);
7069 writeb(0xff, spec->mem_base + 0x304);
7070 writeb(0xff, spec->mem_base + 0x304);
7071 writeb(0xff, spec->mem_base + 0x304);
7072 writeb(0x00, spec->mem_base + 0x100);
7073 writeb(0xff, spec->mem_base + 0x304);
7074 writeb(0x00, spec->mem_base + 0x100);
7075 writeb(0xff, spec->mem_base + 0x304);
7076 writeb(0x00, spec->mem_base + 0x100);
7077 writeb(0xff, spec->mem_base + 0x304);
7078 writeb(0x00, spec->mem_base + 0x100);
7079 writeb(0xff, spec->mem_base + 0x304);
7080
7081 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7082 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7083 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7084}
7085
7086static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7087{
7088 /*
7089 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7090 * which seems to be 'multichannel'. This is also mentioned in the
7091 * AE-5's registry values in Windows.
7092 */
7093 chipio_set_control_param(codec, 3, 0);
7094 /*
7095 * I believe ASI is 'audio serial interface' and that it's used to
7096 * change colors on the external LED strip connected to the AE-5.
7097 */
7098 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7099
7100 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7101 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7102
7103 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7104 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7105 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7106 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7107 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7108 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7109}
7110
7111static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7112{
7113 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7114 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7115 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7116 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7117
7118 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7119 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7120 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7121 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7122
7123 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7124 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7125 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7126 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7127
7128 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7129 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7130 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7131 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7132
7133 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7134 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7135 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7136 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7137}
7138
7139static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7140{
7141 struct ca0132_spec *spec = codec->spec;
7142
7143 mutex_lock(&spec->chipio_mutex);
7144
7145 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7146
7147 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7148
7149 chipio_set_stream_channels(codec, 0x0C, 6);
7150 chipio_set_stream_control(codec, 0x0C, 1);
7151
7152 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7153
7154 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7155 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7156 chipio_set_stream_channels(codec, 0x18, 6);
7157 chipio_set_stream_control(codec, 0x18, 1);
7158
7159 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7160
7161 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7162 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7163 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7164 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7165
7166 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7167
7168 mutex_unlock(&spec->chipio_mutex);
7169}
7170
7171static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7172{
7173 struct ca0132_spec *spec = codec->spec;
7174
7175 mutex_lock(&spec->chipio_mutex);
7176
7177 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7178 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7179 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7180 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7181
7182 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7183 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7184 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7185 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7186 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7187 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7188 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7189 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7190 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7191 ca0113_mmio_gpio_set(codec, 0, true);
7192 ca0113_mmio_gpio_set(codec, 1, true);
7193 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7194
7195 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7196
7197 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7198 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7199
7200 mutex_unlock(&spec->chipio_mutex);
7201}
7202
5aaca44d
IM		 7203/*
7204 * Setup default parameters for DSP
7205 */
7206static void ca0132_setup_defaults(struct hda_codec *codec)
7207{
e8f1bd5d 7208 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7209 unsigned int tmp;
7210 int num_fx;
7211 int idx, i;
7212
e8f1bd5d 7213 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 7214 return;
7215
7216 /* out, in effects + voicefx */
7217 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7218 for (idx = 0; idx < num_fx; idx++) {
7219 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7220 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7221 ca0132_effects[idx].reqs[i],
7222 ca0132_effects[idx].def_vals[i]);
7223 }
7224 }
7225
7226 /*remove DSP headroom*/
7227 tmp = FLOAT_ZERO;
7228 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7229
7230 /*set speaker EQ bypass attenuation*/
7231 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7232
7233 /* set AMic1 and AMic2 as mono mic */
7234 tmp = FLOAT_ONE;
7235 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7236 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7237
7238 /* set AMic1 as CrystalVoice input */
7239 tmp = FLOAT_ONE;
7240 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7241
7242 /* set WUH source */
7243 tmp = FLOAT_TWO;
7244 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7245}
7246
7e6ed62e 7247/*
c986f50c 7248 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 7249 */
7250
c986f50c 7251static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 7252{
7253 struct ca0132_spec *spec = codec->spec;
7254 unsigned int tmp;
7255 int num_fx;
7256 int idx, i;
7257
7258 if (spec->dsp_state != DSP_DOWNLOADED)
7259 return;
7260
6ef0e91e
CM		 7261 ca0132_alt_dsp_scp_startup(codec);
7262 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 7263
7264 /*remove DSP headroom*/
7265 tmp = FLOAT_ZERO;
7266 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7267
7268 /* set WUH source */
7269 tmp = FLOAT_TWO;
7270 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7271 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7272
7273 /* Set speaker source? */
7274 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7275
c986f50c
CM		 7276 if (spec->quirk == QUIRK_R3DI)
7277 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 7278
7279 /* Setup effect defaults */
7280 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7281 for (idx = 0; idx < num_fx; idx++) {
7282 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7283 dspio_set_uint_param(codec,
7284 ca0132_effects[idx].mid,
7285 ca0132_effects[idx].reqs[i],
7286 ca0132_effects[idx].def_vals[i]);
7287 }
7288 }
7e6ed62e
CM		 7289}
7290
38ba69ff
CM		 7291/*
7292 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7293 * than the Chromebook setup.
7294 */
7295static void sbz_setup_defaults(struct hda_codec *codec)
7296{
7297 struct ca0132_spec *spec = codec->spec;
6ef0e91e 7298 unsigned int tmp;
38ba69ff
CM		 7299 int num_fx;
7300 int idx, i;
7301
7302 if (spec->dsp_state != DSP_DOWNLOADED)
7303 return;
7304
6ef0e91e
CM		 7305 ca0132_alt_dsp_scp_startup(codec);
7306 ca0132_alt_init_analog_mics(codec);
38ba69ff 7307 sbz_connect_streams(codec);
38ba69ff
CM		 7308 sbz_chipio_startup_data(codec);
7309
7310 chipio_set_stream_control(codec, 0x03, 1);
7311 chipio_set_stream_control(codec, 0x04, 1);
7312
7313 /*
7314 * Sets internal input loopback to off, used to have a switch to
7315 * enable input loopback, but turned out to be way too buggy.
7316 */
7317 tmp = FLOAT_ONE;
7318 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7319 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7320
7321 /*remove DSP headroom*/
7322 tmp = FLOAT_ZERO;
7323 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7324
7325 /* set WUH source */
7326 tmp = FLOAT_TWO;
7327 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7328 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7329
7330 /* Set speaker source? */
7331 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7332
6ef0e91e 7333 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 7334
7335 /* out, in effects + voicefx */
7336 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7337 for (idx = 0; idx < num_fx; idx++) {
7338 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7339 dspio_set_uint_param(codec,
7340 ca0132_effects[idx].mid,
7341 ca0132_effects[idx].reqs[i],
7342 ca0132_effects[idx].def_vals[i]);
7343 }
7344 }
7345
6ef0e91e 7346 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 7347}
7348
415cd844
CM		 7349/*
7350 * Setup default parameters for the Sound BlasterX AE-5 DSP.
7351 */
7352static void ae5_setup_defaults(struct hda_codec *codec)
7353{
7354 struct ca0132_spec *spec = codec->spec;
7355 unsigned int tmp;
7356 int num_fx;
7357 int idx, i;
7358
7359 if (spec->dsp_state != DSP_DOWNLOADED)
7360 return;
7361
7362 ca0132_alt_dsp_scp_startup(codec);
7363 ca0132_alt_init_analog_mics(codec);
7364 chipio_set_stream_control(codec, 0x03, 1);
7365 chipio_set_stream_control(codec, 0x04, 1);
7366
7367 /* New, unknown SCP req's */
7368 tmp = FLOAT_ZERO;
7369 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7370 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7371 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7372 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7373
7374 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7375 ca0113_mmio_gpio_set(codec, 0, false);
7376 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7377
7378 /* Internal loopback off */
7379 tmp = FLOAT_ONE;
7380 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7381 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7382
7383 /*remove DSP headroom*/
7384 tmp = FLOAT_ZERO;
7385 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7386
7387 /* set WUH source */
7388 tmp = FLOAT_TWO;
7389 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7390 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7391
7392 /* Set speaker source? */
7393 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7394
7395 ca0132_alt_dsp_initial_mic_setup(codec);
7396 ae5_post_dsp_register_set(codec);
7397 ae5_post_dsp_param_setup(codec);
7398 ae5_post_dsp_pll_setup(codec);
7399 ae5_post_dsp_stream_setup(codec);
7400 ae5_post_dsp_startup_data(codec);
7401
7402 /* out, in effects + voicefx */
7403 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7404 for (idx = 0; idx < num_fx; idx++) {
7405 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7406 dspio_set_uint_param(codec,
7407 ca0132_effects[idx].mid,
7408 ca0132_effects[idx].reqs[i],
7409 ca0132_effects[idx].def_vals[i]);
7410 }
7411 }
7412
7413 ca0132_alt_create_dummy_stream(codec);
7414}
7415
5aaca44d
IM		 7416/*
7417 * Initialization of flags in chip
7418 */
7419static void ca0132_init_flags(struct hda_codec *codec)
7420{
009b8f97
CM		 7421 struct ca0132_spec *spec = codec->spec;
7422
7423 if (spec->use_alt_functions) {
7424 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7425 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7426 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7427 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7428 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7429 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7430 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7431 chipio_set_control_flag(codec,
7432 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7433 chipio_set_control_flag(codec,
7434 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7435 } else {
7436 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7437 chipio_set_control_flag(codec,
7438 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7439 chipio_set_control_flag(codec,
7440 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7441 chipio_set_control_flag(codec,
7442 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7443 chipio_set_control_flag(codec,
7444 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7445 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7446 }
5aaca44d
IM		 7447}
7448
7449/*
7450 * Initialization of parameters in chip
7451 */
7452static void ca0132_init_params(struct hda_codec *codec)
7453{
009b8f97
CM		 7454 struct ca0132_spec *spec = codec->spec;
7455
7456 if (spec->use_alt_functions) {
7457 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7458 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7459 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7460 chipio_set_control_param(codec, 0, 0);
7461 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7462 }
7463
5aaca44d
IM		 7464 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7465 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7466}
95c6e9cb 7467
e90f29e4
IM		 7468static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7469{
7470 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7471 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7472 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7473 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7474 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7475 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7476
406261ce
IM		 7477 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7478 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 7479 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7480}
7481
7482static bool ca0132_download_dsp_images(struct hda_codec *codec)
7483{
7484 bool dsp_loaded = false;
8a19bcee 7485 struct ca0132_spec *spec = codec->spec;
e90f29e4 7486 const struct dsp_image_seg *dsp_os_image;
15e4ba66 7487 const struct firmware *fw_entry;
8a19bcee
CM		 7488 /*
7489 * Alternate firmwares for different variants. The Recon3Di apparently
7490 * can use the default firmware, but I'll leave the option in case
7491 * it needs it again.
7492 */
7493 switch (spec->quirk) {
7494 case QUIRK_SBZ:
7a928186
CM		 7495 case QUIRK_R3D:
7496 case QUIRK_AE5:
7497 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8a19bcee 7498 codec->card->dev) != 0) {
6ef0e91e 7499 codec_dbg(codec, "Desktop firmware not found.");
8a19bcee
CM		 7500 spec->alt_firmware_present = false;
7501 } else {
7a928186 7502 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 7503 spec->alt_firmware_present = true;
7504 }
7505 break;
7506 case QUIRK_R3DI:
7507 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
7508 codec->card->dev) != 0) {
7509 codec_dbg(codec, "Recon3Di alt firmware not detected.");
7510 spec->alt_firmware_present = false;
7511 } else {
7512 codec_dbg(codec, "Recon3Di firmware selected.");
7513 spec->alt_firmware_present = true;
7514 }
7515 break;
7516 default:
7517 spec->alt_firmware_present = false;
7518 break;
7519 }
7520 /*
7521 * Use default ctefx.bin if no alt firmware is detected, or if none
7522 * exists for your particular codec.
7523 */
7524 if (!spec->alt_firmware_present) {
7525 codec_dbg(codec, "Default firmware selected.");
7526 if (request_firmware(&fw_entry, EFX_FILE,
7527 codec->card->dev) != 0)
7528 return false;
7529 }
e90f29e4 7530
15e4ba66 7531 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 7532 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 7533 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 7534 goto exit_download;
7535 }
7536
e90f29e4
IM		 7537 dsp_loaded = dspload_wait_loaded(codec);
7538
d1d28500 7539exit_download:
15e4ba66
TI		 7540 release_firmware(fw_entry);
7541
e90f29e4
IM		 7542 return dsp_loaded;
7543}
7544
7545static void ca0132_download_dsp(struct hda_codec *codec)
7546{
7547 struct ca0132_spec *spec = codec->spec;
7548
9a0869f4
TI		 7549#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7550 return; /* NOP */
7551#endif
e90f29e4 7552
e24aa0a4
TI		 7553 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7554 return; /* don't retry failures */
7555
b714a710 7556 chipio_enable_clocks(codec);
e93ac30a
CM		 7557 if (spec->dsp_state != DSP_DOWNLOADED) {
7558 spec->dsp_state = DSP_DOWNLOADING;
7559
7560 if (!ca0132_download_dsp_images(codec))
7561 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7562 else
7563 spec->dsp_state = DSP_DOWNLOADED;
7564 }
e90f29e4 7565
009b8f97
CM		 7566 /* For codecs using alt functions, this is already done earlier */
7567 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 7568 ca0132_set_dsp_msr(codec, true);
7569}
7570
f8fb1170
TI		 7571static void ca0132_process_dsp_response(struct hda_codec *codec,
7572 struct hda_jack_callback *callback)
e90f29e4
IM		 7573{
7574 struct ca0132_spec *spec = codec->spec;
7575
4e76a883 7576 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 7577 if (spec->wait_scp) {
7578 if (dspio_get_response_data(codec) >= 0)
7579 spec->wait_scp = 0;
7580 }
7581
7582 dspio_clear_response_queue(codec);
7583}
7584
f8fb1170 7585static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 7586{
993884f6 7587 struct ca0132_spec *spec = codec->spec;
2ebab40e 7588 struct hda_jack_tbl *tbl;
e90f29e4 7589
f8fb1170
TI		 7590 /* Delay enabling the HP amp, to let the mic-detection
7591 * state machine run.
7592 */
7593 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 7594 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 7595 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7596 if (tbl)
7597 tbl->block_report = 1;
f8fb1170
TI		 7598}
7599
7600static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7601{
a1b7f016
CM		 7602 struct ca0132_spec *spec = codec->spec;
7603
7604 if (spec->use_alt_functions)
7605 ca0132_alt_select_in(codec);
7606 else
7607 ca0132_select_mic(codec);
f8fb1170
TI		 7608}
7609
7610static void ca0132_init_unsol(struct hda_codec *codec)
7611{
d5c016b5
GM		 7612 struct ca0132_spec *spec = codec->spec;
7613 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7614 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 7615 amic_callback);
7616 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7617 ca0132_process_dsp_response);
63177afc 7618 /* Front headphone jack detection */
009b8f97 7619 if (spec->use_alt_functions)
63177afc
CM		 7620 snd_hda_jack_detect_enable_callback(codec,
7621 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 7622}
7623
5aaca44d
IM		 7624/*
7625 * Verbs tables.
7626 */
7627
7628/* Sends before DSP download. */
7629static struct hda_verb ca0132_base_init_verbs[] = {
7630 /*enable ct extension*/
7631 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 7632 {}
7633};
7634
7635/* Send at exit. */
7636static struct hda_verb ca0132_base_exit_verbs[] = {
7637 /*set afg to D3*/
7638 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7639 /*disable ct extension*/
7640 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7641 {}
7642};
7643
8a19bcee 7644/* Other verbs tables. Sends after DSP download. */
e93ac30a 7645
5aaca44d
IM		 7646static struct hda_verb ca0132_init_verbs0[] = {
7647 /* chip init verbs */
7648 {0x15, 0x70D, 0xF0},
7649 {0x15, 0x70E, 0xFE},
7650 {0x15, 0x707, 0x75},
7651 {0x15, 0x707, 0xD3},
7652 {0x15, 0x707, 0x09},
7653 {0x15, 0x707, 0x53},
7654 {0x15, 0x707, 0xD4},
7655 {0x15, 0x707, 0xEF},
7656 {0x15, 0x707, 0x75},
7657 {0x15, 0x707, 0xD3},
7658 {0x15, 0x707, 0x09},
7659 {0x15, 0x707, 0x02},
7660 {0x15, 0x707, 0x37},
7661 {0x15, 0x707, 0x78},
7662 {0x15, 0x53C, 0xCE},
7663 {0x15, 0x575, 0xC9},
7664 {0x15, 0x53D, 0xCE},
7665 {0x15, 0x5B7, 0xC9},
7666 {0x15, 0x70D, 0xE8},
7667 {0x15, 0x70E, 0xFE},
7668 {0x15, 0x707, 0x02},
7669 {0x15, 0x707, 0x68},
7670 {0x15, 0x707, 0x62},
7671 {0x15, 0x53A, 0xCE},
7672 {0x15, 0x546, 0xC9},
7673 {0x15, 0x53B, 0xCE},
7674 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 7675 {}
7676};
7677
e42c7c73
CM		 7678/* Extra init verbs for desktop cards. */
7679static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 7680 {0x15, 0x70D, 0x20},
7681 {0x15, 0x70E, 0x19},
7682 {0x15, 0x707, 0x00},
7683 {0x15, 0x539, 0xCE},
7684 {0x15, 0x546, 0xC9},
7685 {0x15, 0x70D, 0xB7},
7686 {0x15, 0x70E, 0x09},
7687 {0x15, 0x707, 0x10},
7688 {0x15, 0x70D, 0xAF},
7689 {0x15, 0x70E, 0x09},
7690 {0x15, 0x707, 0x01},
7691 {0x15, 0x707, 0x05},
7692 {0x15, 0x70D, 0x73},
7693 {0x15, 0x70E, 0x09},
7694 {0x15, 0x707, 0x14},
7695 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 7696 {}
7697};
7698
95c6e9cb
IM		 7699static void ca0132_init_chip(struct hda_codec *codec)
7700{
7701 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7702 int num_fx;
7703 int i;
7704 unsigned int on;
95c6e9cb
IM		 7705
7706 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 7707
7708 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 7709 if (!spec->use_alt_functions)
7710 spec->cur_mic_type = DIGITAL_MIC;
7711 else
7712 spec->cur_mic_type = REAR_MIC;
7713
5aaca44d
IM		 7714 spec->cur_mic_boost = 0;
7715
7716 for (i = 0; i < VNODES_COUNT; i++) {
7717 spec->vnode_lvol[i] = 0x5a;
7718 spec->vnode_rvol[i] = 0x5a;
7719 spec->vnode_lswitch[i] = 0;
7720 spec->vnode_rswitch[i] = 0;
7721 }
7722
7723 /*
7724 * Default states for effects are in ca0132_effects[].
7725 */
7726 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7727 for (i = 0; i < num_fx; i++) {
7728 on = (unsigned int)ca0132_effects[i].reqs[0];
7729 spec->effects_switch[i] = on ? 1 : 0;
7730 }
47cdf76e
CM		 7731 /*
7732 * Sets defaults for the effect slider controls, only for alternative
7733 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7734 */
7735 if (spec->use_alt_controls) {
7736 spec->xbass_xover_freq = 8;
7737 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7738 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7739 }
5aaca44d
IM		 7740
7741 spec->voicefx_val = 0;
7742 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7743 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7744
76dea4db
CM		 7745 /*
7746 * The ZxR doesn't have a front panel header, and it's line-in is on
7747 * the daughter board. So, there is no input enum control, and we need
7748 * to make sure that spec->in_enum_val is set properly.
7749 */
7750 if (spec->quirk == QUIRK_ZXR)
7751 spec->in_enum_val = REAR_MIC;
7752
44f0c978
IM		 7753#ifdef ENABLE_TUNING_CONTROLS
7754 ca0132_init_tuning_defaults(codec);
7755#endif
95c6e9cb
IM		 7756}
7757
2e48b2b7
CM		 7758/*
7759 * Recon3Di exit specific commands.
7760 */
7761/* prevents popping noise on shutdown */
7762static void r3di_gpio_shutdown(struct hda_codec *codec)
7763{
7764 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7765}
7766
7767/*
7768 * Sound Blaster Z exit specific commands.
7769 */
7770static void sbz_region2_exit(struct hda_codec *codec)
7771{
7772 struct ca0132_spec *spec = codec->spec;
7773 unsigned int i;
7774
7775 for (i = 0; i < 4; i++)
7776 writeb(0x0, spec->mem_base + 0x100);
7777 for (i = 0; i < 8; i++)
7778 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7779
b9b41345
CM		 7780 ca0113_mmio_gpio_set(codec, 0, false);
7781 ca0113_mmio_gpio_set(codec, 1, false);
7782 ca0113_mmio_gpio_set(codec, 4, true);
7783 ca0113_mmio_gpio_set(codec, 5, false);
7784 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7785}
7786
7787static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7788{
7789 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7790 unsigned int i;
7791
7792 snd_hda_codec_write(codec, 0x11, 0,
7793 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7794
7795 for (i = 0; i < 5; i++)
7796 snd_hda_codec_write(codec, pins[i], 0,
7797 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7798}
7799
2f295f91 7800static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7801{
7802 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7803 unsigned int i;
7804
7805 for (i = 0; i < 7; i++) {
7806 snd_hda_codec_write(codec, pins[i], 0,
7807 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7808 }
7809}
7810
7811/* On shutdown, sends commands in sets of three */
7812static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7813 int mask, int data)
7814{
7815 if (dir >= 0)
7816 snd_hda_codec_write(codec, 0x01, 0,
7817 AC_VERB_SET_GPIO_DIRECTION, dir);
7818 if (mask >= 0)
7819 snd_hda_codec_write(codec, 0x01, 0,
7820 AC_VERB_SET_GPIO_MASK, mask);
7821
7822 if (data >= 0)
7823 snd_hda_codec_write(codec, 0x01, 0,
7824 AC_VERB_SET_GPIO_DATA, data);
7825}
7826
7675a2a9
CM		 7827static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
7828{
7829 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
7830 unsigned int i;
7831
7832 for (i = 0; i < 7; i++)
7833 snd_hda_codec_write(codec, pins[i], 0,
7834 AC_VERB_SET_POWER_STATE, 0x03);
7835}
7836
2e48b2b7
CM		 7837static void sbz_exit_chip(struct hda_codec *codec)
7838{
009b8f97
CM		 7839 chipio_set_stream_control(codec, 0x03, 0);
7840 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7841
7842 /* Mess with GPIO */
7843 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7844 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7845 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7846
009b8f97
CM		 7847 chipio_set_stream_control(codec, 0x14, 0);
7848 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7849
7850 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7851 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7852
7853 chipio_write(codec, 0x18a020, 0x00000083);
7854
7855 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7856 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7857 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7858
009b8f97 7859 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7860
7861 chipio_set_control_param(codec, 0x0D, 0x24);
7862
2f295f91 7863 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7864 sbz_set_pin_ctl_default(codec);
7865
7866 snd_hda_codec_write(codec, 0x0B, 0,
7867 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7868
2e48b2b7
CM		 7869 sbz_region2_exit(codec);
7870}
7871
2f295f91
CM		 7872static void r3d_exit_chip(struct hda_codec *codec)
7873{
7874 ca0132_clear_unsolicited(codec);
7875 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7876 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7877}
7878
edb1b3ab
CM		 7879static void ae5_exit_chip(struct hda_codec *codec)
7880{
7881 chipio_set_stream_control(codec, 0x03, 0);
7882 chipio_set_stream_control(codec, 0x04, 0);
7883
7884 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7885 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7886 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7887 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7888 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7889 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
7890 ca0113_mmio_gpio_set(codec, 0, false);
7891 ca0113_mmio_gpio_set(codec, 1, false);
7892
7893 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7894 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7895
7896 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7897
7898 chipio_set_stream_control(codec, 0x18, 0);
7899 chipio_set_stream_control(codec, 0x0c, 0);
7900
7901 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
7902}
7903
96395e86
CM		 7904static void zxr_exit_chip(struct hda_codec *codec)
7905{
7906 chipio_set_stream_control(codec, 0x03, 0);
7907 chipio_set_stream_control(codec, 0x04, 0);
7908 chipio_set_stream_control(codec, 0x14, 0);
7909 chipio_set_stream_control(codec, 0x0C, 0);
7910
7911 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7912 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7913
7914 chipio_write(codec, 0x18a020, 0x00000083);
7915
7916 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7917 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7918
7919 ca0132_clear_unsolicited(codec);
7920 sbz_set_pin_ctl_default(codec);
7921 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7922
7923 ca0113_mmio_gpio_set(codec, 5, false);
7924 ca0113_mmio_gpio_set(codec, 2, false);
7925 ca0113_mmio_gpio_set(codec, 3, false);
7926 ca0113_mmio_gpio_set(codec, 0, false);
7927 ca0113_mmio_gpio_set(codec, 4, true);
7928 ca0113_mmio_gpio_set(codec, 0, true);
7929 ca0113_mmio_gpio_set(codec, 5, true);
7930 ca0113_mmio_gpio_set(codec, 2, false);
7931 ca0113_mmio_gpio_set(codec, 3, false);
7932}
7933
95c6e9cb
IM		 7934static void ca0132_exit_chip(struct hda_codec *codec)
7935{
7936 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7937
7938 if (dspload_is_loaded(codec))
7939 dsp_reset(codec);
95c6e9cb
IM		 7940}
7941
38ba69ff
CM		 7942/*
7943 * This fixes a problem that was hard to reproduce. Very rarely, I would
7944 * boot up, and there would be no sound, but the DSP indicated it had loaded
7945 * properly. I did a few memory dumps to see if anything was different, and
7946 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7947 * checks if those areas are uninitialized, and if they are, it'll attempt to
7948 * reload the card 3 times. Usually it fixes by the second.
7949 */
7950static void sbz_dsp_startup_check(struct hda_codec *codec)
7951{
7952 struct ca0132_spec *spec = codec->spec;
7953 unsigned int dsp_data_check[4];
7954 unsigned int cur_address = 0x390;
7955 unsigned int i;
7956 unsigned int failure = 0;
7957 unsigned int reload = 3;
7958
7959 if (spec->startup_check_entered)
7960 return;
7961
7962 spec->startup_check_entered = true;
7963
7964 for (i = 0; i < 4; i++) {
7965 chipio_read(codec, cur_address, &dsp_data_check[i]);
7966 cur_address += 0x4;
7967 }
7968 for (i = 0; i < 4; i++) {
7969 if (dsp_data_check[i] == 0xa1a2a3a4)
7970 failure = 1;
7971 }
7972
7973 codec_dbg(codec, "Startup Check: %d ", failure);
7974 if (failure)
7975 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7976 /*
7977 * While the failure condition is true, and we haven't reached our
7978 * three reload limit, continue trying to reload the driver and
7979 * fix the issue.
7980 */
7981 while (failure && (reload != 0)) {
7982 codec_info(codec, "Reloading... Tries left: %d", reload);
7983 sbz_exit_chip(codec);
7984 spec->dsp_state = DSP_DOWNLOAD_INIT;
7985 codec->patch_ops.init(codec);
7986 failure = 0;
7987 for (i = 0; i < 4; i++) {
7988 chipio_read(codec, cur_address, &dsp_data_check[i]);
7989 cur_address += 0x4;
7990 }
7991 for (i = 0; i < 4; i++) {
7992 if (dsp_data_check[i] == 0xa1a2a3a4)
7993 failure = 1;
7994 }
7995 reload--;
7996 }
7997
7998 if (!failure && reload < 3)
7999 codec_info(codec, "DSP fixed.");
8000
8001 if (!failure)
8002 return;
8003
8004 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8005}
8006
e93ac30a
CM		 8007/*
8008 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8009 * extra precision for decibel values. If you had the dB value in floating point
8010 * you would take the value after the decimal point, multiply by 64, and divide
8011 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8012 * implement fixed point or floating point dB volumes. For now, I'll set them
8013 * to 0 just incase a value has lingered from a boot into Windows.
8014 */
8015static void ca0132_alt_vol_setup(struct hda_codec *codec)
8016{
8017 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8018 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8019 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8020 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8021 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8022 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8023 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8024 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8025}
8026
8027/*
8028 * Extra commands that don't really fit anywhere else.
8029 */
8030static void sbz_pre_dsp_setup(struct hda_codec *codec)
8031{
8032 struct ca0132_spec *spec = codec->spec;
8033
8034 writel(0x00820680, spec->mem_base + 0x01C);
8035 writel(0x00820680, spec->mem_base + 0x01C);
8036
e93ac30a
CM		 8037 chipio_write(codec, 0x18b0a4, 0x000000c2);
8038
8039 snd_hda_codec_write(codec, 0x11, 0,
8040 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8041}
8042
e42c7c73
CM		 8043static void r3d_pre_dsp_setup(struct hda_codec *codec)
8044{
e42c7c73
CM		 8045 chipio_write(codec, 0x18b0a4, 0x000000c2);
8046
8047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8048 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8050 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8051 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8052 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8053
8054 snd_hda_codec_write(codec, 0x11, 0,
8055 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8056}
8057
e93ac30a
CM		 8058static void r3di_pre_dsp_setup(struct hda_codec *codec)
8059{
8060 chipio_write(codec, 0x18b0a4, 0x000000c2);
8061
8062 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8063 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8064 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8065 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8066 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8067 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8068
8069 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8070 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
8071 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8072 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
8073 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8074 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
8075 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8076 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
8077
8078 snd_hda_codec_write(codec, 0x11, 0,
8079 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
8080}
8081
e93ac30a
CM		 8082/*
8083 * These are sent before the DSP is downloaded. Not sure
8084 * what they do, or if they're necessary. Could possibly
8085 * be removed. Figure they're better to leave in.
8086 */
e42c7c73 8087static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 8088{
8089 struct ca0132_spec *spec = codec->spec;
8090
ce715448
CM		 8091 if (spec->quirk == QUIRK_AE5)
8092 writel(0x00000001, spec->mem_base + 0x400);
8093 else
8094 writel(0x00000000, spec->mem_base + 0x400);
8095
8096 if (spec->quirk == QUIRK_AE5)
8097 writel(0x00000001, spec->mem_base + 0x408);
8098 else
8099 writel(0x00000000, spec->mem_base + 0x408);
8100
8101 if (spec->quirk == QUIRK_AE5)
8102 writel(0x00000001, spec->mem_base + 0x40c);
8103 else
8104 writel(0x00000000, spec->mem_base + 0x40C);
8105
2e492b8e
CM		 8106 if (spec->quirk == QUIRK_ZXR)
8107 writel(0x00880640, spec->mem_base + 0x01C);
8108 else
8109 writel(0x00880680, spec->mem_base + 0x01C);
ce715448
CM		 8110
8111 if (spec->quirk == QUIRK_AE5)
8112 writel(0x00000080, spec->mem_base + 0xC0C);
8113 else
8114 writel(0x00000083, spec->mem_base + 0xC0C);
8115
e93ac30a
CM		 8116 writel(0x00000030, spec->mem_base + 0xC00);
8117 writel(0x00000000, spec->mem_base + 0xC04);
ce715448
CM		 8118
8119 if (spec->quirk == QUIRK_AE5)
8120 writel(0x00000000, spec->mem_base + 0xC0C);
8121 else
8122 writel(0x00000003, spec->mem_base + 0xC0C);
8123
e93ac30a
CM		 8124 writel(0x00000003, spec->mem_base + 0xC0C);
8125 writel(0x00000003, spec->mem_base + 0xC0C);
8126 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448
CM		 8127
8128 if (spec->quirk == QUIRK_AE5)
8129 writel(0x00000001, spec->mem_base + 0xC08);
8130 else
8131 writel(0x000000C1, spec->mem_base + 0xC08);
8132
e93ac30a
CM		 8133 writel(0x000000F1, spec->mem_base + 0xC08);
8134 writel(0x00000001, spec->mem_base + 0xC08);
8135 writel(0x000000C7, spec->mem_base + 0xC08);
8136 writel(0x000000C1, spec->mem_base + 0xC08);
8137 writel(0x00000080, spec->mem_base + 0xC04);
ce715448
CM		 8138
8139 if (spec->quirk == QUIRK_AE5) {
8140 writel(0x00000000, spec->mem_base + 0x42c);
8141 writel(0x00000000, spec->mem_base + 0x46c);
8142 writel(0x00000000, spec->mem_base + 0x4ac);
8143 writel(0x00000000, spec->mem_base + 0x4ec);
8144 writel(0x00000000, spec->mem_base + 0x43c);
8145 writel(0x00000000, spec->mem_base + 0x47c);
8146 writel(0x00000000, spec->mem_base + 0x4bc);
8147 writel(0x00000000, spec->mem_base + 0x4fc);
8148 writel(0x00000600, spec->mem_base + 0x100);
8149 writel(0x00000014, spec->mem_base + 0x410);
8150 writel(0x0000060f, spec->mem_base + 0x100);
8151 writel(0x0000070f, spec->mem_base + 0x100);
8152 writel(0x00000aff, spec->mem_base + 0x830);
8153 writel(0x00000000, spec->mem_base + 0x86c);
8154 writel(0x0000006b, spec->mem_base + 0x800);
8155 writel(0x00000001, spec->mem_base + 0x86c);
8156 writel(0x0000006b, spec->mem_base + 0x800);
8157 writel(0x00000057, spec->mem_base + 0x804);
8158 writel(0x00800000, spec->mem_base + 0x20c);
8159 }
e93ac30a
CM		 8160}
8161
b9b41345
CM		 8162/*
8163 * This function writes to some SFR's, does some region2 writes, and then
8164 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
8165 * what it does.
8166 */
8167static void ae5_register_set(struct hda_codec *codec)
8168{
8169 struct ca0132_spec *spec = codec->spec;
8170
8171 chipio_8051_write_direct(codec, 0x93, 0x10);
8172 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8173 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8174 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8175 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8176
8177 writeb(0x0f, spec->mem_base + 0x304);
8178 writeb(0x0f, spec->mem_base + 0x304);
8179 writeb(0x0f, spec->mem_base + 0x304);
8180 writeb(0x0f, spec->mem_base + 0x304);
8181 writeb(0x0e, spec->mem_base + 0x100);
8182 writeb(0x1f, spec->mem_base + 0x304);
8183 writeb(0x0c, spec->mem_base + 0x100);
8184 writeb(0x3f, spec->mem_base + 0x304);
8185 writeb(0x08, spec->mem_base + 0x100);
8186 writeb(0x7f, spec->mem_base + 0x304);
8187 writeb(0x00, spec->mem_base + 0x100);
8188 writeb(0xff, spec->mem_base + 0x304);
8189
8190 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
8191
8192 chipio_8051_write_direct(codec, 0x90, 0x00);
8193 chipio_8051_write_direct(codec, 0x90, 0x10);
8194
8195 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8196
8197 chipio_write(codec, 0x18b0a4, 0x000000c2);
8198
8199 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8200 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8201}
8202
e93ac30a
CM		 8203/*
8204 * Extra init functions for alternative ca0132 codecs. Done
8205 * here so they don't clutter up the main ca0132_init function
8206 * anymore than they have to.
8207 */
8208static void ca0132_alt_init(struct hda_codec *codec)
8209{
8210 struct ca0132_spec *spec = codec->spec;
8211
8212 ca0132_alt_vol_setup(codec);
8213
8214 switch (spec->quirk) {
8215 case QUIRK_SBZ:
8216 codec_dbg(codec, "SBZ alt_init");
8217 ca0132_gpio_init(codec);
8218 sbz_pre_dsp_setup(codec);
8219 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 8220 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 8221 break;
8222 case QUIRK_R3DI:
8223 codec_dbg(codec, "R3DI alt_init");
8224 ca0132_gpio_init(codec);
8225 ca0132_gpio_setup(codec);
7e6ed62e 8226 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 8227 r3di_pre_dsp_setup(codec);
8228 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8229 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
8230 break;
e42c7c73
CM		 8231 case QUIRK_R3D:
8232 r3d_pre_dsp_setup(codec);
8233 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8234 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8235 break;
03c9b6b1
CM		 8236 case QUIRK_AE5:
8237 ca0132_gpio_init(codec);
8238 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8239 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
8240 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8241 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
8242 chipio_write(codec, 0x18b030, 0x00000020);
8243 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8244 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8245 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8246 break;
2e492b8e
CM		 8247 case QUIRK_ZXR:
8248 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8249 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8250 break;
e93ac30a
CM		 8251 }
8252}
8253
95c6e9cb
IM		 8254static int ca0132_init(struct hda_codec *codec)
8255{
8256 struct ca0132_spec *spec = codec->spec;
8257 struct auto_pin_cfg *cfg = &spec->autocfg;
8258 int i;
e93ac30a
CM		 8259 bool dsp_loaded;
8260
8261 /*
8262 * If the DSP is already downloaded, and init has been entered again,
8263 * there's only two reasons for it. One, the codec has awaken from a
8264 * suspended state, and in that case dspload_is_loaded will return
8265 * false, and the init will be ran again. The other reason it gets
8266 * re entered is on startup for some reason it triggers a suspend and
8267 * resume state. In this case, it will check if the DSP is downloaded,
8268 * and not run the init function again. For codecs using alt_functions,
8269 * it will check if the DSP is loaded properly.
8270 */
8271 if (spec->dsp_state == DSP_DOWNLOADED) {
8272 dsp_loaded = dspload_is_loaded(codec);
8273 if (!dsp_loaded) {
8274 spec->dsp_reload = true;
8275 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 8276 } else {
8277 if (spec->quirk == QUIRK_SBZ)
8278 sbz_dsp_startup_check(codec);
e93ac30a 8279 return 0;
38ba69ff 8280 }
e93ac30a 8281 }
95c6e9cb 8282
e24aa0a4
TI		 8283 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8284 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 8285 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 8286
e42c7c73
CM		 8287 if (spec->use_pci_mmio)
8288 ca0132_mmio_init(codec);
e93ac30a 8289
664c7155 8290 snd_hda_power_up_pm(codec);
5aaca44d 8291
b9b41345
CM		 8292 if (spec->quirk == QUIRK_AE5)
8293 ae5_register_set(codec);
8294
f8fb1170 8295 ca0132_init_unsol(codec);
5aaca44d
IM		 8296 ca0132_init_params(codec);
8297 ca0132_init_flags(codec);
7e6ed62e 8298
5aaca44d 8299 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 8300
365c7f25 8301 if (spec->use_alt_functions)
e93ac30a
CM		 8302 ca0132_alt_init(codec);
8303
01ef7dbf 8304 ca0132_download_dsp(codec);
7e6ed62e 8305
5aaca44d 8306 ca0132_refresh_widget_caps(codec);
e93ac30a 8307
7e6ed62e
CM		 8308 switch (spec->quirk) {
8309 case QUIRK_R3DI:
c986f50c
CM		 8310 case QUIRK_R3D:
8311 r3d_setup_defaults(codec);
7e6ed62e 8312 break;
126b75e0 8313 case QUIRK_SBZ:
c25c73e0 8314 case QUIRK_ZXR:
d97420d2 8315 sbz_setup_defaults(codec);
126b75e0 8316 break;
415cd844
CM		 8317 case QUIRK_AE5:
8318 ae5_setup_defaults(codec);
8319 break;
126b75e0 8320 default:
38ba69ff
CM		 8321 ca0132_setup_defaults(codec);
8322 ca0132_init_analog_mic2(codec);
8323 ca0132_init_dmic(codec);
7e6ed62e 8324 break;
38ba69ff 8325 }
5aaca44d
IM		 8326
8327 for (i = 0; i < spec->num_outputs; i++)
8328 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 8329
95c6e9cb
IM		 8330 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8331
8332 for (i = 0; i < spec->num_inputs; i++)
8333 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8334
8335 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8336
009b8f97 8337 if (!spec->use_alt_functions) {
e93ac30a
CM		 8338 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8339 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8340 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8341 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8342 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8343 }
8344
7cb9d94c 8345 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 8346 ca0132_gpio_setup(codec);
8347
d5c016b5 8348 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 8349 if (spec->use_alt_functions) {
7cb9d94c
CM		 8350 ca0132_alt_select_out(codec);
8351 ca0132_alt_select_in(codec);
d97420d2 8352 } else {
7cb9d94c
CM		 8353 ca0132_select_out(codec);
8354 ca0132_select_mic(codec);
7cb9d94c 8355 }
5aaca44d 8356
a73d511c
IM		 8357 snd_hda_jack_report_sync(codec);
8358
e93ac30a
CM		 8359 /*
8360 * Re set the PlayEnhancement switch on a resume event, because the
8361 * controls will not be reloaded.
8362 */
8363 if (spec->dsp_reload) {
8364 spec->dsp_reload = false;
8365 ca0132_pe_switch_set(codec);
8366 }
8367
664c7155 8368 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 8369
8370 return 0;
8371}
8372
7675a2a9
CM		 8373static int dbpro_init(struct hda_codec *codec)
8374{
8375 struct ca0132_spec *spec = codec->spec;
8376 struct auto_pin_cfg *cfg = &spec->autocfg;
8377 unsigned int i;
8378
8379 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8380 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8381
8382 for (i = 0; i < spec->num_inputs; i++)
8383 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8384
8385 return 0;
8386}
8387
95c6e9cb
IM		 8388static void ca0132_free(struct hda_codec *codec)
8389{
5aaca44d
IM		 8390 struct ca0132_spec *spec = codec->spec;
8391
993884f6 8392 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 8393 snd_hda_power_up(codec);
2e48b2b7
CM		 8394 switch (spec->quirk) {
8395 case QUIRK_SBZ:
8396 sbz_exit_chip(codec);
8397 break;
96395e86
CM		 8398 case QUIRK_ZXR:
8399 zxr_exit_chip(codec);
8400 break;
2f295f91
CM		 8401 case QUIRK_R3D:
8402 r3d_exit_chip(codec);
8403 break;
edb1b3ab
CM		 8404 case QUIRK_AE5:
8405 ae5_exit_chip(codec);
8406 break;
2e48b2b7
CM		 8407 case QUIRK_R3DI:
8408 r3di_gpio_shutdown(codec);
2e48b2b7
CM		 8409 break;
8410 }
2f295f91
CM		 8411
8412 snd_hda_sequence_write(codec, spec->base_exit_verbs);
8413 ca0132_exit_chip(codec);
8414
5aaca44d 8415 snd_hda_power_down(codec);
aa31704f 8416 if (spec->mem_base)
d99501b8 8417 pci_iounmap(codec->bus->pci, spec->mem_base);
d5c016b5 8418 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 8419 kfree(codec->spec);
8420}
8421
7675a2a9
CM		 8422static void dbpro_free(struct hda_codec *codec)
8423{
8424 struct ca0132_spec *spec = codec->spec;
8425
8426 zxr_dbpro_power_state_shutdown(codec);
8427
8428 kfree(spec->spec_init_verbs);
8429 kfree(codec->spec);
8430}
8431
2e48b2b7
CM		 8432static void ca0132_reboot_notify(struct hda_codec *codec)
8433{
8434 codec->patch_ops.free(codec);
8435}
8436
071f1344 8437static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 8438 .build_controls = ca0132_build_controls,
8439 .build_pcms = ca0132_build_pcms,
8440 .init = ca0132_init,
8441 .free = ca0132_free,
f8fb1170 8442 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 8443 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 8444};
8445
7675a2a9
CM		 8446static const struct hda_codec_ops dbpro_patch_ops = {
8447 .build_controls = dbpro_build_controls,
8448 .build_pcms = dbpro_build_pcms,
8449 .init = dbpro_init,
8450 .free = dbpro_free,
8451};
8452
441aa6a0
IM		 8453static void ca0132_config(struct hda_codec *codec)
8454{
8455 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 8456
8457 spec->dacs[0] = 0x2;
8458 spec->dacs[1] = 0x3;
8459 spec->dacs[2] = 0x4;
8460
8461 spec->multiout.dac_nids = spec->dacs;
8462 spec->multiout.num_dacs = 3;
441aa6a0 8463
009b8f97 8464 if (!spec->use_alt_functions)
63177afc
CM		 8465 spec->multiout.max_channels = 2;
8466 else
8467 spec->multiout.max_channels = 6;
8468
8469 switch (spec->quirk) {
8470 case QUIRK_ALIENWARE:
d06feaf0 8471 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 8472 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 8473 break;
8474 case QUIRK_SBZ:
8475 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8476 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8477 break;
6dcd7244
CM		 8478 case QUIRK_ZXR:
8479 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
8480 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
8481 break;
d06feaf0
CM		 8482 case QUIRK_R3D:
8483 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8484 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8485 break;
8486 case QUIRK_R3DI:
8487 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8488 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8489 break;
8490 case QUIRK_AE5:
8491 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
a6b0961b 8492 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
d06feaf0
CM		 8493 break;
8494 }
fe14f39e 8495
d06feaf0
CM		 8496 switch (spec->quirk) {
8497 case QUIRK_ALIENWARE:
fe14f39e
TI		 8498 spec->num_outputs = 2;
8499 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8500 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 8501 spec->shared_out_nid = 0x2;
8502 spec->unsol_tag_hp = 0x0f;
8503
8504 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8505 spec->adcs[1] = 0x8; /* analog mic2 */
8506 spec->adcs[2] = 0xa; /* what u hear */
8507
8508 spec->num_inputs = 3;
8509 spec->input_pins[0] = 0x12;
8510 spec->input_pins[1] = 0x11;
8511 spec->input_pins[2] = 0x13;
8512 spec->shared_mic_nid = 0x7;
8513 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 8514 break;
8515 case QUIRK_SBZ:
7f73df95 8516 case QUIRK_R3D:
63177afc
CM		 8517 spec->num_outputs = 2;
8518 spec->out_pins[0] = 0x0B; /* Line out */
8519 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8520 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8521 spec->out_pins[3] = 0x11; /* Rear surround */
8522 spec->shared_out_nid = 0x2;
8523 spec->unsol_tag_hp = spec->out_pins[1];
8524 spec->unsol_tag_front_hp = spec->out_pins[2];
8525
8526 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8527 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8528 spec->adcs[2] = 0xa; /* what u hear */
8529
8530 spec->num_inputs = 2;
8531 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8532 spec->input_pins[1] = 0x13; /* What U Hear */
8533 spec->shared_mic_nid = 0x7;
8534 spec->unsol_tag_amic1 = spec->input_pins[0];
8535
8536 /* SPDIF I/O */
8537 spec->dig_out = 0x05;
8538 spec->multiout.dig_out_nid = spec->dig_out;
6dcd7244
CM		 8539 spec->dig_in = 0x09;
8540 break;
8541 case QUIRK_ZXR:
8542 spec->num_outputs = 2;
8543 spec->out_pins[0] = 0x0B; /* Line out */
8544 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8545 spec->out_pins[2] = 0x10; /* Center/LFE */
8546 spec->out_pins[3] = 0x11; /* Rear surround */
8547 spec->shared_out_nid = 0x2;
8548 spec->unsol_tag_hp = spec->out_pins[1];
8549 spec->unsol_tag_front_hp = spec->out_pins[2];
8550
8551 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8552 spec->adcs[1] = 0x8; /* Not connected, no front mic */
8553 spec->adcs[2] = 0xa; /* what u hear */
8554
8555 spec->num_inputs = 2;
8556 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8557 spec->input_pins[1] = 0x13; /* What U Hear */
8558 spec->shared_mic_nid = 0x7;
8559 spec->unsol_tag_amic1 = spec->input_pins[0];
8560 break;
8561 case QUIRK_ZXR_DBPRO:
8562 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
8563
8564 spec->num_inputs = 1;
8565 spec->input_pins[0] = 0x11; /* RCA Line-in */
8566
8567 spec->dig_out = 0x05;
8568 spec->multiout.dig_out_nid = spec->dig_out;
8569
63177afc 8570 spec->dig_in = 0x09;
63177afc 8571 break;
d06feaf0
CM		 8572 case QUIRK_AE5:
8573 spec->num_outputs = 2;
8574 spec->out_pins[0] = 0x0B; /* Line out */
8575 spec->out_pins[1] = 0x11; /* Rear headphone out */
8576 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8577 spec->out_pins[3] = 0x0F; /* Rear surround */
8578 spec->shared_out_nid = 0x2;
8579 spec->unsol_tag_hp = spec->out_pins[1];
8580 spec->unsol_tag_front_hp = spec->out_pins[2];
8581
8582 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8583 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8584 spec->adcs[2] = 0xa; /* what u hear */
63177afc 8585
d06feaf0
CM		 8586 spec->num_inputs = 2;
8587 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8588 spec->input_pins[1] = 0x13; /* What U Hear */
8589 spec->shared_mic_nid = 0x7;
8590 spec->unsol_tag_amic1 = spec->input_pins[0];
8591
8592 /* SPDIF I/O */
8593 spec->dig_out = 0x05;
8594 spec->multiout.dig_out_nid = spec->dig_out;
8595 break;
8596 case QUIRK_R3DI:
63177afc
CM		 8597 spec->num_outputs = 2;
8598 spec->out_pins[0] = 0x0B; /* Line out */
8599 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8600 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8601 spec->out_pins[3] = 0x11; /* Rear surround */
8602 spec->shared_out_nid = 0x2;
8603 spec->unsol_tag_hp = spec->out_pins[1];
8604 spec->unsol_tag_front_hp = spec->out_pins[2];
8605
8606 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8607 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8608 spec->adcs[2] = 0x0a; /* what u hear */
8609
8610 spec->num_inputs = 2;
8611 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8612 spec->input_pins[1] = 0x13; /* What U Hear */
8613 spec->shared_mic_nid = 0x7;
8614 spec->unsol_tag_amic1 = spec->input_pins[0];
8615
8616 /* SPDIF I/O */
8617 spec->dig_out = 0x05;
8618 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 8619 break;
8620 default:
fe14f39e
TI		 8621 spec->num_outputs = 2;
8622 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8623 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 8624 spec->shared_out_nid = 0x2;
8625 spec->unsol_tag_hp = spec->out_pins[1];
8626
8627 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8628 spec->adcs[1] = 0x8; /* analog mic2 */
8629 spec->adcs[2] = 0xa; /* what u hear */
8630
8631 spec->num_inputs = 3;
8632 spec->input_pins[0] = 0x12;
8633 spec->input_pins[1] = 0x11;
8634 spec->input_pins[2] = 0x13;
8635 spec->shared_mic_nid = 0x7;
8636 spec->unsol_tag_amic1 = spec->input_pins[0];
8637
8638 /* SPDIF I/O */
8639 spec->dig_out = 0x05;
8640 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 8641 spec->dig_in = 0x09;
63177afc 8642 break;
d5c016b5 8643 }
441aa6a0
IM		 8644}
8645
d5c016b5
GM		 8646static int ca0132_prepare_verbs(struct hda_codec *codec)
8647{
8648/* Verbs + terminator (an empty element) */
a3d90d67 8649#define NUM_SPEC_VERBS 2
d5c016b5
GM		 8650 struct ca0132_spec *spec = codec->spec;
8651
8652 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 8653 /*
8654 * Since desktop cards use pci_mmio, this can be used to determine
8655 * whether or not to use these verbs instead of a separate bool.
8656 */
8657 if (spec->use_pci_mmio)
e42c7c73 8658 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 8659 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8660 sizeof(struct hda_verb),
8661 GFP_KERNEL);
d5c016b5
GM		 8662 if (!spec->spec_init_verbs)
8663 return -ENOMEM;
8664
d5c016b5 8665 /* config EAPD */
a3d90d67
AB		 8666 spec->spec_init_verbs[0].nid = 0x0b;
8667 spec->spec_init_verbs[0].param = 0x78D;
8668 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 8669
8670 /* Previously commented configuration */
8671 /*
a3d90d67
AB		 8672 spec->spec_init_verbs[2].nid = 0x0b;
8673 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8674 spec->spec_init_verbs[2].verb = 0x02;
8675
8676 spec->spec_init_verbs[3].nid = 0x10;
8677 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 8678 spec->spec_init_verbs[3].verb = 0x02;
8679
8680 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 8681 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 8682 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 8683 */
8684
8685 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8686 return 0;
8687}
8688
b29733db
CM		 8689/*
8690 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
8691 * Sound Blaster Z cards. However, they have different HDA codec subsystem
8692 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
8693 * daughter boards ID.
8694 */
8695static void sbz_detect_quirk(struct hda_codec *codec)
8696{
8697 struct ca0132_spec *spec = codec->spec;
8698
8699 switch (codec->core.subsystem_id) {
8700 case 0x11020033:
8701 spec->quirk = QUIRK_ZXR;
8702 break;
8703 case 0x1102003f:
8704 spec->quirk = QUIRK_ZXR_DBPRO;
8705 break;
8706 default:
8707 spec->quirk = QUIRK_SBZ;
8708 break;
8709 }
8710}
8711
95c6e9cb
IM		 8712static int patch_ca0132(struct hda_codec *codec)
8713{
8714 struct ca0132_spec *spec;
a73d511c 8715 int err;
d5c016b5 8716 const struct snd_pci_quirk *quirk;
95c6e9cb 8717
4e76a883 8718 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 8719
8720 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8721 if (!spec)
8722 return -ENOMEM;
8723 codec->spec = spec;
993884f6 8724 spec->codec = codec;
95c6e9cb 8725
d5c016b5
GM		 8726 /* Detect codec quirk */
8727 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8728 if (quirk)
8729 spec->quirk = quirk->value;
8730 else
8731 spec->quirk = QUIRK_NONE;
8732
b29733db
CM		 8733 if (spec->quirk == QUIRK_SBZ)
8734 sbz_detect_quirk(codec);
8735
ebabde1e
CM		 8736 if (spec->quirk == QUIRK_ZXR_DBPRO)
8737 codec->patch_ops = dbpro_patch_ops;
8738 else
8739 codec->patch_ops = ca0132_patch_ops;
8740
8741 codec->pcm_format_first = 1;
8742 codec->no_sticky_stream = 1;
8743
8744
e24aa0a4 8745 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 8746 spec->num_mixers = 1;
017310fb
CM		 8747
8748 /* Set which mixers each quirk uses. */
8749 switch (spec->quirk) {
8750 case QUIRK_SBZ:
e25e3445 8751 spec->mixers[0] = desktop_mixer;
017310fb
CM		 8752 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8753 break;
2e492b8e
CM		 8754 case QUIRK_ZXR:
8755 spec->mixers[0] = desktop_mixer;
8756 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
8757 break;
7675a2a9 8758 case QUIRK_ZXR_DBPRO:
7675a2a9 8759 break;
e25e3445
CM		 8760 case QUIRK_R3D:
8761 spec->mixers[0] = desktop_mixer;
8762 snd_hda_codec_set_name(codec, "Recon3D");
8763 break;
017310fb
CM		 8764 case QUIRK_R3DI:
8765 spec->mixers[0] = r3di_mixer;
8766 snd_hda_codec_set_name(codec, "Recon3Di");
8767 break;
88268ce8
CM		 8768 case QUIRK_AE5:
8769 spec->mixers[0] = desktop_mixer;
8770 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8771 break;
017310fb
CM		 8772 default:
8773 spec->mixers[0] = ca0132_mixer;
8774 break;
8775 }
a7e76271 8776
08eca6b1 8777 /* Setup whether or not to use alt functions/controls/pci_mmio */
009b8f97
CM		 8778 switch (spec->quirk) {
8779 case QUIRK_SBZ:
e42c7c73 8780 case QUIRK_R3D:
88268ce8 8781 case QUIRK_AE5:
2e492b8e 8782 case QUIRK_ZXR:
08eca6b1
CM		 8783 spec->use_alt_controls = true;
8784 spec->use_alt_functions = true;
8785 spec->use_pci_mmio = true;
8786 break;
009b8f97 8787 case QUIRK_R3DI:
47cdf76e 8788 spec->use_alt_controls = true;
009b8f97 8789 spec->use_alt_functions = true;
08eca6b1 8790 spec->use_pci_mmio = false;
009b8f97
CM		 8791 break;
8792 default:
47cdf76e 8793 spec->use_alt_controls = false;
009b8f97 8794 spec->use_alt_functions = false;
08eca6b1 8795 spec->use_pci_mmio = false;
009b8f97
CM		 8796 break;
8797 }
8798
08eca6b1
CM		 8799 if (spec->use_pci_mmio) {
8800 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8801 if (spec->mem_base == NULL) {
8802 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8803 spec->quirk = QUIRK_NONE;
8804 }
8805 }
8806
5aaca44d
IM		 8807 spec->base_init_verbs = ca0132_base_init_verbs;
8808 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 8809
993884f6
CCC		 8810 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8811
95c6e9cb
IM		 8812 ca0132_init_chip(codec);
8813
8814 ca0132_config(codec);
8815
d5c016b5
GM		 8816 err = ca0132_prepare_verbs(codec);
8817 if (err < 0)
cc91ceaf 8818 goto error;
d5c016b5 8819
a73d511c
IM		 8820 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8821 if (err < 0)
cc91ceaf 8822 goto error;
a73d511c 8823
95c6e9cb 8824 return 0;
cc91ceaf
TI		 8825
8826 error:
8827 ca0132_free(codec);
8828 return err;
95c6e9cb
IM		 8829}
8830
8831/*
8832 * patch entries
8833 */
b9a94a9c
TI		 8834static struct hda_device_id snd_hda_id_ca0132[] = {
8835 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 8836 {} /* terminator */
8837};
b9a94a9c 8838MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 8839
8840MODULE_LICENSE("GPL");
406261ce 8841MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 8842
d8a766a1 8843static struct hda_codec_driver ca0132_driver = {
b9a94a9c 8844 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 8845};
8846
d8a766a1 8847module_hda_codec_driver(ca0132_driver);
Empty description
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