[linux.git] / drivers / usb / dwc3 / dwc3-pci.c

// SPDX-License-Identifier: GPL-2.0
/**
 * dwc3-pci.c - PCI Specific glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <[email protected]>,
 *	    Sebastian Andrzej Siewior <[email protected]>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/workqueue.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <linux/acpi.h>
#include <linux/delay.h>

#define PCI_DEVICE_ID_INTEL_BYT			0x0f37
#define PCI_DEVICE_ID_INTEL_MRFLD		0x119e
#define PCI_DEVICE_ID_INTEL_BSW			0x22b7
#define PCI_DEVICE_ID_INTEL_SPTLP		0x9d30
#define PCI_DEVICE_ID_INTEL_SPTH		0xa130
#define PCI_DEVICE_ID_INTEL_BXT			0x0aaa
#define PCI_DEVICE_ID_INTEL_BXT_M		0x1aaa
#define PCI_DEVICE_ID_INTEL_APL			0x5aaa
#define PCI_DEVICE_ID_INTEL_KBP			0xa2b0
#define PCI_DEVICE_ID_INTEL_GLK			0x31aa
#define PCI_DEVICE_ID_INTEL_CNPLP		0x9dee
#define PCI_DEVICE_ID_INTEL_CNPH		0xa36e
#define PCI_DEVICE_ID_INTEL_ICLLP		0x34ee

#define PCI_INTEL_BXT_DSM_GUID		"732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
#define PCI_INTEL_BXT_FUNC_PMU_PWR	4
#define PCI_INTEL_BXT_STATE_D0		0
#define PCI_INTEL_BXT_STATE_D3		3

#define GP_RWBAR			1
#define GP_RWREG1			0xa0
#define GP_RWREG1_ULPI_REFCLK_DISABLE	(1 << 17)

/**
 * struct dwc3_pci - Driver private structure
 * @dwc3: child dwc3 platform_device
 * @pci: our link to PCI bus
 * @guid: _DSM GUID
 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
 * @wakeup_work: work for asynchronous resume
 */
struct dwc3_pci {
	struct platform_device *dwc3;
	struct pci_dev *pci;

	guid_t guid;

	unsigned int has_dsm_for_pm:1;
	struct work_struct wakeup_work;
};

static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
static const struct acpi_gpio_params cs_gpios = { 1, 0, false };

static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
	{ "reset-gpios", &reset_gpios, 1 },
	{ "cs-gpios", &cs_gpios, 1 },
	{ },
};

static struct gpiod_lookup_table platform_bytcr_gpios = {
	.dev_id		= "0000:00:16.0",
	.table		= {
		GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
		{}
	},
};

static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
{
	void __iomem	*reg;
	u32		value;

	reg = pcim_iomap(pci, GP_RWBAR, 0);
	if (!reg)
		return -ENOMEM;

	value = readl(reg + GP_RWREG1);
	if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
		goto unmap; /* ULPI refclk already enabled */

	value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
	writel(value, reg + GP_RWREG1);
	/* This comes from the Intel Android x86 tree w/o any explanation */
	msleep(100);
unmap:
	pcim_iounmap(pci, reg);
	return 0;
}

static const struct property_entry dwc3_pci_intel_properties[] = {
	PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	{}
};

static const struct property_entry dwc3_pci_mrfld_properties[] = {
	PROPERTY_ENTRY_STRING("dr_mode", "otg"),
	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	{}
};

static const struct property_entry dwc3_pci_amd_properties[] = {
	PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
	PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
	PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
	PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
	PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
	PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
	PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
	PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
	PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
	PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
	PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
	/* FIXME these quirks should be removed when AMD NL tapes out */
	PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
	PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
	PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	{}
};

static int dwc3_pci_quirks(struct dwc3_pci *dwc)
{
	struct pci_dev			*pdev = dwc->pci;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
				pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
			guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
			dwc->has_dsm_for_pm = true;
		}

		if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
			struct gpio_desc *gpio;
			int ret;

			/* On BYT the FW does not always enable the refclock */
			ret = dwc3_byt_enable_ulpi_refclock(pdev);
			if (ret)
				return ret;

			ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
					acpi_dwc3_byt_gpios);
			if (ret)
				dev_dbg(&pdev->dev, "failed to add mapping table\n");

			/*
			 * A lot of BYT devices lack ACPI resource entries for
			 * the GPIOs, add a fallback mapping to the reference
			 * design GPIOs which all boards seem to use.
			 */
			gpiod_add_lookup_table(&platform_bytcr_gpios);

			/*
			 * These GPIOs will turn on the USB2 PHY. Note that we have to
			 * put the gpio descriptors again here because the phy driver
			 * might want to grab them, too.
			 */
			gpio = devm_gpiod_get_optional(&pdev->dev, "cs",
						       GPIOD_OUT_LOW);
			if (IS_ERR(gpio))
				return PTR_ERR(gpio);

			gpiod_set_value_cansleep(gpio, 1);

			gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
						       GPIOD_OUT_LOW);
			if (IS_ERR(gpio))
				return PTR_ERR(gpio);

			if (gpio) {
				gpiod_set_value_cansleep(gpio, 1);
				usleep_range(10000, 11000);
			}
		}
	}

	return 0;
}

#ifdef CONFIG_PM
static void dwc3_pci_resume_work(struct work_struct *work)
{
	struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
	struct platform_device *dwc3 = dwc->dwc3;
	int ret;

	ret = pm_runtime_get_sync(&dwc3->dev);
	if (ret)
		return;

	pm_runtime_mark_last_busy(&dwc3->dev);
	pm_runtime_put_sync_autosuspend(&dwc3->dev);
}
#endif

static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
{
	struct property_entry *p = (struct property_entry *)id->driver_data;
	struct dwc3_pci		*dwc;
	struct resource		res[2];
	int			ret;
	struct device		*dev = &pci->dev;

	ret = pcim_enable_device(pci);
	if (ret) {
		dev_err(dev, "failed to enable pci device\n");
		return -ENODEV;
	}

	pci_set_master(pci);

	dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
	if (!dwc)
		return -ENOMEM;

	dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
	if (!dwc->dwc3)
		return -ENOMEM;

	memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));

	res[0].start	= pci_resource_start(pci, 0);
	res[0].end	= pci_resource_end(pci, 0);
	res[0].name	= "dwc_usb3";
	res[0].flags	= IORESOURCE_MEM;

	res[1].start	= pci->irq;
	res[1].name	= "dwc_usb3";
	res[1].flags	= IORESOURCE_IRQ;

	ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
	if (ret) {
		dev_err(dev, "couldn't add resources to dwc3 device\n");
		goto err;
	}

	dwc->pci = pci;
	dwc->dwc3->dev.parent = dev;
	ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));

	ret = platform_device_add_properties(dwc->dwc3, p);
	if (ret < 0)
		return ret;

	ret = dwc3_pci_quirks(dwc);
	if (ret)
		goto err;

	ret = platform_device_add(dwc->dwc3);
	if (ret) {
		dev_err(dev, "failed to register dwc3 device\n");
		goto err;
	}

	device_init_wakeup(dev, true);
	pci_set_drvdata(pci, dwc);
	pm_runtime_put(dev);
#ifdef CONFIG_PM
	INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
#endif

	return 0;
err:
	platform_device_put(dwc->dwc3);
	return ret;
}

static void dwc3_pci_remove(struct pci_dev *pci)
{
	struct dwc3_pci		*dwc = pci_get_drvdata(pci);
	struct pci_dev		*pdev = dwc->pci;

	if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
		gpiod_remove_lookup_table(&platform_bytcr_gpios);
#ifdef CONFIG_PM
	cancel_work_sync(&dwc->wakeup_work);
#endif
	device_init_wakeup(&pci->dev, false);
	pm_runtime_get(&pci->dev);
	platform_device_unregister(dwc->dwc3);
}

static const struct pci_device_id dwc3_pci_id_table[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
	  (kernel_ulong_t) &dwc3_pci_intel_properties },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
	  (kernel_ulong_t) &dwc3_pci_mrfld_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
	  (kernel_ulong_t) &dwc3_pci_intel_properties, },

	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
	  (kernel_ulong_t) &dwc3_pci_amd_properties, },
	{  }	/* Terminating Entry */
};
MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);

#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
{
	union acpi_object *obj;
	union acpi_object tmp;
	union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);

	if (!dwc->has_dsm_for_pm)
		return 0;

	tmp.type = ACPI_TYPE_INTEGER;
	tmp.integer.value = param;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
			1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
	if (!obj) {
		dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
		return -EIO;
	}

	ACPI_FREE(obj);

	return 0;
}
#endif /* CONFIG_PM || CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int dwc3_pci_runtime_suspend(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);

	if (device_can_wakeup(dev))
		return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);

	return -EBUSY;
}

static int dwc3_pci_runtime_resume(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);
	int			ret;

	ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
	if (ret)
		return ret;

	queue_work(pm_wq, &dwc->wakeup_work);

	return 0;
}
#endif /* CONFIG_PM */

#ifdef CONFIG_PM_SLEEP
static int dwc3_pci_suspend(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);

	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
}

static int dwc3_pci_resume(struct device *dev)
{
	struct dwc3_pci		*dwc = dev_get_drvdata(dev);

	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
	SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
		NULL)
};

static struct pci_driver dwc3_pci_driver = {
	.name		= "dwc3-pci",
	.id_table	= dwc3_pci_id_table,
	.probe		= dwc3_pci_probe,
	.remove		= dwc3_pci_remove,
	.driver		= {
		.pm	= &dwc3_pci_dev_pm_ops,
	}
};

MODULE_AUTHOR("Felipe Balbi <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");

module_pci_driver(dwc3_pci_driver);
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
72246da4 FB	2	/**
	3	* dwc3-pci.c - PCI Specific glue layer
	4	*
	5	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	6	*
	7	* Authors: Felipe Balbi <[email protected]>,
	8	* Sebastian Andrzej Siewior <[email protected]>
72246da4 FB	9	*/
	10
	11	#include <linux/kernel.h>
46a57283	12	#include <linux/module.h>
72246da4 FB	13	#include <linux/slab.h>
72246da4 FB	14	#include <linux/pci.h>
8eed00b2	15	#include <linux/workqueue.h>
e9af9229	16	#include <linux/pm_runtime.h>
72246da4	17	#include <linux/platform_device.h>
a89d977c	18	#include <linux/gpio/consumer.h>
5741022c	19	#include <linux/gpio/machine.h>
a89d977c	20	#include <linux/acpi.h>
cf48305d	21	#include <linux/delay.h>
8f317b47	22
9a5a0783 JY	23	#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
	24	#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
	25	#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
	26	#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
	27	#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
b4c580a4	28	#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
1ffb4d5c	29	#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
b4c580a4	30	#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
4491ed50	31	#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
8f8983a5	32	#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
68217959 HK	33	#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
68217959 HK	34	#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
00908693	35	#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
72246da4	36
94116f81	37	#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
9cecca75 FB	38	#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
	39	#define PCI_INTEL_BXT_STATE_D0 0
	40	#define PCI_INTEL_BXT_STATE_D3 3
	41
7740d04d HG	42	#define GP_RWBAR 1
	43	#define GP_RWREG1 0xa0
	44	#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
	45
0f817ae6 FB	46	/**
	47	* struct dwc3_pci - Driver private structure
	48	* @dwc3: child dwc3 platform_device
	49	* @pci: our link to PCI bus
94116f81	50	* @guid: _DSM GUID
9cecca75	51	* @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
87d852de	52	* @wakeup_work: work for asynchronous resume
0f817ae6 FB	53	*/
	54	struct dwc3_pci {
	55	struct platform_device *dwc3;
	56	struct pci_dev *pci;
9cecca75	57
94116f81	58	guid_t guid;
9cecca75 FB	59
9cecca75 FB	60	unsigned int has_dsm_for_pm:1;
8eed00b2	61	struct work_struct wakeup_work;
0f817ae6 FB	62	};
0f817ae6 FB	63
a89d977c HK	64	static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
	65	static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
	66
	67	static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
	68	{ "reset-gpios", &reset_gpios, 1 },
	69	{ "cs-gpios", &cs_gpios, 1 },
	70	{ },
	71	};
	72
5741022c HG	73	static struct gpiod_lookup_table platform_bytcr_gpios = {
	74	.dev_id = "0000:00:16.0",
	75	.table = {
	76	GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
	77	GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
	78	{}
	79	},
	80	};
	81
7740d04d HG	82	static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
	83	{
	84	void __iomem *reg;
	85	u32 value;
	86
	87	reg = pcim_iomap(pci, GP_RWBAR, 0);
b497fff6 WY	88	if (!reg)
b497fff6 WY	89	return -ENOMEM;
7740d04d HG	90
	91	value = readl(reg + GP_RWREG1);
	92	if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
	93	goto unmap; /* ULPI refclk already enabled */
	94
	95	value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
	96	writel(value, reg + GP_RWREG1);
	97	/* This comes from the Intel Android x86 tree w/o any explanation */
	98	msleep(100);
	99	unmap:
	100	pcim_iounmap(pci, reg);
	101	return 0;
	102	}
	103
1a7b12f6 AS	104	static const struct property_entry dwc3_pci_intel_properties[] = {
	105	PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
	106	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	107	{}
	108	};
	109
c31d983b AS	110	static const struct property_entry dwc3_pci_mrfld_properties[] = {
	111	PROPERTY_ENTRY_STRING("dr_mode", "otg"),
	112	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	113	{}
	114	};
	115
1a7b12f6 AS	116	static const struct property_entry dwc3_pci_amd_properties[] = {
	117	PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
	118	PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
	119	PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
	120	PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
	121	PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
	122	PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
	123	PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
	124	PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
	125	PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
	126	PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
	127	PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
	128	/* FIXME these quirks should be removed when AMD NL tapes out */
	129	PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
	130	PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
	131	PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
	132	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
	133	{}
	134	};
	135
0f817ae6	136	static int dwc3_pci_quirks(struct dwc3_pci *dwc)
2cd9ddf7	137	{
0f817ae6 FB	138	struct pci_dev *pdev = dwc->pci;
0f817ae6 FB	139
e6fe66fe	140	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
9cecca75 FB	141	if (pdev->device == PCI_DEVICE_ID_INTEL_BXT \|\|
9cecca75 FB	142	pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
94116f81	143	guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
9cecca75 FB	144	dwc->has_dsm_for_pm = true;
	145	}
	146
e6fe66fe FB	147	if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
e6fe66fe FB	148	struct gpio_desc *gpio;
1a7b12f6	149	int ret;
e6fe66fe	150
7740d04d HG	151	/* On BYT the FW does not always enable the refclock */
	152	ret = dwc3_byt_enable_ulpi_refclock(pdev);
	153	if (ret)
	154	return ret;
	155
4a56e413	156	ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
e6fe66fe	157	acpi_dwc3_byt_gpios);
4a56e413 AS	158	if (ret)
4a56e413 AS	159	dev_dbg(&pdev->dev, "failed to add mapping table\n");
e6fe66fe	160
5741022c HG	161	/*
	162	* A lot of BYT devices lack ACPI resource entries for
	163	* the GPIOs, add a fallback mapping to the reference
	164	* design GPIOs which all boards seem to use.
	165	*/
	166	gpiod_add_lookup_table(&platform_bytcr_gpios);
	167
e6fe66fe FB	168	/*
	169	* These GPIOs will turn on the USB2 PHY. Note that we have to
	170	* put the gpio descriptors again here because the phy driver
	171	* might want to grab them, too.
	172	*/
211f658b HG	173	gpio = devm_gpiod_get_optional(&pdev->dev, "cs",
211f658b HG	174	GPIOD_OUT_LOW);
e6fe66fe FB	175	if (IS_ERR(gpio))
	176	return PTR_ERR(gpio);
	177
a89d977c	178	gpiod_set_value_cansleep(gpio, 1);
e6fe66fe	179
211f658b HG	180	gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
211f658b HG	181	GPIOD_OUT_LOW);
e6fe66fe FB	182	if (IS_ERR(gpio))
	183	return PTR_ERR(gpio);
	184
	185	if (gpio) {
	186	gpiod_set_value_cansleep(gpio, 1);
e6fe66fe FB	187	usleep_range(10000, 11000);
e6fe66fe FB	188	}
a89d977c HK	189	}
	190	}
	191
2cd9ddf7 HK	192	return 0;
2cd9ddf7 HK	193	}
72246da4	194
8eed00b2 MG	195	#ifdef CONFIG_PM
	196	static void dwc3_pci_resume_work(struct work_struct *work)
	197	{
	198	struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
	199	struct platform_device *dwc3 = dwc->dwc3;
	200	int ret;
	201
	202	ret = pm_runtime_get_sync(&dwc3->dev);
	203	if (ret)
	204	return;
	205
	206	pm_runtime_mark_last_busy(&dwc3->dev);
	207	pm_runtime_put_sync_autosuspend(&dwc3->dev);
	208	}
	209	#endif
	210
1a7b12f6	211	static int dwc3_pci_probe(struct pci_dev pci, const struct pci_device_id id)
72246da4	212	{
1a7b12f6	213	struct property_entry p = (struct property_entry )id->driver_data;
0f817ae6	214	struct dwc3_pci *dwc;
72246da4	215	struct resource res[2];
b09e99ee	216	int ret;
802ca850	217	struct device *dev = &pci->dev;
72246da4	218
f1c7e710	219	ret = pcim_enable_device(pci);
72246da4	220	if (ret) {
802ca850 CP	221	dev_err(dev, "failed to enable pci device\n");
802ca850 CP	222	return -ENODEV;
72246da4 FB	223	}
72246da4 FB	224
72246da4 FB	225	pci_set_master(pci);
72246da4 FB	226
0f817ae6 FB	227	dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
	228	if (!dwc)
	229	return -ENOMEM;
	230
	231	dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
	232	if (!dwc->dwc3)
f1c7e710	233	return -ENOMEM;
72246da4 FB	234
	235	memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
	236
	237	res[0].start = pci_resource_start(pci, 0);
	238	res[0].end = pci_resource_end(pci, 0);
	239	res[0].name = "dwc_usb3";
	240	res[0].flags = IORESOURCE_MEM;
	241
	242	res[1].start = pci->irq;
	243	res[1].name = "dwc_usb3";
	244	res[1].flags = IORESOURCE_IRQ;
	245
0f817ae6	246	ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
72246da4	247	if (ret) {
802ca850	248	dev_err(dev, "couldn't add resources to dwc3 device\n");
cabdf83d	249	goto err;
72246da4 FB	250	}
72246da4 FB	251
0f817ae6 FB	252	dwc->pci = pci;
	253	dwc->dwc3->dev.parent = dev;
	254	ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
72246da4	255
1a7b12f6 AS	256	ret = platform_device_add_properties(dwc->dwc3, p);
	257	if (ret < 0)
	258	return ret;
	259
0f817ae6	260	ret = dwc3_pci_quirks(dwc);
474799f0 HK	261	if (ret)
	262	goto err;
	263
0f817ae6	264	ret = platform_device_add(dwc->dwc3);
72246da4	265	if (ret) {
802ca850	266	dev_err(dev, "failed to register dwc3 device\n");
2cd9ddf7	267	goto err;
72246da4 FB	268	}
72246da4 FB	269
e9af9229	270	device_init_wakeup(dev, true);
0f817ae6	271	pci_set_drvdata(pci, dwc);
e9af9229	272	pm_runtime_put(dev);
8eed00b2 MG	273	#ifdef CONFIG_PM
	274	INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
	275	#endif
e9af9229	276
72246da4	277	return 0;
2cd9ddf7	278	err:
0f817ae6	279	platform_device_put(dwc->dwc3);
72246da4 FB	280	return ret;
	281	}
	282
fb4e98ab	283	static void dwc3_pci_remove(struct pci_dev *pci)
72246da4	284	{
0f817ae6	285	struct dwc3_pci *dwc = pci_get_drvdata(pci);
7b412b04	286	struct pci_dev *pdev = dwc->pci;
0f817ae6	287
7b412b04 KS	288	if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
7b412b04 KS	289	gpiod_remove_lookup_table(&platform_bytcr_gpios);
8eed00b2 MG	290	#ifdef CONFIG_PM
	291	cancel_work_sync(&dwc->wakeup_work);
	292	#endif
e9af9229 FB	293	device_init_wakeup(&pci->dev, false);
e9af9229 FB	294	pm_runtime_get(&pci->dev);
0f817ae6	295	platform_device_unregister(dwc->dwc3);
72246da4 FB	296	}
72246da4 FB	297
782df20c	298	static const struct pci_device_id dwc3_pci_id_table[] = {
1a7b12f6 AS	299	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
	300	(kernel_ulong_t) &dwc3_pci_intel_properties },
	301
	302	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
	303	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	304
	305	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
c31d983b	306	(kernel_ulong_t) &dwc3_pci_mrfld_properties, },
1a7b12f6 AS	307
	308	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
	309	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	310
	311	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
	312	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	313
	314	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
	315	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	316
	317	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
	318	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	319
	320	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
	321	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	322
	323	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
	324	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	325
	326	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
	327	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	328
	329	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
	330	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	331
	332	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
	333	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	334
	335	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
	336	(kernel_ulong_t) &dwc3_pci_intel_properties, },
	337
	338	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
	339	(kernel_ulong_t) &dwc3_pci_amd_properties, },
72246da4 FB	340	{ } /* Terminating Entry */
	341	};
	342	MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
	343
36daf3aa FB	344	#if defined(CONFIG_PM) \|\| defined(CONFIG_PM_SLEEP)
	345	static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
	346	{
	347	union acpi_object *obj;
	348	union acpi_object tmp;
	349	union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
	350
	351	if (!dwc->has_dsm_for_pm)
	352	return 0;
	353
	354	tmp.type = ACPI_TYPE_INTEGER;
	355	tmp.integer.value = param;
	356
94116f81	357	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
36daf3aa FB	358	1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
	359	if (!obj) {
	360	dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
	361	return -EIO;
	362	}
	363
	364	ACPI_FREE(obj);
	365
	366	return 0;
	367	}
	368	#endif /* CONFIG_PM \|\| CONFIG_PM_SLEEP */
	369
e9af9229 FB	370	#ifdef CONFIG_PM
	371	static int dwc3_pci_runtime_suspend(struct device *dev)
	372	{
9cecca75 FB	373	struct dwc3_pci *dwc = dev_get_drvdata(dev);
9cecca75 FB	374
de3ef1eb	375	if (device_can_wakeup(dev))
9cecca75	376	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
e9af9229 FB	377
	378	return -EBUSY;
	379	}
	380
f6c274e1 FB	381	static int dwc3_pci_runtime_resume(struct device *dev)
f6c274e1 FB	382	{
0f817ae6	383	struct dwc3_pci *dwc = dev_get_drvdata(dev);
9cecca75 FB	384	int ret;
	385
	386	ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
	387	if (ret)
	388	return ret;
f6c274e1	389
8eed00b2 MG	390	queue_work(pm_wq, &dwc->wakeup_work);
	391
	392	return 0;
f6c274e1	393	}
696118c0	394	#endif /* CONFIG_PM */
f6c274e1	395
696118c0	396	#ifdef CONFIG_PM_SLEEP
9cecca75	397	static int dwc3_pci_suspend(struct device *dev)
e9af9229	398	{
9cecca75 FB	399	struct dwc3_pci *dwc = dev_get_drvdata(dev);
	400
	401	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
	402	}
	403
	404	static int dwc3_pci_resume(struct device *dev)
	405	{
	406	struct dwc3_pci *dwc = dev_get_drvdata(dev);
	407
	408	return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
e9af9229	409	}
696118c0	410	#endif /* CONFIG_PM_SLEEP */
e9af9229	411
95aa932c	412	static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
9cecca75	413	SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
f6c274e1	414	SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
e9af9229 FB	415	NULL)
	416	};
	417
72246da4	418	static struct pci_driver dwc3_pci_driver = {
0949e99b	419	.name = "dwc3-pci",
72246da4 FB	420	.id_table = dwc3_pci_id_table,
72246da4 FB	421	.probe = dwc3_pci_probe,
7690417d	422	.remove = dwc3_pci_remove,
e9af9229 FB	423	.driver = {
	424	.pm = &dwc3_pci_dev_pm_ops,
	425	}
72246da4 FB	426	};
	427
	428	MODULE_AUTHOR("Felipe Balbi <[email protected]>");
5945f789	429	MODULE_LICENSE("GPL v2");
72246da4 FB	430	MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
72246da4 FB	431
95656336	432	module_pci_driver(dwc3_pci_driver);