[linux.git] / drivers / net / wireless / mediatek / mt76 / mt76x02.h

/*
 * Copyright (C) 2016 Felix Fietkau <[email protected]>
 * Copyright (C) 2018 Stanislaw Gruszka <[email protected]>
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef __MT76X02_UTIL_H
#define __MT76X02_UTIL_H

#include <linux/kfifo.h>

#include "mt76.h"
#include "mt76x02_regs.h"
#include "mt76x02_mac.h"
#include "mt76x02_dfs.h"
#include "mt76x02_dma.h"

struct mt76x02_mac_stats {
	u64 rx_stat[6];
	u64 tx_stat[6];
	u64 aggr_stat[2];
	u64 aggr_n[32];
	u64 zero_len_del[2];
};

#define MT_MAX_CHAINS		2
struct mt76x02_rx_freq_cal {
	s8 high_gain[MT_MAX_CHAINS];
	s8 rssi_offset[MT_MAX_CHAINS];
	s8 lna_gain;
	u32 mcu_gain;
	s16 temp_offset;
	u8 freq_offset;
};

struct mt76x02_calibration {
	struct mt76x02_rx_freq_cal rx;

	u8 agc_gain_init[MT_MAX_CHAINS];
	u8 agc_gain_cur[MT_MAX_CHAINS];

	u16 false_cca;
	s8 avg_rssi_all;
	s8 agc_gain_adjust;
	s8 low_gain;

	s8 temp_vco;
	s8 temp;

	bool init_cal_done;
	bool tssi_cal_done;
	bool tssi_comp_pending;
	bool dpd_cal_done;
	bool channel_cal_done;
};

struct mt76x02_dev {
	struct mt76_dev mt76; /* must be first */

	struct mac_address macaddr_list[8];

	struct mutex phy_mutex;

	u8 txdone_seq;
	DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status);

	struct sk_buff *rx_head;

	struct tasklet_struct tx_tasklet;
	struct tasklet_struct pre_tbtt_tasklet;
	struct delayed_work cal_work;
	struct delayed_work mac_work;

	struct mt76x02_mac_stats stats;
	atomic_t avg_ampdu_len;
	u32 aggr_stats[32];

	struct sk_buff *beacons[8];
	u8 beacon_mask;
	u8 beacon_data_mask;

	u8 tbtt_count;
	u16 beacon_int;

	struct mt76x02_calibration cal;

	s8 target_power;
	s8 target_power_delta[2];
	bool enable_tpc;

	bool no_2ghz;

	u8 coverage_class;
	u8 slottime;

	struct mt76x02_dfs_pattern_detector dfs_pd;
};

extern struct ieee80211_rate mt76x02_rates[12];

void mt76x02_configure_filter(struct ieee80211_hw *hw,
			     unsigned int changed_flags,
			     unsigned int *total_flags, u64 multicast);
int mt76x02_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
		   struct ieee80211_sta *sta);
int mt76x02_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
		      struct ieee80211_sta *sta);

void mt76x02_vif_init(struct mt76x02_dev *dev, struct ieee80211_vif *vif,
		      unsigned int idx);
int mt76x02_add_interface(struct ieee80211_hw *hw,
			 struct ieee80211_vif *vif);
void mt76x02_remove_interface(struct ieee80211_hw *hw,
			     struct ieee80211_vif *vif);

int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
			struct ieee80211_ampdu_params *params);
int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
		   struct ieee80211_vif *vif, struct ieee80211_sta *sta,
		   struct ieee80211_key_conf *key);
int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
		   u16 queue, const struct ieee80211_tx_queue_params *params);
void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
				struct ieee80211_vif *vif,
				struct ieee80211_sta *sta);
s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev,
				const struct ieee80211_tx_rate *rate);
s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr,
			    s8 max_txpwr_adj);
void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr);
int mt76x02_insert_hdr_pad(struct sk_buff *skb);
void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
void mt76x02_tx_complete(struct mt76_dev *dev, struct sk_buff *skb);
bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
			  struct sk_buff *skb);
void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
		struct sk_buff *skb);
int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
			   struct sk_buff *skb, struct mt76_queue *q,
			   struct mt76_wcid *wcid, struct ieee80211_sta *sta,
			   u32 *tx_info);

extern const u16 mt76x02_beacon_offsets[16];
void mt76x02_set_beacon_offsets(struct mt76x02_dev *dev);
void mt76x02_set_irq_mask(struct mt76x02_dev *dev, u32 clear, u32 set);
void mt76x02_mac_start(struct mt76x02_dev *dev);

static inline bool is_mt76x2(struct mt76x02_dev *dev)
{
	return mt76_chip(&dev->mt76) == 0x7612 ||
	       mt76_chip(&dev->mt76) == 0x7662 ||
	       mt76_chip(&dev->mt76) == 0x7602;
}

static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask)
{
	mt76x02_set_irq_mask(dev, 0, mask);
}

static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask)
{
	mt76x02_set_irq_mask(dev, mask, 0);
}

static inline bool
mt76x02_wait_for_txrx_idle(struct mt76_dev *dev)
{
	return __mt76_poll_msec(dev, MT_MAC_STATUS,
				MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,
				0, 100);
}

static inline struct mt76x02_sta *
mt76x02_rx_get_sta(struct mt76_dev *dev, u8 idx)
{
	struct mt76_wcid *wcid;

	if (idx >= ARRAY_SIZE(dev->wcid))
		return NULL;

	wcid = rcu_dereference(dev->wcid[idx]);
	if (!wcid)
		return NULL;

	return container_of(wcid, struct mt76x02_sta, wcid);
}

static inline struct mt76_wcid *
mt76x02_rx_get_sta_wcid(struct mt76x02_sta *sta, bool unicast)
{
	if (!sta)
		return NULL;

	if (unicast)
		return &sta->wcid;
	else
		return &sta->vif->group_wcid;
}

#endif
Commit	Line	Data
108a4861 SG	1	/*
	2	* Copyright (C) 2016 Felix Fietkau <[email protected]>
	3	* Copyright (C) 2018 Stanislaw Gruszka <[email protected]>
	4	*
	5	* Permission to use, copy, modify, and/or distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*/
	17
	18	#ifndef __MT76X02_UTIL_H
	19	#define __MT76X02_UTIL_H
	20
e40803f2 LB	21	#include <linux/kfifo.h>
e40803f2 LB	22
7a07adcd LB	23	#include "mt76.h"
7a07adcd LB	24	#include "mt76x02_regs.h"
56e8d4dd	25	#include "mt76x02_mac.h"
e40803f2	26	#include "mt76x02_dfs.h"
7a07adcd	27	#include "mt76x02_dma.h"
e40803f2	28
b2d871c0 LB	29	struct mt76x02_mac_stats {
	30	u64 rx_stat[6];
	31	u64 tx_stat[6];
	32	u64 aggr_stat[2];
	33	u64 aggr_n[32];
	34	u64 zero_len_del[2];
	35	};
	36
e40803f2 LB	37	#define MT_MAX_CHAINS 2
	38	struct mt76x02_rx_freq_cal {
	39	s8 high_gain[MT_MAX_CHAINS];
	40	s8 rssi_offset[MT_MAX_CHAINS];
	41	s8 lna_gain;
	42	u32 mcu_gain;
b2d871c0 LB	43	s16 temp_offset;
b2d871c0 LB	44	u8 freq_offset;
e40803f2 LB	45	};
	46
	47	struct mt76x02_calibration {
	48	struct mt76x02_rx_freq_cal rx;
	49
	50	u8 agc_gain_init[MT_MAX_CHAINS];
	51	u8 agc_gain_cur[MT_MAX_CHAINS];
	52
	53	u16 false_cca;
	54	s8 avg_rssi_all;
	55	s8 agc_gain_adjust;
	56	s8 low_gain;
	57
66a34c66 LB	58	s8 temp_vco;
66a34c66 LB	59	s8 temp;
e40803f2 LB	60
	61	bool init_cal_done;
	62	bool tssi_cal_done;
	63	bool tssi_comp_pending;
	64	bool dpd_cal_done;
	65	bool channel_cal_done;
	66	};
	67
	68	struct mt76x02_dev {
	69	struct mt76_dev mt76; /* must be first */
	70
	71	struct mac_address macaddr_list[8];
	72
b2d871c0	73	struct mutex phy_mutex;
e40803f2 LB	74
	75	u8 txdone_seq;
	76	DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status);
	77
	78	struct sk_buff *rx_head;
	79
	80	struct tasklet_struct tx_tasklet;
	81	struct tasklet_struct pre_tbtt_tasklet;
	82	struct delayed_work cal_work;
	83	struct delayed_work mac_work;
	84
b2d871c0 LB	85	struct mt76x02_mac_stats stats;
b2d871c0 LB	86	atomic_t avg_ampdu_len;
e40803f2 LB	87	u32 aggr_stats[32];
	88
	89	struct sk_buff *beacons[8];
	90	u8 beacon_mask;
	91	u8 beacon_data_mask;
	92
	93	u8 tbtt_count;
	94	u16 beacon_int;
	95
	96	struct mt76x02_calibration cal;
	97
	98	s8 target_power;
	99	s8 target_power_delta[2];
	100	bool enable_tpc;
	101
b2d871c0 LB	102	bool no_2ghz;
b2d871c0 LB	103
e40803f2 LB	104	u8 coverage_class;
	105	u8 slottime;
	106
	107	struct mt76x02_dfs_pattern_detector dfs_pd;
	108	};
56e8d4dd	109
58b5eb8c LB	110	extern struct ieee80211_rate mt76x02_rates[12];
58b5eb8c LB	111
108a4861 SG	112	void mt76x02_configure_filter(struct ieee80211_hw *hw,
	113	unsigned int changed_flags,
	114	unsigned int *total_flags, u64 multicast);
624400e4 SG	115	int mt76x02_sta_add(struct ieee80211_hw hw, struct ieee80211_vif vif,
	116	struct ieee80211_sta *sta);
	117	int mt76x02_sta_remove(struct ieee80211_hw hw, struct ieee80211_vif vif,
	118	struct ieee80211_sta *sta);
cab12953	119
d87cf75f LB	120	void mt76x02_vif_init(struct mt76x02_dev dev, struct ieee80211_vif vif,
d87cf75f LB	121	unsigned int idx);
212926eb SG	122	int mt76x02_add_interface(struct ieee80211_hw *hw,
212926eb SG	123	struct ieee80211_vif *vif);
0cd47bae SG	124	void mt76x02_remove_interface(struct ieee80211_hw *hw,
0cd47bae SG	125	struct ieee80211_vif *vif);
22c575c4 SG	126
	127	int mt76x02_ampdu_action(struct ieee80211_hw hw, struct ieee80211_vif vif,
	128	struct ieee80211_ampdu_params *params);
60c26859 SG	129	int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
	130	struct ieee80211_vif vif, struct ieee80211_sta sta,
	131	struct ieee80211_key_conf *key);
10337263 SG	132	int mt76x02_conf_tx(struct ieee80211_hw hw, struct ieee80211_vif vif,
10337263 SG	133	u16 queue, const struct ieee80211_tx_queue_params *params);
5327b5ea SG	134	void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
	135	struct ieee80211_vif *vif,
	136	struct ieee80211_sta *sta);
91be8e8a	137	s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev,
d697b00b	138	const struct ieee80211_tx_rate *rate);
91be8e8a LB	139	s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr,
91be8e8a LB	140	s8 max_txpwr_adj);
1ea0a1b1	141	void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr);
0e59cba8 SG	142	int mt76x02_insert_hdr_pad(struct sk_buff *skb);
0e59cba8 SG	143	void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
2a45ad31	144	void mt76x02_tx_complete(struct mt76_dev dev, struct sk_buff skb);
8d66af49	145	bool mt76x02_tx_status_data(struct mt76_dev mdev, u8 update);
9ba1e0e6 LB	146	void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
9ba1e0e6 LB	147	struct sk_buff *skb);
9b43960b LB	148	void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
9b43960b LB	149	irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
2f0308d0 LB	150	void mt76x02_tx(struct ieee80211_hw hw, struct ieee80211_tx_control control,
2f0308d0 LB	151	struct sk_buff *skb);
5ec57485 LB	152	int mt76x02_tx_prepare_skb(struct mt76_dev mdev, void txwi,
	153	struct sk_buff skb, struct mt76_queue q,
	154	struct mt76_wcid wcid, struct ieee80211_sta sta,
	155	u32 *tx_info);
957068c2	156
a6daf796	157	extern const u16 mt76x02_beacon_offsets[16];
d87cf75f	158	void mt76x02_set_beacon_offsets(struct mt76x02_dev *dev);
a23fde09 LB	159	void mt76x02_set_irq_mask(struct mt76x02_dev *dev, u32 clear, u32 set);
a23fde09 LB	160	void mt76x02_mac_start(struct mt76x02_dev *dev);
957068c2	161
320c85e6 LB	162	static inline bool is_mt76x2(struct mt76x02_dev *dev)
	163	{
	164	return mt76_chip(&dev->mt76) == 0x7612 \|\|
	165	mt76_chip(&dev->mt76) == 0x7662 \|\|
	166	mt76_chip(&dev->mt76) == 0x7602;
	167	}
	168
a23fde09	169	static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask)
957068c2 LB	170	{
	171	mt76x02_set_irq_mask(dev, 0, mask);
	172	}
	173
a23fde09	174	static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask)
957068c2 LB	175	{
	176	mt76x02_set_irq_mask(dev, mask, 0);
	177	}
	178
71322416 LB	179	static inline bool
	180	mt76x02_wait_for_txrx_idle(struct mt76_dev *dev)
	181	{
	182	return __mt76_poll_msec(dev, MT_MAC_STATUS,
	183	MT_MAC_STATUS_TX \| MT_MAC_STATUS_RX,
	184	0, 100);
	185	}
	186
56e8d4dd LB	187	static inline struct mt76x02_sta *
	188	mt76x02_rx_get_sta(struct mt76_dev *dev, u8 idx)
	189	{
	190	struct mt76_wcid *wcid;
	191
	192	if (idx >= ARRAY_SIZE(dev->wcid))
	193	return NULL;
	194
	195	wcid = rcu_dereference(dev->wcid[idx]);
	196	if (!wcid)
	197	return NULL;
	198
	199	return container_of(wcid, struct mt76x02_sta, wcid);
	200	}
	201
	202	static inline struct mt76_wcid *
	203	mt76x02_rx_get_sta_wcid(struct mt76x02_sta *sta, bool unicast)
	204	{
	205	if (!sta)
	206	return NULL;
	207
	208	if (unicast)
	209	return &sta->wcid;
	210	else
	211	return &sta->vif->group_wcid;
	212	}
	213
108a4861	214	#endif