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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
4fb06283 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
d4a7e708 | 10 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
9c4f7d51 | 11 | * Copyright(c) 2018 Intel Corporation |
8ca151b5 JB |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of version 2 of the GNU General Public License as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
8ca151b5 | 22 | * The full GNU General Public License is included in this distribution |
410dc5aa | 23 | * in the file called COPYING. |
8ca151b5 JB |
24 | * |
25 | * Contact Information: | |
cb2f8277 | 26 | * Intel Linux Wireless <[email protected]> |
8ca151b5 JB |
27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
28 | * | |
29 | * BSD LICENSE | |
30 | * | |
51368bf7 | 31 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
4fb06283 | 32 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
d4a7e708 | 33 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
9c4f7d51 | 34 | * Copyright(c) 2018 Intel Corporation |
8ca151b5 JB |
35 | * All rights reserved. |
36 | * | |
37 | * Redistribution and use in source and binary forms, with or without | |
38 | * modification, are permitted provided that the following conditions | |
39 | * are met: | |
40 | * | |
41 | * * Redistributions of source code must retain the above copyright | |
42 | * notice, this list of conditions and the following disclaimer. | |
43 | * * Redistributions in binary form must reproduce the above copyright | |
44 | * notice, this list of conditions and the following disclaimer in | |
45 | * the documentation and/or other materials provided with the | |
46 | * distribution. | |
47 | * * Neither the name Intel Corporation nor the names of its | |
48 | * contributors may be used to endorse or promote products derived | |
49 | * from this software without specific prior written permission. | |
50 | * | |
51 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
52 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
53 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
54 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
55 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
56 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
57 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
58 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
59 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
60 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
61 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
62 | * | |
63 | *****************************************************************************/ | |
1214755c | 64 | #include <linux/firmware.h> |
90d4f7db | 65 | #include <linux/rtnetlink.h> |
8ca151b5 | 66 | #include "iwl-trans.h" |
c2a2b28b | 67 | #include "iwl-csr.h" |
8ca151b5 JB |
68 | #include "mvm.h" |
69 | #include "iwl-eeprom-parse.h" | |
70 | #include "iwl-eeprom-read.h" | |
71 | #include "iwl-nvm-parse.h" | |
8ba2d7a1 | 72 | #include "iwl-prph.h" |
45f65569 | 73 | #include "fw/acpi.h" |
8ca151b5 | 74 | |
1fd4afe2 | 75 | /* Default NVM size to read */ |
9c4f7d51 | 76 | #define IWL_NVM_DEFAULT_CHUNK_SIZE (2 * 1024) |
1fd4afe2 | 77 | |
1214755c EH |
78 | #define NVM_WRITE_OPCODE 1 |
79 | #define NVM_READ_OPCODE 0 | |
80 | ||
d6aeb354 EH |
81 | /* load nvm chunk response */ |
82 | enum { | |
83 | READ_NVM_CHUNK_SUCCEED = 0, | |
84 | READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 | |
85 | }; | |
86 | ||
1214755c EH |
87 | /* |
88 | * prepare the NVM host command w/ the pointers to the nvm buffer | |
89 | * and send it to fw | |
90 | */ | |
91 | static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, | |
92 | u16 offset, u16 length, const u8 *data) | |
8ca151b5 | 93 | { |
1214755c EH |
94 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
95 | .offset = cpu_to_le16(offset), | |
96 | .length = cpu_to_le16(length), | |
97 | .type = cpu_to_le16(section), | |
98 | .op_code = NVM_WRITE_OPCODE, | |
99 | }; | |
100 | struct iwl_host_cmd cmd = { | |
101 | .id = NVM_ACCESS_CMD, | |
102 | .len = { sizeof(struct iwl_nvm_access_cmd), length }, | |
9a57f650 | 103 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
1214755c EH |
104 | .data = { &nvm_access_cmd, data }, |
105 | /* data may come from vmalloc, so use _DUP */ | |
106 | .dataflags = { 0, IWL_HCMD_DFL_DUP }, | |
107 | }; | |
9a57f650 MG |
108 | struct iwl_rx_packet *pkt; |
109 | struct iwl_nvm_access_resp *nvm_resp; | |
110 | int ret; | |
1214755c | 111 | |
9a57f650 MG |
112 | ret = iwl_mvm_send_cmd(mvm, &cmd); |
113 | if (ret) | |
114 | return ret; | |
115 | ||
116 | pkt = cmd.resp_pkt; | |
9a57f650 MG |
117 | /* Extract & check NVM write response */ |
118 | nvm_resp = (void *)pkt->data; | |
119 | if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) { | |
120 | IWL_ERR(mvm, | |
121 | "NVM access write command failed for section %u (status = 0x%x)\n", | |
122 | section, le16_to_cpu(nvm_resp->status)); | |
123 | ret = -EIO; | |
124 | } | |
125 | ||
126 | iwl_free_resp(&cmd); | |
127 | return ret; | |
8ca151b5 JB |
128 | } |
129 | ||
130 | static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, | |
131 | u16 offset, u16 length, u8 *data) | |
132 | { | |
1214755c EH |
133 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
134 | .offset = cpu_to_le16(offset), | |
135 | .length = cpu_to_le16(length), | |
136 | .type = cpu_to_le16(section), | |
137 | .op_code = NVM_READ_OPCODE, | |
138 | }; | |
b9545b48 | 139 | struct iwl_nvm_access_resp *nvm_resp; |
8ca151b5 JB |
140 | struct iwl_rx_packet *pkt; |
141 | struct iwl_host_cmd cmd = { | |
142 | .id = NVM_ACCESS_CMD, | |
a1022927 | 143 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
8ca151b5 JB |
144 | .data = { &nvm_access_cmd, }, |
145 | }; | |
146 | int ret, bytes_read, offset_read; | |
147 | u8 *resp_data; | |
148 | ||
b9545b48 | 149 | cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); |
8ca151b5 JB |
150 | |
151 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
152 | if (ret) | |
153 | return ret; | |
154 | ||
155 | pkt = cmd.resp_pkt; | |
8ca151b5 JB |
156 | |
157 | /* Extract NVM response */ | |
158 | nvm_resp = (void *)pkt->data; | |
b9545b48 EG |
159 | ret = le16_to_cpu(nvm_resp->status); |
160 | bytes_read = le16_to_cpu(nvm_resp->length); | |
161 | offset_read = le16_to_cpu(nvm_resp->offset); | |
162 | resp_data = nvm_resp->data; | |
8ca151b5 | 163 | if (ret) { |
d6aeb354 EH |
164 | if ((offset != 0) && |
165 | (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { | |
166 | /* | |
167 | * meaning of NOT_VALID_ADDRESS: | |
168 | * driver try to read chunk from address that is | |
169 | * multiple of 2K and got an error since addr is empty. | |
170 | * meaning of (offset != 0): driver already | |
171 | * read valid data from another chunk so this case | |
172 | * is not an error. | |
173 | */ | |
174 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
175 | "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", | |
176 | offset); | |
177 | ret = 0; | |
178 | } else { | |
179 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
180 | "NVM access command failed with status %d (device: %s)\n", | |
181 | ret, mvm->cfg->name); | |
182 | ret = -EIO; | |
183 | } | |
8ca151b5 JB |
184 | goto exit; |
185 | } | |
186 | ||
187 | if (offset_read != offset) { | |
188 | IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", | |
189 | offset_read); | |
190 | ret = -EINVAL; | |
191 | goto exit; | |
192 | } | |
193 | ||
194 | /* Write data to NVM */ | |
195 | memcpy(data + offset, resp_data, bytes_read); | |
196 | ret = bytes_read; | |
197 | ||
198 | exit: | |
199 | iwl_free_resp(&cmd); | |
200 | return ret; | |
201 | } | |
202 | ||
1214755c EH |
203 | static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, |
204 | const u8 *data, u16 length) | |
205 | { | |
206 | int offset = 0; | |
207 | ||
208 | /* copy data in chunks of 2k (and remainder if any) */ | |
209 | ||
210 | while (offset < length) { | |
211 | int chunk_size, ret; | |
212 | ||
213 | chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, | |
214 | length - offset); | |
215 | ||
216 | ret = iwl_nvm_write_chunk(mvm, section, offset, | |
217 | chunk_size, data + offset); | |
218 | if (ret < 0) | |
219 | return ret; | |
220 | ||
221 | offset += chunk_size; | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
8ca151b5 JB |
227 | /* |
228 | * Reads an NVM section completely. | |
229 | * NICs prior to 7000 family doesn't have a real NVM, but just read | |
230 | * section 0 which is the EEPROM. Because the EEPROM reading is unlimited | |
231 | * by uCode, we need to manually check in this case that we don't | |
232 | * overflow and try to read more than the EEPROM size. | |
233 | * For 7000 family NICs, we supply the maximal size we can read, and | |
234 | * the uCode fills the response with as much data as we can, | |
235 | * without overflowing, so no check is needed. | |
236 | */ | |
237 | static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, | |
5daddc99 | 238 | u8 *data, u32 size_read) |
8ca151b5 JB |
239 | { |
240 | u16 length, offset = 0; | |
241 | int ret; | |
8ca151b5 | 242 | |
1fd4afe2 DS |
243 | /* Set nvm section read length */ |
244 | length = IWL_NVM_DEFAULT_CHUNK_SIZE; | |
245 | ||
8ca151b5 JB |
246 | ret = length; |
247 | ||
248 | /* Read the NVM until exhausted (reading less than requested) */ | |
249 | while (ret == length) { | |
5daddc99 LK |
250 | /* Check no memory assumptions fail and cause an overflow */ |
251 | if ((size_read + offset + length) > | |
252 | mvm->cfg->base_params->eeprom_size) { | |
253 | IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); | |
254 | return -ENOBUFS; | |
255 | } | |
256 | ||
8ca151b5 JB |
257 | ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); |
258 | if (ret < 0) { | |
d6aeb354 EH |
259 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
260 | "Cannot read NVM from section %d offset %d, length %d\n", | |
261 | section, offset, length); | |
8ca151b5 JB |
262 | return ret; |
263 | } | |
264 | offset += ret; | |
8ca151b5 JB |
265 | } |
266 | ||
9c4f7d51 | 267 | iwl_nvm_fixups(mvm->trans->hw_id, section, data, offset); |
7d162045 | 268 | |
07fd7d28 JB |
269 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
270 | "NVM section %d read completed\n", section); | |
8ca151b5 JB |
271 | return offset; |
272 | } | |
273 | ||
274 | static struct iwl_nvm_data * | |
275 | iwl_parse_nvm_sections(struct iwl_mvm *mvm) | |
276 | { | |
277 | struct iwl_nvm_section *sections = mvm->nvm_sections; | |
8fe34b06 LC |
278 | const __be16 *hw; |
279 | const __le16 *sw, *calib, *regulatory, *mac_override, *phy_sku; | |
5dd9c68a | 280 | bool lar_enabled; |
44fd09da | 281 | int regulatory_type; |
8ca151b5 JB |
282 | |
283 | /* Checking for required sections */ | |
44fd09da | 284 | if (mvm->trans->cfg->nvm_type != IWL_NVM_EXT) { |
77db0a3c EH |
285 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
286 | !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { | |
abf09c56 | 287 | IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); |
77db0a3c EH |
288 | return NULL; |
289 | } | |
290 | } else { | |
44fd09da CRI |
291 | if (mvm->trans->cfg->nvm_type == IWL_NVM_SDP) |
292 | regulatory_type = NVM_SECTION_TYPE_REGULATORY_SDP; | |
293 | else | |
294 | regulatory_type = NVM_SECTION_TYPE_REGULATORY; | |
295 | ||
9f32e017 | 296 | /* SW and REGULATORY sections are mandatory */ |
77db0a3c | 297 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
44fd09da | 298 | !mvm->nvm_sections[regulatory_type].data) { |
77db0a3c | 299 | IWL_ERR(mvm, |
abf09c56 | 300 | "Can't parse empty family 8000 OTP/NVM sections\n"); |
77db0a3c EH |
301 | return NULL; |
302 | } | |
9f32e017 | 303 | /* MAC_OVERRIDE or at least HW section must exist */ |
bb926924 | 304 | if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && |
9f32e017 EH |
305 | !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { |
306 | IWL_ERR(mvm, | |
307 | "Can't parse mac_address, empty sections\n"); | |
308 | return NULL; | |
309 | } | |
ce500071 | 310 | |
ce500071 | 311 | /* PHY_SKU section is mandatory in B0 */ |
5dd9c68a | 312 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) { |
ce500071 EH |
313 | IWL_ERR(mvm, |
314 | "Can't parse phy_sku in B0, empty sections\n"); | |
315 | return NULL; | |
316 | } | |
8ca151b5 JB |
317 | } |
318 | ||
8fe34b06 | 319 | hw = (const __be16 *)sections[mvm->cfg->nvm_hw_section_num].data; |
8ca151b5 JB |
320 | sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; |
321 | calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; | |
77db0a3c EH |
322 | mac_override = |
323 | (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; | |
ce500071 | 324 | phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data; |
77db0a3c | 325 | |
44fd09da CRI |
326 | regulatory = mvm->trans->cfg->nvm_type == IWL_NVM_SDP ? |
327 | (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY_SDP].data : | |
328 | (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; | |
329 | ||
5711cac4 | 330 | lar_enabled = !iwlwifi_mod_params.lar_disable && |
859d914c JB |
331 | fw_has_capa(&mvm->fw->ucode_capa, |
332 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
5711cac4 | 333 | |
afd5b170 | 334 | return iwl_parse_nvm_data(mvm->trans, mvm->cfg, hw, sw, calib, |
ce500071 | 335 | regulatory, mac_override, phy_sku, |
5711cac4 | 336 | mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant, |
afd5b170 | 337 | lar_enabled); |
8ca151b5 JB |
338 | } |
339 | ||
81a67e32 EL |
340 | /* Loads the NVM data stored in mvm->nvm_sections into the NIC */ |
341 | int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) | |
342 | { | |
05159fcc | 343 | int i, ret = 0; |
81a67e32 EL |
344 | struct iwl_nvm_section *sections = mvm->nvm_sections; |
345 | ||
346 | IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); | |
347 | ||
099d8f20 EG |
348 | for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { |
349 | if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) | |
350 | continue; | |
351 | ret = iwl_nvm_write_section(mvm, i, sections[i].data, | |
352 | sections[i].length); | |
81a67e32 EL |
353 | if (ret < 0) { |
354 | IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); | |
355 | break; | |
356 | } | |
357 | } | |
358 | return ret; | |
359 | } | |
360 | ||
5bd1d2c1 | 361 | int iwl_nvm_init(struct iwl_mvm *mvm) |
8ca151b5 | 362 | { |
d6aeb354 | 363 | int ret, section; |
5daddc99 | 364 | u32 size_read = 0; |
8ca151b5 | 365 | u8 *nvm_buffer, *temp; |
d383c740 | 366 | const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step; |
8ca151b5 | 367 | |
ae2b21b0 EH |
368 | if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) |
369 | return -EINVAL; | |
370 | ||
26481bf4 | 371 | /* load NVM values from nic */ |
5bd1d2c1 LC |
372 | /* Read From FW NVM */ |
373 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); | |
374 | ||
375 | nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size, | |
376 | GFP_KERNEL); | |
377 | if (!nvm_buffer) | |
378 | return -ENOMEM; | |
379 | for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { | |
380 | /* we override the constness for initial read */ | |
381 | ret = iwl_nvm_read_section(mvm, section, nvm_buffer, | |
382 | size_read); | |
383 | if (ret < 0) | |
384 | continue; | |
385 | size_read += ret; | |
386 | temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); | |
387 | if (!temp) { | |
388 | ret = -ENOMEM; | |
389 | break; | |
390 | } | |
7d162045 | 391 | |
9c4f7d51 | 392 | iwl_nvm_fixups(mvm->trans->hw_id, section, temp, ret); |
7d162045 | 393 | |
5bd1d2c1 LC |
394 | mvm->nvm_sections[section].data = temp; |
395 | mvm->nvm_sections[section].length = ret; | |
086f7368 EG |
396 | |
397 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
5bd1d2c1 LC |
398 | switch (section) { |
399 | case NVM_SECTION_TYPE_SW: | |
400 | mvm->nvm_sw_blob.data = temp; | |
401 | mvm->nvm_sw_blob.size = ret; | |
402 | break; | |
403 | case NVM_SECTION_TYPE_CALIBRATION: | |
404 | mvm->nvm_calib_blob.data = temp; | |
405 | mvm->nvm_calib_blob.size = ret; | |
406 | break; | |
407 | case NVM_SECTION_TYPE_PRODUCTION: | |
408 | mvm->nvm_prod_blob.data = temp; | |
409 | mvm->nvm_prod_blob.size = ret; | |
410 | break; | |
411 | case NVM_SECTION_TYPE_PHY_SKU: | |
412 | mvm->nvm_phy_sku_blob.data = temp; | |
413 | mvm->nvm_phy_sku_blob.size = ret; | |
414 | break; | |
415 | default: | |
416 | if (section == mvm->cfg->nvm_hw_section_num) { | |
417 | mvm->nvm_hw_blob.data = temp; | |
418 | mvm->nvm_hw_blob.size = ret; | |
91fac940 | 419 | break; |
086f7368 | 420 | } |
8ca151b5 | 421 | } |
5bd1d2c1 | 422 | #endif |
8ca151b5 | 423 | } |
5bd1d2c1 LC |
424 | if (!size_read) |
425 | IWL_ERR(mvm, "OTP is blank\n"); | |
426 | kfree(nvm_buffer); | |
8ca151b5 | 427 | |
4fb06283 | 428 | /* Only if PNVM selected in the mod param - load external NVM */ |
e02a9d60 | 429 | if (mvm->nvm_file_name) { |
4fb06283 | 430 | /* read External NVM file from the mod param */ |
9c4f7d51 ST |
431 | ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, |
432 | mvm->nvm_sections); | |
d383c740 | 433 | if (ret) { |
8b4d6495 | 434 | mvm->nvm_file_name = nvm_file_C; |
d383c740 | 435 | |
488c28e1 OG |
436 | if ((ret == -EFAULT || ret == -ENOENT) && |
437 | mvm->nvm_file_name) { | |
d383c740 | 438 | /* in case nvm file was failed try again */ |
9c4f7d51 ST |
439 | ret = iwl_read_external_nvm(mvm->trans, |
440 | mvm->nvm_file_name, | |
441 | mvm->nvm_sections); | |
d383c740 EH |
442 | if (ret) |
443 | return ret; | |
444 | } else { | |
445 | return ret; | |
446 | } | |
447 | } | |
26481bf4 EH |
448 | } |
449 | ||
450 | /* parse the relevant nvm sections */ | |
b9545b48 | 451 | mvm->nvm_data = iwl_parse_nvm_sections(mvm); |
82598b4f JB |
452 | if (!mvm->nvm_data) |
453 | return -ENODATA; | |
2a831e08 EH |
454 | IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", |
455 | mvm->nvm_data->nvm_version); | |
8ca151b5 | 456 | |
82598b4f | 457 | return 0; |
8ca151b5 | 458 | } |
dcaf9f5e AN |
459 | |
460 | struct iwl_mcc_update_resp * | |
8ba2d7a1 EH |
461 | iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2, |
462 | enum iwl_mcc_source src_id) | |
dcaf9f5e AN |
463 | { |
464 | struct iwl_mcc_update_cmd mcc_update_cmd = { | |
465 | .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), | |
8ba2d7a1 | 466 | .source_id = (u8)src_id, |
dcaf9f5e | 467 | }; |
5a7d87da | 468 | struct iwl_mcc_update_resp *resp_cp; |
dcaf9f5e AN |
469 | struct iwl_rx_packet *pkt; |
470 | struct iwl_host_cmd cmd = { | |
471 | .id = MCC_UPDATE_CMD, | |
472 | .flags = CMD_WANT_SKB, | |
473 | .data = { &mcc_update_cmd }, | |
474 | }; | |
475 | ||
476 | int ret; | |
477 | u32 status; | |
478 | int resp_len, n_channels; | |
479 | u16 mcc; | |
480 | ||
481 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
482 | return ERR_PTR(-EOPNOTSUPP); | |
483 | ||
484 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); | |
485 | ||
8ba2d7a1 EH |
486 | IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n", |
487 | alpha2[0], alpha2[1], src_id); | |
dcaf9f5e AN |
488 | |
489 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
490 | if (ret) | |
491 | return ERR_PTR(ret); | |
492 | ||
493 | pkt = cmd.resp_pkt; | |
dcaf9f5e AN |
494 | |
495 | /* Extract MCC response */ | |
47fe2f8e HD |
496 | if (fw_has_capa(&mvm->fw->ucode_capa, |
497 | IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT)) { | |
5a7d87da AB |
498 | struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data; |
499 | ||
6fa52430 | 500 | n_channels = __le32_to_cpu(mcc_resp->n_channels); |
5a7d87da AB |
501 | resp_len = sizeof(struct iwl_mcc_update_resp) + |
502 | n_channels * sizeof(__le32); | |
503 | resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); | |
28269897 JB |
504 | if (!resp_cp) { |
505 | resp_cp = ERR_PTR(-ENOMEM); | |
506 | goto exit; | |
507 | } | |
6fa52430 | 508 | } else { |
47fe2f8e | 509 | struct iwl_mcc_update_resp_v3 *mcc_resp_v3 = (void *)pkt->data; |
5a7d87da | 510 | |
47fe2f8e | 511 | n_channels = __le32_to_cpu(mcc_resp_v3->n_channels); |
5a7d87da AB |
512 | resp_len = sizeof(struct iwl_mcc_update_resp) + |
513 | n_channels * sizeof(__le32); | |
514 | resp_cp = kzalloc(resp_len, GFP_KERNEL); | |
28269897 JB |
515 | if (!resp_cp) { |
516 | resp_cp = ERR_PTR(-ENOMEM); | |
517 | goto exit; | |
5a7d87da | 518 | } |
dcaf9f5e | 519 | |
47fe2f8e HD |
520 | resp_cp->status = mcc_resp_v3->status; |
521 | resp_cp->mcc = mcc_resp_v3->mcc; | |
522 | resp_cp->cap = cpu_to_le16(mcc_resp_v3->cap); | |
523 | resp_cp->source_id = mcc_resp_v3->source_id; | |
524 | resp_cp->time = mcc_resp_v3->time; | |
525 | resp_cp->geo_info = mcc_resp_v3->geo_info; | |
526 | resp_cp->n_channels = mcc_resp_v3->n_channels; | |
527 | memcpy(resp_cp->channels, mcc_resp_v3->channels, | |
28269897 | 528 | n_channels * sizeof(__le32)); |
6fa52430 MG |
529 | } |
530 | ||
6fa52430 MG |
531 | status = le32_to_cpu(resp_cp->status); |
532 | ||
533 | mcc = le16_to_cpu(resp_cp->mcc); | |
dcaf9f5e AN |
534 | |
535 | /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ | |
536 | if (mcc == 0) { | |
537 | mcc = 0x3030; /* "00" - world */ | |
6fa52430 | 538 | resp_cp->mcc = cpu_to_le16(mcc); |
dcaf9f5e AN |
539 | } |
540 | ||
dcaf9f5e | 541 | IWL_DEBUG_LAR(mvm, |
82715ac7 EG |
542 | "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') n_chans: %d\n", |
543 | status, mcc, mcc >> 8, mcc & 0xff, n_channels); | |
dcaf9f5e | 544 | |
dcaf9f5e AN |
545 | exit: |
546 | iwl_free_resp(&cmd); | |
dcaf9f5e AN |
547 | return resp_cp; |
548 | } | |
90d4f7db AN |
549 | |
550 | int iwl_mvm_init_mcc(struct iwl_mvm *mvm) | |
551 | { | |
d0d15197 MG |
552 | bool tlv_lar; |
553 | bool nvm_lar; | |
8ba2d7a1 EH |
554 | int retval; |
555 | struct ieee80211_regdomain *regd; | |
7f0344c2 | 556 | char mcc[3]; |
d0d15197 | 557 | |
44fd09da | 558 | if (mvm->cfg->nvm_type == IWL_NVM_EXT) { |
859d914c JB |
559 | tlv_lar = fw_has_capa(&mvm->fw->ucode_capa, |
560 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
d0d15197 MG |
561 | nvm_lar = mvm->nvm_data->lar_enabled; |
562 | if (tlv_lar != nvm_lar) | |
563 | IWL_INFO(mvm, | |
564 | "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n", | |
565 | tlv_lar ? "enabled" : "disabled", | |
566 | nvm_lar ? "enabled" : "disabled"); | |
567 | } | |
568 | ||
90d4f7db AN |
569 | if (!iwl_mvm_is_lar_supported(mvm)) |
570 | return 0; | |
571 | ||
572 | /* | |
b6e160ab | 573 | * try to replay the last set MCC to FW. If it doesn't exist, |
90d4f7db AN |
574 | * queue an update to cfg80211 to retrieve the default alpha2 from FW. |
575 | */ | |
b6e160ab AN |
576 | retval = iwl_mvm_init_fw_regd(mvm); |
577 | if (retval != -ENOENT) | |
578 | return retval; | |
90d4f7db AN |
579 | |
580 | /* | |
8ba2d7a1 EH |
581 | * Driver regulatory hint for initial update, this also informs the |
582 | * firmware we support wifi location updates. | |
88931cc9 AN |
583 | * Disallow scans that might crash the FW while the LAR regdomain |
584 | * is not set. | |
90d4f7db | 585 | */ |
88931cc9 | 586 | mvm->lar_regdom_set = false; |
8ba2d7a1 | 587 | |
47c8b154 | 588 | regd = iwl_mvm_get_current_regdomain(mvm, NULL); |
8ba2d7a1 EH |
589 | if (IS_ERR_OR_NULL(regd)) |
590 | return -EIO; | |
591 | ||
7f0344c2 | 592 | if (iwl_mvm_is_wifi_mcc_supported(mvm) && |
45f65569 | 593 | !iwl_acpi_get_mcc(mvm->dev, mcc)) { |
7f0344c2 JD |
594 | kfree(regd); |
595 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, | |
47c8b154 | 596 | MCC_SOURCE_BIOS, NULL); |
7f0344c2 JD |
597 | if (IS_ERR_OR_NULL(regd)) |
598 | return -EIO; | |
599 | } | |
600 | ||
8ba2d7a1 EH |
601 | retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd); |
602 | kfree(regd); | |
603 | return retval; | |
88931cc9 AN |
604 | } |
605 | ||
0416841d JB |
606 | void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, |
607 | struct iwl_rx_cmd_buffer *rxb) | |
88931cc9 AN |
608 | { |
609 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
610 | struct iwl_mcc_chub_notif *notif = (void *)pkt->data; | |
8ba2d7a1 | 611 | enum iwl_mcc_source src; |
88931cc9 | 612 | char mcc[3]; |
8ba2d7a1 EH |
613 | struct ieee80211_regdomain *regd; |
614 | ||
615 | lockdep_assert_held(&mvm->mutex); | |
88931cc9 | 616 | |
d4a7e708 HD |
617 | if (iwl_mvm_is_vif_assoc(mvm) && notif->source_id == MCC_SOURCE_WIFI) { |
618 | IWL_DEBUG_LAR(mvm, "Ignore mcc update while associated\n"); | |
619 | return; | |
620 | } | |
621 | ||
88931cc9 | 622 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) |
0416841d | 623 | return; |
88931cc9 | 624 | |
56c1f3c4 JB |
625 | mcc[0] = le16_to_cpu(notif->mcc) >> 8; |
626 | mcc[1] = le16_to_cpu(notif->mcc) & 0xff; | |
88931cc9 | 627 | mcc[2] = '\0'; |
8ba2d7a1 | 628 | src = notif->source_id; |
88931cc9 AN |
629 | |
630 | IWL_DEBUG_LAR(mvm, | |
8ba2d7a1 EH |
631 | "RX: received chub update mcc cmd (mcc '%s' src %d)\n", |
632 | mcc, src); | |
47c8b154 | 633 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL); |
8ba2d7a1 | 634 | if (IS_ERR_OR_NULL(regd)) |
0416841d | 635 | return; |
8ba2d7a1 EH |
636 | |
637 | regulatory_set_wiphy_regd(mvm->hw->wiphy, regd); | |
638 | kfree(regd); | |
90d4f7db | 639 | } |