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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
bdccdb85 | 10 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
9c4f7d51 | 11 | * Copyright(c) 2018 Intel Corporation |
8ca151b5 JB |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of version 2 of the GNU General Public License as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
8ca151b5 | 22 | * The full GNU General Public License is included in this distribution |
410dc5aa | 23 | * in the file called COPYING. |
8ca151b5 JB |
24 | * |
25 | * Contact Information: | |
cb2f8277 | 26 | * Intel Linux Wireless <[email protected]> |
8ca151b5 JB |
27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
28 | * | |
29 | * BSD LICENSE | |
30 | * | |
51368bf7 | 31 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 32 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
bdccdb85 | 33 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
9c4f7d51 | 34 | * Copyright(c) 2018 Intel Corporation |
8ca151b5 JB |
35 | * All rights reserved. |
36 | * | |
37 | * Redistribution and use in source and binary forms, with or without | |
38 | * modification, are permitted provided that the following conditions | |
39 | * are met: | |
40 | * | |
41 | * * Redistributions of source code must retain the above copyright | |
42 | * notice, this list of conditions and the following disclaimer. | |
43 | * * Redistributions in binary form must reproduce the above copyright | |
44 | * notice, this list of conditions and the following disclaimer in | |
45 | * the documentation and/or other materials provided with the | |
46 | * distribution. | |
47 | * * Neither the name Intel Corporation nor the names of its | |
48 | * contributors may be used to endorse or promote products derived | |
49 | * from this software without specific prior written permission. | |
50 | * | |
51 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
52 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
53 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
54 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
55 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
56 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
57 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
58 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
59 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
60 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
61 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
62 | * | |
63 | *****************************************************************************/ | |
64 | #include <net/mac80211.h> | |
854d773e | 65 | #include <linux/netdevice.h> |
8ca151b5 JB |
66 | |
67 | #include "iwl-trans.h" | |
68 | #include "iwl-op-mode.h" | |
d962f9b1 | 69 | #include "fw/img.h" |
8ca151b5 JB |
70 | #include "iwl-debug.h" |
71 | #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ | |
72 | #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ | |
8c23f95c | 73 | #include "iwl-prph.h" |
813df5ce | 74 | #include "fw/acpi.h" |
8ca151b5 JB |
75 | |
76 | #include "mvm.h" | |
7174beb6 | 77 | #include "fw/dbg.h" |
8ca151b5 | 78 | #include "iwl-phy-db.h" |
9c4f7d51 ST |
79 | #include "iwl-modparams.h" |
80 | #include "iwl-nvm-parse.h" | |
8ca151b5 JB |
81 | |
82 | #define MVM_UCODE_ALIVE_TIMEOUT HZ | |
83 | #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) | |
84 | ||
85 | #define UCODE_VALID_OK cpu_to_le32(0x1) | |
86 | ||
8ca151b5 JB |
87 | struct iwl_mvm_alive_data { |
88 | bool valid; | |
89 | u32 scd_base_addr; | |
90 | }; | |
91 | ||
8ca151b5 JB |
92 | static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) |
93 | { | |
94 | struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { | |
95 | .valid = cpu_to_le32(valid_tx_ant), | |
96 | }; | |
97 | ||
33223542 | 98 | IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); |
a1022927 | 99 | return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
100 | sizeof(tx_ant_cmd), &tx_ant_cmd); |
101 | } | |
102 | ||
43413a97 SS |
103 | static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) |
104 | { | |
105 | int i; | |
106 | struct iwl_rss_config_cmd cmd = { | |
107 | .flags = cpu_to_le32(IWL_RSS_ENABLE), | |
108 | .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP | | |
854d773e | 109 | IWL_RSS_HASH_TYPE_IPV4_UDP | |
43413a97 SS |
110 | IWL_RSS_HASH_TYPE_IPV4_PAYLOAD | |
111 | IWL_RSS_HASH_TYPE_IPV6_TCP | | |
854d773e | 112 | IWL_RSS_HASH_TYPE_IPV6_UDP | |
43413a97 SS |
113 | IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, |
114 | }; | |
115 | ||
f43495fd SS |
116 | if (mvm->trans->num_rx_queues == 1) |
117 | return 0; | |
118 | ||
854d773e | 119 | /* Do not direct RSS traffic to Q 0 which is our fallback queue */ |
43413a97 | 120 | for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) |
854d773e SS |
121 | cmd.indirection_table[i] = |
122 | 1 + (i % (mvm->trans->num_rx_queues - 1)); | |
123 | netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); | |
43413a97 SS |
124 | |
125 | return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); | |
126 | } | |
127 | ||
8edbfaa1 SS |
128 | static int iwl_configure_rxq(struct iwl_mvm *mvm) |
129 | { | |
130 | int i, num_queues, size; | |
131 | struct iwl_rfh_queue_config *cmd; | |
132 | ||
133 | /* Do not configure default queue, it is configured via context info */ | |
134 | num_queues = mvm->trans->num_rx_queues - 1; | |
135 | ||
136 | size = sizeof(*cmd) + num_queues * sizeof(struct iwl_rfh_queue_data); | |
137 | ||
138 | cmd = kzalloc(size, GFP_KERNEL); | |
139 | if (!cmd) | |
140 | return -ENOMEM; | |
141 | ||
142 | cmd->num_queues = num_queues; | |
143 | ||
144 | for (i = 0; i < num_queues; i++) { | |
145 | struct iwl_trans_rxq_dma_data data; | |
146 | ||
147 | cmd->data[i].q_num = i + 1; | |
148 | iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data); | |
149 | ||
150 | cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb); | |
151 | cmd->data[i].urbd_stts_wrptr = | |
152 | cpu_to_le64(data.urbd_stts_wrptr); | |
153 | cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb); | |
154 | cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid); | |
155 | } | |
156 | ||
157 | return iwl_mvm_send_cmd_pdu(mvm, | |
158 | WIDE_ID(DATA_PATH_GROUP, | |
159 | RFH_QUEUE_CONFIG_CMD), | |
160 | 0, size, cmd); | |
161 | } | |
162 | ||
97d5be7e LK |
163 | static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) |
164 | { | |
165 | struct iwl_dqa_enable_cmd dqa_cmd = { | |
166 | .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), | |
167 | }; | |
168 | u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); | |
169 | int ret; | |
170 | ||
171 | ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); | |
172 | if (ret) | |
173 | IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); | |
174 | else | |
175 | IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); | |
176 | ||
177 | return ret; | |
178 | } | |
179 | ||
bdccdb85 GBA |
180 | void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm, |
181 | struct iwl_rx_cmd_buffer *rxb) | |
182 | { | |
183 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
184 | struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data; | |
185 | __le32 *dump_data = mfu_dump_notif->data; | |
186 | int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32); | |
187 | int i; | |
188 | ||
189 | if (mfu_dump_notif->index_num == 0) | |
190 | IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n", | |
191 | le32_to_cpu(mfu_dump_notif->assert_id)); | |
192 | ||
193 | for (i = 0; i < n_words; i++) | |
194 | IWL_DEBUG_INFO(mvm, | |
195 | "MFUART assert dump, dword %u: 0x%08x\n", | |
196 | le16_to_cpu(mfu_dump_notif->index_num) * | |
197 | n_words + i, | |
198 | le32_to_cpu(dump_data[i])); | |
199 | } | |
200 | ||
8ca151b5 JB |
201 | static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
202 | struct iwl_rx_packet *pkt, void *data) | |
203 | { | |
204 | struct iwl_mvm *mvm = | |
205 | container_of(notif_wait, struct iwl_mvm, notif_wait); | |
206 | struct iwl_mvm_alive_data *alive_data = data; | |
5c228d63 | 207 | struct mvm_alive_resp_v3 *palive3; |
7e1223b5 | 208 | struct mvm_alive_resp *palive; |
5c228d63 SS |
209 | struct iwl_umac_alive *umac; |
210 | struct iwl_lmac_alive *lmac1; | |
211 | struct iwl_lmac_alive *lmac2 = NULL; | |
212 | u16 status; | |
3485e76e | 213 | u32 umac_error_event_table; |
01a9ca51 | 214 | |
5c228d63 SS |
215 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { |
216 | palive = (void *)pkt->data; | |
217 | umac = &palive->umac_data; | |
218 | lmac1 = &palive->lmac_data[0]; | |
219 | lmac2 = &palive->lmac_data[1]; | |
220 | status = le16_to_cpu(palive->status); | |
221 | } else { | |
222 | palive3 = (void *)pkt->data; | |
223 | umac = &palive3->umac_data; | |
224 | lmac1 = &palive3->lmac_data; | |
225 | status = le16_to_cpu(palive3->status); | |
226 | } | |
01a9ca51 | 227 | |
5c228d63 SS |
228 | mvm->error_event_table[0] = le32_to_cpu(lmac1->error_event_table_ptr); |
229 | if (lmac2) | |
230 | mvm->error_event_table[1] = | |
231 | le32_to_cpu(lmac2->error_event_table_ptr); | |
232 | mvm->log_event_table = le32_to_cpu(lmac1->log_event_table_ptr); | |
ffa70264 | 233 | |
3485e76e | 234 | umac_error_event_table = le32_to_cpu(umac->error_info_addr); |
01a9ca51 | 235 | |
3485e76e LC |
236 | if (!umac_error_event_table) { |
237 | mvm->support_umac_log = false; | |
238 | } else if (umac_error_event_table >= | |
239 | mvm->trans->cfg->min_umac_error_event_table) { | |
240 | mvm->support_umac_log = true; | |
241 | mvm->umac_error_event_table = umac_error_event_table; | |
242 | } else { | |
fb5b2846 LC |
243 | IWL_ERR(mvm, |
244 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
245 | mvm->umac_error_event_table, | |
246 | (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ? | |
247 | "Init" : "RT"); | |
3485e76e LC |
248 | mvm->support_umac_log = false; |
249 | } | |
fb5b2846 | 250 | |
5c228d63 SS |
251 | alive_data->scd_base_addr = le32_to_cpu(lmac1->scd_base_ptr); |
252 | alive_data->valid = status == IWL_ALIVE_STATUS_OK; | |
7e1223b5 | 253 | |
5c228d63 SS |
254 | IWL_DEBUG_FW(mvm, |
255 | "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", | |
256 | status, lmac1->ver_type, lmac1->ver_subtype); | |
7e1223b5 | 257 | |
5c228d63 SS |
258 | if (lmac2) |
259 | IWL_DEBUG_FW(mvm, "Alive ucode CDB\n"); | |
7e1223b5 | 260 | |
5c228d63 SS |
261 | IWL_DEBUG_FW(mvm, |
262 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
263 | le32_to_cpu(umac->umac_major), | |
264 | le32_to_cpu(umac->umac_minor)); | |
8ca151b5 JB |
265 | |
266 | return true; | |
267 | } | |
268 | ||
1f370650 SS |
269 | static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait, |
270 | struct iwl_rx_packet *pkt, void *data) | |
271 | { | |
272 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
273 | ||
274 | return true; | |
275 | } | |
276 | ||
8ca151b5 JB |
277 | static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, |
278 | struct iwl_rx_packet *pkt, void *data) | |
279 | { | |
280 | struct iwl_phy_db *phy_db = data; | |
281 | ||
282 | if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { | |
283 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
284 | return true; | |
285 | } | |
286 | ||
ce1f2778 | 287 | WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); |
8ca151b5 JB |
288 | |
289 | return false; | |
290 | } | |
291 | ||
292 | static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, | |
293 | enum iwl_ucode_type ucode_type) | |
294 | { | |
295 | struct iwl_notification_wait alive_wait; | |
296 | struct iwl_mvm_alive_data alive_data; | |
297 | const struct fw_img *fw; | |
298 | int ret, i; | |
702e975d | 299 | enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img; |
6eb031d2 | 300 | static const u16 alive_cmd[] = { MVM_ALIVE }; |
8ca151b5 | 301 | |
f38efdb2 | 302 | set_bit(IWL_FWRT_STATUS_WAIT_ALIVE, &mvm->fwrt.status); |
61df750c | 303 | if (ucode_type == IWL_UCODE_REGULAR && |
3d2d4422 GBA |
304 | iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && |
305 | !(fw_has_capa(&mvm->fw->ucode_capa, | |
306 | IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) | |
612da1ef | 307 | fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER); |
61df750c | 308 | else |
612da1ef | 309 | fw = iwl_get_ucode_image(mvm->fw, ucode_type); |
befe9b6f | 310 | if (WARN_ON(!fw)) |
8ca151b5 | 311 | return -EINVAL; |
702e975d | 312 | iwl_fw_set_current_image(&mvm->fwrt, ucode_type); |
65b280fe | 313 | clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); |
8ca151b5 JB |
314 | |
315 | iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, | |
316 | alive_cmd, ARRAY_SIZE(alive_cmd), | |
317 | iwl_alive_fn, &alive_data); | |
318 | ||
319 | ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT); | |
320 | if (ret) { | |
702e975d | 321 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
322 | iwl_remove_notification(&mvm->notif_wait, &alive_wait); |
323 | return ret; | |
324 | } | |
325 | ||
326 | /* | |
327 | * Some things may run in the background now, but we | |
328 | * just wait for the ALIVE notification here. | |
329 | */ | |
330 | ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, | |
331 | MVM_UCODE_ALIVE_TIMEOUT); | |
332 | if (ret) { | |
d6be9c1d SS |
333 | struct iwl_trans *trans = mvm->trans; |
334 | ||
5f01df3f | 335 | if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) |
d6be9c1d SS |
336 | IWL_ERR(mvm, |
337 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
338 | iwl_read_prph(trans, UMAG_SB_CPU_1_STATUS), | |
339 | iwl_read_prph(trans, UMAG_SB_CPU_2_STATUS)); | |
6e584873 | 340 | else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) |
192de2b4 DS |
341 | IWL_ERR(mvm, |
342 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
d6be9c1d SS |
343 | iwl_read_prph(trans, SB_CPU_1_STATUS), |
344 | iwl_read_prph(trans, SB_CPU_2_STATUS)); | |
702e975d | 345 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
346 | return ret; |
347 | } | |
348 | ||
349 | if (!alive_data.valid) { | |
350 | IWL_ERR(mvm, "Loaded ucode is not valid!\n"); | |
702e975d | 351 | iwl_fw_set_current_image(&mvm->fwrt, old_type); |
8ca151b5 JB |
352 | return -EIO; |
353 | } | |
354 | ||
355 | iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); | |
356 | ||
357 | /* | |
358 | * Note: all the queues are enabled as part of the interface | |
359 | * initialization, but in firmware restart scenarios they | |
360 | * could be stopped, so wake them up. In firmware restart, | |
361 | * mac80211 will have the queues stopped as well until the | |
362 | * reconfiguration completes. During normal startup, they | |
363 | * will be empty. | |
364 | */ | |
365 | ||
4ecafae9 | 366 | memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); |
1c14089e JB |
367 | /* |
368 | * Set a 'fake' TID for the command queue, since we use the | |
369 | * hweight() of the tid_bitmap as a refcount now. Not that | |
370 | * we ever even consider the command queue as one we might | |
371 | * want to reuse, but be safe nevertheless. | |
372 | */ | |
373 | mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap = | |
374 | BIT(IWL_MAX_TID_COUNT + 2); | |
8ca151b5 | 375 | |
df197c00 JB |
376 | for (i = 0; i < IEEE80211_MAX_QUEUES; i++) |
377 | atomic_set(&mvm->mac80211_queue_stop_count[i], 0); | |
8ca151b5 | 378 | |
65b280fe | 379 | set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); |
f38efdb2 | 380 | clear_bit(IWL_FWRT_STATUS_WAIT_ALIVE, &mvm->fwrt.status); |
8ca151b5 JB |
381 | |
382 | return 0; | |
383 | } | |
8ca151b5 | 384 | |
8c5f47b1 JB |
385 | static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
386 | { | |
387 | struct iwl_notification_wait init_wait; | |
388 | struct iwl_nvm_access_complete_cmd nvm_complete = {}; | |
389 | struct iwl_init_extended_cfg_cmd init_cfg = { | |
390 | .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), | |
391 | }; | |
392 | static const u16 init_complete[] = { | |
393 | INIT_COMPLETE_NOTIF, | |
394 | }; | |
395 | int ret; | |
396 | ||
397 | lockdep_assert_held(&mvm->mutex); | |
398 | ||
399 | iwl_init_notification_wait(&mvm->notif_wait, | |
400 | &init_wait, | |
401 | init_complete, | |
402 | ARRAY_SIZE(init_complete), | |
403 | iwl_wait_init_complete, | |
404 | NULL); | |
405 | ||
406 | /* Will also start the device */ | |
407 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
408 | if (ret) { | |
409 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
410 | goto error; | |
411 | } | |
412 | ||
413 | /* Send init config command to mark that we are sending NVM access | |
414 | * commands | |
415 | */ | |
416 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP, | |
417 | INIT_EXTENDED_CFG_CMD), 0, | |
418 | sizeof(init_cfg), &init_cfg); | |
419 | if (ret) { | |
420 | IWL_ERR(mvm, "Failed to run init config command: %d\n", | |
421 | ret); | |
422 | goto error; | |
423 | } | |
424 | ||
e9e1ba3d SS |
425 | /* Load NVM to NIC if needed */ |
426 | if (mvm->nvm_file_name) { | |
9c4f7d51 ST |
427 | iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, |
428 | mvm->nvm_sections); | |
8c5f47b1 | 429 | iwl_mvm_load_nvm_to_nic(mvm); |
e9e1ba3d | 430 | } |
8c5f47b1 | 431 | |
d4f3695e | 432 | if (IWL_MVM_PARSE_NVM && read_nvm) { |
5bd1d2c1 | 433 | ret = iwl_nvm_init(mvm); |
d4f3695e SS |
434 | if (ret) { |
435 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
436 | goto error; | |
437 | } | |
438 | } | |
439 | ||
8c5f47b1 JB |
440 | ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, |
441 | NVM_ACCESS_COMPLETE), 0, | |
442 | sizeof(nvm_complete), &nvm_complete); | |
443 | if (ret) { | |
444 | IWL_ERR(mvm, "Failed to run complete NVM access: %d\n", | |
445 | ret); | |
446 | goto error; | |
447 | } | |
448 | ||
449 | /* We wait for the INIT complete notification */ | |
e9e1ba3d SS |
450 | ret = iwl_wait_notification(&mvm->notif_wait, &init_wait, |
451 | MVM_UCODE_ALIVE_TIMEOUT); | |
452 | if (ret) | |
453 | return ret; | |
454 | ||
455 | /* Read the NVM only at driver load time, no need to do this twice */ | |
d4f3695e | 456 | if (!IWL_MVM_PARSE_NVM && read_nvm) { |
4c625c56 | 457 | mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw); |
c135cb56 ST |
458 | if (IS_ERR(mvm->nvm_data)) { |
459 | ret = PTR_ERR(mvm->nvm_data); | |
460 | mvm->nvm_data = NULL; | |
e9e1ba3d SS |
461 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); |
462 | return ret; | |
463 | } | |
464 | } | |
465 | ||
466 | return 0; | |
8c5f47b1 JB |
467 | |
468 | error: | |
469 | iwl_remove_notification(&mvm->notif_wait, &init_wait); | |
470 | return ret; | |
471 | } | |
472 | ||
8ca151b5 JB |
473 | static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) |
474 | { | |
475 | struct iwl_phy_cfg_cmd phy_cfg_cmd; | |
702e975d | 476 | enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img; |
8ca151b5 JB |
477 | |
478 | /* Set parameters */ | |
a0544272 | 479 | phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); |
86a2b204 LC |
480 | |
481 | /* set flags extra PHY configuration flags from the device's cfg */ | |
482 | phy_cfg_cmd.phy_cfg |= cpu_to_le32(mvm->cfg->extra_phy_cfg_flags); | |
483 | ||
8ca151b5 JB |
484 | phy_cfg_cmd.calib_control.event_trigger = |
485 | mvm->fw->default_calib[ucode_type].event_trigger; | |
486 | phy_cfg_cmd.calib_control.flow_trigger = | |
487 | mvm->fw->default_calib[ucode_type].flow_trigger; | |
488 | ||
489 | IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", | |
490 | phy_cfg_cmd.phy_cfg); | |
491 | ||
a1022927 | 492 | return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
493 | sizeof(phy_cfg_cmd), &phy_cfg_cmd); |
494 | } | |
495 | ||
8ca151b5 JB |
496 | int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
497 | { | |
498 | struct iwl_notification_wait calib_wait; | |
6eb031d2 | 499 | static const u16 init_complete[] = { |
8ca151b5 JB |
500 | INIT_COMPLETE_NOTIF, |
501 | CALIB_RES_NOTIF_PHY_DB | |
502 | }; | |
503 | int ret; | |
504 | ||
7d6222e2 | 505 | if (iwl_mvm_has_unified_ucode(mvm)) |
8c5f47b1 JB |
506 | return iwl_run_unified_mvm_ucode(mvm, true); |
507 | ||
8ca151b5 JB |
508 | lockdep_assert_held(&mvm->mutex); |
509 | ||
8d193ca2 | 510 | if (WARN_ON_ONCE(mvm->calibrating)) |
8ca151b5 JB |
511 | return 0; |
512 | ||
513 | iwl_init_notification_wait(&mvm->notif_wait, | |
514 | &calib_wait, | |
515 | init_complete, | |
516 | ARRAY_SIZE(init_complete), | |
517 | iwl_wait_phy_db_entry, | |
518 | mvm->phy_db); | |
519 | ||
520 | /* Will also start the device */ | |
521 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); | |
522 | if (ret) { | |
523 | IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); | |
00e0c6c8 | 524 | goto remove_notif; |
8ca151b5 JB |
525 | } |
526 | ||
b3de3ef4 EG |
527 | if (mvm->cfg->device_family < IWL_DEVICE_FAMILY_8000) { |
528 | ret = iwl_mvm_send_bt_init_conf(mvm); | |
529 | if (ret) | |
00e0c6c8 | 530 | goto remove_notif; |
b3de3ef4 | 531 | } |
931d4160 | 532 | |
81a67e32 | 533 | /* Read the NVM only at driver load time, no need to do this twice */ |
8ca151b5 | 534 | if (read_nvm) { |
5bd1d2c1 | 535 | ret = iwl_nvm_init(mvm); |
8ca151b5 JB |
536 | if (ret) { |
537 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
00e0c6c8 | 538 | goto remove_notif; |
8ca151b5 JB |
539 | } |
540 | } | |
541 | ||
81a67e32 | 542 | /* In case we read the NVM from external file, load it to the NIC */ |
e02a9d60 | 543 | if (mvm->nvm_file_name) |
81a67e32 EL |
544 | iwl_mvm_load_nvm_to_nic(mvm); |
545 | ||
00e0c6c8 | 546 | WARN_ON(iwl_nvm_check_version(mvm->nvm_data, mvm->trans)); |
8ca151b5 | 547 | |
4f59334b EH |
548 | /* |
549 | * abort after reading the nvm in case RF Kill is on, we will complete | |
550 | * the init seq later when RF kill will switch to off | |
551 | */ | |
1a3fe0b2 | 552 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
4f59334b EH |
553 | IWL_DEBUG_RF_KILL(mvm, |
554 | "jump over all phy activities due to RF kill\n"); | |
00e0c6c8 | 555 | goto remove_notif; |
4f59334b EH |
556 | } |
557 | ||
31b8b343 EG |
558 | mvm->calibrating = true; |
559 | ||
e07cbb53 | 560 | /* Send TX valid antennas before triggering calibrations */ |
a0544272 | 561 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
e07cbb53 | 562 | if (ret) |
00e0c6c8 | 563 | goto remove_notif; |
e07cbb53 | 564 | |
8ca151b5 JB |
565 | ret = iwl_send_phy_cfg_cmd(mvm); |
566 | if (ret) { | |
567 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
568 | ret); | |
00e0c6c8 | 569 | goto remove_notif; |
8ca151b5 JB |
570 | } |
571 | ||
572 | /* | |
573 | * Some things may run in the background now, but we | |
574 | * just wait for the calibration complete notification. | |
575 | */ | |
576 | ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, | |
00e0c6c8 LC |
577 | MVM_UCODE_CALIB_TIMEOUT); |
578 | if (!ret) | |
579 | goto out; | |
31b8b343 | 580 | |
00e0c6c8 | 581 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
31b8b343 | 582 | IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); |
00e0c6c8 LC |
583 | ret = 0; |
584 | } else { | |
585 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
586 | ret); | |
31b8b343 | 587 | } |
00e0c6c8 | 588 | |
8ca151b5 JB |
589 | goto out; |
590 | ||
00e0c6c8 | 591 | remove_notif: |
8ca151b5 JB |
592 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); |
593 | out: | |
31b8b343 | 594 | mvm->calibrating = false; |
a4082843 | 595 | if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { |
8ca151b5 JB |
596 | /* we want to debug INIT and we have no NVM - fake */ |
597 | mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + | |
598 | sizeof(struct ieee80211_channel) + | |
599 | sizeof(struct ieee80211_rate), | |
600 | GFP_KERNEL); | |
601 | if (!mvm->nvm_data) | |
602 | return -ENOMEM; | |
8ca151b5 JB |
603 | mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; |
604 | mvm->nvm_data->bands[0].n_channels = 1; | |
605 | mvm->nvm_data->bands[0].n_bitrates = 1; | |
606 | mvm->nvm_data->bands[0].bitrates = | |
607 | (void *)mvm->nvm_data->channels + 1; | |
608 | mvm->nvm_data->bands[0].bitrates->hw_value = 10; | |
609 | } | |
610 | ||
611 | return ret; | |
612 | } | |
613 | ||
84bfffa9 EG |
614 | static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) |
615 | { | |
616 | struct iwl_ltr_config_cmd cmd = { | |
617 | .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), | |
618 | }; | |
619 | ||
620 | if (!mvm->trans->ltr_enabled) | |
621 | return 0; | |
622 | ||
84bfffa9 EG |
623 | return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, |
624 | sizeof(cmd), &cmd); | |
625 | } | |
626 | ||
c386dacb | 627 | #ifdef CONFIG_ACPI |
c386dacb HD |
628 | static int iwl_mvm_sar_set_profile(struct iwl_mvm *mvm, |
629 | union acpi_object *table, | |
630 | struct iwl_mvm_sar_profile *profile, | |
631 | bool enabled) | |
632 | { | |
633 | int i; | |
da2830ac | 634 | |
c386dacb | 635 | profile->enabled = enabled; |
da2830ac | 636 | |
e7a3b8d8 | 637 | for (i = 0; i < ACPI_SAR_TABLE_SIZE; i++) { |
c386dacb HD |
638 | if ((table[i].type != ACPI_TYPE_INTEGER) || |
639 | (table[i].integer.value > U8_MAX)) | |
640 | return -EINVAL; | |
641 | ||
642 | profile->table[i] = table[i].integer.value; | |
643 | } | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
c386dacb | 648 | static int iwl_mvm_sar_get_wrds_table(struct iwl_mvm *mvm) |
da2830ac | 649 | { |
813df5ce | 650 | union acpi_object *wifi_pkg, *table, *data; |
c386dacb | 651 | bool enabled; |
da2830ac LC |
652 | int ret; |
653 | ||
813df5ce LC |
654 | data = iwl_acpi_get_object(mvm->dev, ACPI_WRDS_METHOD); |
655 | if (IS_ERR(data)) | |
656 | return PTR_ERR(data); | |
da2830ac | 657 | |
2fa388cf LC |
658 | wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, |
659 | ACPI_WRDS_WIFI_DATA_SIZE); | |
c386dacb HD |
660 | if (IS_ERR(wifi_pkg)) { |
661 | ret = PTR_ERR(wifi_pkg); | |
662 | goto out_free; | |
663 | } | |
664 | ||
665 | if (wifi_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) { | |
666 | ret = -EINVAL; | |
667 | goto out_free; | |
668 | } | |
669 | ||
670 | enabled = !!(wifi_pkg->package.elements[1].integer.value); | |
da2830ac | 671 | |
c386dacb HD |
672 | /* position of the actual table */ |
673 | table = &wifi_pkg->package.elements[2]; | |
674 | ||
675 | /* The profile from WRDS is officially profile 1, but goes | |
676 | * into sar_profiles[0] (because we don't have a profile 0). | |
677 | */ | |
678 | ret = iwl_mvm_sar_set_profile(mvm, table, &mvm->sar_profiles[0], | |
679 | enabled); | |
c386dacb | 680 | out_free: |
813df5ce | 681 | kfree(data); |
da2830ac LC |
682 | return ret; |
683 | } | |
da2830ac | 684 | |
69964905 LC |
685 | static int iwl_mvm_sar_get_ewrd_table(struct iwl_mvm *mvm) |
686 | { | |
813df5ce | 687 | union acpi_object *wifi_pkg, *data; |
69964905 LC |
688 | bool enabled; |
689 | int i, n_profiles, ret; | |
690 | ||
813df5ce LC |
691 | data = iwl_acpi_get_object(mvm->dev, ACPI_EWRD_METHOD); |
692 | if (IS_ERR(data)) | |
693 | return PTR_ERR(data); | |
69964905 | 694 | |
2fa388cf LC |
695 | wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, |
696 | ACPI_EWRD_WIFI_DATA_SIZE); | |
69964905 LC |
697 | if (IS_ERR(wifi_pkg)) { |
698 | ret = PTR_ERR(wifi_pkg); | |
699 | goto out_free; | |
700 | } | |
701 | ||
702 | if ((wifi_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) || | |
703 | (wifi_pkg->package.elements[2].type != ACPI_TYPE_INTEGER)) { | |
704 | ret = -EINVAL; | |
705 | goto out_free; | |
706 | } | |
707 | ||
708 | enabled = !!(wifi_pkg->package.elements[1].integer.value); | |
709 | n_profiles = wifi_pkg->package.elements[2].integer.value; | |
710 | ||
2e1976bb LC |
711 | /* |
712 | * Check the validity of n_profiles. The EWRD profiles start | |
713 | * from index 1, so the maximum value allowed here is | |
714 | * ACPI_SAR_PROFILES_NUM - 1. | |
715 | */ | |
716 | if (n_profiles <= 0 || n_profiles >= ACPI_SAR_PROFILE_NUM) { | |
e2ef1476 SD |
717 | ret = -EINVAL; |
718 | goto out_free; | |
719 | } | |
720 | ||
69964905 LC |
721 | for (i = 0; i < n_profiles; i++) { |
722 | /* the tables start at element 3 */ | |
723 | static int pos = 3; | |
724 | ||
725 | /* The EWRD profiles officially go from 2 to 4, but we | |
726 | * save them in sar_profiles[1-3] (because we don't | |
727 | * have profile 0). So in the array we start from 1. | |
728 | */ | |
729 | ret = iwl_mvm_sar_set_profile(mvm, | |
730 | &wifi_pkg->package.elements[pos], | |
731 | &mvm->sar_profiles[i + 1], | |
732 | enabled); | |
733 | if (ret < 0) | |
734 | break; | |
735 | ||
736 | /* go to the next table */ | |
e7a3b8d8 | 737 | pos += ACPI_SAR_TABLE_SIZE; |
69964905 LC |
738 | } |
739 | ||
740 | out_free: | |
813df5ce | 741 | kfree(data); |
69964905 LC |
742 | return ret; |
743 | } | |
744 | ||
7fe90e0e | 745 | static int iwl_mvm_sar_get_wgds_table(struct iwl_mvm *mvm) |
a6bff3cb | 746 | { |
813df5ce | 747 | union acpi_object *wifi_pkg, *data; |
7fe90e0e HD |
748 | int i, j, ret; |
749 | int idx = 1; | |
a6bff3cb | 750 | |
813df5ce LC |
751 | data = iwl_acpi_get_object(mvm->dev, ACPI_WGDS_METHOD); |
752 | if (IS_ERR(data)) | |
753 | return PTR_ERR(data); | |
a6bff3cb | 754 | |
2fa388cf LC |
755 | wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, |
756 | ACPI_WGDS_WIFI_DATA_SIZE); | |
a6bff3cb HD |
757 | if (IS_ERR(wifi_pkg)) { |
758 | ret = PTR_ERR(wifi_pkg); | |
759 | goto out_free; | |
760 | } | |
761 | ||
e7a3b8d8 LC |
762 | for (i = 0; i < ACPI_NUM_GEO_PROFILES; i++) { |
763 | for (j = 0; j < ACPI_GEO_TABLE_SIZE; j++) { | |
7fe90e0e | 764 | union acpi_object *entry; |
a6bff3cb | 765 | |
7fe90e0e HD |
766 | entry = &wifi_pkg->package.elements[idx++]; |
767 | if ((entry->type != ACPI_TYPE_INTEGER) || | |
aae9d563 CJ |
768 | (entry->integer.value > U8_MAX)) { |
769 | ret = -EINVAL; | |
770 | goto out_free; | |
771 | } | |
a6bff3cb | 772 | |
7fe90e0e HD |
773 | mvm->geo_profiles[i].values[j] = entry->integer.value; |
774 | } | |
a6bff3cb HD |
775 | } |
776 | ret = 0; | |
777 | out_free: | |
813df5ce | 778 | kfree(data); |
a6bff3cb HD |
779 | return ret; |
780 | } | |
781 | ||
42ce76d6 | 782 | int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) |
da2830ac | 783 | { |
0791c2fc HD |
784 | union { |
785 | struct iwl_dev_tx_power_cmd v5; | |
786 | struct iwl_dev_tx_power_cmd_v4 v4; | |
787 | } cmd; | |
42ce76d6 | 788 | int i, j, idx; |
e7a3b8d8 | 789 | int profs[ACPI_SAR_NUM_CHAIN_LIMITS] = { prof_a, prof_b }; |
0791c2fc | 790 | int len; |
da2830ac | 791 | |
e7a3b8d8 LC |
792 | BUILD_BUG_ON(ACPI_SAR_NUM_CHAIN_LIMITS < 2); |
793 | BUILD_BUG_ON(ACPI_SAR_NUM_CHAIN_LIMITS * ACPI_SAR_NUM_SUB_BANDS != | |
794 | ACPI_SAR_TABLE_SIZE); | |
42ce76d6 | 795 | |
0791c2fc HD |
796 | cmd.v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS); |
797 | ||
798 | if (fw_has_api(&mvm->fw->ucode_capa, | |
799 | IWL_UCODE_TLV_API_REDUCE_TX_POWER)) | |
800 | len = sizeof(cmd.v5); | |
801 | else if (fw_has_capa(&mvm->fw->ucode_capa, | |
802 | IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) | |
803 | len = sizeof(cmd.v4); | |
804 | else | |
805 | len = sizeof(cmd.v4.v3); | |
55bfa4b9 | 806 | |
e7a3b8d8 | 807 | for (i = 0; i < ACPI_SAR_NUM_CHAIN_LIMITS; i++) { |
42ce76d6 | 808 | struct iwl_mvm_sar_profile *prof; |
da2830ac | 809 | |
42ce76d6 LC |
810 | /* don't allow SAR to be disabled (profile 0 means disable) */ |
811 | if (profs[i] == 0) | |
812 | return -EPERM; | |
da2830ac | 813 | |
e7a3b8d8 LC |
814 | /* we are off by one, so allow up to ACPI_SAR_PROFILE_NUM */ |
815 | if (profs[i] > ACPI_SAR_PROFILE_NUM) | |
42ce76d6 | 816 | return -EINVAL; |
da2830ac | 817 | |
42ce76d6 LC |
818 | /* profiles go from 1 to 4, so decrement to access the array */ |
819 | prof = &mvm->sar_profiles[profs[i] - 1]; | |
820 | ||
821 | /* if the profile is disabled, do nothing */ | |
822 | if (!prof->enabled) { | |
823 | IWL_DEBUG_RADIO(mvm, "SAR profile %d is disabled.\n", | |
824 | profs[i]); | |
825 | /* if one of the profiles is disabled, we fail all */ | |
826 | return -ENOENT; | |
827 | } | |
da2830ac | 828 | |
da2830ac | 829 | IWL_DEBUG_RADIO(mvm, " Chain[%d]:\n", i); |
e7a3b8d8 LC |
830 | for (j = 0; j < ACPI_SAR_NUM_SUB_BANDS; j++) { |
831 | idx = (i * ACPI_SAR_NUM_SUB_BANDS) + j; | |
0791c2fc | 832 | cmd.v5.v3.per_chain_restriction[i][j] = |
42ce76d6 | 833 | cpu_to_le16(prof->table[idx]); |
da2830ac | 834 | IWL_DEBUG_RADIO(mvm, " Band[%d] = %d * .125dBm\n", |
42ce76d6 | 835 | j, prof->table[idx]); |
da2830ac LC |
836 | } |
837 | } | |
838 | ||
42ce76d6 LC |
839 | IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); |
840 | ||
841 | return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd); | |
842 | } | |
843 | ||
7fe90e0e HD |
844 | int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) |
845 | { | |
846 | struct iwl_geo_tx_power_profiles_resp *resp; | |
847 | int ret; | |
848 | ||
849 | struct iwl_geo_tx_power_profiles_cmd geo_cmd = { | |
850 | .ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE), | |
851 | }; | |
852 | struct iwl_host_cmd cmd = { | |
853 | .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), | |
854 | .len = { sizeof(geo_cmd), }, | |
855 | .flags = CMD_WANT_SKB, | |
856 | .data = { &geo_cmd }, | |
857 | }; | |
858 | ||
859 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
860 | if (ret) { | |
861 | IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret); | |
862 | return ret; | |
863 | } | |
864 | ||
865 | resp = (void *)cmd.resp_pkt->data; | |
866 | ret = le32_to_cpu(resp->profile_idx); | |
e7a3b8d8 | 867 | if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES)) { |
7fe90e0e HD |
868 | ret = -EIO; |
869 | IWL_WARN(mvm, "Invalid geographic profile idx (%d)\n", ret); | |
870 | } | |
871 | ||
872 | iwl_free_resp(&cmd); | |
873 | return ret; | |
874 | } | |
875 | ||
a6bff3cb HD |
876 | static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) |
877 | { | |
a6bff3cb HD |
878 | struct iwl_geo_tx_power_profiles_cmd cmd = { |
879 | .ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES), | |
880 | }; | |
7fe90e0e | 881 | int ret, i, j; |
a6bff3cb HD |
882 | u16 cmd_wide_id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT); |
883 | ||
7fe90e0e | 884 | ret = iwl_mvm_sar_get_wgds_table(mvm); |
a6bff3cb HD |
885 | if (ret < 0) { |
886 | IWL_DEBUG_RADIO(mvm, | |
887 | "Geo SAR BIOS table invalid or unavailable. (%d)\n", | |
888 | ret); | |
889 | /* we don't fail if the table is not available */ | |
890 | return 0; | |
891 | } | |
892 | ||
893 | IWL_DEBUG_RADIO(mvm, "Sending GEO_TX_POWER_LIMIT\n"); | |
894 | ||
e7a3b8d8 | 895 | BUILD_BUG_ON(ACPI_NUM_GEO_PROFILES * ACPI_WGDS_NUM_BANDS * |
66e83903 | 896 | ACPI_WGDS_TABLE_SIZE + 1 != ACPI_WGDS_WIFI_DATA_SIZE); |
a6bff3cb | 897 | |
e7a3b8d8 LC |
898 | BUILD_BUG_ON(ACPI_NUM_GEO_PROFILES > IWL_NUM_GEO_PROFILES); |
899 | ||
900 | for (i = 0; i < ACPI_NUM_GEO_PROFILES; i++) { | |
a6bff3cb HD |
901 | struct iwl_per_chain_offset *chain = |
902 | (struct iwl_per_chain_offset *)&cmd.table[i]; | |
903 | ||
904 | for (j = 0; j < ACPI_WGDS_NUM_BANDS; j++) { | |
905 | u8 *value; | |
906 | ||
7fe90e0e | 907 | value = &mvm->geo_profiles[i].values[j * |
e7a3b8d8 | 908 | ACPI_GEO_PER_CHAIN_SIZE]; |
a6bff3cb HD |
909 | chain[j].max_tx_power = cpu_to_le16(value[0]); |
910 | chain[j].chain_a = value[1]; | |
911 | chain[j].chain_b = value[2]; | |
912 | IWL_DEBUG_RADIO(mvm, | |
913 | "SAR geographic profile[%d] Band[%d]: chain A = %d chain B = %d max_tx_power = %d\n", | |
914 | i, j, value[1], value[2], value[0]); | |
915 | } | |
916 | } | |
917 | return iwl_mvm_send_cmd_pdu(mvm, cmd_wide_id, 0, sizeof(cmd), &cmd); | |
918 | } | |
919 | ||
69964905 LC |
920 | #else /* CONFIG_ACPI */ |
921 | static int iwl_mvm_sar_get_wrds_table(struct iwl_mvm *mvm) | |
922 | { | |
923 | return -ENOENT; | |
924 | } | |
925 | ||
926 | static int iwl_mvm_sar_get_ewrd_table(struct iwl_mvm *mvm) | |
927 | { | |
928 | return -ENOENT; | |
929 | } | |
a6bff3cb | 930 | |
5d041c46 LC |
931 | static int iwl_mvm_sar_get_wgds_table(struct iwl_mvm *mvm) |
932 | { | |
933 | return -ENOENT; | |
934 | } | |
935 | ||
a6bff3cb HD |
936 | static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) |
937 | { | |
938 | return 0; | |
939 | } | |
18f1755d LC |
940 | |
941 | int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, | |
942 | int prof_b) | |
943 | { | |
944 | return -ENOENT; | |
945 | } | |
946 | ||
947 | int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) | |
948 | { | |
949 | return -ENOENT; | |
950 | } | |
69964905 LC |
951 | #endif /* CONFIG_ACPI */ |
952 | ||
42ce76d6 LC |
953 | static int iwl_mvm_sar_init(struct iwl_mvm *mvm) |
954 | { | |
955 | int ret; | |
956 | ||
957 | ret = iwl_mvm_sar_get_wrds_table(mvm); | |
958 | if (ret < 0) { | |
959 | IWL_DEBUG_RADIO(mvm, | |
69964905 | 960 | "WRDS SAR BIOS table invalid or unavailable. (%d)\n", |
42ce76d6 | 961 | ret); |
5d041c46 LC |
962 | /* |
963 | * If not available, don't fail and don't bother with EWRD. | |
964 | * Return 1 to tell that we can't use WGDS either. | |
965 | */ | |
966 | return 1; | |
42ce76d6 LC |
967 | } |
968 | ||
69964905 LC |
969 | ret = iwl_mvm_sar_get_ewrd_table(mvm); |
970 | /* if EWRD is not available, we can still use WRDS, so don't fail */ | |
971 | if (ret < 0) | |
972 | IWL_DEBUG_RADIO(mvm, | |
973 | "EWRD SAR BIOS table invalid or unavailable. (%d)\n", | |
974 | ret); | |
975 | ||
42ce76d6 LC |
976 | /* choose profile 1 (WRDS) as default for both chains */ |
977 | ret = iwl_mvm_sar_select_profile(mvm, 1, 1); | |
978 | ||
5d041c46 LC |
979 | /* |
980 | * If we don't have profile 0 from BIOS, just skip it. This | |
981 | * means that SAR Geo will not be enabled either, even if we | |
982 | * have other valid profiles. | |
983 | */ | |
42ce76d6 | 984 | if (ret == -ENOENT) |
5d041c46 | 985 | return 1; |
da2830ac LC |
986 | |
987 | return ret; | |
988 | } | |
989 | ||
1f370650 | 990 | static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm) |
8ca151b5 | 991 | { |
1f370650 | 992 | int ret; |
8ca151b5 | 993 | |
7d6222e2 | 994 | if (iwl_mvm_has_unified_ucode(mvm)) |
1f370650 | 995 | return iwl_run_unified_mvm_ucode(mvm, false); |
8ca151b5 | 996 | |
8d193ca2 | 997 | ret = iwl_run_init_mvm_ucode(mvm, false); |
f2082a53 | 998 | |
f2082a53 | 999 | if (ret) { |
8d193ca2 | 1000 | IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); |
f4744258 LK |
1001 | |
1002 | if (iwlmvm_mod_params.init_dbg) | |
1003 | return 0; | |
1f370650 | 1004 | return ret; |
8d193ca2 | 1005 | } |
8ca151b5 | 1006 | |
f2082a53 SS |
1007 | /* |
1008 | * Stop and start the transport without entering low power | |
1009 | * mode. This will save the state of other components on the | |
1010 | * device that are triggered by the INIT firwmare (MFUART). | |
1011 | */ | |
1012 | _iwl_trans_stop_device(mvm->trans, false); | |
1013 | ret = _iwl_trans_start_hw(mvm->trans, false); | |
1014 | if (ret) | |
1f370650 | 1015 | return ret; |
8ca151b5 JB |
1016 | |
1017 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
1f370650 SS |
1018 | if (ret) |
1019 | return ret; | |
1020 | ||
702e975d | 1021 | return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img); |
1f370650 SS |
1022 | } |
1023 | ||
1024 | int iwl_mvm_up(struct iwl_mvm *mvm) | |
1025 | { | |
1026 | int ret, i; | |
1027 | struct ieee80211_channel *chan; | |
1028 | struct cfg80211_chan_def chandef; | |
1029 | ||
1030 | lockdep_assert_held(&mvm->mutex); | |
1031 | ||
1032 | ret = iwl_trans_start_hw(mvm->trans); | |
1033 | if (ret) | |
1034 | return ret; | |
1035 | ||
1036 | ret = iwl_mvm_load_rt_fw(mvm); | |
8ca151b5 JB |
1037 | if (ret) { |
1038 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
1039 | goto error; | |
1040 | } | |
1041 | ||
d0b813fc | 1042 | iwl_get_shared_mem_conf(&mvm->fwrt); |
04fd2c28 | 1043 | |
1f3b0ff8 LE |
1044 | ret = iwl_mvm_sf_update(mvm, NULL, false); |
1045 | if (ret) | |
1046 | IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); | |
1047 | ||
7174beb6 | 1048 | mvm->fwrt.dump.conf = FW_DBG_INVALID; |
945d4202 | 1049 | /* if we have a destination, assume EARLY START */ |
17b809c9 | 1050 | if (mvm->fw->dbg.dest_tlv) |
7174beb6 JB |
1051 | mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE; |
1052 | iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE); | |
6a951267 | 1053 | |
a0544272 | 1054 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1055 | if (ret) |
1056 | goto error; | |
1057 | ||
7d6222e2 JB |
1058 | if (!iwl_mvm_has_unified_ucode(mvm)) { |
1059 | /* Send phy db control command and then phy db calibration */ | |
1f370650 SS |
1060 | ret = iwl_send_phy_db_data(mvm->phy_db); |
1061 | if (ret) | |
1062 | goto error; | |
8ca151b5 | 1063 | |
1f370650 SS |
1064 | ret = iwl_send_phy_cfg_cmd(mvm); |
1065 | if (ret) | |
1066 | goto error; | |
1067 | } | |
8ca151b5 | 1068 | |
b3de3ef4 EG |
1069 | ret = iwl_mvm_send_bt_init_conf(mvm); |
1070 | if (ret) | |
1071 | goto error; | |
1072 | ||
43413a97 | 1073 | /* Init RSS configuration */ |
8edbfaa1 SS |
1074 | if (mvm->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) { |
1075 | ret = iwl_configure_rxq(mvm); | |
1076 | if (ret) { | |
1077 | IWL_ERR(mvm, "Failed to configure RX queues: %d\n", | |
1078 | ret); | |
1079 | goto error; | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | if (iwl_mvm_has_new_rx_api(mvm)) { | |
43413a97 SS |
1084 | ret = iwl_send_rss_cfg_cmd(mvm); |
1085 | if (ret) { | |
1086 | IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", | |
1087 | ret); | |
1088 | goto error; | |
1089 | } | |
1090 | } | |
1091 | ||
8ca151b5 | 1092 | /* init the fw <-> mac80211 STA mapping */ |
0ae98812 | 1093 | for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) |
8ca151b5 JB |
1094 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); |
1095 | ||
0ae98812 | 1096 | mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA; |
1d3c3f63 | 1097 | |
b2b7875b JB |
1098 | /* reset quota debouncing buffer - 0xff will yield invalid data */ |
1099 | memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); | |
1100 | ||
c8f54701 JB |
1101 | ret = iwl_mvm_send_dqa_cmd(mvm); |
1102 | if (ret) | |
1103 | goto error; | |
97d5be7e | 1104 | |
8ca151b5 JB |
1105 | /* Add auxiliary station for scanning */ |
1106 | ret = iwl_mvm_add_aux_sta(mvm); | |
1107 | if (ret) | |
1108 | goto error; | |
1109 | ||
53a9d61e | 1110 | /* Add all the PHY contexts */ |
57fbcce3 | 1111 | chan = &mvm->hw->wiphy->bands[NL80211_BAND_2GHZ]->channels[0]; |
53a9d61e IP |
1112 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); |
1113 | for (i = 0; i < NUM_PHY_CTX; i++) { | |
1114 | /* | |
1115 | * The channel used here isn't relevant as it's | |
1116 | * going to be overwritten in the other flows. | |
1117 | * For now use the first channel we have. | |
1118 | */ | |
1119 | ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], | |
1120 | &chandef, 1, 1); | |
1121 | if (ret) | |
1122 | goto error; | |
1123 | } | |
8ca151b5 | 1124 | |
c221daf2 CRI |
1125 | #ifdef CONFIG_THERMAL |
1126 | if (iwl_mvm_is_tt_in_fw(mvm)) { | |
1127 | /* in order to give the responsibility of ct-kill and | |
1128 | * TX backoff to FW we need to send empty temperature reporting | |
1129 | * cmd during init time | |
1130 | */ | |
1131 | iwl_mvm_send_temp_report_ths_cmd(mvm); | |
1132 | } else { | |
1133 | /* Initialize tx backoffs to the minimal possible */ | |
1134 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
1135 | } | |
5c89e7bc CRI |
1136 | |
1137 | /* TODO: read the budget from BIOS / Platform NVM */ | |
944eafc2 CRI |
1138 | |
1139 | /* | |
1140 | * In case there is no budget from BIOS / Platform NVM the default | |
1141 | * budget should be 2000mW (cooling state 0). | |
1142 | */ | |
1143 | if (iwl_mvm_is_ctdp_supported(mvm)) { | |
5c89e7bc CRI |
1144 | ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, |
1145 | mvm->cooling_dev.cur_state); | |
75cfe338 LC |
1146 | if (ret) |
1147 | goto error; | |
1148 | } | |
c221daf2 | 1149 | #else |
0c0e2c71 IY |
1150 | /* Initialize tx backoffs to the minimal possible */ |
1151 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
c221daf2 | 1152 | #endif |
0c0e2c71 | 1153 | |
84bfffa9 | 1154 | WARN_ON(iwl_mvm_config_ltr(mvm)); |
9180ac50 | 1155 | |
c1cb92fc | 1156 | ret = iwl_mvm_power_update_device(mvm); |
64b928c4 AB |
1157 | if (ret) |
1158 | goto error; | |
1159 | ||
35af15d1 AN |
1160 | /* |
1161 | * RTNL is not taken during Ct-kill, but we don't need to scan/Tx | |
1162 | * anyway, so don't init MCC. | |
1163 | */ | |
1164 | if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { | |
1165 | ret = iwl_mvm_init_mcc(mvm); | |
1166 | if (ret) | |
1167 | goto error; | |
1168 | } | |
90d4f7db | 1169 | |
859d914c | 1170 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { |
4ca87a5f | 1171 | mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; |
b66b5817 | 1172 | mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET; |
d2496221 DS |
1173 | ret = iwl_mvm_config_scan(mvm); |
1174 | if (ret) | |
1175 | goto error; | |
1176 | } | |
1177 | ||
7498cf4c EP |
1178 | /* allow FW/transport low power modes if not during restart */ |
1179 | if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) | |
1180 | iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); | |
1181 | ||
da2830ac | 1182 | ret = iwl_mvm_sar_init(mvm); |
5d041c46 LC |
1183 | if (ret == 0) { |
1184 | ret = iwl_mvm_sar_geo_init(mvm); | |
1185 | } else if (ret > 0 && !iwl_mvm_sar_get_wgds_table(mvm)) { | |
1186 | /* | |
1187 | * If basic SAR is not available, we check for WGDS, | |
1188 | * which should *not* be available either. If it is | |
1189 | * available, issue an error, because we can't use SAR | |
1190 | * Geo without basic SAR. | |
1191 | */ | |
1192 | IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); | |
1193 | } | |
da2830ac | 1194 | |
5d041c46 | 1195 | if (ret < 0) |
a6bff3cb HD |
1196 | goto error; |
1197 | ||
7089ae63 JB |
1198 | iwl_mvm_leds_sync(mvm); |
1199 | ||
53a9d61e | 1200 | IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); |
8ca151b5 JB |
1201 | return 0; |
1202 | error: | |
f4744258 | 1203 | if (!iwlmvm_mod_params.init_dbg || !ret) |
de8ba41b | 1204 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1205 | return ret; |
1206 | } | |
1207 | ||
1208 | int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) | |
1209 | { | |
1210 | int ret, i; | |
1211 | ||
1212 | lockdep_assert_held(&mvm->mutex); | |
1213 | ||
1214 | ret = iwl_trans_start_hw(mvm->trans); | |
1215 | if (ret) | |
1216 | return ret; | |
1217 | ||
1218 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); | |
1219 | if (ret) { | |
1220 | IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); | |
1221 | goto error; | |
1222 | } | |
1223 | ||
a0544272 | 1224 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1225 | if (ret) |
1226 | goto error; | |
1227 | ||
1228 | /* Send phy db control command and then phy db calibration*/ | |
1229 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1230 | if (ret) | |
1231 | goto error; | |
1232 | ||
1233 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1234 | if (ret) | |
1235 | goto error; | |
1236 | ||
1237 | /* init the fw <-> mac80211 STA mapping */ | |
0ae98812 | 1238 | for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) |
8ca151b5 JB |
1239 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); |
1240 | ||
1241 | /* Add auxiliary station for scanning */ | |
1242 | ret = iwl_mvm_add_aux_sta(mvm); | |
1243 | if (ret) | |
1244 | goto error; | |
1245 | ||
1246 | return 0; | |
1247 | error: | |
fcb6b92a | 1248 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1249 | return ret; |
1250 | } | |
1251 | ||
0416841d JB |
1252 | void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, |
1253 | struct iwl_rx_cmd_buffer *rxb) | |
8ca151b5 JB |
1254 | { |
1255 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1256 | struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; | |
1257 | u32 flags = le32_to_cpu(card_state_notif->flags); | |
1258 | ||
1259 | IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", | |
1260 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
1261 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
1262 | (flags & CT_KILL_CARD_DISABLED) ? | |
1263 | "Reached" : "Not reached"); | |
8ca151b5 JB |
1264 | } |
1265 | ||
0416841d JB |
1266 | void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, |
1267 | struct iwl_rx_cmd_buffer *rxb) | |
30269c12 CRI |
1268 | { |
1269 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1270 | struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; | |
1271 | ||
0c8d0a47 GBA |
1272 | IWL_DEBUG_INFO(mvm, |
1273 | "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", | |
1274 | le32_to_cpu(mfuart_notif->installed_ver), | |
1275 | le32_to_cpu(mfuart_notif->external_ver), | |
1276 | le32_to_cpu(mfuart_notif->status), | |
1277 | le32_to_cpu(mfuart_notif->duration)); | |
1278 | ||
19f63c53 GBA |
1279 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif)) |
1280 | IWL_DEBUG_INFO(mvm, | |
0c8d0a47 | 1281 | "MFUART: image size: 0x%08x\n", |
19f63c53 | 1282 | le32_to_cpu(mfuart_notif->image_size)); |
30269c12 | 1283 | } |