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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
358aa5ce 53#include "lib/vxlan.h"
3f6d08d1 54#include "fs_core.h"
2c81bfd5 55#include "en/port.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
b8aee822 64 struct mlx5_fc *counter;
3bc4b7bf
OG		 65};
66
60bd4af8
OG		 67#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
65ba8fb7 69enum {
60bd4af8
OG		 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
72 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
73 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
5dbe906f 77 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 5),
65ba8fb7
OG		 78};
79
e4ad91f2
CM		 80#define MLX5E_TC_MAX_SPLITS 1
81
e8f887ac
AV		 82struct mlx5e_tc_flow {
83 struct rhash_head node;
655dc3d2 84 struct mlx5e_priv *priv;
e8f887ac 85 u64 cookie;
5dbe906f 86 u16 flags;
e4ad91f2 87 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
11c9c548
OG		 88 struct list_head encap; /* flows sharing the same encap ID */
89 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 90 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 91 union {
92 struct mlx5_esw_flow_attr esw_attr[0];
93 struct mlx5_nic_flow_attr nic_attr[0];
94 };
e8f887ac
AV		 95};
96
17091853 97struct mlx5e_tc_flow_parse_attr {
3c37745e 98 struct ip_tunnel_info tun_info;
17091853 99 struct mlx5_flow_spec spec;
d79b6df6
OG		 100 int num_mod_hdr_actions;
101 void *mod_hdr_actions;
3c37745e 102 int mirred_ifindex;
17091853
OG		 103};
104
acff797c 105#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 106#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 107
77ab67b7
OG		 108struct mlx5e_hairpin {
109 struct mlx5_hairpin *pair;
110
111 struct mlx5_core_dev *func_mdev;
3f6d08d1 112 struct mlx5e_priv *func_priv;
77ab67b7
OG		 113 u32 tdn;
114 u32 tirn;
3f6d08d1
OG		 115
116 int num_channels;
117 struct mlx5e_rqt indir_rqt;
118 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
119 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 120};
121
5c65c564
OG		 122struct mlx5e_hairpin_entry {
123 /* a node of a hash table which keeps all the hairpin entries */
124 struct hlist_node hairpin_hlist;
125
126 /* flows sharing the same hairpin */
127 struct list_head flows;
128
d8822868 129 u16 peer_vhca_id;
106be53b 130 u8 prio;
5c65c564
OG		 131 struct mlx5e_hairpin *hp;
132};
133
11c9c548
OG		 134struct mod_hdr_key {
135 int num_actions;
136 void *actions;
137};
138
139struct mlx5e_mod_hdr_entry {
140 /* a node of a hash table which keeps all the mod_hdr entries */
141 struct hlist_node mod_hdr_hlist;
142
143 /* flows sharing the same mod_hdr entry */
144 struct list_head flows;
145
146 struct mod_hdr_key key;
147
148 u32 mod_hdr_id;
149};
150
151#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
152
153static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
154{
155 return jhash(key->actions,
156 key->num_actions * MLX5_MH_ACT_SZ, 0);
157}
158
159static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
160 struct mod_hdr_key *b)
161{
162 if (a->num_actions != b->num_actions)
163 return 1;
164
165 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
166}
167
168static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
169 struct mlx5e_tc_flow *flow,
170 struct mlx5e_tc_flow_parse_attr *parse_attr)
171{
172 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
173 int num_actions, actions_size, namespace, err;
174 struct mlx5e_mod_hdr_entry *mh;
175 struct mod_hdr_key key;
176 bool found = false;
177 u32 hash_key;
178
179 num_actions = parse_attr->num_mod_hdr_actions;
180 actions_size = MLX5_MH_ACT_SZ * num_actions;
181
182 key.actions = parse_attr->mod_hdr_actions;
183 key.num_actions = num_actions;
184
185 hash_key = hash_mod_hdr_info(&key);
186
187 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
188 namespace = MLX5_FLOW_NAMESPACE_FDB;
189 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
190 mod_hdr_hlist, hash_key) {
191 if (!cmp_mod_hdr_info(&mh->key, &key)) {
192 found = true;
193 break;
194 }
195 }
196 } else {
197 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
198 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
199 mod_hdr_hlist, hash_key) {
200 if (!cmp_mod_hdr_info(&mh->key, &key)) {
201 found = true;
202 break;
203 }
204 }
205 }
206
207 if (found)
208 goto attach_flow;
209
210 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
211 if (!mh)
212 return -ENOMEM;
213
214 mh->key.actions = (void *)mh + sizeof(*mh);
215 memcpy(mh->key.actions, key.actions, actions_size);
216 mh->key.num_actions = num_actions;
217 INIT_LIST_HEAD(&mh->flows);
218
219 err = mlx5_modify_header_alloc(priv->mdev, namespace,
220 mh->key.num_actions,
221 mh->key.actions,
222 &mh->mod_hdr_id);
223 if (err)
224 goto out_err;
225
226 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
227 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
228 else
229 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
230
231attach_flow:
232 list_add(&flow->mod_hdr, &mh->flows);
233 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
234 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
235 else
236 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
237
238 return 0;
239
240out_err:
241 kfree(mh);
242 return err;
243}
244
245static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
246 struct mlx5e_tc_flow *flow)
247{
248 struct list_head *next = flow->mod_hdr.next;
249
250 list_del(&flow->mod_hdr);
251
252 if (list_empty(next)) {
253 struct mlx5e_mod_hdr_entry *mh;
254
255 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
256
257 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
258 hash_del(&mh->mod_hdr_hlist);
259 kfree(mh);
260 }
261}
262
77ab67b7
OG		 263static
264struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
265{
266 struct net_device *netdev;
267 struct mlx5e_priv *priv;
268
269 netdev = __dev_get_by_index(net, ifindex);
270 priv = netdev_priv(netdev);
271 return priv->mdev;
272}
273
274static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
275{
276 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
277 void *tirc;
278 int err;
279
280 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
281 if (err)
282 goto alloc_tdn_err;
283
284 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
285
286 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 287 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 288 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
289
290 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
291 if (err)
292 goto create_tir_err;
293
294 return 0;
295
296create_tir_err:
297 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
298alloc_tdn_err:
299 return err;
300}
301
302static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
303{
304 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
305 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
306}
307
3f6d08d1
OG		 308static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
309{
310 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
311 struct mlx5e_priv *priv = hp->func_priv;
312 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
313
314 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
315 hp->num_channels);
316
317 for (i = 0; i < sz; i++) {
318 ix = i;
319 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
320 ix = mlx5e_bits_invert(i, ilog2(sz));
321 ix = indirection_rqt[ix];
322 rqn = hp->pair->rqn[ix];
323 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
324 }
325}
326
327static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
328{
329 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
330 struct mlx5e_priv *priv = hp->func_priv;
331 struct mlx5_core_dev *mdev = priv->mdev;
332 void *rqtc;
333 u32 *in;
334
335 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
336 in = kvzalloc(inlen, GFP_KERNEL);
337 if (!in)
338 return -ENOMEM;
339
340 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
341
342 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
343 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
344
345 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
346
347 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
348 if (!err)
349 hp->indir_rqt.enabled = true;
350
351 kvfree(in);
352 return err;
353}
354
355static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
356{
357 struct mlx5e_priv *priv = hp->func_priv;
358 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
359 int tt, i, err;
360 void *tirc;
361
362 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
363 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
364 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
365
366 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
367 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
368 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
369 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
370
371 err = mlx5_core_create_tir(hp->func_mdev, in,
372 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
373 if (err) {
374 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
375 goto err_destroy_tirs;
376 }
377 }
378 return 0;
379
380err_destroy_tirs:
381 for (i = 0; i < tt; i++)
382 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
383 return err;
384}
385
386static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
387{
388 int tt;
389
390 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
391 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
392}
393
394static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
395 struct ttc_params *ttc_params)
396{
397 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
398 int tt;
399
400 memset(ttc_params, 0, sizeof(*ttc_params));
401
402 ttc_params->any_tt_tirn = hp->tirn;
403
404 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
405 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
406
407 ft_attr->max_fte = MLX5E_NUM_TT;
408 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
409 ft_attr->prio = MLX5E_TC_PRIO;
410}
411
412static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
413{
414 struct mlx5e_priv *priv = hp->func_priv;
415 struct ttc_params ttc_params;
416 int err;
417
418 err = mlx5e_hairpin_create_indirect_rqt(hp);
419 if (err)
420 return err;
421
422 err = mlx5e_hairpin_create_indirect_tirs(hp);
423 if (err)
424 goto err_create_indirect_tirs;
425
426 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
427 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
428 if (err)
429 goto err_create_ttc_table;
430
431 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
432 hp->num_channels, hp->ttc.ft.t->id);
433
434 return 0;
435
436err_create_ttc_table:
437 mlx5e_hairpin_destroy_indirect_tirs(hp);
438err_create_indirect_tirs:
439 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
440
441 return err;
442}
443
444static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
445{
446 struct mlx5e_priv *priv = hp->func_priv;
447
448 mlx5e_destroy_ttc_table(priv, &hp->ttc);
449 mlx5e_hairpin_destroy_indirect_tirs(hp);
450 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
451}
452
77ab67b7
OG		 453static struct mlx5e_hairpin *
454mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
455 int peer_ifindex)
456{
457 struct mlx5_core_dev *func_mdev, *peer_mdev;
458 struct mlx5e_hairpin *hp;
459 struct mlx5_hairpin *pair;
460 int err;
461
462 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
463 if (!hp)
464 return ERR_PTR(-ENOMEM);
465
466 func_mdev = priv->mdev;
467 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
468
469 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
470 if (IS_ERR(pair)) {
471 err = PTR_ERR(pair);
472 goto create_pair_err;
473 }
474 hp->pair = pair;
475 hp->func_mdev = func_mdev;
3f6d08d1
OG		 476 hp->func_priv = priv;
477 hp->num_channels = params->num_channels;
77ab67b7
OG		 478
479 err = mlx5e_hairpin_create_transport(hp);
480 if (err)
481 goto create_transport_err;
482
3f6d08d1
OG		 483 if (hp->num_channels > 1) {
484 err = mlx5e_hairpin_rss_init(hp);
485 if (err)
486 goto rss_init_err;
487 }
488
77ab67b7
OG		 489 return hp;
490
3f6d08d1
OG		 491rss_init_err:
492 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 493create_transport_err:
494 mlx5_core_hairpin_destroy(hp->pair);
495create_pair_err:
496 kfree(hp);
497 return ERR_PTR(err);
498}
499
500static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
501{
3f6d08d1
OG		 502 if (hp->num_channels > 1)
503 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 504 mlx5e_hairpin_destroy_transport(hp);
505 mlx5_core_hairpin_destroy(hp->pair);
506 kvfree(hp);
507}
508
106be53b
OG		 509static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
510{
511 return (peer_vhca_id << 16 | prio);
512}
513
5c65c564 514static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 515 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 516{
517 struct mlx5e_hairpin_entry *hpe;
106be53b 518 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 519
520 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 521 hairpin_hlist, hash_key) {
522 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 523 return hpe;
524 }
525
526 return NULL;
527}
528
106be53b
OG		 529#define UNKNOWN_MATCH_PRIO 8
530
531static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 532 struct mlx5_flow_spec *spec, u8 *match_prio,
533 struct netlink_ext_ack *extack)
106be53b
OG		 534{
535 void *headers_c, *headers_v;
536 u8 prio_val, prio_mask = 0;
537 bool vlan_present;
538
539#ifdef CONFIG_MLX5_CORE_EN_DCB
540 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 541 NL_SET_ERR_MSG_MOD(extack,
542 "only PCP trust state supported for hairpin");
106be53b
OG		 543 return -EOPNOTSUPP;
544 }
545#endif
546 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
547 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
548
549 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
550 if (vlan_present) {
551 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
552 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
553 }
554
555 if (!vlan_present || !prio_mask) {
556 prio_val = UNKNOWN_MATCH_PRIO;
557 } else if (prio_mask != 0x7) {
e98bedf5
EB		 558 NL_SET_ERR_MSG_MOD(extack,
559 "masked priority match not supported for hairpin");
106be53b
OG		 560 return -EOPNOTSUPP;
561 }
562
563 *match_prio = prio_val;
564 return 0;
565}
566
5c65c564
OG		 567static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
568 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 569 struct mlx5e_tc_flow_parse_attr *parse_attr,
570 struct netlink_ext_ack *extack)
5c65c564
OG		 571{
572 int peer_ifindex = parse_attr->mirred_ifindex;
573 struct mlx5_hairpin_params params;
d8822868 574 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 575 struct mlx5e_hairpin_entry *hpe;
576 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 577 u64 link_speed64;
578 u32 link_speed;
106be53b 579 u8 match_prio;
d8822868 580 u16 peer_id;
5c65c564
OG		 581 int err;
582
d8822868
OG		 583 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
584 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 585 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 586 return -EOPNOTSUPP;
587 }
588
d8822868 589 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 590 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
591 extack);
106be53b
OG		 592 if (err)
593 return err;
594 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 595 if (hpe)
596 goto attach_flow;
597
598 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
599 if (!hpe)
600 return -ENOMEM;
601
602 INIT_LIST_HEAD(&hpe->flows);
d8822868 603 hpe->peer_vhca_id = peer_id;
106be53b 604 hpe->prio = match_prio;
5c65c564
OG		 605
606 params.log_data_size = 15;
607 params.log_data_size = min_t(u8, params.log_data_size,
608 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
609 params.log_data_size = max_t(u8, params.log_data_size,
610 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 611
eb9180f7
OG		 612 params.log_num_packets = params.log_data_size -
613 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
614 params.log_num_packets = min_t(u8, params.log_num_packets,
615 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
616
617 params.q_counter = priv->q_counter;
3f6d08d1 618 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 619 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 620 link_speed = max_t(u32, link_speed, 50000);
621 link_speed64 = link_speed;
622 do_div(link_speed64, 50000);
623 params.num_channels = link_speed64;
624
5c65c564
OG		 625 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
626 if (IS_ERR(hp)) {
627 err = PTR_ERR(hp);
628 goto create_hairpin_err;
629 }
630
eb9180f7 631 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 632 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 633 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 634
635 hpe->hp = hp;
106be53b
OG		 636 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
637 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 638
639attach_flow:
3f6d08d1
OG		 640 if (hpe->hp->num_channels > 1) {
641 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
642 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
643 } else {
644 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
645 }
5c65c564 646 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 647
5c65c564
OG		 648 return 0;
649
650create_hairpin_err:
651 kfree(hpe);
652 return err;
653}
654
655static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
656 struct mlx5e_tc_flow *flow)
657{
658 struct list_head *next = flow->hairpin.next;
659
660 list_del(&flow->hairpin);
661
662 /* no more hairpin flows for us, release the hairpin pair */
663 if (list_empty(next)) {
664 struct mlx5e_hairpin_entry *hpe;
665
666 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
667
668 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
669 hpe->hp->pair->peer_mdev->priv.name);
670
671 mlx5e_hairpin_destroy(hpe->hp);
672 hash_del(&hpe->hairpin_hlist);
673 kfree(hpe);
674 }
675}
676
c83954ab 677static int
74491de9 678mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 679 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 680 struct mlx5e_tc_flow *flow,
681 struct netlink_ext_ack *extack)
e8f887ac 682{
aa0cbbae 683 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 684 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 685 struct mlx5_flow_destination dest[2] = {};
66958ed9 686 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 687 .action = attr->action,
688 .flow_tag = attr->flow_tag,
60786f09 689 .reformat_id = 0,
42f7ad67 690 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 691 };
aad7e08d 692 struct mlx5_fc *counter = NULL;
e8f887ac 693 bool table_created = false;
5c65c564 694 int err, dest_ix = 0;
e8f887ac 695
3f6d08d1 696 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 697 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 698 if (err) {
3f6d08d1
OG		 699 goto err_add_hairpin_flow;
700 }
701 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
702 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
703 dest[dest_ix].ft = attr->hairpin_ft;
704 } else {
5c65c564
OG		 705 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
706 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 707 }
708 dest_ix++;
3f6d08d1
OG		 709 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
710 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
711 dest[dest_ix].ft = priv->fs.vlan.ft.t;
712 dest_ix++;
5c65c564 713 }
aad7e08d 714
5c65c564
OG		 715 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
716 counter = mlx5_fc_create(dev, true);
717 if (IS_ERR(counter)) {
c83954ab 718 err = PTR_ERR(counter);
5c65c564
OG		 719 goto err_fc_create;
720 }
721 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 722 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 723 dest_ix++;
b8aee822 724 attr->counter = counter;
aad7e08d
AV		 725 }
726
2f4fe4ca 727 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 728 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 729 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 730 kfree(parse_attr->mod_hdr_actions);
c83954ab 731 if (err)
2f4fe4ca 732 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 733 }
734
acff797c 735 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 736 int tc_grp_size, tc_tbl_size;
737 u32 max_flow_counter;
738
739 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
740 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
741
742 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
743
744 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
745 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
746
acff797c
MG		 747 priv->fs.tc.t =
748 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
749 MLX5E_TC_PRIO,
21b9c144 750 tc_tbl_size,
acff797c 751 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 752 MLX5E_TC_FT_LEVEL, 0);
acff797c 753 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 754 NL_SET_ERR_MSG_MOD(extack,
755 "Failed to create tc offload table\n");
e8f887ac
AV		 756 netdev_err(priv->netdev,
757 "Failed to create tc offload table\n");
c83954ab 758 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 759 goto err_create_ft;
e8f887ac
AV		 760 }
761
762 table_created = true;
763 }
764
38aa51c1
OG		 765 if (attr->match_level != MLX5_MATCH_NONE)
766 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
767
c83954ab
RL		 768 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
769 &flow_act, dest, dest_ix);
aad7e08d 770
c83954ab
RL		 771 if (IS_ERR(flow->rule[0])) {
772 err = PTR_ERR(flow->rule[0]);
aad7e08d 773 goto err_add_rule;
c83954ab 774 }
aad7e08d 775
c83954ab 776 return 0;
e8f887ac 777
aad7e08d
AV		 778err_add_rule:
779 if (table_created) {
acff797c
MG		 780 mlx5_destroy_flow_table(priv->fs.tc.t);
781 priv->fs.tc.t = NULL;
e8f887ac 782 }
aad7e08d 783err_create_ft:
2f4fe4ca 784 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 785 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 786err_create_mod_hdr_id:
aad7e08d 787 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 788err_fc_create:
789 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
790 mlx5e_hairpin_flow_del(priv, flow);
791err_add_hairpin_flow:
c83954ab 792 return err;
e8f887ac
AV		 793}
794
d85cdccb
OG		 795static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
796 struct mlx5e_tc_flow *flow)
797{
513f8f7f 798 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 799 struct mlx5_fc *counter = NULL;
800
b8aee822 801 counter = attr->counter;
e4ad91f2 802 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 803 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 804
b3a433de 805 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 806 mlx5_destroy_flow_table(priv->fs.tc.t);
807 priv->fs.tc.t = NULL;
808 }
2f4fe4ca 809
513f8f7f 810 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 811 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 812
813 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
814 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 815}
816
aa0cbbae
OG		 817static void mlx5e_detach_encap(struct mlx5e_priv *priv,
818 struct mlx5e_tc_flow *flow);
819
3c37745e
OG		 820static int mlx5e_attach_encap(struct mlx5e_priv *priv,
821 struct ip_tunnel_info *tun_info,
822 struct net_device *mirred_dev,
823 struct net_device **encap_dev,
e98bedf5
EB		 824 struct mlx5e_tc_flow *flow,
825 struct netlink_ext_ack *extack);
3c37745e 826
6d2a3ed0
OG		 827static struct mlx5_flow_handle *
828mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
829 struct mlx5e_tc_flow *flow,
830 struct mlx5_flow_spec *spec,
831 struct mlx5_esw_flow_attr *attr)
832{
833 struct mlx5_flow_handle *rule;
834
835 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
836 if (IS_ERR(rule))
837 return rule;
838
839 if (attr->mirror_count) {
840 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
841 if (IS_ERR(flow->rule[1])) {
842 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
843 return flow->rule[1];
844 }
845 }
846
847 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
848 return rule;
849}
850
851static void
852mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
853 struct mlx5e_tc_flow *flow,
854 struct mlx5_esw_flow_attr *attr)
855{
856 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
857
858 if (attr->mirror_count)
859 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
860
861 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
862}
863
5dbe906f
PB		 864static struct mlx5_flow_handle *
865mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
866 struct mlx5e_tc_flow *flow,
867 struct mlx5_flow_spec *spec,
868 struct mlx5_esw_flow_attr *slow_attr)
869{
870 struct mlx5_flow_handle *rule;
871
872 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
873 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
874 slow_attr->mirror_count = 0,
875 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN,
876
877 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
878 if (!IS_ERR(rule))
879 flow->flags |= MLX5E_TC_FLOW_SLOW;
880
881 return rule;
882}
883
884static void
885mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
886 struct mlx5e_tc_flow *flow,
887 struct mlx5_esw_flow_attr *slow_attr)
888{
889 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
890 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
891 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
892}
893
c83954ab 894static int
74491de9 895mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 896 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 897 struct mlx5e_tc_flow *flow,
898 struct netlink_ext_ack *extack)
adb4c123
OG		 899{
900 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 901 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 902 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
bf07aa73 903 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 904 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 905 struct mlx5_fc *counter = NULL;
3c37745e
OG		 906 struct mlx5e_rep_priv *rpriv;
907 struct mlx5e_priv *out_priv;
c83954ab 908 int err = 0, encap_err = 0;
8b32580d 909
bf07aa73
PB		 910 /* if prios are not supported, keep the old behaviour of using same prio
911 * for all offloaded rules.
912 */
913 if (!mlx5_eswitch_prios_supported(esw))
914 attr->prio = 1;
915
916 if (attr->chain > max_chain) {
917 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
918 err = -EOPNOTSUPP;
919 goto err_max_prio_chain;
920 }
921
922 if (attr->prio > max_prio) {
923 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
924 err = -EOPNOTSUPP;
925 goto err_max_prio_chain;
926 }
e52c2802 927
60786f09 928 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
3c37745e
OG		 929 out_dev = __dev_get_by_index(dev_net(priv->netdev),
930 attr->parse_attr->mirred_ifindex);
c83954ab
RL		 931 encap_err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
932 out_dev, &encap_dev, flow,
933 extack);
934 if (encap_err && encap_err != -EAGAIN) {
935 err = encap_err;
936 goto err_attach_encap;
3c37745e
OG		 937 }
938 out_priv = netdev_priv(encap_dev);
939 rpriv = out_priv->ppriv;
592d3651
CM		 940 attr->out_rep[attr->out_count] = rpriv->rep;
941 attr->out_mdev[attr->out_count++] = out_priv->mdev;
3c37745e
OG		 942 }
943
8b32580d 944 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 945 if (err)
aa0cbbae 946 goto err_add_vlan;
adb4c123 947
d7e75a32 948 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 949 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 950 kfree(parse_attr->mod_hdr_actions);
c83954ab 951 if (err)
d7e75a32 952 goto err_mod_hdr;
d7e75a32
OG		 953 }
954
b8aee822
MB		 955 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
956 counter = mlx5_fc_create(esw->dev, true);
957 if (IS_ERR(counter)) {
c83954ab 958 err = PTR_ERR(counter);
b8aee822
MB		 959 goto err_create_counter;
960 }
961
962 attr->counter = counter;
963 }
964
c83954ab 965 /* we get here if (1) there's no error or when
3c37745e
OG		 966 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
967 */
5dbe906f
PB		 968 if (encap_err == -EAGAIN) {
969 /* continue with goto slow path rule instead */
970 struct mlx5_esw_flow_attr slow_attr;
971
972 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
973 } else {
6d2a3ed0 974 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 975 }
c83954ab 976
5dbe906f
PB		 977 if (IS_ERR(flow->rule[0])) {
978 err = PTR_ERR(flow->rule[0]);
979 goto err_add_rule;
980 }
981
982 return 0;
aa0cbbae
OG		 983
984err_add_rule:
b8aee822
MB		 985 mlx5_fc_destroy(esw->dev, counter);
986err_create_counter:
513f8f7f 987 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 988 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 989err_mod_hdr:
aa0cbbae
OG		 990 mlx5_eswitch_del_vlan_action(esw, attr);
991err_add_vlan:
60786f09 992 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
aa0cbbae 993 mlx5e_detach_encap(priv, flow);
3c37745e 994err_attach_encap:
bf07aa73 995err_max_prio_chain:
c83954ab 996 return err;
aa0cbbae 997}
d85cdccb
OG		 998
999static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1000 struct mlx5e_tc_flow *flow)
1001{
1002 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1003 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1004 struct mlx5_esw_flow_attr slow_attr;
d85cdccb 1005
5dbe906f
PB		 1006 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1007 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1008 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1009 else
1010 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1011 }
d85cdccb 1012
513f8f7f 1013 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1014
60786f09 1015 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
d85cdccb 1016 mlx5e_detach_encap(priv, flow);
513f8f7f 1017 kvfree(attr->parse_attr);
232c0013 1018 }
d7e75a32 1019
513f8f7f 1020 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1021 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1022
1023 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1024 mlx5_fc_destroy(esw->dev, attr->counter);
d85cdccb
OG		 1025}
1026
232c0013
HHZ		 1027void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1028 struct mlx5e_encap_entry *e)
1029{
3c37745e 1030 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1031 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1032 struct mlx5_flow_handle *rule;
1033 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1034 struct mlx5e_tc_flow *flow;
1035 int err;
1036
60786f09
MB		 1037 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
1038 e->encap_size, e->encap_header,
31ca3648 1039 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1040 &e->encap_id);
232c0013
HHZ		 1041 if (err) {
1042 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1043 err);
1044 return;
1045 }
1046 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1047 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 1048
1049 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 1050 esw_attr = flow->esw_attr;
1051 esw_attr->encap_id = e->encap_id;
6d2a3ed0
OG		 1052 spec = &esw_attr->parse_attr->spec;
1053
5dbe906f 1054 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1055 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1056 if (IS_ERR(rule)) {
1057 err = PTR_ERR(rule);
232c0013
HHZ		 1058 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1059 err);
1060 continue;
1061 }
5dbe906f
PB		 1062
1063 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1064 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1065 flow->rule[0] = rule;
232c0013
HHZ		 1066 }
1067}
1068
1069void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1070 struct mlx5e_encap_entry *e)
1071{
3c37745e 1072 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1073 struct mlx5_esw_flow_attr slow_attr;
1074 struct mlx5_flow_handle *rule;
1075 struct mlx5_flow_spec *spec;
232c0013 1076 struct mlx5e_tc_flow *flow;
5dbe906f 1077 int err;
232c0013
HHZ		 1078
1079 list_for_each_entry(flow, &e->flows, encap) {
5dbe906f
PB		 1080 spec = &flow->esw_attr->parse_attr->spec;
1081
1082 /* update from encap rule to slow path rule */
1083 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1084
1085 if (IS_ERR(rule)) {
1086 err = PTR_ERR(rule);
1087 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1088 err);
1089 continue;
1090 }
1091
1092 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1093 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1094 flow->rule[0] = rule;
232c0013
HHZ		 1095 }
1096
1097 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
1098 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
60786f09 1099 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1100 }
1101}
1102
b8aee822
MB		 1103static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1104{
1105 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1106 return flow->esw_attr->counter;
1107 else
1108 return flow->nic_attr->counter;
1109}
1110
f6dfb4c3
HHZ		 1111void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1112{
1113 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1114 u64 bytes, packets, lastuse = 0;
1115 struct mlx5e_tc_flow *flow;
1116 struct mlx5e_encap_entry *e;
1117 struct mlx5_fc *counter;
1118 struct neigh_table *tbl;
1119 bool neigh_used = false;
1120 struct neighbour *n;
1121
1122 if (m_neigh->family == AF_INET)
1123 tbl = &arp_tbl;
1124#if IS_ENABLED(CONFIG_IPV6)
1125 else if (m_neigh->family == AF_INET6)
423c9db2 1126 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1127#endif
1128 else
1129 return;
1130
1131 list_for_each_entry(e, &nhe->encap_list, encap_list) {
1132 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1133 continue;
1134 list_for_each_entry(flow, &e->flows, encap) {
1135 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1136 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1137 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1138 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1139 neigh_used = true;
1140 break;
1141 }
1142 }
1143 }
e36d4810
RD		 1144 if (neigh_used)
1145 break;
f6dfb4c3
HHZ		 1146 }
1147
1148 if (neigh_used) {
1149 nhe->reported_lastuse = jiffies;
1150
1151 /* find the relevant neigh according to the cached device and
1152 * dst ip pair
1153 */
1154 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1155 if (!n)
f6dfb4c3 1156 return;
f6dfb4c3
HHZ		 1157
1158 neigh_event_send(n, NULL);
1159 neigh_release(n);
1160 }
1161}
1162
d85cdccb
OG		 1163static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1164 struct mlx5e_tc_flow *flow)
1165{
5067b602
RD		 1166 struct list_head *next = flow->encap.next;
1167
1168 list_del(&flow->encap);
1169 if (list_empty(next)) {
c1ae1152 1170 struct mlx5e_encap_entry *e;
5067b602 1171
c1ae1152 1172 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1173 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1174
1175 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1176 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1177
cdc5a7f3 1178 hash_del_rcu(&e->encap_hlist);
232c0013 1179 kfree(e->encap_header);
5067b602
RD		 1180 kfree(e);
1181 }
1182}
1183
e8f887ac 1184static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1185 struct mlx5e_tc_flow *flow)
e8f887ac 1186{
d85cdccb
OG		 1187 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1188 mlx5e_tc_del_fdb_flow(priv, flow);
1189 else
1190 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1191}
1192
bbd00f7e
HHZ		 1193static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1194 struct tc_cls_flower_offload *f)
1195{
1196 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1197 outer_headers);
1198 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1199 outer_headers);
1200 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1201 misc_parameters);
1202 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1203 misc_parameters);
1204
1205 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1206 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1207
1208 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1209 struct flow_dissector_key_keyid *key =
1210 skb_flow_dissector_target(f->dissector,
1211 FLOW_DISSECTOR_KEY_ENC_KEYID,
1212 f->key);
1213 struct flow_dissector_key_keyid *mask =
1214 skb_flow_dissector_target(f->dissector,
1215 FLOW_DISSECTOR_KEY_ENC_KEYID,
1216 f->mask);
1217 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1218 be32_to_cpu(mask->keyid));
1219 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1220 be32_to_cpu(key->keyid));
1221 }
1222}
1223
1224static int parse_tunnel_attr(struct mlx5e_priv *priv,
1225 struct mlx5_flow_spec *spec,
1226 struct tc_cls_flower_offload *f)
1227{
e98bedf5 1228 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1229 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1230 outer_headers);
1231 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1232 outer_headers);
1233
2e72eb43
OG		 1234 struct flow_dissector_key_control *enc_control =
1235 skb_flow_dissector_target(f->dissector,
1236 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1237 f->key);
1238
bbd00f7e
HHZ		 1239 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1240 struct flow_dissector_key_ports *key =
1241 skb_flow_dissector_target(f->dissector,
1242 FLOW_DISSECTOR_KEY_ENC_PORTS,
1243 f->key);
1244 struct flow_dissector_key_ports *mask =
1245 skb_flow_dissector_target(f->dissector,
1246 FLOW_DISSECTOR_KEY_ENC_PORTS,
1247 f->mask);
1248
1249 /* Full udp dst port must be given */
1250 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 1251 goto vxlan_match_offload_err;
bbd00f7e 1252
a3e67366 1253 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 1254 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1255 parse_vxlan_attr(spec, f);
2fcd82e9 1256 else {
e98bedf5
EB		 1257 NL_SET_ERR_MSG_MOD(extack,
1258 "port isn't an offloaded vxlan udp dport");
2fcd82e9
OG		 1259 netdev_warn(priv->netdev,
1260 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 1261 return -EOPNOTSUPP;
2fcd82e9 1262 }
bbd00f7e
HHZ		 1263
1264 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1265 udp_dport, ntohs(mask->dst));
1266 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1267 udp_dport, ntohs(key->dst));
1268
cd377663
OG		 1269 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1270 udp_sport, ntohs(mask->src));
1271 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1272 udp_sport, ntohs(key->src));
bbd00f7e 1273 } else { /* udp dst port must be given */
2fcd82e9 1274vxlan_match_offload_err:
e98bedf5
EB		 1275 NL_SET_ERR_MSG_MOD(extack,
1276 "IP tunnel decap offload supported only for vxlan, must set UDP dport");
2fcd82e9
OG		 1277 netdev_warn(priv->netdev,
1278 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1279 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1280 }
1281
2e72eb43 1282 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1283 struct flow_dissector_key_ipv4_addrs *key =
1284 skb_flow_dissector_target(f->dissector,
1285 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1286 f->key);
1287 struct flow_dissector_key_ipv4_addrs *mask =
1288 skb_flow_dissector_target(f->dissector,
1289 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1290 f->mask);
1291 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1292 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1293 ntohl(mask->src));
1294 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1295 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1296 ntohl(key->src));
1297
1298 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1299 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1300 ntohl(mask->dst));
1301 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1302 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1303 ntohl(key->dst));
bbd00f7e 1304
2e72eb43
OG		 1305 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1306 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1307 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1308 struct flow_dissector_key_ipv6_addrs *key =
1309 skb_flow_dissector_target(f->dissector,
1310 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1311 f->key);
1312 struct flow_dissector_key_ipv6_addrs *mask =
1313 skb_flow_dissector_target(f->dissector,
1314 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1315 f->mask);
1316
1317 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1318 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1319 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1320 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1321 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1322 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1323
1324 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1325 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1326 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1327 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1328 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1329 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1330
1331 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1332 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1333 }
bbd00f7e 1334
bcef735c
OG		 1335 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1336 struct flow_dissector_key_ip *key =
1337 skb_flow_dissector_target(f->dissector,
1338 FLOW_DISSECTOR_KEY_ENC_IP,
1339 f->key);
1340 struct flow_dissector_key_ip *mask =
1341 skb_flow_dissector_target(f->dissector,
1342 FLOW_DISSECTOR_KEY_ENC_IP,
1343 f->mask);
1344
1345 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1346 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1347
1348 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1349 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1350
1351 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1352 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
e98bedf5
EB		 1353
1354 if (mask->ttl &&
1355 !MLX5_CAP_ESW_FLOWTABLE_FDB
1356 (priv->mdev,
1357 ft_field_support.outer_ipv4_ttl)) {
1358 NL_SET_ERR_MSG_MOD(extack,
1359 "Matching on TTL is not supported");
1360 return -EOPNOTSUPP;
1361 }
1362
bcef735c
OG		 1363 }
1364
bbd00f7e
HHZ		 1365 /* Enforce DMAC when offloading incoming tunneled flows.
1366 * Flow counters require a match on the DMAC.
1367 */
1368 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1369 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1370 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1371 dmac_47_16), priv->netdev->dev_addr);
1372
1373 /* let software handle IP fragments */
1374 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1375 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1376
1377 return 0;
1378}
1379
de0af0bf
RD		 1380static int __parse_cls_flower(struct mlx5e_priv *priv,
1381 struct mlx5_flow_spec *spec,
1382 struct tc_cls_flower_offload *f,
d708f902 1383 u8 *match_level)
e3a2b7ed 1384{
e98bedf5 1385 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1386 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1387 outer_headers);
1388 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1389 outer_headers);
699e96dd
JL		 1390 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1391 misc_parameters);
1392 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1393 misc_parameters);
e3a2b7ed
AV		 1394 u16 addr_type = 0;
1395 u8 ip_proto = 0;
1396
d708f902 1397 *match_level = MLX5_MATCH_NONE;
de0af0bf 1398
e3a2b7ed
AV		 1399 if (f->dissector->used_keys &
1400 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1401 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1402 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1403 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1404 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1405 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1406 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1407 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1408 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1409 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1410 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1411 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1412 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1413 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1414 BIT(FLOW_DISSECTOR_KEY_IP) |
1415 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1416 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed
AV		 1417 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1418 f->dissector->used_keys);
1419 return -EOPNOTSUPP;
1420 }
1421
bbd00f7e
HHZ		 1422 if ((dissector_uses_key(f->dissector,
1423 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1424 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1425 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1426 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1427 struct flow_dissector_key_control *key =
1428 skb_flow_dissector_target(f->dissector,
1429 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1430 f->key);
1431 switch (key->addr_type) {
1432 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1433 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1434 if (parse_tunnel_attr(priv, spec, f))
1435 return -EOPNOTSUPP;
1436 break;
1437 default:
1438 return -EOPNOTSUPP;
1439 }
1440
1441 /* In decap flow, header pointers should point to the inner
1442 * headers, outer header were already set by parse_tunnel_attr
1443 */
1444 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1445 inner_headers);
1446 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1447 inner_headers);
1448 }
1449
d3a80bb5
OG		 1450 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1451 struct flow_dissector_key_basic *key =
e3a2b7ed 1452 skb_flow_dissector_target(f->dissector,
d3a80bb5 1453 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1454 f->key);
d3a80bb5 1455 struct flow_dissector_key_basic *mask =
e3a2b7ed 1456 skb_flow_dissector_target(f->dissector,
d3a80bb5 1457 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1458 f->mask);
d3a80bb5
OG		 1459 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1460 ntohs(mask->n_proto));
1461 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1462 ntohs(key->n_proto));
e3a2b7ed 1463
d3a80bb5 1464 if (mask->n_proto)
d708f902 1465 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1466 }
1467
095b6cfd
OG		 1468 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1469 struct flow_dissector_key_vlan *key =
1470 skb_flow_dissector_target(f->dissector,
1471 FLOW_DISSECTOR_KEY_VLAN,
1472 f->key);
1473 struct flow_dissector_key_vlan *mask =
1474 skb_flow_dissector_target(f->dissector,
1475 FLOW_DISSECTOR_KEY_VLAN,
1476 f->mask);
699e96dd
JL		 1477 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1478 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1479 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1480 svlan_tag, 1);
1481 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1482 svlan_tag, 1);
1483 } else {
1484 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1485 cvlan_tag, 1);
1486 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1487 cvlan_tag, 1);
1488 }
095b6cfd
OG		 1489
1490 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1492
1493 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1494 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1495
d708f902 1496 *match_level = MLX5_MATCH_L2;
54782900 1497 }
d3a80bb5 1498 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1499 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1500 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1501 *match_level = MLX5_MATCH_L2;
54782900
OG		 1502 }
1503
699e96dd
JL		 1504 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1505 struct flow_dissector_key_vlan *key =
1506 skb_flow_dissector_target(f->dissector,
1507 FLOW_DISSECTOR_KEY_CVLAN,
1508 f->key);
1509 struct flow_dissector_key_vlan *mask =
1510 skb_flow_dissector_target(f->dissector,
1511 FLOW_DISSECTOR_KEY_CVLAN,
1512 f->mask);
1513 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1514 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1515 MLX5_SET(fte_match_set_misc, misc_c,
1516 outer_second_svlan_tag, 1);
1517 MLX5_SET(fte_match_set_misc, misc_v,
1518 outer_second_svlan_tag, 1);
1519 } else {
1520 MLX5_SET(fte_match_set_misc, misc_c,
1521 outer_second_cvlan_tag, 1);
1522 MLX5_SET(fte_match_set_misc, misc_v,
1523 outer_second_cvlan_tag, 1);
1524 }
1525
1526 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1527 mask->vlan_id);
1528 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1529 key->vlan_id);
1530 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1531 mask->vlan_priority);
1532 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1533 key->vlan_priority);
1534
1535 *match_level = MLX5_MATCH_L2;
1536 }
1537 }
1538
d3a80bb5
OG		 1539 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1540 struct flow_dissector_key_eth_addrs *key =
54782900 1541 skb_flow_dissector_target(f->dissector,
d3a80bb5 1542 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1543 f->key);
d3a80bb5 1544 struct flow_dissector_key_eth_addrs *mask =
54782900 1545 skb_flow_dissector_target(f->dissector,
d3a80bb5 1546 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1547 f->mask);
54782900 1548
d3a80bb5
OG		 1549 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1550 dmac_47_16),
1551 mask->dst);
1552 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1553 dmac_47_16),
1554 key->dst);
1555
1556 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1557 smac_47_16),
1558 mask->src);
1559 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1560 smac_47_16),
1561 key->src);
1562
1563 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1564 *match_level = MLX5_MATCH_L2;
54782900
OG		 1565 }
1566
1567 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1568 struct flow_dissector_key_control *key =
1569 skb_flow_dissector_target(f->dissector,
1570 FLOW_DISSECTOR_KEY_CONTROL,
1571 f->key);
1572
1573 struct flow_dissector_key_control *mask =
1574 skb_flow_dissector_target(f->dissector,
1575 FLOW_DISSECTOR_KEY_CONTROL,
1576 f->mask);
1577 addr_type = key->addr_type;
1578
1579 /* the HW doesn't support frag first/later */
1580 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1581 return -EOPNOTSUPP;
1582
1583 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1584 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1585 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1586 key->flags & FLOW_DIS_IS_FRAGMENT);
1587
1588 /* the HW doesn't need L3 inline to match on frag=no */
1589 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1590 *match_level = MLX5_MATCH_L2;
54782900
OG		 1591 /* *** L2 attributes parsing up to here *** */
1592 else
83621b7d 1593 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1594 }
1595 }
1596
54782900
OG		 1597 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1598 struct flow_dissector_key_basic *key =
1599 skb_flow_dissector_target(f->dissector,
1600 FLOW_DISSECTOR_KEY_BASIC,
1601 f->key);
1602 struct flow_dissector_key_basic *mask =
1603 skb_flow_dissector_target(f->dissector,
1604 FLOW_DISSECTOR_KEY_BASIC,
1605 f->mask);
1606 ip_proto = key->ip_proto;
1607
1608 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1609 mask->ip_proto);
1610 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1611 key->ip_proto);
1612
1613 if (mask->ip_proto)
d708f902 1614 *match_level = MLX5_MATCH_L3;
54782900
OG		 1615 }
1616
e3a2b7ed
AV		 1617 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1618 struct flow_dissector_key_ipv4_addrs *key =
1619 skb_flow_dissector_target(f->dissector,
1620 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1621 f->key);
1622 struct flow_dissector_key_ipv4_addrs *mask =
1623 skb_flow_dissector_target(f->dissector,
1624 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1625 f->mask);
1626
1627 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1628 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1629 &mask->src, sizeof(mask->src));
1630 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1631 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1632 &key->src, sizeof(key->src));
1633 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1634 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1635 &mask->dst, sizeof(mask->dst));
1636 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1637 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1638 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1639
1640 if (mask->src || mask->dst)
d708f902 1641 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1642 }
1643
1644 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1645 struct flow_dissector_key_ipv6_addrs *key =
1646 skb_flow_dissector_target(f->dissector,
1647 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1648 f->key);
1649 struct flow_dissector_key_ipv6_addrs *mask =
1650 skb_flow_dissector_target(f->dissector,
1651 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1652 f->mask);
1653
1654 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1655 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1656 &mask->src, sizeof(mask->src));
1657 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1658 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1659 &key->src, sizeof(key->src));
1660
1661 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1662 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1663 &mask->dst, sizeof(mask->dst));
1664 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1665 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1666 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1667
1668 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1669 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1670 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1671 }
1672
1f97a526
OG		 1673 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1674 struct flow_dissector_key_ip *key =
1675 skb_flow_dissector_target(f->dissector,
1676 FLOW_DISSECTOR_KEY_IP,
1677 f->key);
1678 struct flow_dissector_key_ip *mask =
1679 skb_flow_dissector_target(f->dissector,
1680 FLOW_DISSECTOR_KEY_IP,
1681 f->mask);
1682
1683 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1685
1686 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1687 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1688
a8ade55f
OG		 1689 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1691
a8ade55f
OG		 1692 if (mask->ttl &&
1693 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1694 ft_field_support.outer_ipv4_ttl)) {
1695 NL_SET_ERR_MSG_MOD(extack,
1696 "Matching on TTL is not supported");
1f97a526 1697 return -EOPNOTSUPP;
e98bedf5 1698 }
a8ade55f
OG		 1699
1700 if (mask->tos || mask->ttl)
d708f902 1701 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1702 }
1703
54782900
OG		 1704 /* *** L3 attributes parsing up to here *** */
1705
e3a2b7ed
AV		 1706 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1707 struct flow_dissector_key_ports *key =
1708 skb_flow_dissector_target(f->dissector,
1709 FLOW_DISSECTOR_KEY_PORTS,
1710 f->key);
1711 struct flow_dissector_key_ports *mask =
1712 skb_flow_dissector_target(f->dissector,
1713 FLOW_DISSECTOR_KEY_PORTS,
1714 f->mask);
1715 switch (ip_proto) {
1716 case IPPROTO_TCP:
1717 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1718 tcp_sport, ntohs(mask->src));
1719 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1720 tcp_sport, ntohs(key->src));
1721
1722 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1723 tcp_dport, ntohs(mask->dst));
1724 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1725 tcp_dport, ntohs(key->dst));
1726 break;
1727
1728 case IPPROTO_UDP:
1729 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1730 udp_sport, ntohs(mask->src));
1731 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1732 udp_sport, ntohs(key->src));
1733
1734 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1735 udp_dport, ntohs(mask->dst));
1736 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1737 udp_dport, ntohs(key->dst));
1738 break;
1739 default:
e98bedf5
EB		 1740 NL_SET_ERR_MSG_MOD(extack,
1741 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1742 netdev_err(priv->netdev,
1743 "Only UDP and TCP transport are supported\n");
1744 return -EINVAL;
1745 }
de0af0bf
RD		 1746
1747 if (mask->src || mask->dst)
d708f902 1748 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1749 }
1750
e77834ec
OG		 1751 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1752 struct flow_dissector_key_tcp *key =
1753 skb_flow_dissector_target(f->dissector,
1754 FLOW_DISSECTOR_KEY_TCP,
1755 f->key);
1756 struct flow_dissector_key_tcp *mask =
1757 skb_flow_dissector_target(f->dissector,
1758 FLOW_DISSECTOR_KEY_TCP,
1759 f->mask);
1760
1761 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1762 ntohs(mask->flags));
1763 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1764 ntohs(key->flags));
1765
1766 if (mask->flags)
d708f902 1767 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1768 }
1769
e3a2b7ed
AV		 1770 return 0;
1771}
1772
de0af0bf 1773static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1774 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1775 struct mlx5_flow_spec *spec,
1776 struct tc_cls_flower_offload *f)
1777{
e98bedf5 1778 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1779 struct mlx5_core_dev *dev = priv->mdev;
1780 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1781 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1782 struct mlx5_eswitch_rep *rep;
d708f902 1783 u8 match_level;
de0af0bf
RD		 1784 int err;
1785
d708f902 1786 err = __parse_cls_flower(priv, spec, f, &match_level);
de0af0bf 1787
1d447a39
SM		 1788 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1789 rep = rpriv->rep;
1790 if (rep->vport != FDB_UPLINK_VPORT &&
1791 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1792 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1793 NL_SET_ERR_MSG_MOD(extack,
1794 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1795 netdev_warn(priv->netdev,
1796 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1797 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1798 return -EOPNOTSUPP;
1799 }
1800 }
1801
38aa51c1
OG		 1802 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1803 flow->esw_attr->match_level = match_level;
1804 else
1805 flow->nic_attr->match_level = match_level;
1806
de0af0bf
RD		 1807 return err;
1808}
1809
d79b6df6
OG		 1810struct pedit_headers {
1811 struct ethhdr eth;
1812 struct iphdr ip4;
1813 struct ipv6hdr ip6;
1814 struct tcphdr tcp;
1815 struct udphdr udp;
1816};
1817
1818static int pedit_header_offsets[] = {
1819 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1820 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1821 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1822 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1823 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1824};
1825
1826#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1827
1828static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1829 struct pedit_headers *masks,
1830 struct pedit_headers *vals)
1831{
1832 u32 *curr_pmask, *curr_pval;
1833
1834 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1835 goto out_err;
1836
1837 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1838 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1839
1840 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1841 goto out_err;
1842
1843 *curr_pmask |= mask;
1844 *curr_pval |= (val & mask);
1845
1846 return 0;
1847
1848out_err:
1849 return -EOPNOTSUPP;
1850}
1851
1852struct mlx5_fields {
1853 u8 field;
1854 u8 size;
1855 u32 offset;
1856};
1857
a8e4f0c4
OG		 1858#define OFFLOAD(fw_field, size, field, off) \
1859 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1860
d79b6df6 1861static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1862 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1863 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1864 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1865 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1866 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1867
1868 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1869 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1870 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1871
1872 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1873 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1874 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1875 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1876 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1877 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1878 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1879 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1880 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1881
1882 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1883 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1884 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1885
1886 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1887 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1888};
1889
1890/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1891 * max from the SW pedit action. On success, it says how many HW actions were
1892 * actually parsed.
1893 */
1894static int offload_pedit_fields(struct pedit_headers *masks,
1895 struct pedit_headers *vals,
e98bedf5
EB		 1896 struct mlx5e_tc_flow_parse_attr *parse_attr,
1897 struct netlink_ext_ack *extack)
d79b6df6
OG		 1898{
1899 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1900 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1901 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1902 struct mlx5_fields *f;
1903 u8 cmd, field_bsize;
e3ca4e05 1904 u32 s_mask, a_mask;
d79b6df6 1905 unsigned long mask;
2b64beba
OG		 1906 __be32 mask_be32;
1907 __be16 mask_be16;
d79b6df6
OG		 1908 void *action;
1909
1910 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1911 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1912 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1913 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1914
1915 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1916 action = parse_attr->mod_hdr_actions;
1917 max_actions = parse_attr->num_mod_hdr_actions;
1918 nactions = 0;
1919
1920 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1921 f = &fields[i];
1922 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1923 s_mask = 0;
1924 a_mask = 0;
d79b6df6
OG		 1925
1926 s_masks_p = (void *)set_masks + f->offset;
1927 a_masks_p = (void *)add_masks + f->offset;
1928
1929 memcpy(&s_mask, s_masks_p, f->size);
1930 memcpy(&a_mask, a_masks_p, f->size);
1931
1932 if (!s_mask && !a_mask) /* nothing to offload here */
1933 continue;
1934
1935 if (s_mask && a_mask) {
e98bedf5
EB		 1936 NL_SET_ERR_MSG_MOD(extack,
1937 "can't set and add to the same HW field");
d79b6df6
OG		 1938 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1939 return -EOPNOTSUPP;
1940 }
1941
1942 if (nactions == max_actions) {
e98bedf5
EB		 1943 NL_SET_ERR_MSG_MOD(extack,
1944 "too many pedit actions, can't offload");
d79b6df6
OG		 1945 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1946 return -EOPNOTSUPP;
1947 }
1948
1949 if (s_mask) {
1950 cmd = MLX5_ACTION_TYPE_SET;
1951 mask = s_mask;
1952 vals_p = (void *)set_vals + f->offset;
1953 /* clear to denote we consumed this field */
1954 memset(s_masks_p, 0, f->size);
1955 } else {
1956 cmd = MLX5_ACTION_TYPE_ADD;
1957 mask = a_mask;
1958 vals_p = (void *)add_vals + f->offset;
1959 /* clear to denote we consumed this field */
1960 memset(a_masks_p, 0, f->size);
1961 }
1962
d79b6df6 1963 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1964
2b64beba
OG		 1965 if (field_bsize == 32) {
1966 mask_be32 = *(__be32 *)&mask;
1967 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1968 } else if (field_bsize == 16) {
1969 mask_be16 = *(__be16 *)&mask;
1970 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1971 }
1972
d79b6df6 1973 first = find_first_bit(&mask, field_bsize);
2b64beba 1974 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1975 last = find_last_bit(&mask, field_bsize);
2b64beba 1976 if (first < next_z && next_z < last) {
e98bedf5
EB		 1977 NL_SET_ERR_MSG_MOD(extack,
1978 "rewrite of few sub-fields isn't supported");
2b64beba 1979 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1980 mask);
1981 return -EOPNOTSUPP;
1982 }
1983
1984 MLX5_SET(set_action_in, action, action_type, cmd);
1985 MLX5_SET(set_action_in, action, field, f->field);
1986
1987 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1988 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1989 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1990 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1991 }
1992
1993 if (field_bsize == 32)
2b64beba 1994 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1995 else if (field_bsize == 16)
2b64beba 1996 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1997 else if (field_bsize == 8)
2b64beba 1998 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1999
2000 action += action_size;
2001 nactions++;
2002 }
2003
2004 parse_attr->num_mod_hdr_actions = nactions;
2005 return 0;
2006}
2007
2008static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2009 const struct tc_action *a, int namespace,
2010 struct mlx5e_tc_flow_parse_attr *parse_attr)
2011{
2012 int nkeys, action_size, max_actions;
2013
2014 nkeys = tcf_pedit_nkeys(a);
2015 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2016
2017 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2018 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2019 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2020 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2021
2022 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2023 max_actions = min(max_actions, nkeys * 16);
2024
2025 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2026 if (!parse_attr->mod_hdr_actions)
2027 return -ENOMEM;
2028
2029 parse_attr->num_mod_hdr_actions = max_actions;
2030 return 0;
2031}
2032
2033static const struct pedit_headers zero_masks = {};
2034
2035static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2036 const struct tc_action *a, int namespace,
e98bedf5
EB		 2037 struct mlx5e_tc_flow_parse_attr *parse_attr,
2038 struct netlink_ext_ack *extack)
d79b6df6
OG		 2039{
2040 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
2041 int nkeys, i, err = -EOPNOTSUPP;
2042 u32 mask, val, offset;
2043 u8 cmd, htype;
2044
2045 nkeys = tcf_pedit_nkeys(a);
2046
2047 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2048 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2049
2050 for (i = 0; i < nkeys; i++) {
2051 htype = tcf_pedit_htype(a, i);
2052 cmd = tcf_pedit_cmd(a, i);
2053 err = -EOPNOTSUPP; /* can't be all optimistic */
2054
2055 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
e98bedf5
EB		 2056 NL_SET_ERR_MSG_MOD(extack,
2057 "legacy pedit isn't offloaded");
d79b6df6
OG		 2058 goto out_err;
2059 }
2060
2061 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
e98bedf5 2062 NL_SET_ERR_MSG_MOD(extack, "pedit cmd isn't offloaded");
d79b6df6
OG		 2063 goto out_err;
2064 }
2065
2066 mask = tcf_pedit_mask(a, i);
2067 val = tcf_pedit_val(a, i);
2068 offset = tcf_pedit_offset(a, i);
2069
2070 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
2071 if (err)
2072 goto out_err;
2073 }
2074
2075 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
2076 if (err)
2077 goto out_err;
2078
e98bedf5 2079 err = offload_pedit_fields(masks, vals, parse_attr, extack);
d79b6df6
OG		 2080 if (err < 0)
2081 goto out_dealloc_parsed_actions;
2082
2083 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2084 cmd_masks = &masks[cmd];
2085 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2086 NL_SET_ERR_MSG_MOD(extack,
2087 "attempt to offload an unsupported field");
b3a433de 2088 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2089 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2090 16, 1, cmd_masks, sizeof(zero_masks), true);
2091 err = -EOPNOTSUPP;
2092 goto out_dealloc_parsed_actions;
2093 }
2094 }
2095
2096 return 0;
2097
2098out_dealloc_parsed_actions:
2099 kfree(parse_attr->mod_hdr_actions);
2100out_err:
2101 return err;
2102}
2103
e98bedf5
EB		 2104static bool csum_offload_supported(struct mlx5e_priv *priv,
2105 u32 action,
2106 u32 update_flags,
2107 struct netlink_ext_ack *extack)
26c02749
OG		 2108{
2109 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2110 TCA_CSUM_UPDATE_FLAG_UDP;
2111
2112 /* The HW recalcs checksums only if re-writing headers */
2113 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2114 NL_SET_ERR_MSG_MOD(extack,
2115 "TC csum action is only offloaded with pedit");
26c02749
OG		 2116 netdev_warn(priv->netdev,
2117 "TC csum action is only offloaded with pedit\n");
2118 return false;
2119 }
2120
2121 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2122 NL_SET_ERR_MSG_MOD(extack,
2123 "can't offload TC csum action for some header/s");
26c02749
OG		 2124 netdev_warn(priv->netdev,
2125 "can't offload TC csum action for some header/s - flags %#x\n",
2126 update_flags);
2127 return false;
2128 }
2129
2130 return true;
2131}
2132
bdd66ac0 2133static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
e98bedf5
EB		 2134 struct tcf_exts *exts,
2135 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2136{
2137 const struct tc_action *a;
2138 bool modify_ip_header;
2139 LIST_HEAD(actions);
2140 u8 htype, ip_proto;
2141 void *headers_v;
2142 u16 ethertype;
2143 int nkeys, i;
2144
2145 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2146 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2147
2148 /* for non-IP we only re-write MACs, so we're okay */
2149 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2150 goto out_ok;
2151
2152 modify_ip_header = false;
244cd96a
CW		 2153 tcf_exts_for_each_action(i, a, exts) {
2154 int k;
2155
bdd66ac0
OG		 2156 if (!is_tcf_pedit(a))
2157 continue;
2158
2159 nkeys = tcf_pedit_nkeys(a);
244cd96a
CW		 2160 for (k = 0; k < nkeys; k++) {
2161 htype = tcf_pedit_htype(a, k);
bdd66ac0
OG		 2162 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2163 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2164 modify_ip_header = true;
2165 break;
2166 }
2167 }
2168 }
2169
2170 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2171 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2172 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2173 NL_SET_ERR_MSG_MOD(extack,
2174 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2175 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2176 return false;
2177 }
2178
2179out_ok:
2180 return true;
2181}
2182
2183static bool actions_match_supported(struct mlx5e_priv *priv,
2184 struct tcf_exts *exts,
2185 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2186 struct mlx5e_tc_flow *flow,
2187 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2188{
2189 u32 actions;
2190
2191 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2192 actions = flow->esw_attr->action;
2193 else
2194 actions = flow->nic_attr->action;
2195
7e29392e
RD		 2196 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2197 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2198 return false;
2199
bdd66ac0 2200 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
e98bedf5
EB		 2201 return modify_header_match_supported(&parse_attr->spec, exts,
2202 extack);
bdd66ac0
OG		 2203
2204 return true;
2205}
2206
5c65c564
OG		 2207static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2208{
2209 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2210 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2211
2212 fmdev = priv->mdev;
2213 pmdev = peer_priv->mdev;
2214
59c9d35e
AH		 2215 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2216 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2217
816f6706 2218 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2219}
2220
5c40348c 2221static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae 2222 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2223 struct mlx5e_tc_flow *flow,
2224 struct netlink_ext_ack *extack)
e3a2b7ed 2225{
aa0cbbae 2226 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 2227 const struct tc_action *a;
22dc13c8 2228 LIST_HEAD(actions);
1cab1cd7 2229 u32 action = 0;
244cd96a 2230 int err, i;
e3a2b7ed 2231
3bcc0cec 2232 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 2233 return -EINVAL;
2234
3bc4b7bf 2235 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2236
244cd96a 2237 tcf_exts_for_each_action(i, a, exts) {
e3a2b7ed 2238 if (is_tcf_gact_shot(a)) {
1cab1cd7 2239 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2240 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2241 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2242 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 2243 continue;
2244 }
2245
2f4fe4ca
OG		 2246 if (is_tcf_pedit(a)) {
2247 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
e98bedf5 2248 parse_attr, extack);
2f4fe4ca
OG		 2249 if (err)
2250 return err;
2251
1cab1cd7
OG		 2252 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2253 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 2254 continue;
2255 }
2256
26c02749 2257 if (is_tcf_csum(a)) {
1cab1cd7 2258 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2259 tcf_csum_update_flags(a),
2260 extack))
26c02749
OG		 2261 continue;
2262
2263 return -EOPNOTSUPP;
2264 }
2265
5c65c564
OG		 2266 if (is_tcf_mirred_egress_redirect(a)) {
2267 struct net_device *peer_dev = tcf_mirred_dev(a);
2268
2269 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2270 same_hw_devs(priv, netdev_priv(peer_dev))) {
2271 parse_attr->mirred_ifindex = peer_dev->ifindex;
2272 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2273 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2274 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2275 } else {
e98bedf5
EB		 2276 NL_SET_ERR_MSG_MOD(extack,
2277 "device is not on same HW, can't offload");
5c65c564
OG		 2278 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2279 peer_dev->name);
2280 return -EINVAL;
2281 }
2282 continue;
2283 }
2284
e3a2b7ed
AV		 2285 if (is_tcf_skbedit_mark(a)) {
2286 u32 mark = tcf_skbedit_mark(a);
2287
2288 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2289 NL_SET_ERR_MSG_MOD(extack,
2290 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2291 return -EINVAL;
2292 }
2293
3bc4b7bf 2294 attr->flow_tag = mark;
1cab1cd7 2295 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2296 continue;
2297 }
2298
2299 return -EINVAL;
2300 }
2301
1cab1cd7 2302 attr->action = action;
e98bedf5 2303 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2304 return -EOPNOTSUPP;
2305
e3a2b7ed
AV		 2306 return 0;
2307}
2308
76f7444d
OG		 2309static inline int cmp_encap_info(struct ip_tunnel_key *a,
2310 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2311{
2312 return memcmp(a, b, sizeof(*a));
2313}
2314
76f7444d 2315static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2316{
76f7444d 2317 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2318}
2319
2320static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2321 struct net_device *mirred_dev,
2322 struct net_device **out_dev,
2323 struct flowi4 *fl4,
2324 struct neighbour **out_n,
6360cd62 2325 u8 *out_ttl)
a54e20b4 2326{
3e621b19 2327 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 2328 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 2329 struct rtable *rt;
2330 struct neighbour *n = NULL;
a54e20b4
HHZ		 2331
2332#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 2333 int ret;
2334
a54e20b4 2335 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 2336 ret = PTR_ERR_OR_ZERO(rt);
2337 if (ret)
2338 return ret;
a54e20b4
HHZ		 2339#else
2340 return -EOPNOTSUPP;
2341#endif
a4b97ab4 2342 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 2343 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2344 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 2345 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 2346 else
2347 *out_dev = rt->dst.dev;
a54e20b4 2348
6360cd62
OG		 2349 if (!(*out_ttl))
2350 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 2351 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2352 ip_rt_put(rt);
2353 if (!n)
2354 return -ENOMEM;
2355
2356 *out_n = n;
a54e20b4
HHZ		 2357 return 0;
2358}
2359
b1d90e6b
RL		 2360static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2361 struct net_device *peer_netdev)
2362{
2363 struct mlx5e_priv *peer_priv;
2364
2365 peer_priv = netdev_priv(peer_netdev);
2366
2367 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2368 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2369 same_hw_devs(priv, peer_priv) &&
2370 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2371 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2372}
2373
ce99f6b9
OG		 2374static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2375 struct net_device *mirred_dev,
2376 struct net_device **out_dev,
2377 struct flowi6 *fl6,
2378 struct neighbour **out_n,
6360cd62 2379 u8 *out_ttl)
ce99f6b9
OG		 2380{
2381 struct neighbour *n = NULL;
2382 struct dst_entry *dst;
2383
2384#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 2385 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 2386 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2387 int ret;
2388
08820528
PB		 2389 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2390 fl6);
2391 if (ret < 0)
ce99f6b9 2392 return ret;
ce99f6b9 2393
6360cd62
OG		 2394 if (!(*out_ttl))
2395 *out_ttl = ip6_dst_hoplimit(dst);
ce99f6b9 2396
a4b97ab4 2397 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 2398 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2399 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 2400 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 2401 else
2402 *out_dev = dst->dev;
2403#else
2404 return -EOPNOTSUPP;
2405#endif
2406
2407 n = dst_neigh_lookup(dst, &fl6->daddr);
2408 dst_release(dst);
2409 if (!n)
2410 return -ENOMEM;
2411
2412 *out_n = n;
2413 return 0;
2414}
2415
32f3671f
OG		 2416static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2417 char buf[], int encap_size,
2418 unsigned char h_dest[ETH_ALEN],
f35f800d 2419 u8 tos, u8 ttl,
32f3671f
OG		 2420 __be32 daddr,
2421 __be32 saddr,
2422 __be16 udp_dst_port,
2423 __be32 vx_vni)
a54e20b4 2424{
a54e20b4
HHZ		 2425 struct ethhdr *eth = (struct ethhdr *)buf;
2426 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2427 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2428 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2429
2430 memset(buf, 0, encap_size);
2431
2432 ether_addr_copy(eth->h_dest, h_dest);
2433 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2434 eth->h_proto = htons(ETH_P_IP);
2435
2436 ip->daddr = daddr;
2437 ip->saddr = saddr;
2438
f35f800d 2439 ip->tos = tos;
a54e20b4
HHZ		 2440 ip->ttl = ttl;
2441 ip->protocol = IPPROTO_UDP;
2442 ip->version = 0x4;
2443 ip->ihl = 0x5;
2444
2445 udp->dest = udp_dst_port;
2446 vxh->vx_flags = VXLAN_HF_VNI;
2447 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 2448}
2449
225aabaf
OG		 2450static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2451 char buf[], int encap_size,
2452 unsigned char h_dest[ETH_ALEN],
f35f800d 2453 u8 tos, u8 ttl,
225aabaf
OG		 2454 struct in6_addr *daddr,
2455 struct in6_addr *saddr,
2456 __be16 udp_dst_port,
2457 __be32 vx_vni)
ce99f6b9 2458{
ce99f6b9
OG		 2459 struct ethhdr *eth = (struct ethhdr *)buf;
2460 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2461 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2462 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2463
2464 memset(buf, 0, encap_size);
2465
2466 ether_addr_copy(eth->h_dest, h_dest);
2467 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2468 eth->h_proto = htons(ETH_P_IPV6);
2469
f35f800d 2470 ip6_flow_hdr(ip6h, tos, 0);
ce99f6b9
OG		 2471 /* the HW fills up ipv6 payload len */
2472 ip6h->nexthdr = IPPROTO_UDP;
2473 ip6h->hop_limit = ttl;
2474 ip6h->daddr = *daddr;
2475 ip6h->saddr = *saddr;
2476
2477 udp->dest = udp_dst_port;
2478 vxh->vx_flags = VXLAN_HF_VNI;
2479 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 2480}
2481
a54e20b4
HHZ		 2482static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2483 struct net_device *mirred_dev,
1a8552bd 2484 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 2485{
2486 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 2487 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 2488 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2489 struct net_device *out_dev;
a42485eb 2490 struct neighbour *n = NULL;
a54e20b4 2491 struct flowi4 fl4 = {};
f35f800d 2492 u8 nud_state, tos, ttl;
a54e20b4 2493 char *encap_header;
6360cd62 2494 int err;
32f3671f
OG		 2495
2496 if (max_encap_size < ipv4_encap_size) {
2497 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2498 ipv4_encap_size, max_encap_size);
2499 return -EOPNOTSUPP;
2500 }
a54e20b4 2501
32f3671f 2502 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 2503 if (!encap_header)
2504 return -ENOMEM;
2505
2506 switch (e->tunnel_type) {
60786f09 2507 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
a54e20b4 2508 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 2509 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 2510 break;
2511 default:
2512 err = -EOPNOTSUPP;
ace74321 2513 goto free_encap;
a54e20b4 2514 }
6360cd62 2515
f35f800d
OG		 2516 tos = tun_key->tos;
2517 ttl = tun_key->ttl;
6360cd62 2518
9a941117 2519 fl4.flowi4_tos = tun_key->tos;
76f7444d 2520 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 2521 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 2522
1a8552bd 2523 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 2524 &fl4, &n, &ttl);
a54e20b4 2525 if (err)
ace74321 2526 goto free_encap;
a54e20b4 2527
232c0013
HHZ		 2528 /* used by mlx5e_detach_encap to lookup a neigh hash table
2529 * entry in the neigh hash table when a user deletes a rule
2530 */
2531 e->m_neigh.dev = n->dev;
f6dfb4c3 2532 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2533 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2534 e->out_dev = out_dev;
2535
2536 /* It's importent to add the neigh to the hash table before checking
2537 * the neigh validity state. So if we'll get a notification, in case the
2538 * neigh changes it's validity state, we would find the relevant neigh
2539 * in the hash.
2540 */
2541 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2542 if (err)
ace74321 2543 goto free_encap;
232c0013 2544
033354d5
HHZ		 2545 read_lock_bh(&n->lock);
2546 nud_state = n->nud_state;
2547 ether_addr_copy(e->h_dest, n->ha);
2548 read_unlock_bh(&n->lock);
2549
a54e20b4 2550 switch (e->tunnel_type) {
60786f09 2551 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
1a8552bd 2552 gen_vxlan_header_ipv4(out_dev, encap_header,
f35f800d 2553 ipv4_encap_size, e->h_dest, tos, ttl,
32f3671f
OG		 2554 fl4.daddr,
2555 fl4.saddr, tun_key->tp_dst,
2556 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2557 break;
2558 default:
2559 err = -EOPNOTSUPP;
232c0013
HHZ		 2560 goto destroy_neigh_entry;
2561 }
2562 e->encap_size = ipv4_encap_size;
2563 e->encap_header = encap_header;
2564
2565 if (!(nud_state & NUD_VALID)) {
2566 neigh_event_send(n, NULL);
27902f08
WY		 2567 err = -EAGAIN;
2568 goto out;
a54e20b4
HHZ		 2569 }
2570
60786f09
MB		 2571 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2572 ipv4_encap_size, encap_header,
31ca3648 2573 MLX5_FLOW_NAMESPACE_FDB,
60786f09 2574 &e->encap_id);
232c0013
HHZ		 2575 if (err)
2576 goto destroy_neigh_entry;
2577
2578 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2579 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2580 neigh_release(n);
2581 return err;
2582
2583destroy_neigh_entry:
2584 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2585free_encap:
a54e20b4 2586 kfree(encap_header);
ace74321 2587out:
232c0013
HHZ		 2588 if (n)
2589 neigh_release(n);
a54e20b4
HHZ		 2590 return err;
2591}
2592
ce99f6b9
OG		 2593static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2594 struct net_device *mirred_dev,
1a8552bd 2595 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2596{
2597 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2598 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2599 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2600 struct net_device *out_dev;
ce99f6b9
OG		 2601 struct neighbour *n = NULL;
2602 struct flowi6 fl6 = {};
f35f800d 2603 u8 nud_state, tos, ttl;
ce99f6b9 2604 char *encap_header;
6360cd62 2605 int err;
ce99f6b9 2606
225aabaf
OG		 2607 if (max_encap_size < ipv6_encap_size) {
2608 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2609 ipv6_encap_size, max_encap_size);
2610 return -EOPNOTSUPP;
2611 }
ce99f6b9 2612
225aabaf 2613 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2614 if (!encap_header)
2615 return -ENOMEM;
2616
2617 switch (e->tunnel_type) {
60786f09 2618 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
ce99f6b9
OG		 2619 fl6.flowi6_proto = IPPROTO_UDP;
2620 fl6.fl6_dport = tun_key->tp_dst;
2621 break;
2622 default:
2623 err = -EOPNOTSUPP;
ace74321 2624 goto free_encap;
ce99f6b9
OG		 2625 }
2626
f35f800d
OG		 2627 tos = tun_key->tos;
2628 ttl = tun_key->ttl;
6360cd62 2629
ce99f6b9
OG		 2630 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2631 fl6.daddr = tun_key->u.ipv6.dst;
2632 fl6.saddr = tun_key->u.ipv6.src;
2633
1a8552bd 2634 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2635 &fl6, &n, &ttl);
2636 if (err)
ace74321 2637 goto free_encap;
ce99f6b9 2638
232c0013
HHZ		 2639 /* used by mlx5e_detach_encap to lookup a neigh hash table
2640 * entry in the neigh hash table when a user deletes a rule
2641 */
2642 e->m_neigh.dev = n->dev;
f6dfb4c3 2643 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2644 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2645 e->out_dev = out_dev;
2646
2647 /* It's importent to add the neigh to the hash table before checking
2648 * the neigh validity state. So if we'll get a notification, in case the
2649 * neigh changes it's validity state, we would find the relevant neigh
2650 * in the hash.
2651 */
2652 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2653 if (err)
ace74321 2654 goto free_encap;
232c0013 2655
033354d5
HHZ		 2656 read_lock_bh(&n->lock);
2657 nud_state = n->nud_state;
2658 ether_addr_copy(e->h_dest, n->ha);
2659 read_unlock_bh(&n->lock);
2660
ce99f6b9 2661 switch (e->tunnel_type) {
60786f09 2662 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
1a8552bd 2663 gen_vxlan_header_ipv6(out_dev, encap_header,
f35f800d 2664 ipv6_encap_size, e->h_dest, tos, ttl,
225aabaf
OG		 2665 &fl6.daddr,
2666 &fl6.saddr, tun_key->tp_dst,
2667 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2668 break;
2669 default:
2670 err = -EOPNOTSUPP;
232c0013
HHZ		 2671 goto destroy_neigh_entry;
2672 }
2673
2674 e->encap_size = ipv6_encap_size;
2675 e->encap_header = encap_header;
2676
2677 if (!(nud_state & NUD_VALID)) {
2678 neigh_event_send(n, NULL);
27902f08
WY		 2679 err = -EAGAIN;
2680 goto out;
ce99f6b9
OG		 2681 }
2682
60786f09
MB		 2683 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2684 ipv6_encap_size, encap_header,
31ca3648 2685 MLX5_FLOW_NAMESPACE_FDB,
60786f09 2686 &e->encap_id);
232c0013
HHZ		 2687 if (err)
2688 goto destroy_neigh_entry;
2689
2690 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2691 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2692 neigh_release(n);
2693 return err;
2694
2695destroy_neigh_entry:
2696 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2697free_encap:
ce99f6b9 2698 kfree(encap_header);
ace74321 2699out:
232c0013
HHZ		 2700 if (n)
2701 neigh_release(n);
ce99f6b9
OG		 2702 return err;
2703}
2704
a54e20b4
HHZ		 2705static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2706 struct ip_tunnel_info *tun_info,
2707 struct net_device *mirred_dev,
45247bf2 2708 struct net_device **encap_dev,
e98bedf5
EB		 2709 struct mlx5e_tc_flow *flow,
2710 struct netlink_ext_ack *extack)
a54e20b4
HHZ		 2711{
2712 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2713 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2 2714 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2715 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2716 struct mlx5e_encap_entry *e;
45247bf2 2717 int tunnel_type, err = 0;
a54e20b4
HHZ		 2718 uintptr_t hash_key;
2719 bool found = false;
a54e20b4 2720
2fcd82e9 2721 /* udp dst port must be set */
a54e20b4 2722 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2723 goto vxlan_encap_offload_err;
a54e20b4 2724
cd377663 2725 /* setting udp src port isn't supported */
2fcd82e9
OG		 2726 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2727vxlan_encap_offload_err:
e98bedf5
EB		 2728 NL_SET_ERR_MSG_MOD(extack,
2729 "must set udp dst port and not set udp src port");
2fcd82e9
OG		 2730 netdev_warn(priv->netdev,
2731 "must set udp dst port and not set udp src port\n");
cd377663 2732 return -EOPNOTSUPP;
2fcd82e9 2733 }
cd377663 2734
a3e67366 2735 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2736 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
60786f09 2737 tunnel_type = MLX5_REFORMAT_TYPE_L2_TO_VXLAN;
a54e20b4 2738 } else {
e98bedf5
EB		 2739 NL_SET_ERR_MSG_MOD(extack,
2740 "port isn't an offloaded vxlan udp dport");
2fcd82e9
OG		 2741 netdev_warn(priv->netdev,
2742 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2743 return -EOPNOTSUPP;
2744 }
2745
76f7444d 2746 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2747
2748 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2749 encap_hlist, hash_key) {
76f7444d 2750 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2751 found = true;
2752 break;
2753 }
2754 }
2755
b2812089 2756 /* must verify if encap is valid or not */
45247bf2
OG		 2757 if (found)
2758 goto attach_flow;
a54e20b4
HHZ		 2759
2760 e = kzalloc(sizeof(*e), GFP_KERNEL);
2761 if (!e)
2762 return -ENOMEM;
2763
76f7444d 2764 e->tun_info = *tun_info;
a54e20b4
HHZ		 2765 e->tunnel_type = tunnel_type;
2766 INIT_LIST_HEAD(&e->flows);
2767
ce99f6b9 2768 if (family == AF_INET)
1a8552bd 2769 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2770 else if (family == AF_INET6)
1a8552bd 2771 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2772
232c0013 2773 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2774 goto out_err;
2775
a54e20b4
HHZ		 2776 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2777
45247bf2
OG		 2778attach_flow:
2779 list_add(&flow->encap, &e->flows);
2780 *encap_dev = e->out_dev;
232c0013
HHZ		 2781 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2782 attr->encap_id = e->encap_id;
b2812089
VB		 2783 else
2784 err = -EAGAIN;
45247bf2 2785
232c0013 2786 return err;
a54e20b4
HHZ		 2787
2788out_err:
2789 kfree(e);
2790 return err;
2791}
2792
1482bd3d
JL		 2793static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2794 const struct tc_action *a,
2795 struct mlx5_esw_flow_attr *attr,
2796 u32 *action)
2797{
cc495188
JL		 2798 u8 vlan_idx = attr->total_vlan;
2799
2800 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2801 return -EOPNOTSUPP;
2802
1482bd3d 2803 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
cc495188
JL		 2804 if (vlan_idx) {
2805 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2806 MLX5_FS_VLAN_DEPTH))
2807 return -EOPNOTSUPP;
2808
2809 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2810 } else {
2811 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2812 }
1482bd3d 2813 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
cc495188
JL		 2814 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2815 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2816 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2817 if (!attr->vlan_proto[vlan_idx])
2818 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2819
2820 if (vlan_idx) {
2821 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2822 MLX5_FS_VLAN_DEPTH))
2823 return -EOPNOTSUPP;
2824
2825 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2826 } else {
2827 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2828 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2829 tcf_vlan_push_prio(a)))
2830 return -EOPNOTSUPP;
2831
2832 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d
JL		 2833 }
2834 } else { /* action is TCA_VLAN_ACT_MODIFY */
2835 return -EOPNOTSUPP;
2836 }
2837
cc495188
JL		 2838 attr->total_vlan = vlan_idx + 1;
2839
1482bd3d
JL		 2840 return 0;
2841}
2842
03a9d11e 2843static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2844 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2845 struct mlx5e_tc_flow *flow,
2846 struct netlink_ext_ack *extack)
03a9d11e 2847{
bf07aa73 2848 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2849 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2850 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2851 struct ip_tunnel_info *info = NULL;
03a9d11e 2852 const struct tc_action *a;
22dc13c8 2853 LIST_HEAD(actions);
a54e20b4 2854 bool encap = false;
1cab1cd7 2855 u32 action = 0;
244cd96a 2856 int err, i;
03a9d11e 2857
3bcc0cec 2858 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2859 return -EINVAL;
2860
1d447a39 2861 attr->in_rep = rpriv->rep;
10ff5359 2862 attr->in_mdev = priv->mdev;
03a9d11e 2863
244cd96a 2864 tcf_exts_for_each_action(i, a, exts) {
03a9d11e 2865 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2866 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2867 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2868 continue;
2869 }
2870
d7e75a32
OG		 2871 if (is_tcf_pedit(a)) {
2872 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
e98bedf5 2873 parse_attr, extack);
d7e75a32
OG		 2874 if (err)
2875 return err;
2876
1cab1cd7 2877 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
592d3651 2878 attr->mirror_count = attr->out_count;
d7e75a32
OG		 2879 continue;
2880 }
2881
26c02749 2882 if (is_tcf_csum(a)) {
1cab1cd7 2883 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2884 tcf_csum_update_flags(a),
2885 extack))
26c02749
OG		 2886 continue;
2887
2888 return -EOPNOTSUPP;
2889 }
2890
592d3651 2891 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
03a9d11e 2892 struct mlx5e_priv *out_priv;
592d3651 2893 struct net_device *out_dev;
03a9d11e 2894
9f8a739e 2895 out_dev = tcf_mirred_dev(a);
03a9d11e 2896
592d3651 2897 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2898 NL_SET_ERR_MSG_MOD(extack,
2899 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2900 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2901 attr->out_count);
2902 return -EOPNOTSUPP;
2903 }
2904
a54e20b4 2905 if (switchdev_port_same_parent_id(priv->netdev,
b1d90e6b
RL		 2906 out_dev) ||
2907 is_merged_eswitch_dev(priv, out_dev)) {
1cab1cd7
OG		 2908 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2909 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2910 out_priv = netdev_priv(out_dev);
1d447a39 2911 rpriv = out_priv->ppriv;
592d3651
CM		 2912 attr->out_rep[attr->out_count] = rpriv->rep;
2913 attr->out_mdev[attr->out_count++] = out_priv->mdev;
a54e20b4 2914 } else if (encap) {
9f8a739e 2915 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2916 parse_attr->tun_info = *info;
2917 attr->parse_attr = parse_attr;
60786f09 2918 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
1cab1cd7
OG		 2919 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2920 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2921 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2922 } else {
e98bedf5
EB		 2923 NL_SET_ERR_MSG_MOD(extack,
2924 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2925 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2926 priv->netdev->name, out_dev->name);
2927 return -EINVAL;
2928 }
a54e20b4
HHZ		 2929 continue;
2930 }
03a9d11e 2931
a54e20b4
HHZ		 2932 if (is_tcf_tunnel_set(a)) {
2933 info = tcf_tunnel_info(a);
2934 if (info)
2935 encap = true;
2936 else
2937 return -EOPNOTSUPP;
592d3651 2938 attr->mirror_count = attr->out_count;
03a9d11e
OG		 2939 continue;
2940 }
2941
8b32580d 2942 if (is_tcf_vlan(a)) {
1482bd3d
JL		 2943 err = parse_tc_vlan_action(priv, a, attr, &action);
2944
2945 if (err)
2946 return err;
2947
592d3651 2948 attr->mirror_count = attr->out_count;
8b32580d
OG		 2949 continue;
2950 }
2951
bbd00f7e 2952 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2953 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2954 continue;
2955 }
2956
bf07aa73
PB		 2957 if (is_tcf_gact_goto_chain(a)) {
2958 u32 dest_chain = tcf_gact_goto_chain_index(a);
2959 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2960
2961 if (dest_chain <= attr->chain) {
2962 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2963 return -EOPNOTSUPP;
2964 }
2965 if (dest_chain > max_chain) {
2966 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2967 return -EOPNOTSUPP;
2968 }
2969 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2970 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2971 attr->dest_chain = dest_chain;
2972
2973 continue;
2974 }
2975
03a9d11e
OG		 2976 return -EINVAL;
2977 }
bdd66ac0 2978
1cab1cd7 2979 attr->action = action;
e98bedf5 2980 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2981 return -EOPNOTSUPP;
2982
1392f44b 2983 if (attr->mirror_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2984 NL_SET_ERR_MSG_MOD(extack,
2985 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2986 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2987 return -EOPNOTSUPP;
2988 }
2989
31c8eba5 2990 return 0;
03a9d11e
OG		 2991}
2992
5dbe906f 2993static void get_flags(int flags, u16 *flow_flags)
60bd4af8 2994{
5dbe906f 2995 u16 __flow_flags = 0;
60bd4af8
OG		 2996
2997 if (flags & MLX5E_TC_INGRESS)
2998 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2999 if (flags & MLX5E_TC_EGRESS)
3000 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
3001
3002 *flow_flags = __flow_flags;
3003}
3004
05866c82
OG		 3005static const struct rhashtable_params tc_ht_params = {
3006 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3007 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3008 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3009 .automatic_shrinking = true,
3010};
3011
3012static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
3013{
655dc3d2
OG		 3014 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3015 struct mlx5e_rep_priv *uplink_rpriv;
3016
3017 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
3018 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3019 return &uplink_rpriv->tc_ht;
3020 } else
3021 return &priv->fs.tc.ht;
05866c82
OG		 3022}
3023
a88780a9
RD		 3024static int
3025mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 3026 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 3027 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3028 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3029{
17091853 3030 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3031 struct mlx5e_tc_flow *flow;
a88780a9 3032 int err;
e3a2b7ed 3033
65ba8fb7 3034 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3035 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3036 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3037 err = -ENOMEM;
3038 goto err_free;
3039 }
3040
3041 flow->cookie = f->cookie;
65ba8fb7 3042 flow->flags = flow_flags;
655dc3d2 3043 flow->priv = priv;
e3a2b7ed 3044
17091853 3045 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
a88780a9 3046 if (err)
e3a2b7ed
AV		 3047 goto err_free;
3048
a88780a9
RD		 3049 *__flow = flow;
3050 *__parse_attr = parse_attr;
3051
3052 return 0;
3053
3054err_free:
3055 kfree(flow);
3056 kvfree(parse_attr);
3057 return err;
3058}
3059
3060static int
3061mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3062 struct tc_cls_flower_offload *f,
5dbe906f 3063 u16 flow_flags,
a88780a9
RD		 3064 struct mlx5e_tc_flow **__flow)
3065{
3066 struct netlink_ext_ack *extack = f->common.extack;
3067 struct mlx5e_tc_flow_parse_attr *parse_attr;
3068 struct mlx5e_tc_flow *flow;
3069 int attr_size, err;
e3a2b7ed 3070
a88780a9
RD		 3071 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
3072 attr_size = sizeof(struct mlx5_esw_flow_attr);
3073 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3074 &parse_attr, &flow);
3075 if (err)
3076 goto out;
3077
bf07aa73
PB		 3078 flow->esw_attr->chain = f->common.chain_index;
3079 flow->esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
a88780a9
RD		 3080 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow, extack);
3081 if (err)
3082 goto err_free;
3083
3084 err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
5dbe906f 3085 if (err)
c83954ab 3086 goto err_free;
e3a2b7ed 3087
a88780a9 3088 if (!(flow->esw_attr->action &
60786f09 3089 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT))
af1607c3
JL		 3090 kvfree(parse_attr);
3091
a88780a9 3092 *__flow = flow;
5c40348c 3093
a88780a9
RD		 3094 return 0;
3095
3096err_free:
3097 kfree(flow);
3098 kvfree(parse_attr);
3099out:
232c0013 3100 return err;
a88780a9
RD		 3101}
3102
3103static int
3104mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3105 struct tc_cls_flower_offload *f,
5dbe906f 3106 u16 flow_flags,
a88780a9
RD		 3107 struct mlx5e_tc_flow **__flow)
3108{
3109 struct netlink_ext_ack *extack = f->common.extack;
3110 struct mlx5e_tc_flow_parse_attr *parse_attr;
3111 struct mlx5e_tc_flow *flow;
3112 int attr_size, err;
3113
bf07aa73
PB		 3114 /* multi-chain not supported for NIC rules */
3115 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3116 return -EOPNOTSUPP;
3117
a88780a9
RD		 3118 flow_flags |= MLX5E_TC_FLOW_NIC;
3119 attr_size = sizeof(struct mlx5_nic_flow_attr);
3120 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3121 &parse_attr, &flow);
3122 if (err)
3123 goto out;
3124
3125 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow, extack);
3126 if (err)
3127 goto err_free;
3128
3129 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3130 if (err)
3131 goto err_free;
3132
3133 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
3134 kvfree(parse_attr);
3135 *__flow = flow;
3136
3137 return 0;
e3a2b7ed 3138
e3a2b7ed 3139err_free:
a88780a9 3140 kfree(flow);
17091853 3141 kvfree(parse_attr);
a88780a9
RD		 3142out:
3143 return err;
3144}
3145
3146static int
3147mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3148 struct tc_cls_flower_offload *f,
3149 int flags,
3150 struct mlx5e_tc_flow **flow)
3151{
3152 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 3153 u16 flow_flags;
a88780a9
RD		 3154 int err;
3155
3156 get_flags(flags, &flow_flags);
3157
bf07aa73
PB		 3158 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3159 return -EOPNOTSUPP;
3160
a88780a9
RD		 3161 if (esw && esw->mode == SRIOV_OFFLOADS)
3162 err = mlx5e_add_fdb_flow(priv, f, flow_flags, flow);
3163 else
3164 err = mlx5e_add_nic_flow(priv, f, flow_flags, flow);
3165
3166 return err;
3167}
3168
3169int mlx5e_configure_flower(struct mlx5e_priv *priv,
3170 struct tc_cls_flower_offload *f, int flags)
3171{
3172 struct netlink_ext_ack *extack = f->common.extack;
3173 struct rhashtable *tc_ht = get_tc_ht(priv);
3174 struct mlx5e_tc_flow *flow;
3175 int err = 0;
3176
3177 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3178 if (flow) {
3179 NL_SET_ERR_MSG_MOD(extack,
3180 "flow cookie already exists, ignoring");
3181 netdev_warn_once(priv->netdev,
3182 "flow cookie %lx already exists, ignoring\n",
3183 f->cookie);
3184 goto out;
3185 }
3186
3187 err = mlx5e_tc_add_flow(priv, f, flags, &flow);
3188 if (err)
3189 goto out;
3190
3191 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
3192 if (err)
3193 goto err_free;
3194
3195 return 0;
3196
3197err_free:
3198 mlx5e_tc_del_flow(priv, flow);
232c0013 3199 kfree(flow);
a88780a9 3200out:
e3a2b7ed
AV		 3201 return err;
3202}
3203
8f8ae895
OG		 3204#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
3205#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
3206
3207static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3208{
3209 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
3210 return true;
3211
3212 return false;
3213}
3214
e3a2b7ed 3215int mlx5e_delete_flower(struct mlx5e_priv *priv,
60bd4af8 3216 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3217{
05866c82 3218 struct rhashtable *tc_ht = get_tc_ht(priv);
e3a2b7ed 3219 struct mlx5e_tc_flow *flow;
e3a2b7ed 3220
05866c82 3221 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3222 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3223 return -EINVAL;
3224
05866c82 3225 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3226
961e8979 3227 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3228
3229 kfree(flow);
3230
3231 return 0;
3232}
3233
aad7e08d 3234int mlx5e_stats_flower(struct mlx5e_priv *priv,
60bd4af8 3235 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3236{
05866c82 3237 struct rhashtable *tc_ht = get_tc_ht(priv);
aad7e08d 3238 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 3239 struct mlx5_fc *counter;
3240 u64 bytes;
3241 u64 packets;
3242 u64 lastuse;
3243
05866c82 3244 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3245 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3246 return -EINVAL;
3247
0b67a38f
HHZ		 3248 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
3249 return 0;
3250
b8aee822 3251 counter = mlx5e_tc_get_counter(flow);
aad7e08d
AV		 3252 if (!counter)
3253 return 0;
3254
3255 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3256
d897a638 3257 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 3258
aad7e08d
AV		 3259 return 0;
3260}
3261
4d8fcf21
AH		 3262static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3263 struct mlx5e_priv *peer_priv)
3264{
3265 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3266 struct mlx5e_hairpin_entry *hpe;
3267 u16 peer_vhca_id;
3268 int bkt;
3269
3270 if (!same_hw_devs(priv, peer_priv))
3271 return;
3272
3273 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3274
3275 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3276 if (hpe->peer_vhca_id == peer_vhca_id)
3277 hpe->hp->pair->peer_gone = true;
3278 }
3279}
3280
3281static int mlx5e_tc_netdev_event(struct notifier_block *this,
3282 unsigned long event, void *ptr)
3283{
3284 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3285 struct mlx5e_flow_steering *fs;
3286 struct mlx5e_priv *peer_priv;
3287 struct mlx5e_tc_table *tc;
3288 struct mlx5e_priv *priv;
3289
3290 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3291 event != NETDEV_UNREGISTER ||
3292 ndev->reg_state == NETREG_REGISTERED)
3293 return NOTIFY_DONE;
3294
3295 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3296 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3297 priv = container_of(fs, struct mlx5e_priv, fs);
3298 peer_priv = netdev_priv(ndev);
3299 if (priv == peer_priv ||
3300 !(priv->netdev->features & NETIF_F_HW_TC))
3301 return NOTIFY_DONE;
3302
3303 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3304
3305 return NOTIFY_DONE;
3306}
3307
655dc3d2 3308int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3309{
acff797c 3310 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3311 int err;
e8f887ac 3312
11c9c548 3313 hash_init(tc->mod_hdr_tbl);
5c65c564 3314 hash_init(tc->hairpin_tbl);
11c9c548 3315
4d8fcf21
AH		 3316 err = rhashtable_init(&tc->ht, &tc_ht_params);
3317 if (err)
3318 return err;
3319
3320 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3321 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3322 tc->netdevice_nb.notifier_call = NULL;
3323 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3324 }
3325
3326 return err;
e8f887ac
AV		 3327}
3328
3329static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3330{
3331 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3332 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3333
961e8979 3334 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3335 kfree(flow);
3336}
3337
655dc3d2 3338void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3339{
acff797c 3340 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3341
4d8fcf21
AH		 3342 if (tc->netdevice_nb.notifier_call)
3343 unregister_netdevice_notifier(&tc->netdevice_nb);
3344
655dc3d2 3345 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 3346
acff797c
MG		 3347 if (!IS_ERR_OR_NULL(tc->t)) {
3348 mlx5_destroy_flow_table(tc->t);
3349 tc->t = NULL;
e8f887ac
AV		 3350 }
3351}
655dc3d2
OG		 3352
3353int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3354{
3355 return rhashtable_init(tc_ht, &tc_ht_params);
3356}
3357
3358void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3359{
3360 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3361}
01252a27
OG		 3362
3363int mlx5e_tc_num_filters(struct mlx5e_priv *priv)
3364{
3365 struct rhashtable *tc_ht = get_tc_ht(priv);
3366
3367 return atomic_read(&tc_ht->nelems);
3368}
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