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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
60bbf7ee 38#include <net/page_pool.h>
1d447a39 39#include "eswitch.h"
f62b8bb8 40#include "en.h"
e8f887ac 41#include "en_tc.h"
1d447a39 42#include "en_rep.h"
547eede0 43#include "en_accel/ipsec.h"
899a59d3 44#include "en_accel/ipsec_rxtx.h"
c83294b9 45#include "en_accel/tls.h"
899a59d3 46#include "accel/ipsec.h"
c83294b9 47#include "accel/tls.h"
358aa5ce 48#include "lib/vxlan.h"
6dbc80ca 49#include "lib/clock.h"
2c81bfd5 50#include "en/port.h"
159d2131 51#include "en/xdp.h"
f62b8bb8
AV		 52
53struct mlx5e_rq_param {
cb3c7fd4
GR		 54 u32 rqc[MLX5_ST_SZ_DW(rqc)];
55 struct mlx5_wq_param wq;
069d1146 56 struct mlx5e_rq_frags_info frags_info;
f62b8bb8
AV		 57};
58
59struct mlx5e_sq_param {
60 u32 sqc[MLX5_ST_SZ_DW(sqc)];
61 struct mlx5_wq_param wq;
62};
63
64struct mlx5e_cq_param {
65 u32 cqc[MLX5_ST_SZ_DW(cqc)];
66 struct mlx5_wq_param wq;
67 u16 eq_ix;
9908aa29 68 u8 cq_period_mode;
f62b8bb8
AV		 69};
70
71struct mlx5e_channel_param {
72 struct mlx5e_rq_param rq;
73 struct mlx5e_sq_param sq;
b5503b99 74 struct mlx5e_sq_param xdp_sq;
d3c9bc27 75 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 76 struct mlx5e_cq_param rx_cq;
77 struct mlx5e_cq_param tx_cq;
d3c9bc27 78 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 79};
80
2ccb0a79 81bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2fc4bfb7 82{
ea3886ca 83 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
2fc4bfb7
SM		 84 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
85 MLX5_CAP_ETH(mdev, reg_umr_sq);
ea3886ca
TT		 86 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
87 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
88
89 if (!striding_rq_umr)
90 return false;
91 if (!inline_umr) {
92 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
93 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
94 return false;
95 }
96 return true;
2fc4bfb7
SM		 97}
98
069d1146 99static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
73281b78 100{
a26a5bdf
TT		 101 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
102 u16 linear_rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104 u32 frag_sz;
73281b78 105
a26a5bdf 106 linear_rq_headroom += NET_IP_ALIGN;
619a8f2a 107
a26a5bdf
TT		 108 frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
109
110 if (params->xdp_prog && frag_sz < PAGE_SIZE)
111 frag_sz = PAGE_SIZE;
112
113 return frag_sz;
73281b78
TT		 114}
115
116static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
117{
069d1146 118 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
73281b78
TT		 119
120 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
121}
122
069d1146
TT		 123static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
124 struct mlx5e_params *params)
125{
126 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
127
128 return !params->lro_en && frag_sz <= PAGE_SIZE;
129}
130
619a8f2a
TT		 131static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
132 struct mlx5e_params *params)
133{
069d1146 134 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
619a8f2a
TT		 135 s8 signed_log_num_strides_param;
136 u8 log_num_strides;
137
069d1146 138 if (!mlx5e_rx_is_linear_skb(mdev, params))
619a8f2a
TT		 139 return false;
140
141 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
142 return true;
143
144 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
145 signed_log_num_strides_param =
146 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
147
148 return signed_log_num_strides_param >= 0;
149}
150
73281b78
TT		 151static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
152{
153 if (params->log_rq_mtu_frames <
154 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
155 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
156
157 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
158}
159
160static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
161 struct mlx5e_params *params)
f1e4fc9b 162{
619a8f2a 163 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
069d1146 164 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
619a8f2a 165
f1e4fc9b
TT		 166 return MLX5E_MPWQE_STRIDE_SZ(mdev,
167 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
168}
169
73281b78
TT		 170static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
171 struct mlx5e_params *params)
f1e4fc9b
TT		 172{
173 return MLX5_MPWRQ_LOG_WQE_SZ -
174 mlx5e_mpwqe_get_log_stride_size(mdev, params);
175}
176
619a8f2a
TT		 177static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
178 struct mlx5e_params *params)
b0cedc84
TT		 179{
180 u16 linear_rq_headroom = params->xdp_prog ?
181 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
069d1146 182 bool is_linear_skb;
b0cedc84
TT		 183
184 linear_rq_headroom += NET_IP_ALIGN;
185
069d1146
TT		 186 is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
187 mlx5e_rx_is_linear_skb(mdev, params) :
188 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
b0cedc84 189
069d1146 190 return is_linear_skb ? linear_rq_headroom : 0;
b0cedc84
TT		 191}
192
696a97cf 193void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
2a0f561b 194 struct mlx5e_params *params)
2fc4bfb7 195{
6a9764ef 196 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
73281b78
TT		 197 params->log_rq_mtu_frames = is_kdump_kernel() ?
198 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
199 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2fc4bfb7 200
6a9764ef
SM		 201 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
202 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
619a8f2a
TT		 203 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
204 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
73281b78 205 BIT(params->log_rq_mtu_frames),
f1e4fc9b 206 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
6a9764ef 207 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 208}
209
2ccb0a79
TT		 210bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
211 struct mlx5e_params *params)
212{
213 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
22f45398
TT		 214 !MLX5_IPSEC_DEV(mdev) &&
215 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
2ccb0a79 216}
291f445e 217
2ccb0a79 218void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 219{
2ccb0a79
TT		 220 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
221 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
291f445e 222 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
99cbfa93 223 MLX5_WQ_TYPE_CYCLIC;
2fc4bfb7
SM		 224}
225
f62b8bb8
AV		 226static void mlx5e_update_carrier(struct mlx5e_priv *priv)
227{
228 struct mlx5_core_dev *mdev = priv->mdev;
229 u8 port_state;
230
231 port_state = mlx5_query_vport_state(mdev,
cc9c82a8 232 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
e53eef63 233 0);
f62b8bb8 234
87424ad5
SD		 235 if (port_state == VPORT_STATE_UP) {
236 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 237 netif_carrier_on(priv->netdev);
87424ad5
SD		 238 } else {
239 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 240 netif_carrier_off(priv->netdev);
87424ad5 241 }
f62b8bb8
AV		 242}
243
244static void mlx5e_update_carrier_work(struct work_struct *work)
245{
246 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
247 update_carrier_work);
248
249 mutex_lock(&priv->state_lock);
250 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 251 if (priv->profile->update_carrier)
252 priv->profile->update_carrier(priv);
f62b8bb8
AV		 253 mutex_unlock(&priv->state_lock);
254}
255
19386177 256void mlx5e_update_stats(struct mlx5e_priv *priv)
f62b8bb8 257{
19386177 258 int i;
f62b8bb8 259
19386177
KH		 260 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
261 if (mlx5e_stats_grps[i].update_stats)
262 mlx5e_stats_grps[i].update_stats(priv);
f62b8bb8
AV		 263}
264
3834a5e6
GP		 265static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
266{
19386177
KH		 267 int i;
268
269 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
270 if (mlx5e_stats_grps[i].update_stats_mask &
271 MLX5E_NDO_UPDATE_STATS)
272 mlx5e_stats_grps[i].update_stats(priv);
3834a5e6
GP		 273}
274
303211b4 275static void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8 276{
cdeef2b1 277 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
f62b8bb8 278 update_stats_work);
ed56c519 279
f62b8bb8 280 mutex_lock(&priv->state_lock);
ed56c519 281 priv->profile->update_stats(priv);
f62b8bb8
AV		 282 mutex_unlock(&priv->state_lock);
283}
284
cdeef2b1
SM		 285void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
286{
287 if (!priv->profile->update_stats)
288 return;
289
290 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
291 return;
292
293 queue_work(priv->wq, &priv->update_stats_work);
294}
295
daa21560
TT		 296static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
297 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 298{
daa21560
TT		 299 struct mlx5e_priv *priv = vpriv;
300
e0f46eb9 301 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 302 return;
303
f62b8bb8
AV		 304 switch (event) {
305 case MLX5_DEV_EVENT_PORT_UP:
306 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 307 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 308 break;
f62b8bb8
AV		 309 default:
310 break;
311 }
312}
313
f62b8bb8
AV		 314static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
315{
e0f46eb9 316 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 317}
318
319static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
320{
e0f46eb9 321 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 322 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 323}
324
31391048
SM		 325static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
326 struct mlx5e_icosq *sq,
b8a98a4c 327 struct mlx5e_umr_wqe *wqe)
7e426671
TT		 328{
329 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
330 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
ea3886ca 331 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
7e426671
TT		 332
333 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
334 ds_cnt);
335 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
336 cseg->imm = rq->mkey_be;
337
ea3886ca 338 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
31616255 339 ucseg->xlt_octowords =
7e426671 340 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
7e426671 341 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
7e426671
TT		 342}
343
422d4c40
TT		 344static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
345{
346 switch (rq->wq_type) {
347 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
348 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
349 default:
99cbfa93 350 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
422d4c40
TT		 351 }
352}
353
354static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
355{
356 switch (rq->wq_type) {
357 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
358 return rq->mpwqe.wq.cur_sz;
359 default:
360 return rq->wqe.wq.cur_sz;
361 }
362}
363
7e426671
TT		 364static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
365 struct mlx5e_channel *c)
366{
422d4c40 367 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
7e426671 368
eec4edc9
KC		 369 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
370 sizeof(*rq->mpwqe.info)),
ca11b798 371 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 372 if (!rq->mpwqe.info)
ea3886ca 373 return -ENOMEM;
7e426671 374
b8a98a4c 375 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
7e426671
TT		 376
377 return 0;
7e426671
TT		 378}
379
a43b25da 380static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 381 u64 npages, u8 page_shift,
382 struct mlx5_core_mkey *umr_mkey)
3608ae77 383{
3608ae77
TT		 384 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
385 void *mkc;
386 u32 *in;
387 int err;
388
1b9a07ee 389 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 390 if (!in)
391 return -ENOMEM;
392
393 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
394
3608ae77
TT		 395 MLX5_SET(mkc, mkc, free, 1);
396 MLX5_SET(mkc, mkc, umr_en, 1);
397 MLX5_SET(mkc, mkc, lw, 1);
398 MLX5_SET(mkc, mkc, lr, 1);
cdbd0d2b 399 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
3608ae77
TT		 400
401 MLX5_SET(mkc, mkc, qpn, 0xffffff);
402 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 403 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 404 MLX5_SET(mkc, mkc, translations_octword_size,
405 MLX5_MTT_OCTW(npages));
ec8b9981 406 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 407
ec8b9981 408 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 409
410 kvfree(in);
411 return err;
412}
413
a43b25da 414static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 415{
422d4c40 416 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
ec8b9981 417
a43b25da 418 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 419}
420
b8a98a4c
TT		 421static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
422{
423 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
424}
425
069d1146
TT		 426static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
427{
428 struct mlx5e_wqe_frag_info next_frag, *prev;
429 int i;
430
431 next_frag.di = &rq->wqe.di[0];
432 next_frag.offset = 0;
433 prev = NULL;
434
435 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
436 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
437 struct mlx5e_wqe_frag_info *frag =
438 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
439 int f;
440
441 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
442 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
443 next_frag.di++;
444 next_frag.offset = 0;
445 if (prev)
446 prev->last_in_page = true;
447 }
448 *frag = next_frag;
449
450 /* prepare next */
451 next_frag.offset += frag_info[f].frag_stride;
452 prev = frag;
453 }
454 }
455
456 if (prev)
457 prev->last_in_page = true;
458}
459
460static int mlx5e_init_di_list(struct mlx5e_rq *rq,
461 struct mlx5e_params *params,
462 int wq_sz, int cpu)
463{
464 int len = wq_sz << rq->wqe.info.log_num_frags;
465
84ca176b 466 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
069d1146
TT		 467 GFP_KERNEL, cpu_to_node(cpu));
468 if (!rq->wqe.di)
469 return -ENOMEM;
470
471 mlx5e_init_frags_partition(rq);
472
473 return 0;
474}
475
476static void mlx5e_free_di_list(struct mlx5e_rq *rq)
477{
478 kvfree(rq->wqe.di);
479}
480
3b77235b 481static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 482 struct mlx5e_params *params,
483 struct mlx5e_rq_param *rqp,
3b77235b 484 struct mlx5e_rq *rq)
f62b8bb8 485{
60bbf7ee 486 struct page_pool_params pp_params = { 0 };
a43b25da 487 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 488 void *rqc = rqp->rqc;
f62b8bb8 489 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
069d1146 490 u32 pool_size;
f62b8bb8
AV		 491 int wq_sz;
492 int err;
493 int i;
494
231243c8 495 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 496
6a9764ef 497 rq->wq_type = params->rq_wq_type;
7e426671
TT		 498 rq->pdev = c->pdev;
499 rq->netdev = c->netdev;
a43b25da 500 rq->tstamp = c->tstamp;
7c39afb3 501 rq->clock = &mdev->clock;
7e426671
TT		 502 rq->channel = c;
503 rq->ix = c->ix;
a43b25da 504 rq->mdev = mdev;
0073c8f7 505 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
05909bab 506 rq->stats = &c->priv->channel_stats[c->ix].rq;
97bc402d 507
6a9764ef 508 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 509 if (IS_ERR(rq->xdp_prog)) {
510 err = PTR_ERR(rq->xdp_prog);
511 rq->xdp_prog = NULL;
512 goto err_rq_wq_destroy;
513 }
7e426671 514
e213f5b6
WY		 515 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
516 if (err < 0)
0ddf5432
JDB		 517 goto err_rq_wq_destroy;
518
bce2b2bf 519 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
619a8f2a 520 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
60bbf7ee 521 pool_size = 1 << params->log_rq_mtu_frames;
b5503b99 522
6a9764ef 523 switch (rq->wq_type) {
461017cb 524 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
422d4c40
TT		 525 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
526 &rq->wq_ctrl);
527 if (err)
528 return err;
529
530 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
531
532 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
60bbf7ee
JDB		 533
534 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
422d4c40 535
7cc6d77b 536 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 537 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 538
20fd0c19 539 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 540#ifdef CONFIG_MLX5_EN_IPSEC
541 if (MLX5_IPSEC_DEV(mdev)) {
542 err = -EINVAL;
543 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
544 goto err_rq_wq_destroy;
545 }
546#endif
20fd0c19
SM		 547 if (!rq->handle_rx_cqe) {
548 err = -EINVAL;
549 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
550 goto err_rq_wq_destroy;
551 }
552
619a8f2a
TT		 553 rq->mpwqe.skb_from_cqe_mpwrq =
554 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
555 mlx5e_skb_from_cqe_mpwrq_linear :
556 mlx5e_skb_from_cqe_mpwrq_nonlinear;
f1e4fc9b
TT		 557 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
558 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
1bfecfca 559
a43b25da 560 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 561 if (err)
562 goto err_rq_wq_destroy;
ec8b9981
TT		 563 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
564
565 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
566 if (err)
069d1146 567 goto err_free;
461017cb 568 break;
99cbfa93
TT		 569 default: /* MLX5_WQ_TYPE_CYCLIC */
570 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
571 &rq->wq_ctrl);
422d4c40
TT		 572 if (err)
573 return err;
574
575 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
576
99cbfa93 577 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
422d4c40 578
069d1146
TT		 579 rq->wqe.info = rqp->frags_info;
580 rq->wqe.frags =
84ca176b
KC		 581 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
582 (wq_sz << rq->wqe.info.log_num_frags)),
069d1146 583 GFP_KERNEL, cpu_to_node(c->cpu));
47a6ca3f
WY		 584 if (!rq->wqe.frags) {
585 err = -ENOMEM;
069d1146 586 goto err_free;
47a6ca3f 587 }
069d1146
TT		 588
589 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
590 if (err)
591 goto err_free;
7cc6d77b 592 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 593 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 594
899a59d3
IT		 595#ifdef CONFIG_MLX5_EN_IPSEC
596 if (c->priv->ipsec)
597 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
598 else
599#endif
600 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 601 if (!rq->handle_rx_cqe) {
20fd0c19
SM		 602 err = -EINVAL;
603 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
069d1146 604 goto err_free;
20fd0c19
SM		 605 }
606
069d1146
TT		 607 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
608 mlx5e_skb_from_cqe_linear :
609 mlx5e_skb_from_cqe_nonlinear;
7e426671 610 rq->mkey_be = c->mkey_be;
461017cb 611 }
f62b8bb8 612
60bbf7ee 613 /* Create a page_pool and register it with rxq */
069d1146 614 pp_params.order = 0;
60bbf7ee
JDB		 615 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
616 pp_params.pool_size = pool_size;
617 pp_params.nid = cpu_to_node(c->cpu);
618 pp_params.dev = c->pdev;
619 pp_params.dma_dir = rq->buff.map_dir;
620
621 /* page_pool can be used even when there is no rq->xdp_prog,
622 * given page_pool does not handle DMA mapping there is no
623 * required state to clear. And page_pool gracefully handle
624 * elevated refcnt.
625 */
626 rq->page_pool = page_pool_create(&pp_params);
627 if (IS_ERR(rq->page_pool)) {
60bbf7ee
JDB		 628 err = PTR_ERR(rq->page_pool);
629 rq->page_pool = NULL;
069d1146 630 goto err_free;
84f5e3fb 631 }
60bbf7ee
JDB		 632 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
633 MEM_TYPE_PAGE_POOL, rq->page_pool);
634 if (err)
069d1146 635 goto err_free;
84f5e3fb 636
f62b8bb8 637 for (i = 0; i < wq_sz; i++) {
4c2af5cc 638 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
99cbfa93 639 struct mlx5e_rx_wqe_ll *wqe =
422d4c40 640 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
069d1146
TT		 641 u32 byte_count =
642 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
b8a98a4c 643 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
4c2af5cc 644
99cbfa93
TT		 645 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
646 wqe->data[0].byte_count = cpu_to_be32(byte_count);
647 wqe->data[0].lkey = rq->mkey_be;
422d4c40 648 } else {
99cbfa93
TT		 649 struct mlx5e_rx_wqe_cyc *wqe =
650 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
069d1146
TT		 651 int f;
652
653 for (f = 0; f < rq->wqe.info.num_frags; f++) {
654 u32 frag_size = rq->wqe.info.arr[f].frag_size |
655 MLX5_HW_START_PADDING;
656
657 wqe->data[f].byte_count = cpu_to_be32(frag_size);
658 wqe->data[f].lkey = rq->mkey_be;
659 }
660 /* check if num_frags is not a pow of two */
661 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
662 wqe->data[f].byte_count = 0;
663 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
664 wqe->data[f].addr = 0;
665 }
422d4c40 666 }
f62b8bb8
AV		 667 }
668
9a317425
AG		 669 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
670
671 switch (params->rx_cq_moderation.cq_period_mode) {
672 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
673 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
674 break;
675 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
676 default:
677 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
678 }
679
4415a031
TT		 680 rq->page_cache.head = 0;
681 rq->page_cache.tail = 0;
682
f62b8bb8
AV		 683 return 0;
684
069d1146
TT		 685err_free:
686 switch (rq->wq_type) {
687 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
ca11b798 688 kvfree(rq->mpwqe.info);
069d1146
TT		 689 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
690 break;
691 default: /* MLX5_WQ_TYPE_CYCLIC */
692 kvfree(rq->wqe.frags);
693 mlx5e_free_di_list(rq);
694 }
ec8b9981 695
f62b8bb8 696err_rq_wq_destroy:
97bc402d
DB		 697 if (rq->xdp_prog)
698 bpf_prog_put(rq->xdp_prog);
0ddf5432 699 xdp_rxq_info_unreg(&rq->xdp_rxq);
60bbf7ee
JDB		 700 if (rq->page_pool)
701 page_pool_destroy(rq->page_pool);
f62b8bb8
AV		 702 mlx5_wq_destroy(&rq->wq_ctrl);
703
704 return err;
705}
706
3b77235b 707static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 708{
4415a031
TT		 709 int i;
710
86994156
RS		 711 if (rq->xdp_prog)
712 bpf_prog_put(rq->xdp_prog);
713
0ddf5432 714 xdp_rxq_info_unreg(&rq->xdp_rxq);
60bbf7ee
JDB		 715 if (rq->page_pool)
716 page_pool_destroy(rq->page_pool);
0ddf5432 717
461017cb
TT		 718 switch (rq->wq_type) {
719 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
ca11b798 720 kvfree(rq->mpwqe.info);
a43b25da 721 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb 722 break;
99cbfa93 723 default: /* MLX5_WQ_TYPE_CYCLIC */
069d1146
TT		 724 kvfree(rq->wqe.frags);
725 mlx5e_free_di_list(rq);
461017cb
TT		 726 }
727
4415a031
TT		 728 for (i = rq->page_cache.head; i != rq->page_cache.tail;
729 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
730 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
731
732 mlx5e_page_release(rq, dma_info, false);
733 }
f62b8bb8
AV		 734 mlx5_wq_destroy(&rq->wq_ctrl);
735}
736
6a9764ef
SM		 737static int mlx5e_create_rq(struct mlx5e_rq *rq,
738 struct mlx5e_rq_param *param)
f62b8bb8 739{
a43b25da 740 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 741
742 void *in;
743 void *rqc;
744 void *wq;
745 int inlen;
746 int err;
747
748 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
749 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 750 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 751 if (!in)
752 return -ENOMEM;
753
754 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
755 wq = MLX5_ADDR_OF(rqc, rqc, wq);
756
757 memcpy(rqc, param->rqc, sizeof(param->rqc));
758
97de9f31 759 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 760 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 761 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 762 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 763 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
764
3a2f7033
TT		 765 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
766 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 767
7db22ffb 768 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 769
770 kvfree(in);
771
772 return err;
773}
774
36350114
GP		 775static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
776 int next_state)
f62b8bb8 777{
7cbaf9a3 778 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 779
780 void *in;
781 void *rqc;
782 int inlen;
783 int err;
784
785 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 786 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 787 if (!in)
788 return -ENOMEM;
789
790 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
791
792 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
793 MLX5_SET(rqc, rqc, state, next_state);
794
7db22ffb 795 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 796
797 kvfree(in);
798
799 return err;
800}
801
102722fc
GE		 802static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
803{
804 struct mlx5e_channel *c = rq->channel;
805 struct mlx5e_priv *priv = c->priv;
806 struct mlx5_core_dev *mdev = priv->mdev;
807
808 void *in;
809 void *rqc;
810 int inlen;
811 int err;
812
813 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 814 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 815 if (!in)
816 return -ENOMEM;
817
818 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
819
820 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
821 MLX5_SET64(modify_rq_in, in, modify_bitmask,
822 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
823 MLX5_SET(rqc, rqc, scatter_fcs, enable);
824 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
825
826 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
827
828 kvfree(in);
829
830 return err;
831}
832
36350114
GP		 833static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
834{
835 struct mlx5e_channel *c = rq->channel;
a43b25da 836 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 837 void *in;
838 void *rqc;
839 int inlen;
840 int err;
841
842 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 843 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 844 if (!in)
845 return -ENOMEM;
846
847 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
848
849 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 850 MLX5_SET64(modify_rq_in, in, modify_bitmask,
851 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 852 MLX5_SET(rqc, rqc, vsd, vsd);
853 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
854
855 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
856
857 kvfree(in);
858
859 return err;
860}
861
3b77235b 862static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 863{
a43b25da 864 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 865}
866
1e7477ae 867static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
f62b8bb8 868{
1e7477ae 869 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
f62b8bb8 870 struct mlx5e_channel *c = rq->channel;
a43b25da 871
422d4c40 872 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
f62b8bb8 873
1e7477ae 874 do {
422d4c40 875 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
f62b8bb8
AV		 876 return 0;
877
878 msleep(20);
1e7477ae
EBE		 879 } while (time_before(jiffies, exp_time));
880
881 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
422d4c40 882 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
f62b8bb8
AV		 883
884 return -ETIMEDOUT;
885}
886
f2fde18c
SM		 887static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
888{
f2fde18c
SM		 889 __be16 wqe_ix_be;
890 u16 wqe_ix;
891
422d4c40
TT		 892 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
893 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
894
99cbfa93 895 /* UMR WQE (if in progress) is always at wq->head */
422d4c40 896 if (rq->mpwqe.umr_in_progress)
afab995e 897 rq->dealloc_wqe(rq, wq->head);
422d4c40
TT		 898
899 while (!mlx5_wq_ll_is_empty(wq)) {
99cbfa93 900 struct mlx5e_rx_wqe_ll *wqe;
422d4c40
TT		 901
902 wqe_ix_be = *wq->tail_next;
903 wqe_ix = be16_to_cpu(wqe_ix_be);
904 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
905 rq->dealloc_wqe(rq, wqe_ix);
906 mlx5_wq_ll_pop(wq, wqe_ix_be,
907 &wqe->next.next_wqe_index);
908 }
909 } else {
99cbfa93 910 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
422d4c40 911
99cbfa93
TT		 912 while (!mlx5_wq_cyc_is_empty(wq)) {
913 wqe_ix = mlx5_wq_cyc_get_tail(wq);
422d4c40 914 rq->dealloc_wqe(rq, wqe_ix);
99cbfa93 915 mlx5_wq_cyc_pop(wq);
422d4c40 916 }
accd5883 917 }
069d1146 918
f2fde18c
SM		 919}
920
f62b8bb8 921static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 922 struct mlx5e_params *params,
f62b8bb8
AV		 923 struct mlx5e_rq_param *param,
924 struct mlx5e_rq *rq)
925{
926 int err;
927
6a9764ef 928 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 929 if (err)
930 return err;
931
3b77235b 932 err = mlx5e_create_rq(rq, param);
f62b8bb8 933 if (err)
3b77235b 934 goto err_free_rq;
f62b8bb8 935
36350114 936 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 937 if (err)
3b77235b 938 goto err_destroy_rq;
f62b8bb8 939
9a317425 940 if (params->rx_dim_enabled)
af5a6c93 941 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
cb3c7fd4 942
b856df28
OG		 943 if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE)
944 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
945
f62b8bb8
AV		 946 return 0;
947
f62b8bb8
AV		 948err_destroy_rq:
949 mlx5e_destroy_rq(rq);
3b77235b
SM		 950err_free_rq:
951 mlx5e_free_rq(rq);
f62b8bb8
AV		 952
953 return err;
954}
955
acc6c595
SM		 956static void mlx5e_activate_rq(struct mlx5e_rq *rq)
957{
958 struct mlx5e_icosq *sq = &rq->channel->icosq;
ddf385e3 959 struct mlx5_wq_cyc *wq = &sq->wq;
acc6c595
SM		 960 struct mlx5e_tx_wqe *nopwqe;
961
ddf385e3
TT		 962 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
963
acc6c595
SM		 964 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
965 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
ddf385e3
TT		 966 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
967 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
acc6c595
SM		 968}
969
970static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 971{
c0f1147d 972 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 973 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 974}
cb3c7fd4 975
acc6c595
SM		 976static void mlx5e_close_rq(struct mlx5e_rq *rq)
977{
9a317425 978 cancel_work_sync(&rq->dim.work);
f62b8bb8 979 mlx5e_destroy_rq(rq);
3b77235b
SM		 980 mlx5e_free_rx_descs(rq);
981 mlx5e_free_rq(rq);
f62b8bb8
AV		 982}
983
31391048 984static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 985{
c94e4f11 986 kvfree(sq->db.xdpi);
b5503b99
SM		 987}
988
31391048 989static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 990{
991 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
992
c94e4f11
TT		 993 sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
994 GFP_KERNEL, numa);
995 if (!sq->db.xdpi) {
31391048 996 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 997 return -ENOMEM;
998 }
999
1000 return 0;
1001}
1002
31391048 1003static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 1004 struct mlx5e_params *params,
31391048 1005 struct mlx5e_sq_param *param,
58b99ee3
TT		 1006 struct mlx5e_xdpsq *sq,
1007 bool is_redirect)
31391048
SM		 1008{
1009 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1010 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1011 struct mlx5_wq_cyc *wq = &sq->wq;
31391048
SM		 1012 int err;
1013
1014 sq->pdev = c->pdev;
1015 sq->mkey_be = c->mkey_be;
1016 sq->channel = c;
1017 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1018 sq->min_inline_mode = params->tx_min_inline_mode;
c94e4f11 1019 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
58b99ee3
TT		 1020 sq->stats = is_redirect ?
1021 &c->priv->channel_stats[c->ix].xdpsq :
1022 &c->priv->channel_stats[c->ix].rq_xdpsq;
31391048 1023
231243c8 1024 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1025 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
31391048
SM		 1026 if (err)
1027 return err;
ddf385e3 1028 wq->db = &wq->db[MLX5_SND_DBR];
31391048 1029
231243c8 1030 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1031 if (err)
1032 goto err_sq_wq_destroy;
1033
1034 return 0;
1035
1036err_sq_wq_destroy:
1037 mlx5_wq_destroy(&sq->wq_ctrl);
1038
1039 return err;
1040}
1041
1042static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1043{
1044 mlx5e_free_xdpsq_db(sq);
1045 mlx5_wq_destroy(&sq->wq_ctrl);
1046}
1047
1048static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 1049{
ca11b798 1050 kvfree(sq->db.ico_wqe);
f62b8bb8
AV		 1051}
1052
31391048 1053static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 1054{
1055 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1056
eec4edc9
KC		 1057 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1058 sizeof(*sq->db.ico_wqe)),
ca11b798 1059 GFP_KERNEL, numa);
f10b7cc7
SM		 1060 if (!sq->db.ico_wqe)
1061 return -ENOMEM;
1062
1063 return 0;
1064}
1065
31391048 1066static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1067 struct mlx5e_sq_param *param,
1068 struct mlx5e_icosq *sq)
f10b7cc7 1069{
31391048 1070 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1071 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1072 struct mlx5_wq_cyc *wq = &sq->wq;
31391048 1073 int err;
f10b7cc7 1074
31391048
SM		 1075 sq->channel = c;
1076 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1077
231243c8 1078 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1079 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
31391048
SM		 1080 if (err)
1081 return err;
ddf385e3 1082 wq->db = &wq->db[MLX5_SND_DBR];
f62b8bb8 1083
231243c8 1084 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1085 if (err)
1086 goto err_sq_wq_destroy;
1087
f62b8bb8 1088 return 0;
31391048
SM		 1089
1090err_sq_wq_destroy:
1091 mlx5_wq_destroy(&sq->wq_ctrl);
1092
1093 return err;
f62b8bb8
AV		 1094}
1095
31391048 1096static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1097{
31391048
SM		 1098 mlx5e_free_icosq_db(sq);
1099 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1100}
1101
31391048 1102static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1103{
ca11b798
TT		 1104 kvfree(sq->db.wqe_info);
1105 kvfree(sq->db.dma_fifo);
f10b7cc7
SM		 1106}
1107
31391048 1108static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1109{
31391048
SM		 1110 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1111 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1112
eec4edc9
KC		 1113 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1114 sizeof(*sq->db.dma_fifo)),
ca11b798 1115 GFP_KERNEL, numa);
eec4edc9
KC		 1116 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1117 sizeof(*sq->db.wqe_info)),
ca11b798 1118 GFP_KERNEL, numa);
77bdf895 1119 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1120 mlx5e_free_txqsq_db(sq);
1121 return -ENOMEM;
b5503b99 1122 }
31391048
SM		 1123
1124 sq->dma_fifo_mask = df_sz - 1;
1125
1126 return 0;
b5503b99
SM		 1127}
1128
db75373c 1129static void mlx5e_sq_recover(struct work_struct *work);
31391048 1130static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1131 int txq_ix,
6a9764ef 1132 struct mlx5e_params *params,
31391048 1133 struct mlx5e_sq_param *param,
05909bab
EBE		 1134 struct mlx5e_txqsq *sq,
1135 int tc)
f62b8bb8 1136{
31391048 1137 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1138 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1139 struct mlx5_wq_cyc *wq = &sq->wq;
f62b8bb8
AV		 1140 int err;
1141
f10b7cc7 1142 sq->pdev = c->pdev;
a43b25da 1143 sq->tstamp = c->tstamp;
7c39afb3 1144 sq->clock = &mdev->clock;
f10b7cc7
SM		 1145 sq->mkey_be = c->mkey_be;
1146 sq->channel = c;
acc6c595 1147 sq->txq_ix = txq_ix;
aff26157 1148 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1149 sq->min_inline_mode = params->tx_min_inline_mode;
05909bab 1150 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
db75373c 1151 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
2ac9cfe7
IT		 1152 if (MLX5_IPSEC_DEV(c->priv->mdev))
1153 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
bf239741
IL		 1154 if (mlx5_accel_is_tls_device(c->priv->mdev))
1155 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
f10b7cc7 1156
231243c8 1157 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1158 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
f62b8bb8 1159 if (err)
aff26157 1160 return err;
ddf385e3 1161 wq->db = &wq->db[MLX5_SND_DBR];
f62b8bb8 1162
231243c8 1163 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1164 if (err)
f62b8bb8
AV		 1165 goto err_sq_wq_destroy;
1166
cbce4f44
TG		 1167 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1168 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1169
f62b8bb8
AV		 1170 return 0;
1171
1172err_sq_wq_destroy:
1173 mlx5_wq_destroy(&sq->wq_ctrl);
1174
f62b8bb8
AV		 1175 return err;
1176}
1177
31391048 1178static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1179{
31391048 1180 mlx5e_free_txqsq_db(sq);
f62b8bb8 1181 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1182}
1183
33ad9711
SM		 1184struct mlx5e_create_sq_param {
1185 struct mlx5_wq_ctrl *wq_ctrl;
1186 u32 cqn;
1187 u32 tisn;
1188 u8 tis_lst_sz;
1189 u8 min_inline_mode;
1190};
1191
a43b25da 1192static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1193 struct mlx5e_sq_param *param,
1194 struct mlx5e_create_sq_param *csp,
1195 u32 *sqn)
f62b8bb8 1196{
f62b8bb8
AV		 1197 void *in;
1198 void *sqc;
1199 void *wq;
1200 int inlen;
1201 int err;
1202
1203 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1204 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1205 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1206 if (!in)
1207 return -ENOMEM;
1208
1209 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1210 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1211
1212 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1213 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1214 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1215 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1216
1217 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1218 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1219
33ad9711 1220 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
db75373c 1221 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
f62b8bb8
AV		 1222
1223 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1224 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1225 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1226 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1227 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1228
3a2f7033
TT		 1229 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1230 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1231
33ad9711 1232 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1233
1234 kvfree(in);
1235
1236 return err;
1237}
1238
33ad9711
SM		 1239struct mlx5e_modify_sq_param {
1240 int curr_state;
1241 int next_state;
1242 bool rl_update;
1243 int rl_index;
1244};
1245
a43b25da 1246static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1247 struct mlx5e_modify_sq_param *p)
f62b8bb8 1248{
f62b8bb8
AV		 1249 void *in;
1250 void *sqc;
1251 int inlen;
1252 int err;
1253
1254 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1255 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1256 if (!in)
1257 return -ENOMEM;
1258
1259 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1260
33ad9711
SM		 1261 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1262 MLX5_SET(sqc, sqc, state, p->next_state);
1263 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1264 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1265 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1266 }
f62b8bb8 1267
33ad9711 1268 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1269
1270 kvfree(in);
1271
1272 return err;
1273}
1274
a43b25da 1275static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1276{
a43b25da 1277 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1278}
1279
a43b25da 1280static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1281 struct mlx5e_sq_param *param,
1282 struct mlx5e_create_sq_param *csp,
1283 u32 *sqn)
f62b8bb8 1284{
33ad9711 1285 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1286 int err;
1287
a43b25da 1288 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1289 if (err)
1290 return err;
1291
1292 msp.curr_state = MLX5_SQC_STATE_RST;
1293 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1294 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1295 if (err)
a43b25da 1296 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1297
1298 return err;
1299}
1300
7f859ecf
SM		 1301static int mlx5e_set_sq_maxrate(struct net_device *dev,
1302 struct mlx5e_txqsq *sq, u32 rate);
1303
31391048 1304static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1305 u32 tisn,
acc6c595 1306 int txq_ix,
6a9764ef 1307 struct mlx5e_params *params,
31391048 1308 struct mlx5e_sq_param *param,
05909bab
EBE		 1309 struct mlx5e_txqsq *sq,
1310 int tc)
31391048
SM		 1311{
1312 struct mlx5e_create_sq_param csp = {};
7f859ecf 1313 u32 tx_rate;
f62b8bb8
AV		 1314 int err;
1315
05909bab 1316 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
f62b8bb8
AV		 1317 if (err)
1318 return err;
1319
a43b25da 1320 csp.tisn = tisn;
31391048 1321 csp.tis_lst_sz = 1;
33ad9711
SM		 1322 csp.cqn = sq->cq.mcq.cqn;
1323 csp.wq_ctrl = &sq->wq_ctrl;
1324 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1325 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1326 if (err)
31391048 1327 goto err_free_txqsq;
f62b8bb8 1328
a43b25da 1329 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1330 if (tx_rate)
a43b25da 1331 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1332
cbce4f44
TG		 1333 if (params->tx_dim_enabled)
1334 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1335
f62b8bb8
AV		 1336 return 0;
1337
31391048 1338err_free_txqsq:
3b77235b 1339 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1340 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1341
1342 return err;
1343}
1344
db75373c
EBE		 1345static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1346{
1347 WARN_ONCE(sq->cc != sq->pc,
1348 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1349 sq->sqn, sq->cc, sq->pc);
1350 sq->cc = 0;
1351 sq->dma_fifo_cc = 0;
1352 sq->pc = 0;
1353}
1354
acc6c595
SM		 1355static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1356{
a43b25da 1357 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
db75373c 1358 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
acc6c595
SM		 1359 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1360 netdev_tx_reset_queue(sq->txq);
1361 netif_tx_start_queue(sq->txq);
1362}
1363
f62b8bb8
AV		 1364static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1365{
1366 __netif_tx_lock_bh(txq);
1367 netif_tx_stop_queue(txq);
1368 __netif_tx_unlock_bh(txq);
1369}
1370
acc6c595 1371static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1372{
33ad9711 1373 struct mlx5e_channel *c = sq->channel;
ddf385e3 1374 struct mlx5_wq_cyc *wq = &sq->wq;
33ad9711 1375
c0f1147d 1376 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1377 /* prevent netif_tx_wake_queue */
33ad9711 1378 napi_synchronize(&c->napi);
29429f33 1379
31391048 1380 netif_tx_disable_queue(sq->txq);
f62b8bb8 1381
31391048 1382 /* last doorbell out, godspeed .. */
ddf385e3
TT		 1383 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1384 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
31391048 1385 struct mlx5e_tx_wqe *nop;
864b2d71 1386
ddf385e3
TT		 1387 sq->db.wqe_info[pi].skb = NULL;
1388 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1389 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1390 }
acc6c595
SM		 1391}
1392
1393static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1394{
1395 struct mlx5e_channel *c = sq->channel;
a43b25da 1396 struct mlx5_core_dev *mdev = c->mdev;
05d3ac97 1397 struct mlx5_rate_limit rl = {0};
f62b8bb8 1398
a43b25da 1399 mlx5e_destroy_sq(mdev, sq->sqn);
05d3ac97
BW		 1400 if (sq->rate_limit) {
1401 rl.rate = sq->rate_limit;
1402 mlx5_rl_remove_rate(mdev, &rl);
1403 }
31391048
SM		 1404 mlx5e_free_txqsq_descs(sq);
1405 mlx5e_free_txqsq(sq);
1406}
1407
db75373c
EBE		 1408static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1409{
1410 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1411
1412 while (time_before(jiffies, exp_time)) {
1413 if (sq->cc == sq->pc)
1414 return 0;
1415
1416 msleep(20);
1417 }
1418
1419 netdev_err(sq->channel->netdev,
1420 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1421 sq->sqn, sq->cc, sq->pc);
1422
1423 return -ETIMEDOUT;
1424}
1425
1426static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1427{
1428 struct mlx5_core_dev *mdev = sq->channel->mdev;
1429 struct net_device *dev = sq->channel->netdev;
1430 struct mlx5e_modify_sq_param msp = {0};
1431 int err;
1432
1433 msp.curr_state = curr_state;
1434 msp.next_state = MLX5_SQC_STATE_RST;
1435
1436 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1437 if (err) {
1438 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1439 return err;
1440 }
1441
1442 memset(&msp, 0, sizeof(msp));
1443 msp.curr_state = MLX5_SQC_STATE_RST;
1444 msp.next_state = MLX5_SQC_STATE_RDY;
1445
1446 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1447 if (err) {
1448 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1449 return err;
1450 }
1451
1452 return 0;
1453}
1454
1455static void mlx5e_sq_recover(struct work_struct *work)
1456{
1457 struct mlx5e_txqsq_recover *recover =
1458 container_of(work, struct mlx5e_txqsq_recover,
1459 recover_work);
1460 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1461 recover);
1462 struct mlx5_core_dev *mdev = sq->channel->mdev;
1463 struct net_device *dev = sq->channel->netdev;
1464 u8 state;
1465 int err;
1466
1467 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1468 if (err) {
1469 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1470 sq->sqn, err);
1471 return;
1472 }
1473
1474 if (state != MLX5_RQC_STATE_ERR) {
1475 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1476 return;
1477 }
1478
1479 netif_tx_disable_queue(sq->txq);
1480
1481 if (mlx5e_wait_for_sq_flush(sq))
1482 return;
1483
1484 /* If the interval between two consecutive recovers per SQ is too
1485 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1486 * If we reached this state, there is probably a bug that needs to be
1487 * fixed. let's keep the queue close and let tx timeout cleanup.
1488 */
1489 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1490 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1491 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1492 sq->sqn);
1493 return;
1494 }
1495
1496 /* At this point, no new packets will arrive from the stack as TXQ is
1497 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1498 * pending WQEs. SQ can safely reset the SQ.
1499 */
1500 if (mlx5e_sq_to_ready(sq, state))
1501 return;
1502
1503 mlx5e_reset_txqsq_cc_pc(sq);
05909bab 1504 sq->stats->recover++;
db75373c
EBE		 1505 recover->last_recover = jiffies;
1506 mlx5e_activate_txqsq(sq);
1507}
1508
31391048 1509static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1510 struct mlx5e_params *params,
31391048
SM		 1511 struct mlx5e_sq_param *param,
1512 struct mlx5e_icosq *sq)
1513{
1514 struct mlx5e_create_sq_param csp = {};
1515 int err;
1516
6a9764ef 1517 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1518 if (err)
1519 return err;
1520
1521 csp.cqn = sq->cq.mcq.cqn;
1522 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1523 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1524 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1525 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1526 if (err)
1527 goto err_free_icosq;
1528
1529 return 0;
1530
1531err_free_icosq:
1532 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1533 mlx5e_free_icosq(sq);
1534
1535 return err;
1536}
1537
1538static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1539{
1540 struct mlx5e_channel *c = sq->channel;
1541
1542 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1543 napi_synchronize(&c->napi);
1544
a43b25da 1545 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1546 mlx5e_free_icosq(sq);
1547}
1548
1549static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1550 struct mlx5e_params *params,
31391048 1551 struct mlx5e_sq_param *param,
58b99ee3
TT		 1552 struct mlx5e_xdpsq *sq,
1553 bool is_redirect)
31391048
SM		 1554{
1555 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1556 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1557 unsigned int inline_hdr_sz = 0;
1558 int err;
1559 int i;
1560
58b99ee3 1561 err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
31391048
SM		 1562 if (err)
1563 return err;
1564
1565 csp.tis_lst_sz = 1;
a43b25da 1566 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1567 csp.cqn = sq->cq.mcq.cqn;
1568 csp.wq_ctrl = &sq->wq_ctrl;
1569 csp.min_inline_mode = sq->min_inline_mode;
58b99ee3
TT		 1570 if (is_redirect)
1571 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
31391048 1572 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1573 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1574 if (err)
1575 goto err_free_xdpsq;
1576
1577 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1578 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1579 ds_cnt++;
1580 }
1581
1582 /* Pre initialize fixed WQE fields */
1583 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1584 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1585 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1586 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1587 struct mlx5_wqe_data_seg *dseg;
1588
1589 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1590 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1591
1592 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1593 dseg->lkey = sq->mkey_be;
1594 }
1595
1596 return 0;
1597
1598err_free_xdpsq:
1599 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1600 mlx5e_free_xdpsq(sq);
1601
1602 return err;
1603}
1604
1605static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1606{
1607 struct mlx5e_channel *c = sq->channel;
1608
1609 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1610 napi_synchronize(&c->napi);
1611
a43b25da 1612 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1613 mlx5e_free_xdpsq_descs(sq);
1614 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1615}
1616
95b6c6a5
EBE		 1617static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1618 struct mlx5e_cq_param *param,
1619 struct mlx5e_cq *cq)
f62b8bb8 1620{
f62b8bb8
AV		 1621 struct mlx5_core_cq *mcq = &cq->mcq;
1622 int eqn_not_used;
0b6e26ce 1623 unsigned int irqn;
f62b8bb8
AV		 1624 int err;
1625 u32 i;
1626
a1f240f1
YA		 1627 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1628 if (err)
1629 return err;
1630
f62b8bb8
AV		 1631 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1632 &cq->wq_ctrl);
1633 if (err)
1634 return err;
1635
f62b8bb8
AV		 1636 mcq->cqe_sz = 64;
1637 mcq->set_ci_db = cq->wq_ctrl.db.db;
1638 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1639 *mcq->set_ci_db = 0;
1640 *mcq->arm_db = 0;
1641 mcq->vector = param->eq_ix;
1642 mcq->comp = mlx5e_completion_event;
1643 mcq->event = mlx5e_cq_error_event;
1644 mcq->irqn = irqn;
f62b8bb8
AV		 1645
1646 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1647 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1648
1649 cqe->op_own = 0xf1;
1650 }
1651
a43b25da 1652 cq->mdev = mdev;
f62b8bb8
AV		 1653
1654 return 0;
1655}
1656
95b6c6a5
EBE		 1657static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1658 struct mlx5e_cq_param *param,
1659 struct mlx5e_cq *cq)
1660{
1661 struct mlx5_core_dev *mdev = c->priv->mdev;
1662 int err;
1663
231243c8
SM		 1664 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1665 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1666 param->eq_ix = c->ix;
1667
1668 err = mlx5e_alloc_cq_common(mdev, param, cq);
1669
1670 cq->napi = &c->napi;
1671 cq->channel = c;
1672
1673 return err;
1674}
1675
3b77235b 1676static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1677{
3a2f7033 1678 mlx5_wq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1679}
1680
3b77235b 1681static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1682{
a43b25da 1683 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1684 struct mlx5_core_cq *mcq = &cq->mcq;
1685
1686 void *in;
1687 void *cqc;
1688 int inlen;
0b6e26ce 1689 unsigned int irqn_not_used;
f62b8bb8
AV		 1690 int eqn;
1691 int err;
1692
a1f240f1
YA		 1693 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1694 if (err)
1695 return err;
1696
f62b8bb8 1697 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
3a2f7033 1698 sizeof(u64) * cq->wq_ctrl.buf.npages;
1b9a07ee 1699 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1700 if (!in)
1701 return -ENOMEM;
1702
1703 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1704
1705 memcpy(cqc, param->cqc, sizeof(param->cqc));
1706
3a2f7033 1707 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1c1b5228 1708 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8 1709
9908aa29 1710 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1711 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1712 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
3a2f7033 1713 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 1714 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1715 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1716
1717 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1718
1719 kvfree(in);
1720
1721 if (err)
1722 return err;
1723
1724 mlx5e_cq_arm(cq);
1725
1726 return 0;
1727}
1728
3b77235b 1729static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1730{
a43b25da 1731 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1732}
1733
1734static int mlx5e_open_cq(struct mlx5e_channel *c,
9a317425 1735 struct net_dim_cq_moder moder,
f62b8bb8 1736 struct mlx5e_cq_param *param,
6a9764ef 1737 struct mlx5e_cq *cq)
f62b8bb8 1738{
a43b25da 1739 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1740 int err;
f62b8bb8 1741
3b77235b 1742 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1743 if (err)
1744 return err;
1745
3b77235b 1746 err = mlx5e_create_cq(cq, param);
f62b8bb8 1747 if (err)
3b77235b 1748 goto err_free_cq;
f62b8bb8 1749
7524a5d8 1750 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1751 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1752 return 0;
1753
3b77235b
SM		 1754err_free_cq:
1755 mlx5e_free_cq(cq);
f62b8bb8
AV		 1756
1757 return err;
1758}
1759
1760static void mlx5e_close_cq(struct mlx5e_cq *cq)
1761{
f62b8bb8 1762 mlx5e_destroy_cq(cq);
3b77235b 1763 mlx5e_free_cq(cq);
f62b8bb8
AV		 1764}
1765
231243c8
SM		 1766static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1767{
1768 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1769}
1770
f62b8bb8 1771static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1772 struct mlx5e_params *params,
f62b8bb8
AV		 1773 struct mlx5e_channel_param *cparam)
1774{
f62b8bb8
AV		 1775 int err;
1776 int tc;
1777
1778 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1779 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1780 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1781 if (err)
1782 goto err_close_tx_cqs;
f62b8bb8
AV		 1783 }
1784
1785 return 0;
1786
1787err_close_tx_cqs:
1788 for (tc--; tc >= 0; tc--)
1789 mlx5e_close_cq(&c->sq[tc].cq);
1790
1791 return err;
1792}
1793
1794static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1795{
1796 int tc;
1797
1798 for (tc = 0; tc < c->num_tc; tc++)
1799 mlx5e_close_cq(&c->sq[tc].cq);
1800}
1801
1802static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1803 struct mlx5e_params *params,
f62b8bb8
AV		 1804 struct mlx5e_channel_param *cparam)
1805{
05909bab 1806 struct mlx5e_priv *priv = c->priv;
779d986d 1807 int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
f62b8bb8 1808
6a9764ef 1809 for (tc = 0; tc < params->num_tc; tc++) {
05909bab 1810 int txq_ix = c->ix + tc * max_nch;
acc6c595 1811
a43b25da 1812 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
05909bab 1813 params, &cparam->sq, &c->sq[tc], tc);
f62b8bb8
AV		 1814 if (err)
1815 goto err_close_sqs;
1816 }
1817
1818 return 0;
1819
1820err_close_sqs:
1821 for (tc--; tc >= 0; tc--)
31391048 1822 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1823
1824 return err;
1825}
1826
1827static void mlx5e_close_sqs(struct mlx5e_channel *c)
1828{
1829 int tc;
1830
1831 for (tc = 0; tc < c->num_tc; tc++)
31391048 1832 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1833}
1834
507f0c81 1835static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1836 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1837{
1838 struct mlx5e_priv *priv = netdev_priv(dev);
1839 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1840 struct mlx5e_modify_sq_param msp = {0};
05d3ac97 1841 struct mlx5_rate_limit rl = {0};
507f0c81
YP		 1842 u16 rl_index = 0;
1843 int err;
1844
1845 if (rate == sq->rate_limit)
1846 /* nothing to do */
1847 return 0;
1848
05d3ac97
BW		 1849 if (sq->rate_limit) {
1850 rl.rate = sq->rate_limit;
507f0c81 1851 /* remove current rl index to free space to next ones */
05d3ac97
BW		 1852 mlx5_rl_remove_rate(mdev, &rl);
1853 }
507f0c81
YP		 1854
1855 sq->rate_limit = 0;
1856
1857 if (rate) {
05d3ac97
BW		 1858 rl.rate = rate;
1859 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
507f0c81
YP		 1860 if (err) {
1861 netdev_err(dev, "Failed configuring rate %u: %d\n",
1862 rate, err);
1863 return err;
1864 }
1865 }
1866
33ad9711
SM		 1867 msp.curr_state = MLX5_SQC_STATE_RDY;
1868 msp.next_state = MLX5_SQC_STATE_RDY;
1869 msp.rl_index = rl_index;
1870 msp.rl_update = true;
a43b25da 1871 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1872 if (err) {
1873 netdev_err(dev, "Failed configuring rate %u: %d\n",
1874 rate, err);
1875 /* remove the rate from the table */
1876 if (rate)
05d3ac97 1877 mlx5_rl_remove_rate(mdev, &rl);
507f0c81
YP		 1878 return err;
1879 }
1880
1881 sq->rate_limit = rate;
1882 return 0;
1883}
1884
1885static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1886{
1887 struct mlx5e_priv *priv = netdev_priv(dev);
1888 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1889 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1890 int err = 0;
1891
1892 if (!mlx5_rl_is_supported(mdev)) {
1893 netdev_err(dev, "Rate limiting is not supported on this device\n");
1894 return -EINVAL;
1895 }
1896
1897 /* rate is given in Mb/sec, HW config is in Kb/sec */
1898 rate = rate << 10;
1899
1900 /* Check whether rate in valid range, 0 is always valid */
1901 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1902 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1903 return -ERANGE;
1904 }
1905
1906 mutex_lock(&priv->state_lock);
1907 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1908 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1909 if (!err)
1910 priv->tx_rates[index] = rate;
1911 mutex_unlock(&priv->state_lock);
1912
1913 return err;
1914}
1915
f62b8bb8 1916static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1917 struct mlx5e_params *params,
f62b8bb8
AV		 1918 struct mlx5e_channel_param *cparam,
1919 struct mlx5e_channel **cp)
1920{
9a317425 1921 struct net_dim_cq_moder icocq_moder = {0, 0};
f62b8bb8 1922 struct net_device *netdev = priv->netdev;
231243c8 1923 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1924 struct mlx5e_channel *c;
a8c2eb15 1925 unsigned int irq;
f62b8bb8 1926 int err;
a8c2eb15 1927 int eqn;
f62b8bb8 1928
a1f240f1
YA		 1929 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1930 if (err)
1931 return err;
1932
ca11b798 1933 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1934 if (!c)
1935 return -ENOMEM;
1936
1937 c->priv = priv;
a43b25da
SM		 1938 c->mdev = priv->mdev;
1939 c->tstamp = &priv->tstamp;
f62b8bb8 1940 c->ix = ix;
231243c8 1941 c->cpu = cpu;
f62b8bb8
AV		 1942 c->pdev = &priv->mdev->pdev->dev;
1943 c->netdev = priv->netdev;
b50d292b 1944 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1945 c->num_tc = params->num_tc;
1946 c->xdp = !!params->xdp_prog;
05909bab 1947 c->stats = &priv->channel_stats[ix].ch;
cb3c7fd4 1948
a8c2eb15
TT		 1949 c->irq_desc = irq_to_desc(irq);
1950
f62b8bb8
AV		 1951 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1952
6a9764ef 1953 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1954 if (err)
1955 goto err_napi_del;
1956
6a9764ef 1957 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1958 if (err)
1959 goto err_close_icosq_cq;
1960
58b99ee3 1961 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
f62b8bb8
AV		 1962 if (err)
1963 goto err_close_tx_cqs;
f62b8bb8 1964
58b99ee3
TT		 1965 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1966 if (err)
1967 goto err_close_xdp_tx_cqs;
1968
d7a0ecab 1969 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1970 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1971 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1972 if (err)
1973 goto err_close_rx_cq;
1974
f62b8bb8
AV		 1975 napi_enable(&c->napi);
1976
6a9764ef 1977 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1978 if (err)
1979 goto err_disable_napi;
1980
6a9764ef 1981 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1982 if (err)
1983 goto err_close_icosq;
1984
58b99ee3 1985 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
d7a0ecab
SM		 1986 if (err)
1987 goto err_close_sqs;
b5503b99 1988
6a9764ef 1989 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1990 if (err)
b5503b99 1991 goto err_close_xdp_sq;
f62b8bb8 1992
58b99ee3
TT		 1993 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1994 if (err)
1995 goto err_close_rq;
1996
f62b8bb8
AV		 1997 *cp = c;
1998
1999 return 0;
58b99ee3
TT		 2000
2001err_close_rq:
2002 mlx5e_close_rq(&c->rq);
2003
b5503b99 2004err_close_xdp_sq:
d7a0ecab 2005 if (c->xdp)
31391048 2006 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 2007
2008err_close_sqs:
2009 mlx5e_close_sqs(c);
2010
d3c9bc27 2011err_close_icosq:
31391048 2012 mlx5e_close_icosq(&c->icosq);
d3c9bc27 2013
f62b8bb8
AV		 2014err_disable_napi:
2015 napi_disable(&c->napi);
d7a0ecab 2016 if (c->xdp)
31871f87 2017 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 2018
2019err_close_rx_cq:
f62b8bb8
AV		 2020 mlx5e_close_cq(&c->rq.cq);
2021
58b99ee3
TT		 2022err_close_xdp_tx_cqs:
2023 mlx5e_close_cq(&c->xdpsq.cq);
2024
f62b8bb8
AV		 2025err_close_tx_cqs:
2026 mlx5e_close_tx_cqs(c);
2027
d3c9bc27
TT		 2028err_close_icosq_cq:
2029 mlx5e_close_cq(&c->icosq.cq);
2030
f62b8bb8
AV		 2031err_napi_del:
2032 netif_napi_del(&c->napi);
ca11b798 2033 kvfree(c);
f62b8bb8
AV		 2034
2035 return err;
2036}
2037
acc6c595
SM		 2038static void mlx5e_activate_channel(struct mlx5e_channel *c)
2039{
2040 int tc;
2041
2042 for (tc = 0; tc < c->num_tc; tc++)
2043 mlx5e_activate_txqsq(&c->sq[tc]);
2044 mlx5e_activate_rq(&c->rq);
231243c8 2045 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 2046}
2047
2048static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2049{
2050 int tc;
2051
2052 mlx5e_deactivate_rq(&c->rq);
2053 for (tc = 0; tc < c->num_tc; tc++)
2054 mlx5e_deactivate_txqsq(&c->sq[tc]);
2055}
2056
f62b8bb8
AV		 2057static void mlx5e_close_channel(struct mlx5e_channel *c)
2058{
58b99ee3 2059 mlx5e_close_xdpsq(&c->xdpsq);
f62b8bb8 2060 mlx5e_close_rq(&c->rq);
b5503b99 2061 if (c->xdp)
31391048 2062 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 2063 mlx5e_close_sqs(c);
31391048 2064 mlx5e_close_icosq(&c->icosq);
f62b8bb8 2065 napi_disable(&c->napi);
b5503b99 2066 if (c->xdp)
31871f87 2067 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8 2068 mlx5e_close_cq(&c->rq.cq);
58b99ee3 2069 mlx5e_close_cq(&c->xdpsq.cq);
f62b8bb8 2070 mlx5e_close_tx_cqs(c);
d3c9bc27 2071 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 2072 netif_napi_del(&c->napi);
7ae92ae5 2073
ca11b798 2074 kvfree(c);
f62b8bb8
AV		 2075}
2076
069d1146
TT		 2077#define DEFAULT_FRAG_SIZE (2048)
2078
2079static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2080 struct mlx5e_params *params,
2081 struct mlx5e_rq_frags_info *info)
2082{
2083 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2084 int frag_size_max = DEFAULT_FRAG_SIZE;
2085 u32 buf_size = 0;
2086 int i;
2087
2088#ifdef CONFIG_MLX5_EN_IPSEC
2089 if (MLX5_IPSEC_DEV(mdev))
2090 byte_count += MLX5E_METADATA_ETHER_LEN;
2091#endif
2092
2093 if (mlx5e_rx_is_linear_skb(mdev, params)) {
2094 int frag_stride;
2095
2096 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2097 frag_stride = roundup_pow_of_two(frag_stride);
2098
2099 info->arr[0].frag_size = byte_count;
2100 info->arr[0].frag_stride = frag_stride;
2101 info->num_frags = 1;
2102 info->wqe_bulk = PAGE_SIZE / frag_stride;
2103 goto out;
2104 }
2105
2106 if (byte_count > PAGE_SIZE +
2107 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2108 frag_size_max = PAGE_SIZE;
2109
2110 i = 0;
2111 while (buf_size < byte_count) {
2112 int frag_size = byte_count - buf_size;
2113
2114 if (i < MLX5E_MAX_RX_FRAGS - 1)
2115 frag_size = min(frag_size, frag_size_max);
2116
2117 info->arr[i].frag_size = frag_size;
2118 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2119
2120 buf_size += frag_size;
2121 i++;
2122 }
2123 info->num_frags = i;
2124 /* number of different wqes sharing a page */
2125 info->wqe_bulk = 1 + (info->num_frags % 2);
2126
2127out:
2128 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2129 info->log_num_frags = order_base_2(info->num_frags);
2130}
2131
99cbfa93
TT		 2132static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2133{
2134 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2135
2136 switch (wq_type) {
2137 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2138 sz += sizeof(struct mlx5e_rx_wqe_ll);
2139 break;
2140 default: /* MLX5_WQ_TYPE_CYCLIC */
2141 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2142 }
2143
2144 return order_base_2(sz);
2145}
2146
f62b8bb8 2147static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 2148 struct mlx5e_params *params,
f62b8bb8
AV		 2149 struct mlx5e_rq_param *param)
2150{
f1e4fc9b 2151 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2152 void *rqc = param->rqc;
2153 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
99cbfa93 2154 int ndsegs = 1;
f62b8bb8 2155
6a9764ef 2156 switch (params->rq_wq_type) {
461017cb 2157 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f1e4fc9b 2158 MLX5_SET(wq, wq, log_wqe_num_of_strides,
619a8f2a
TT		 2159 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2160 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
f1e4fc9b 2161 MLX5_SET(wq, wq, log_wqe_stride_size,
619a8f2a
TT		 2162 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2163 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
73281b78 2164 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
461017cb 2165 break;
99cbfa93 2166 default: /* MLX5_WQ_TYPE_CYCLIC */
73281b78 2167 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
069d1146
TT		 2168 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2169 ndsegs = param->frags_info.num_frags;
461017cb
TT		 2170 }
2171
99cbfa93 2172 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
f62b8bb8 2173 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
99cbfa93
TT		 2174 MLX5_SET(wq, wq, log_wq_stride,
2175 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
f1e4fc9b 2176 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
593cf338 2177 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 2178 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 2179 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 2180
f1e4fc9b 2181 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
f62b8bb8
AV		 2182}
2183
7cbaf9a3 2184static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2f0db879 2185 struct mlx5e_rq_param *param)
556dd1b9 2186{
7cbaf9a3 2187 struct mlx5_core_dev *mdev = priv->mdev;
556dd1b9
TT		 2188 void *rqc = param->rqc;
2189 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2190
99cbfa93
TT		 2191 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2192 MLX5_SET(wq, wq, log_wq_stride,
2193 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
7cbaf9a3 2194 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2f0db879
GP		 2195
2196 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
556dd1b9
TT		 2197}
2198
d3c9bc27
TT		 2199static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2200 struct mlx5e_sq_param *param)
f62b8bb8
AV		 2201{
2202 void *sqc = param->sqc;
2203 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2204
f62b8bb8 2205 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 2206 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 2207
311c7c71 2208 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 2209}
2210
2211static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 2212 struct mlx5e_params *params,
d3c9bc27
TT		 2213 struct mlx5e_sq_param *param)
2214{
2215 void *sqc = param->sqc;
2216 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2217
2218 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2219 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 2220 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 2221}
2222
2223static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2224 struct mlx5e_cq_param *param)
2225{
2226 void *cqc = param->cqc;
2227
30aa60b3 2228 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 2229}
2230
2231static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 2232 struct mlx5e_params *params,
f62b8bb8
AV		 2233 struct mlx5e_cq_param *param)
2234{
73281b78 2235 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8 2236 void *cqc = param->cqc;
461017cb 2237 u8 log_cq_size;
f62b8bb8 2238
6a9764ef 2239 switch (params->rq_wq_type) {
461017cb 2240 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
73281b78
TT		 2241 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2242 mlx5e_mpwqe_get_log_num_strides(mdev, params);
461017cb 2243 break;
99cbfa93 2244 default: /* MLX5_WQ_TYPE_CYCLIC */
73281b78 2245 log_cq_size = params->log_rq_mtu_frames;
461017cb
TT		 2246 }
2247
2248 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 2249 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 2250 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2251 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2252 }
f62b8bb8
AV		 2253
2254 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2255 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2256}
2257
2258static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 2259 struct mlx5e_params *params,
f62b8bb8
AV		 2260 struct mlx5e_cq_param *param)
2261{
2262 void *cqc = param->cqc;
2263
6a9764ef 2264 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 2265
2266 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2267 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2268}
2269
d3c9bc27 2270static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2271 u8 log_wq_size,
2272 struct mlx5e_cq_param *param)
d3c9bc27
TT		 2273{
2274 void *cqc = param->cqc;
2275
2276 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2277
2278 mlx5e_build_common_cq_param(priv, param);
9908aa29 2279
9a317425 2280 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 2281}
2282
2283static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2284 u8 log_wq_size,
2285 struct mlx5e_sq_param *param)
d3c9bc27
TT		 2286{
2287 void *sqc = param->sqc;
2288 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2289
2290 mlx5e_build_sq_param_common(priv, param);
2291
2292 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 2293 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 2294}
2295
b5503b99 2296static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 2297 struct mlx5e_params *params,
b5503b99
SM		 2298 struct mlx5e_sq_param *param)
2299{
2300 void *sqc = param->sqc;
2301 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2302
2303 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2304 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 2305}
2306
6a9764ef
SM		 2307static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2308 struct mlx5e_params *params,
2309 struct mlx5e_channel_param *cparam)
f62b8bb8 2310{
bc77b240 2311 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2312
6a9764ef
SM		 2313 mlx5e_build_rq_param(priv, params, &cparam->rq);
2314 mlx5e_build_sq_param(priv, params, &cparam->sq);
2315 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2316 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2317 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2318 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2319 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2320}
2321
55c2503d
SM		 2322int mlx5e_open_channels(struct mlx5e_priv *priv,
2323 struct mlx5e_channels *chs)
f62b8bb8 2324{
6b87663f 2325 struct mlx5e_channel_param *cparam;
03289b88 2326 int err = -ENOMEM;
f62b8bb8 2327 int i;
f62b8bb8 2328
6a9764ef 2329 chs->num = chs->params.num_channels;
03289b88 2330
ff9c852f 2331 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
ca11b798 2332 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2333 if (!chs->c || !cparam)
2334 goto err_free;
f62b8bb8 2335
6a9764ef 2336 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2337 for (i = 0; i < chs->num; i++) {
6a9764ef 2338 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2339 if (err)
2340 goto err_close_channels;
2341 }
2342
ca11b798 2343 kvfree(cparam);
f62b8bb8
AV		 2344 return 0;
2345
2346err_close_channels:
2347 for (i--; i >= 0; i--)
ff9c852f 2348 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2349
acc6c595 2350err_free:
ff9c852f 2351 kfree(chs->c);
ca11b798 2352 kvfree(cparam);
ff9c852f 2353 chs->num = 0;
f62b8bb8
AV		 2354 return err;
2355}
2356
acc6c595 2357static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2358{
2359 int i;
2360
acc6c595
SM		 2361 for (i = 0; i < chs->num; i++)
2362 mlx5e_activate_channel(chs->c[i]);
2363}
2364
2365static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2366{
2367 int err = 0;
2368 int i;
2369
1e7477ae
EBE		 2370 for (i = 0; i < chs->num; i++)
2371 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2372 err ? 0 : 20000);
acc6c595 2373
1e7477ae 2374 return err ? -ETIMEDOUT : 0;
acc6c595
SM		 2375}
2376
2377static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2378{
2379 int i;
2380
2381 for (i = 0; i < chs->num; i++)
2382 mlx5e_deactivate_channel(chs->c[i]);
2383}
2384
55c2503d 2385void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2386{
2387 int i;
c3b7c5c9 2388
ff9c852f
SM		 2389 for (i = 0; i < chs->num; i++)
2390 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2391
ff9c852f
SM		 2392 kfree(chs->c);
2393 chs->num = 0;
f62b8bb8
AV		 2394}
2395
a5f97fee
SM		 2396static int
2397mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2398{
2399 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2400 void *rqtc;
2401 int inlen;
2402 int err;
1da36696 2403 u32 *in;
a5f97fee 2404 int i;
f62b8bb8 2405
f62b8bb8 2406 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2407 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2408 if (!in)
2409 return -ENOMEM;
2410
2411 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2412
2413 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2414 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2415
a5f97fee
SM		 2416 for (i = 0; i < sz; i++)
2417 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2418
398f3351
HHZ		 2419 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2420 if (!err)
2421 rqt->enabled = true;
f62b8bb8
AV		 2422
2423 kvfree(in);
1da36696
TT		 2424 return err;
2425}
2426
cb67b832 2427void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2428{
398f3351
HHZ		 2429 rqt->enabled = false;
2430 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2431}
2432
8f493ffd 2433int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2434{
2435 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2436 int err;
6bfd390b 2437
8f493ffd
SM		 2438 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2439 if (err)
2440 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2441 return err;
6bfd390b
HHZ		 2442}
2443
cb67b832 2444int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2445{
398f3351 2446 struct mlx5e_rqt *rqt;
1da36696
TT		 2447 int err;
2448 int ix;
2449
779d986d 2450 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
398f3351 2451 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2452 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2453 if (err)
2454 goto err_destroy_rqts;
2455 }
2456
2457 return 0;
2458
2459err_destroy_rqts:
8f493ffd 2460 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2461 for (ix--; ix >= 0; ix--)
398f3351 2462 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2463
f62b8bb8
AV		 2464 return err;
2465}
2466
8f493ffd
SM		 2467void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2468{
2469 int i;
2470
779d986d 2471 for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
8f493ffd
SM		 2472 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2473}
2474
a5f97fee
SM		 2475static int mlx5e_rx_hash_fn(int hfunc)
2476{
2477 return (hfunc == ETH_RSS_HASH_TOP) ?
2478 MLX5_RX_HASH_FN_TOEPLITZ :
2479 MLX5_RX_HASH_FN_INVERTED_XOR8;
2480}
2481
3f6d08d1 2482int mlx5e_bits_invert(unsigned long a, int size)
a5f97fee
SM		 2483{
2484 int inv = 0;
2485 int i;
2486
2487 for (i = 0; i < size; i++)
2488 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2489
2490 return inv;
2491}
2492
2493static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2494 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2495{
2496 int i;
2497
2498 for (i = 0; i < sz; i++) {
2499 u32 rqn;
2500
2501 if (rrp.is_rss) {
2502 int ix = i;
2503
2504 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2505 ix = mlx5e_bits_invert(i, ilog2(sz));
2506
6a9764ef 2507 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2508 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2509 } else {
2510 rqn = rrp.rqn;
2511 }
2512 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2513 }
2514}
2515
2516int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2517 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2518{
2519 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2520 void *rqtc;
2521 int inlen;
1da36696 2522 u32 *in;
5c50368f
AS		 2523 int err;
2524
5c50368f 2525 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2526 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2527 if (!in)
2528 return -ENOMEM;
2529
2530 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2531
2532 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2533 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2534 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2535 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2536
2537 kvfree(in);
5c50368f
AS		 2538 return err;
2539}
2540
a5f97fee
SM		 2541static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2542 struct mlx5e_redirect_rqt_param rrp)
2543{
2544 if (!rrp.is_rss)
2545 return rrp.rqn;
2546
2547 if (ix >= rrp.rss.channels->num)
2548 return priv->drop_rq.rqn;
2549
2550 return rrp.rss.channels->c[ix]->rq.rqn;
2551}
2552
2553static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2554 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2555{
1da36696
TT		 2556 u32 rqtn;
2557 int ix;
2558
398f3351 2559 if (priv->indir_rqt.enabled) {
a5f97fee 2560 /* RSS RQ table */
398f3351 2561 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2562 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2563 }
2564
779d986d 2565 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
a5f97fee
SM		 2566 struct mlx5e_redirect_rqt_param direct_rrp = {
2567 .is_rss = false,
95632791
AM		 2568 {
2569 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2570 },
a5f97fee
SM		 2571 };
2572
2573 /* Direct RQ Tables */
398f3351
HHZ		 2574 if (!priv->direct_tir[ix].rqt.enabled)
2575 continue;
a5f97fee 2576
398f3351 2577 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2578 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2579 }
40ab6a6e
AS		 2580}
2581
a5f97fee
SM		 2582static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2583 struct mlx5e_channels *chs)
2584{
2585 struct mlx5e_redirect_rqt_param rrp = {
2586 .is_rss = true,
95632791
AM		 2587 {
2588 .rss = {
2589 .channels = chs,
2590 .hfunc = chs->params.rss_hfunc,
2591 }
2592 },
a5f97fee
SM		 2593 };
2594
2595 mlx5e_redirect_rqts(priv, rrp);
2596}
2597
2598static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2599{
2600 struct mlx5e_redirect_rqt_param drop_rrp = {
2601 .is_rss = false,
95632791
AM		 2602 {
2603 .rqn = priv->drop_rq.rqn,
2604 },
a5f97fee
SM		 2605 };
2606
2607 mlx5e_redirect_rqts(priv, drop_rrp);
2608}
2609
6a9764ef 2610static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2611{
6a9764ef 2612 if (!params->lro_en)
5c50368f
AS		 2613 return;
2614
2615#define ROUGH_MAX_L2_L3_HDR_SZ 256
2616
2617 MLX5_SET(tirc, tirc, lro_enable_mask,
2618 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2619 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2620 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2621 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2622 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2623}
2624
6a9764ef
SM		 2625void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2626 enum mlx5e_traffic_types tt,
7b3722fa 2627 void *tirc, bool inner)
bdfc028d 2628{
7b3722fa
GP		 2629 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2630 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2631
2632#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2633 MLX5_HASH_FIELD_SEL_DST_IP)
2634
2635#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2636 MLX5_HASH_FIELD_SEL_DST_IP |\
2637 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2638 MLX5_HASH_FIELD_SEL_L4_DPORT)
2639
2640#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2641 MLX5_HASH_FIELD_SEL_DST_IP |\
2642 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2643
6a9764ef
SM		 2644 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2645 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2646 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2647 rx_hash_toeplitz_key);
2648 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2649 rx_hash_toeplitz_key);
2650
2651 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2652 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2653 }
a100ff3e
GP		 2654
2655 switch (tt) {
2656 case MLX5E_TT_IPV4_TCP:
2657 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2658 MLX5_L3_PROT_TYPE_IPV4);
2659 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2660 MLX5_L4_PROT_TYPE_TCP);
2661 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2662 MLX5_HASH_IP_L4PORTS);
2663 break;
2664
2665 case MLX5E_TT_IPV6_TCP:
2666 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2667 MLX5_L3_PROT_TYPE_IPV6);
2668 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2669 MLX5_L4_PROT_TYPE_TCP);
2670 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2671 MLX5_HASH_IP_L4PORTS);
2672 break;
2673
2674 case MLX5E_TT_IPV4_UDP:
2675 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2676 MLX5_L3_PROT_TYPE_IPV4);
2677 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2678 MLX5_L4_PROT_TYPE_UDP);
2679 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2680 MLX5_HASH_IP_L4PORTS);
2681 break;
2682
2683 case MLX5E_TT_IPV6_UDP:
2684 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2685 MLX5_L3_PROT_TYPE_IPV6);
2686 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2687 MLX5_L4_PROT_TYPE_UDP);
2688 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2689 MLX5_HASH_IP_L4PORTS);
2690 break;
2691
2692 case MLX5E_TT_IPV4_IPSEC_AH:
2693 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2694 MLX5_L3_PROT_TYPE_IPV4);
2695 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2696 MLX5_HASH_IP_IPSEC_SPI);
2697 break;
2698
2699 case MLX5E_TT_IPV6_IPSEC_AH:
2700 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2701 MLX5_L3_PROT_TYPE_IPV6);
2702 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2703 MLX5_HASH_IP_IPSEC_SPI);
2704 break;
2705
2706 case MLX5E_TT_IPV4_IPSEC_ESP:
2707 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2708 MLX5_L3_PROT_TYPE_IPV4);
2709 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710 MLX5_HASH_IP_IPSEC_SPI);
2711 break;
2712
2713 case MLX5E_TT_IPV6_IPSEC_ESP:
2714 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2715 MLX5_L3_PROT_TYPE_IPV6);
2716 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2717 MLX5_HASH_IP_IPSEC_SPI);
2718 break;
2719
2720 case MLX5E_TT_IPV4:
2721 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2722 MLX5_L3_PROT_TYPE_IPV4);
2723 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2724 MLX5_HASH_IP);
2725 break;
2726
2727 case MLX5E_TT_IPV6:
2728 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2729 MLX5_L3_PROT_TYPE_IPV6);
2730 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2731 MLX5_HASH_IP);
2732 break;
2733 default:
2734 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2735 }
bdfc028d
TT		 2736}
2737
ab0394fe 2738static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2739{
2740 struct mlx5_core_dev *mdev = priv->mdev;
2741
2742 void *in;
2743 void *tirc;
2744 int inlen;
2745 int err;
ab0394fe 2746 int tt;
1da36696 2747 int ix;
5c50368f
AS		 2748
2749 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2750 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2751 if (!in)
2752 return -ENOMEM;
2753
2754 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2755 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2756
6a9764ef 2757 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2758
1da36696 2759 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2760 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2761 inlen);
ab0394fe 2762 if (err)
1da36696 2763 goto free_in;
ab0394fe 2764 }
5c50368f 2765
779d986d 2766 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
1da36696
TT		 2767 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2768 in, inlen);
2769 if (err)
2770 goto free_in;
2771 }
2772
2773free_in:
5c50368f
AS		 2774 kvfree(in);
2775
2776 return err;
2777}
2778
7b3722fa
GP		 2779static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2780 enum mlx5e_traffic_types tt,
2781 u32 *tirc)
2782{
2783 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2784
2785 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2786
2787 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2788 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2789 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2790
2791 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2792}
2793
472a1e44
TT		 2794static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2795 struct mlx5e_params *params, u16 mtu)
40ab6a6e 2796{
472a1e44 2797 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
40ab6a6e
AS		 2798 int err;
2799
cd255eff 2800 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2801 if (err)
2802 return err;
2803
cd255eff
SM		 2804 /* Update vport context MTU */
2805 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2806 return 0;
2807}
40ab6a6e 2808
472a1e44
TT		 2809static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2810 struct mlx5e_params *params, u16 *mtu)
cd255eff 2811{
cd255eff
SM		 2812 u16 hw_mtu = 0;
2813 int err;
40ab6a6e 2814
cd255eff
SM		 2815 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2816 if (err || !hw_mtu) /* fallback to port oper mtu */
2817 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2818
472a1e44 2819 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
cd255eff
SM		 2820}
2821
2e20a151 2822static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2823{
472a1e44 2824 struct mlx5e_params *params = &priv->channels.params;
2e20a151 2825 struct net_device *netdev = priv->netdev;
472a1e44 2826 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff
SM		 2827 u16 mtu;
2828 int err;
2829
472a1e44 2830 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
cd255eff
SM		 2831 if (err)
2832 return err;
40ab6a6e 2833
472a1e44
TT		 2834 mlx5e_query_mtu(mdev, params, &mtu);
2835 if (mtu != params->sw_mtu)
cd255eff 2836 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
472a1e44 2837 __func__, mtu, params->sw_mtu);
40ab6a6e 2838
472a1e44 2839 params->sw_mtu = mtu;
40ab6a6e
AS		 2840 return 0;
2841}
2842
08fb1dac
SM		 2843static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2844{
2845 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2846 int nch = priv->channels.params.num_channels;
2847 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2848 int tc;
2849
2850 netdev_reset_tc(netdev);
2851
2852 if (ntc == 1)
2853 return;
2854
2855 netdev_set_num_tc(netdev, ntc);
2856
7ccdd084
RS		 2857 /* Map netdev TCs to offset 0
2858 * We have our own UP to TXQ mapping for QoS
2859 */
08fb1dac 2860 for (tc = 0; tc < ntc; tc++)
7ccdd084 2861 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2862}
2863
8bfaf07f 2864static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
acc6c595 2865{
779d986d 2866 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
acc6c595
SM		 2867 int i, tc;
2868
8bfaf07f 2869 for (i = 0; i < max_nch; i++)
acc6c595 2870 for (tc = 0; tc < priv->profile->max_tc; tc++)
8bfaf07f
EBE		 2871 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2872}
2873
2874static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2875{
2876 struct mlx5e_channel *c;
2877 struct mlx5e_txqsq *sq;
2878 int i, tc;
acc6c595
SM		 2879
2880 for (i = 0; i < priv->channels.num; i++) {
2881 c = priv->channels.c[i];
2882 for (tc = 0; tc < c->num_tc; tc++) {
2883 sq = &c->sq[tc];
2884 priv->txq2sq[sq->txq_ix] = sq;
2885 }
2886 }
2887}
2888
603f4a45 2889void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2890{
9008ae07
SM		 2891 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2892 struct net_device *netdev = priv->netdev;
2893
2894 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2895 netif_set_real_num_tx_queues(netdev, num_txqs);
2896 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2897
8bfaf07f 2898 mlx5e_build_tx2sq_maps(priv);
acc6c595
SM		 2899 mlx5e_activate_channels(&priv->channels);
2900 netif_tx_start_all_queues(priv->netdev);
9008ae07 2901
733d3e54 2902 if (MLX5_ESWITCH_MANAGER(priv->mdev))
9008ae07
SM		 2903 mlx5e_add_sqs_fwd_rules(priv);
2904
acc6c595 2905 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2906 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2907}
2908
603f4a45 2909void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2910{
9008ae07
SM		 2911 mlx5e_redirect_rqts_to_drop(priv);
2912
733d3e54 2913 if (MLX5_ESWITCH_MANAGER(priv->mdev))
9008ae07
SM		 2914 mlx5e_remove_sqs_fwd_rules(priv);
2915
acc6c595
SM		 2916 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2917 * polling for inactive tx queues.
2918 */
2919 netif_tx_stop_all_queues(priv->netdev);
2920 netif_tx_disable(priv->netdev);
2921 mlx5e_deactivate_channels(&priv->channels);
2922}
2923
55c2503d 2924void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2925 struct mlx5e_channels *new_chs,
2926 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2927{
2928 struct net_device *netdev = priv->netdev;
2929 int new_num_txqs;
7ca42c80 2930 int carrier_ok;
55c2503d
SM		 2931 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2932
7ca42c80 2933 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2934 netif_carrier_off(netdev);
2935
2936 if (new_num_txqs < netdev->real_num_tx_queues)
2937 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2938
2939 mlx5e_deactivate_priv_channels(priv);
2940 mlx5e_close_channels(&priv->channels);
2941
2942 priv->channels = *new_chs;
2943
2e20a151
SM		 2944 /* New channels are ready to roll, modify HW settings if needed */
2945 if (hw_modify)
2946 hw_modify(priv);
2947
55c2503d
SM		 2948 mlx5e_refresh_tirs(priv, false);
2949 mlx5e_activate_priv_channels(priv);
2950
7ca42c80
ES		 2951 /* return carrier back if needed */
2952 if (carrier_ok)
2953 netif_carrier_on(netdev);
55c2503d
SM		 2954}
2955
237f258c 2956void mlx5e_timestamp_init(struct mlx5e_priv *priv)
7c39afb3
FD		 2957{
2958 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2959 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2960}
2961
40ab6a6e
AS		 2962int mlx5e_open_locked(struct net_device *netdev)
2963{
2964 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2965 int err;
2966
2967 set_bit(MLX5E_STATE_OPENED, &priv->state);
2968
ff9c852f 2969 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2970 if (err)
343b29f3 2971 goto err_clear_state_opened_flag;
40ab6a6e 2972
b676f653 2973 mlx5e_refresh_tirs(priv, false);
acc6c595 2974 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2975 if (priv->profile->update_carrier)
2976 priv->profile->update_carrier(priv);
be4891af 2977
cdeef2b1 2978 mlx5e_queue_update_stats(priv);
9b37b07f 2979 return 0;
343b29f3
AS		 2980
2981err_clear_state_opened_flag:
2982 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2983 return err;
40ab6a6e
AS		 2984}
2985
cb67b832 2986int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2987{
2988 struct mlx5e_priv *priv = netdev_priv(netdev);
2989 int err;
2990
2991 mutex_lock(&priv->state_lock);
2992 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2993 if (!err)
2994 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2995 mutex_unlock(&priv->state_lock);
2996
358aa5ce 2997 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
a117f73d
SK		 2998 udp_tunnel_get_rx_info(netdev);
2999
40ab6a6e
AS		 3000 return err;
3001}
3002
3003int mlx5e_close_locked(struct net_device *netdev)
3004{
3005 struct mlx5e_priv *priv = netdev_priv(netdev);
3006
a1985740
AS		 3007 /* May already be CLOSED in case a previous configuration operation
3008 * (e.g RX/TX queue size change) that involves close&open failed.
3009 */
3010 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3011 return 0;
3012
40ab6a6e
AS		 3013 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3014
40ab6a6e 3015 netif_carrier_off(priv->netdev);
acc6c595
SM		 3016 mlx5e_deactivate_priv_channels(priv);
3017 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 3018
3019 return 0;
3020}
3021
cb67b832 3022int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 3023{
3024 struct mlx5e_priv *priv = netdev_priv(netdev);
3025 int err;
3026
26e59d80
MHY		 3027 if (!netif_device_present(netdev))
3028 return -ENODEV;
3029
40ab6a6e 3030 mutex_lock(&priv->state_lock);
63bfd399 3031 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 3032 err = mlx5e_close_locked(netdev);
3033 mutex_unlock(&priv->state_lock);
3034
3035 return err;
3036}
3037
a43b25da 3038static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 3039 struct mlx5e_rq *rq,
3040 struct mlx5e_rq_param *param)
40ab6a6e 3041{
40ab6a6e
AS		 3042 void *rqc = param->rqc;
3043 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3044 int err;
3045
3046 param->wq.db_numa_node = param->wq.buf_numa_node;
3047
99cbfa93
TT		 3048 err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3049 &rq->wq_ctrl);
40ab6a6e
AS		 3050 if (err)
3051 return err;
3052
0ddf5432
JDB		 3053 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3054 xdp_rxq_info_unused(&rq->xdp_rxq);
3055
a43b25da 3056 rq->mdev = mdev;
40ab6a6e
AS		 3057
3058 return 0;
3059}
3060
a43b25da 3061static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 3062 struct mlx5e_cq *cq,
3063 struct mlx5e_cq_param *param)
40ab6a6e 3064{
2f0db879
GP		 3065 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3066 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
3067
95b6c6a5 3068 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 3069}
3070
1462e48d
RD		 3071int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3072 struct mlx5e_rq *drop_rq)
40ab6a6e 3073{
7cbaf9a3 3074 struct mlx5_core_dev *mdev = priv->mdev;
a43b25da
SM		 3075 struct mlx5e_cq_param cq_param = {};
3076 struct mlx5e_rq_param rq_param = {};
3077 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 3078 int err;
3079
7cbaf9a3 3080 mlx5e_build_drop_rq_param(priv, &rq_param);
40ab6a6e 3081
a43b25da 3082 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 3083 if (err)
3084 return err;
3085
3b77235b 3086 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 3087 if (err)
3b77235b 3088 goto err_free_cq;
40ab6a6e 3089
a43b25da 3090 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 3091 if (err)
3b77235b 3092 goto err_destroy_cq;
40ab6a6e 3093
a43b25da 3094 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 3095 if (err)
3b77235b 3096 goto err_free_rq;
40ab6a6e 3097
7cbaf9a3
MS		 3098 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3099 if (err)
3100 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3101
40ab6a6e
AS		 3102 return 0;
3103
3b77235b 3104err_free_rq:
a43b25da 3105 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 3106
3107err_destroy_cq:
a43b25da 3108 mlx5e_destroy_cq(cq);
40ab6a6e 3109
3b77235b 3110err_free_cq:
a43b25da 3111 mlx5e_free_cq(cq);
3b77235b 3112
40ab6a6e
AS		 3113 return err;
3114}
3115
1462e48d 3116void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 3117{
a43b25da
SM		 3118 mlx5e_destroy_rq(drop_rq);
3119 mlx5e_free_rq(drop_rq);
3120 mlx5e_destroy_cq(&drop_rq->cq);
3121 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 3122}
3123
5426a0b2
SM		 3124int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3125 u32 underlay_qpn, u32 *tisn)
40ab6a6e 3126{
c4f287c4 3127 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 3128 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3129
08fb1dac 3130 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 3131 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 3132 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 3133
3134 if (mlx5_lag_is_lacp_owner(mdev))
3135 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3136
5426a0b2 3137 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 3138}
3139
5426a0b2 3140void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 3141{
5426a0b2 3142 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 3143}
3144
cb67b832 3145int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 3146{
3147 int err;
3148 int tc;
3149
6bfd390b 3150 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 3151 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 3152 if (err)
3153 goto err_close_tises;
3154 }
3155
3156 return 0;
3157
3158err_close_tises:
3159 for (tc--; tc >= 0; tc--)
5426a0b2 3160 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 3161
3162 return err;
3163}
3164
cb67b832 3165void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 3166{
3167 int tc;
3168
6bfd390b 3169 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 3170 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 3171}
3172
6a9764ef
SM		 3173static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3174 enum mlx5e_traffic_types tt,
3175 u32 *tirc)
f62b8bb8 3176{
b50d292b 3177 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 3178
6a9764ef 3179 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 3180
4cbeaff5 3181 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 3182 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 3183 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 3184}
3185
6a9764ef 3186static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 3187{
b50d292b 3188 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 3189
6a9764ef 3190 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 3191
3192 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3193 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3194 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3195}
3196
46dc933c 3197int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
1da36696 3198{
724b2aa1 3199 struct mlx5e_tir *tir;
f62b8bb8
AV		 3200 void *tirc;
3201 int inlen;
7b3722fa 3202 int i = 0;
f62b8bb8 3203 int err;
1da36696 3204 u32 *in;
1da36696 3205 int tt;
f62b8bb8
AV		 3206
3207 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 3208 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 3209 if (!in)
3210 return -ENOMEM;
3211
1da36696
TT		 3212 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3213 memset(in, 0, inlen);
724b2aa1 3214 tir = &priv->indir_tir[tt];
1da36696 3215 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 3216 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 3217 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 3218 if (err) {
3219 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3220 goto err_destroy_inner_tirs;
3221 }
f62b8bb8
AV		 3222 }
3223
46dc933c 3224 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
7b3722fa
GP		 3225 goto out;
3226
3227 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3228 memset(in, 0, inlen);
3229 tir = &priv->inner_indir_tir[i];
3230 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3231 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3232 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3233 if (err) {
3234 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3235 goto err_destroy_inner_tirs;
3236 }
3237 }
3238
3239out:
6bfd390b
HHZ		 3240 kvfree(in);
3241
3242 return 0;
3243
7b3722fa
GP		 3244err_destroy_inner_tirs:
3245 for (i--; i >= 0; i--)
3246 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3247
6bfd390b
HHZ		 3248 for (tt--; tt >= 0; tt--)
3249 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3250
3251 kvfree(in);
3252
3253 return err;
3254}
3255
cb67b832 3256int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b 3257{
779d986d 3258 int nch = mlx5e_get_netdev_max_channels(priv->netdev);
6bfd390b
HHZ		 3259 struct mlx5e_tir *tir;
3260 void *tirc;
3261 int inlen;
3262 int err;
3263 u32 *in;
3264 int ix;
3265
3266 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 3267 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 3268 if (!in)
3269 return -ENOMEM;
3270
1da36696
TT		 3271 for (ix = 0; ix < nch; ix++) {
3272 memset(in, 0, inlen);
724b2aa1 3273 tir = &priv->direct_tir[ix];
1da36696 3274 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 3275 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 3276 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 3277 if (err)
3278 goto err_destroy_ch_tirs;
3279 }
3280
3281 kvfree(in);
3282
f62b8bb8
AV		 3283 return 0;
3284
1da36696 3285err_destroy_ch_tirs:
8f493ffd 3286 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 3287 for (ix--; ix >= 0; ix--)
724b2aa1 3288 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 3289
1da36696 3290 kvfree(in);
f62b8bb8
AV		 3291
3292 return err;
3293}
3294
46dc933c 3295void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
f62b8bb8
AV		 3296{
3297 int i;
3298
1da36696 3299 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 3300 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa 3301
46dc933c 3302 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
7b3722fa
GP		 3303 return;
3304
3305 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3306 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 3307}
3308
cb67b832 3309void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b 3310{
779d986d 3311 int nch = mlx5e_get_netdev_max_channels(priv->netdev);
6bfd390b
HHZ		 3312 int i;
3313
3314 for (i = 0; i < nch; i++)
3315 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3316}
3317
102722fc
GE		 3318static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3319{
3320 int err = 0;
3321 int i;
3322
3323 for (i = 0; i < chs->num; i++) {
3324 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3325 if (err)
3326 return err;
3327 }
3328
3329 return 0;
3330}
3331
f6d96a20 3332static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 3333{
3334 int err = 0;
3335 int i;
3336
ff9c852f
SM		 3337 for (i = 0; i < chs->num; i++) {
3338 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 3339 if (err)
3340 return err;
3341 }
3342
3343 return 0;
3344}
3345
0cf0f6d3
JP		 3346static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3347 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 3348{
3349 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 3350 struct mlx5e_channels new_channels = {};
0cf0f6d3 3351 u8 tc = mqprio->num_tc;
08fb1dac
SM		 3352 int err = 0;
3353
0cf0f6d3
JP		 3354 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3355
08fb1dac
SM		 3356 if (tc && tc != MLX5E_MAX_NUM_TC)
3357 return -EINVAL;
3358
3359 mutex_lock(&priv->state_lock);
3360
6f9485af
SM		 3361 new_channels.params = priv->channels.params;
3362 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 3363
20b6a1c7 3364 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 3365 priv->channels.params = new_channels.params;
3366 goto out;
3367 }
08fb1dac 3368
6f9485af
SM		 3369 err = mlx5e_open_channels(priv, &new_channels);
3370 if (err)
3371 goto out;
08fb1dac 3372
05909bab
EBE		 3373 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3374 new_channels.params.num_tc);
2e20a151 3375 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 3376out:
08fb1dac 3377 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 3378 return err;
3379}
3380
e80541ec 3381#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 3382static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
60bd4af8
OG		 3383 struct tc_cls_flower_offload *cls_flower,
3384 int flags)
08fb1dac 3385{
0cf0f6d3
JP		 3386 switch (cls_flower->command) {
3387 case TC_CLSFLOWER_REPLACE:
60bd4af8 3388 return mlx5e_configure_flower(priv, cls_flower, flags);
0cf0f6d3 3389 case TC_CLSFLOWER_DESTROY:
60bd4af8 3390 return mlx5e_delete_flower(priv, cls_flower, flags);
0cf0f6d3 3391 case TC_CLSFLOWER_STATS:
60bd4af8 3392 return mlx5e_stats_flower(priv, cls_flower, flags);
0cf0f6d3 3393 default:
a5fcf8a6 3394 return -EOPNOTSUPP;
0cf0f6d3
JP		 3395 }
3396}
d6c862ba 3397
60bd4af8
OG		 3398static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3399 void *cb_priv)
d6c862ba
JP		 3400{
3401 struct mlx5e_priv *priv = cb_priv;
3402
3403 switch (type) {
3404 case TC_SETUP_CLSFLOWER:
60bd4af8 3405 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
d6c862ba
JP		 3406 default:
3407 return -EOPNOTSUPP;
3408 }
3409}
3410
3411static int mlx5e_setup_tc_block(struct net_device *dev,
3412 struct tc_block_offload *f)
3413{
3414 struct mlx5e_priv *priv = netdev_priv(dev);
3415
3416 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3417 return -EOPNOTSUPP;
3418
3419 switch (f->command) {
3420 case TC_BLOCK_BIND:
3421 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
60513bd8 3422 priv, priv, f->extack);
d6c862ba
JP		 3423 case TC_BLOCK_UNBIND:
3424 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3425 priv);
3426 return 0;
3427 default:
3428 return -EOPNOTSUPP;
3429 }
3430}
e80541ec 3431#endif
a5fcf8a6 3432
9afe9a53
OG		 3433static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3434 void *type_data)
0cf0f6d3 3435{
2572ac53 3436 switch (type) {
fde6af47 3437#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3438 case TC_SETUP_BLOCK:
3439 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3440#endif
575ed7d3 3441 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3442 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3443 default:
3444 return -EOPNOTSUPP;
3445 }
08fb1dac
SM		 3446}
3447
bc1f4470 3448static void
f62b8bb8
AV		 3449mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3450{
3451 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3452 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3453 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3454 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3455
ed56c519 3456 /* update HW stats in background for next time */
cdeef2b1 3457 mlx5e_queue_update_stats(priv);
ed56c519 3458
370bad0f
OG		 3459 if (mlx5e_is_uplink_rep(priv)) {
3460 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3461 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3462 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3463 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3464 } else {
868a01a2 3465 mlx5e_grp_sw_update_stats(priv);
370bad0f
OG		 3466 stats->rx_packets = sstats->rx_packets;
3467 stats->rx_bytes = sstats->rx_bytes;
3468 stats->tx_packets = sstats->tx_packets;
3469 stats->tx_bytes = sstats->tx_bytes;
3470 stats->tx_dropped = sstats->tx_queue_dropped;
3471 }
269e6b3a
GP		 3472
3473 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3474
3475 stats->rx_length_errors =
9218b44d
GP		 3476 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3477 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3478 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3479 stats->rx_crc_errors =
9218b44d
GP		 3480 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3481 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3482 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3483 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3484 stats->rx_frame_errors;
3485 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3486
3487 /* vport multicast also counts packets that are dropped due to steering
3488 * or rx out of buffer
3489 */
9218b44d
GP		 3490 stats->multicast =
3491 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3492}
3493
3494static void mlx5e_set_rx_mode(struct net_device *dev)
3495{
3496 struct mlx5e_priv *priv = netdev_priv(dev);
3497
7bb29755 3498 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3499}
3500
3501static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3502{
3503 struct mlx5e_priv *priv = netdev_priv(netdev);
3504 struct sockaddr *saddr = addr;
3505
3506 if (!is_valid_ether_addr(saddr->sa_data))
3507 return -EADDRNOTAVAIL;
3508
3509 netif_addr_lock_bh(netdev);
3510 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3511 netif_addr_unlock_bh(netdev);
3512
7bb29755 3513 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3514
3515 return 0;
3516}
3517
75b81ce7 3518#define MLX5E_SET_FEATURE(features, feature, enable) \
0e405443
GP		 3519 do { \
3520 if (enable) \
75b81ce7 3521 *features |= feature; \
0e405443 3522 else \
75b81ce7 3523 *features &= ~feature; \
0e405443
GP		 3524 } while (0)
3525
3526typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3527
3528static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3529{
3530 struct mlx5e_priv *priv = netdev_priv(netdev);
619a8f2a 3531 struct mlx5_core_dev *mdev = priv->mdev;
2e20a151 3532 struct mlx5e_channels new_channels = {};
619a8f2a 3533 struct mlx5e_params *old_params;
2e20a151
SM		 3534 int err = 0;
3535 bool reset;
f62b8bb8
AV		 3536
3537 mutex_lock(&priv->state_lock);
f62b8bb8 3538
619a8f2a 3539 old_params = &priv->channels.params;
6c3a823e
TT		 3540 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3541 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3542 err = -EINVAL;
3543 goto out;
3544 }
3545
619a8f2a 3546 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3547
619a8f2a 3548 new_channels.params = *old_params;
2e20a151
SM		 3549 new_channels.params.lro_en = enable;
3550
99cbfa93 3551 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
619a8f2a
TT		 3552 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3553 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3554 reset = false;
3555 }
3556
2e20a151 3557 if (!reset) {
619a8f2a 3558 *old_params = new_channels.params;
2e20a151
SM		 3559 err = mlx5e_modify_tirs_lro(priv);
3560 goto out;
98e81b0a 3561 }
f62b8bb8 3562
2e20a151
SM		 3563 err = mlx5e_open_channels(priv, &new_channels);
3564 if (err)
3565 goto out;
0e405443 3566
2e20a151
SM		 3567 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3568out:
9b37b07f 3569 mutex_unlock(&priv->state_lock);
0e405443
GP		 3570 return err;
3571}
3572
2b52a283 3573static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3574{
3575 struct mlx5e_priv *priv = netdev_priv(netdev);
3576
3577 if (enable)
2b52a283 3578 mlx5e_enable_cvlan_filter(priv);
0e405443 3579 else
2b52a283 3580 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3581
3582 return 0;
3583}
3584
077ecd78 3585#ifdef CONFIG_MLX5_ESWITCH
0e405443
GP		 3586static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3587{
3588 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3589
0e405443 3590 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3591 netdev_err(netdev,
3592 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3593 return -EINVAL;
3594 }
3595
0e405443
GP		 3596 return 0;
3597}
077ecd78 3598#endif
0e405443 3599
94cb1ebb
EBE		 3600static int set_feature_rx_all(struct net_device *netdev, bool enable)
3601{
3602 struct mlx5e_priv *priv = netdev_priv(netdev);
3603 struct mlx5_core_dev *mdev = priv->mdev;
3604
3605 return mlx5_set_port_fcs(mdev, !enable);
3606}
3607
102722fc
GE		 3608static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3609{
3610 struct mlx5e_priv *priv = netdev_priv(netdev);
3611 int err;
3612
3613 mutex_lock(&priv->state_lock);
3614
3615 priv->channels.params.scatter_fcs_en = enable;
3616 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3617 if (err)
3618 priv->channels.params.scatter_fcs_en = !enable;
3619
3620 mutex_unlock(&priv->state_lock);
3621
3622 return err;
3623}
3624
36350114
GP		 3625static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3626{
3627 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3628 int err = 0;
36350114
GP		 3629
3630 mutex_lock(&priv->state_lock);
3631
6a9764ef 3632 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3633 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3634 goto unlock;
3635
3636 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3637 if (err)
6a9764ef 3638 priv->channels.params.vlan_strip_disable = enable;
36350114 3639
ff9c852f 3640unlock:
36350114
GP		 3641 mutex_unlock(&priv->state_lock);
3642
3643 return err;
3644}
3645
ec080045 3646#ifdef CONFIG_MLX5_EN_ARFS
45bf454a
MG		 3647static int set_feature_arfs(struct net_device *netdev, bool enable)
3648{
3649 struct mlx5e_priv *priv = netdev_priv(netdev);
3650 int err;
3651
3652 if (enable)
3653 err = mlx5e_arfs_enable(priv);
3654 else
3655 err = mlx5e_arfs_disable(priv);
3656
3657 return err;
3658}
3659#endif
3660
0e405443 3661static int mlx5e_handle_feature(struct net_device *netdev,
75b81ce7 3662 netdev_features_t *features,
0e405443
GP		 3663 netdev_features_t wanted_features,
3664 netdev_features_t feature,
3665 mlx5e_feature_handler feature_handler)
3666{
3667 netdev_features_t changes = wanted_features ^ netdev->features;
3668 bool enable = !!(wanted_features & feature);
3669 int err;
3670
3671 if (!(changes & feature))
3672 return 0;
3673
3674 err = feature_handler(netdev, enable);
3675 if (err) {
b20eab15
GP		 3676 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3677 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3678 return err;
3679 }
3680
75b81ce7 3681 MLX5E_SET_FEATURE(features, feature, enable);
0e405443
GP		 3682 return 0;
3683}
3684
3685static int mlx5e_set_features(struct net_device *netdev,
3686 netdev_features_t features)
3687{
75b81ce7 3688 netdev_features_t oper_features = netdev->features;
be0f780b
GP		 3689 int err = 0;
3690
3691#define MLX5E_HANDLE_FEATURE(feature, handler) \
3692 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
0e405443 3693
be0f780b
GP		 3694 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3695 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3696 set_feature_cvlan_filter);
077ecd78 3697#ifdef CONFIG_MLX5_ESWITCH
be0f780b 3698 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
077ecd78 3699#endif
be0f780b
GP		 3700 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3701 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3702 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
ec080045 3703#ifdef CONFIG_MLX5_EN_ARFS
be0f780b 3704 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
45bf454a 3705#endif
0e405443 3706
75b81ce7
GP		 3707 if (err) {
3708 netdev->features = oper_features;
3709 return -EINVAL;
3710 }
3711
3712 return 0;
f62b8bb8
AV		 3713}
3714
7d92d580
GP		 3715static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3716 netdev_features_t features)
3717{
3718 struct mlx5e_priv *priv = netdev_priv(netdev);
6c3a823e 3719 struct mlx5e_params *params;
7d92d580
GP		 3720
3721 mutex_lock(&priv->state_lock);
6c3a823e 3722 params = &priv->channels.params;
7d92d580
GP		 3723 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3724 /* HW strips the outer C-tag header, this is a problem
3725 * for S-tag traffic.
3726 */
3727 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6c3a823e 3728 if (!params->vlan_strip_disable)
7d92d580
GP		 3729 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3730 }
6c3a823e
TT		 3731 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3732 features &= ~NETIF_F_LRO;
3733 if (params->lro_en)
3734 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3735 }
3736
7d92d580
GP		 3737 mutex_unlock(&priv->state_lock);
3738
3739 return features;
3740}
3741
250a42b6
AN		 3742int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3743 change_hw_mtu_cb set_mtu_cb)
f62b8bb8
AV		 3744{
3745 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151 3746 struct mlx5e_channels new_channels = {};
472a1e44 3747 struct mlx5e_params *params;
98e81b0a 3748 int err = 0;
506753b0 3749 bool reset;
f62b8bb8 3750
f62b8bb8 3751 mutex_lock(&priv->state_lock);
98e81b0a 3752
472a1e44 3753 params = &priv->channels.params;
506753b0 3754
73281b78 3755 reset = !params->lro_en;
2e20a151 3756 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3757
73281b78
TT		 3758 new_channels.params = *params;
3759 new_channels.params.sw_mtu = new_mtu;
3760
a26a5bdf
TT		 3761 if (params->xdp_prog &&
3762 !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3763 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3764 new_mtu, MLX5E_XDP_MAX_MTU);
3765 err = -EINVAL;
3766 goto out;
3767 }
3768
99cbfa93 3769 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
0073c8f7 3770 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
73281b78
TT		 3771 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3772 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3773
0073c8f7 3774 reset = reset && (is_linear || (ppw_old != ppw_new));
73281b78
TT		 3775 }
3776
2e20a151 3777 if (!reset) {
472a1e44 3778 params->sw_mtu = new_mtu;
eacecf27
AN		 3779 if (set_mtu_cb)
3780 set_mtu_cb(priv);
472a1e44 3781 netdev->mtu = params->sw_mtu;
2e20a151
SM		 3782 goto out;
3783 }
98e81b0a 3784
2e20a151 3785 err = mlx5e_open_channels(priv, &new_channels);
472a1e44 3786 if (err)
2e20a151 3787 goto out;
2e20a151 3788
250a42b6 3789 mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
472a1e44 3790 netdev->mtu = new_channels.params.sw_mtu;
f62b8bb8 3791
2e20a151
SM		 3792out:
3793 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3794 return err;
3795}
3796
250a42b6
AN		 3797static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3798{
3799 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3800}
3801
7c39afb3
FD		 3802int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3803{
3804 struct hwtstamp_config config;
3805 int err;
3806
6dbc80ca
MS		 3807 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3808 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
7c39afb3
FD		 3809 return -EOPNOTSUPP;
3810
3811 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3812 return -EFAULT;
3813
3814 /* TX HW timestamp */
3815 switch (config.tx_type) {
3816 case HWTSTAMP_TX_OFF:
3817 case HWTSTAMP_TX_ON:
3818 break;
3819 default:
3820 return -ERANGE;
3821 }
3822
3823 mutex_lock(&priv->state_lock);
3824 /* RX HW timestamp */
3825 switch (config.rx_filter) {
3826 case HWTSTAMP_FILTER_NONE:
3827 /* Reset CQE compression to Admin default */
3828 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3829 break;
3830 case HWTSTAMP_FILTER_ALL:
3831 case HWTSTAMP_FILTER_SOME:
3832 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3833 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3834 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3835 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3836 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3837 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3838 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3839 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3840 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3841 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3842 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3843 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3844 case HWTSTAMP_FILTER_NTP_ALL:
3845 /* Disable CQE compression */
3846 netdev_warn(priv->netdev, "Disabling cqe compression");
3847 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3848 if (err) {
3849 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3850 mutex_unlock(&priv->state_lock);
3851 return err;
3852 }
3853 config.rx_filter = HWTSTAMP_FILTER_ALL;
3854 break;
3855 default:
3856 mutex_unlock(&priv->state_lock);
3857 return -ERANGE;
3858 }
3859
3860 memcpy(&priv->tstamp, &config, sizeof(config));
3861 mutex_unlock(&priv->state_lock);
3862
3863 return copy_to_user(ifr->ifr_data, &config,
3864 sizeof(config)) ? -EFAULT : 0;
3865}
3866
3867int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3868{
3869 struct hwtstamp_config *cfg = &priv->tstamp;
3870
3871 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3872 return -EOPNOTSUPP;
3873
3874 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3875}
3876
ef9814de
EBE		 3877static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3878{
1170fbd8
FD		 3879 struct mlx5e_priv *priv = netdev_priv(dev);
3880
ef9814de
EBE		 3881 switch (cmd) {
3882 case SIOCSHWTSTAMP:
1170fbd8 3883 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3884 case SIOCGHWTSTAMP:
1170fbd8 3885 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3886 default:
3887 return -EOPNOTSUPP;
3888 }
3889}
3890
e80541ec 3891#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3892static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3893{
3894 struct mlx5e_priv *priv = netdev_priv(dev);
3895 struct mlx5_core_dev *mdev = priv->mdev;
3896
3897 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3898}
3899
79aab093
MS		 3900static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3901 __be16 vlan_proto)
66e49ded
SM		 3902{
3903 struct mlx5e_priv *priv = netdev_priv(dev);
3904 struct mlx5_core_dev *mdev = priv->mdev;
3905
79aab093
MS		 3906 if (vlan_proto != htons(ETH_P_8021Q))
3907 return -EPROTONOSUPPORT;
3908
66e49ded
SM		 3909 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3910 vlan, qos);
3911}
3912
f942380c
MHY		 3913static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3914{
3915 struct mlx5e_priv *priv = netdev_priv(dev);
3916 struct mlx5_core_dev *mdev = priv->mdev;
3917
3918 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3919}
3920
1edc57e2
MHY		 3921static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3922{
3923 struct mlx5e_priv *priv = netdev_priv(dev);
3924 struct mlx5_core_dev *mdev = priv->mdev;
3925
3926 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3927}
bd77bf1c
MHY		 3928
3929static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3930 int max_tx_rate)
3931{
3932 struct mlx5e_priv *priv = netdev_priv(dev);
3933 struct mlx5_core_dev *mdev = priv->mdev;
3934
bd77bf1c 3935 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3936 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3937}
3938
66e49ded
SM		 3939static int mlx5_vport_link2ifla(u8 esw_link)
3940{
3941 switch (esw_link) {
cc9c82a8 3942 case MLX5_VPORT_ADMIN_STATE_DOWN:
66e49ded 3943 return IFLA_VF_LINK_STATE_DISABLE;
cc9c82a8 3944 case MLX5_VPORT_ADMIN_STATE_UP:
66e49ded
SM		 3945 return IFLA_VF_LINK_STATE_ENABLE;
3946 }
3947 return IFLA_VF_LINK_STATE_AUTO;
3948}
3949
3950static int mlx5_ifla_link2vport(u8 ifla_link)
3951{
3952 switch (ifla_link) {
3953 case IFLA_VF_LINK_STATE_DISABLE:
cc9c82a8 3954 return MLX5_VPORT_ADMIN_STATE_DOWN;
66e49ded 3955 case IFLA_VF_LINK_STATE_ENABLE:
cc9c82a8 3956 return MLX5_VPORT_ADMIN_STATE_UP;
66e49ded 3957 }
cc9c82a8 3958 return MLX5_VPORT_ADMIN_STATE_AUTO;
66e49ded
SM		 3959}
3960
3961static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3962 int link_state)
3963{
3964 struct mlx5e_priv *priv = netdev_priv(dev);
3965 struct mlx5_core_dev *mdev = priv->mdev;
3966
3967 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3968 mlx5_ifla_link2vport(link_state));
3969}
3970
3971static int mlx5e_get_vf_config(struct net_device *dev,
3972 int vf, struct ifla_vf_info *ivi)
3973{
3974 struct mlx5e_priv *priv = netdev_priv(dev);
3975 struct mlx5_core_dev *mdev = priv->mdev;
3976 int err;
3977
3978 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3979 if (err)
3980 return err;
3981 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3982 return 0;
3983}
3984
3985static int mlx5e_get_vf_stats(struct net_device *dev,
3986 int vf, struct ifla_vf_stats *vf_stats)
3987{
3988 struct mlx5e_priv *priv = netdev_priv(dev);
3989 struct mlx5_core_dev *mdev = priv->mdev;
3990
3991 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3992 vf_stats);
3993}
e80541ec 3994#endif
66e49ded 3995
dccea6bf
SM		 3996struct mlx5e_vxlan_work {
3997 struct work_struct work;
3998 struct mlx5e_priv *priv;
3999 u16 port;
4000};
4001
4002static void mlx5e_vxlan_add_work(struct work_struct *work)
4003{
4004 struct mlx5e_vxlan_work *vxlan_work =
4005 container_of(work, struct mlx5e_vxlan_work, work);
4006 struct mlx5e_priv *priv = vxlan_work->priv;
4007 u16 port = vxlan_work->port;
4008
4009 mutex_lock(&priv->state_lock);
358aa5ce 4010 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
dccea6bf
SM		 4011 mutex_unlock(&priv->state_lock);
4012
4013 kfree(vxlan_work);
4014}
4015
4016static void mlx5e_vxlan_del_work(struct work_struct *work)
4017{
4018 struct mlx5e_vxlan_work *vxlan_work =
4019 container_of(work, struct mlx5e_vxlan_work, work);
4020 struct mlx5e_priv *priv = vxlan_work->priv;
4021 u16 port = vxlan_work->port;
4022
4023 mutex_lock(&priv->state_lock);
358aa5ce 4024 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
dccea6bf
SM		 4025 mutex_unlock(&priv->state_lock);
4026 kfree(vxlan_work);
4027}
4028
4029static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4030{
4031 struct mlx5e_vxlan_work *vxlan_work;
4032
4033 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4034 if (!vxlan_work)
4035 return;
4036
4037 if (add)
4038 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4039 else
4040 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4041
4042 vxlan_work->priv = priv;
4043 vxlan_work->port = port;
4044 queue_work(priv->wq, &vxlan_work->work);
4045}
4046
1ad9a00a
PB		 4047static void mlx5e_add_vxlan_port(struct net_device *netdev,
4048 struct udp_tunnel_info *ti)
b3f63c3d
MF		 4049{
4050 struct mlx5e_priv *priv = netdev_priv(netdev);
4051
974c3f30
AD		 4052 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4053 return;
4054
358aa5ce 4055 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
b3f63c3d
MF		 4056 return;
4057
278d7f3d 4058 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 4059}
4060
1ad9a00a
PB		 4061static void mlx5e_del_vxlan_port(struct net_device *netdev,
4062 struct udp_tunnel_info *ti)
b3f63c3d
MF		 4063{
4064 struct mlx5e_priv *priv = netdev_priv(netdev);
4065
974c3f30
AD		 4066 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4067 return;
4068
358aa5ce 4069 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
b3f63c3d
MF		 4070 return;
4071
278d7f3d 4072 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 4073}
4074
27299841
GP		 4075static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4076 struct sk_buff *skb,
4077 netdev_features_t features)
b3f63c3d 4078{
2989ad1e 4079 unsigned int offset = 0;
b3f63c3d 4080 struct udphdr *udph;
27299841
GP		 4081 u8 proto;
4082 u16 port;
b3f63c3d
MF		 4083
4084 switch (vlan_get_protocol(skb)) {
4085 case htons(ETH_P_IP):
4086 proto = ip_hdr(skb)->protocol;
4087 break;
4088 case htons(ETH_P_IPV6):
2989ad1e 4089 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
b3f63c3d
MF		 4090 break;
4091 default:
4092 goto out;
4093 }
4094
27299841
GP		 4095 switch (proto) {
4096 case IPPROTO_GRE:
4097 return features;
4098 case IPPROTO_UDP:
b3f63c3d
MF		 4099 udph = udp_hdr(skb);
4100 port = be16_to_cpu(udph->dest);
b3f63c3d 4101
27299841 4102 /* Verify if UDP port is being offloaded by HW */
358aa5ce 4103 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
27299841
GP		 4104 return features;
4105 }
b3f63c3d
MF		 4106
4107out:
4108 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4109 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4110}
4111
4112static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4113 struct net_device *netdev,
4114 netdev_features_t features)
4115{
4116 struct mlx5e_priv *priv = netdev_priv(netdev);
4117
4118 features = vlan_features_check(skb, features);
4119 features = vxlan_features_check(skb, features);
4120
2ac9cfe7
IT		 4121#ifdef CONFIG_MLX5_EN_IPSEC
4122 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4123 return features;
4124#endif
4125
b3f63c3d
MF		 4126 /* Validate if the tunneled packet is being offloaded by HW */
4127 if (skb->encapsulation &&
4128 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 4129 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 4130
4131 return features;
4132}
4133
7ca560b5
EBE		 4134static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4135 struct mlx5e_txqsq *sq)
4136{
7b2117bb 4137 struct mlx5_eq *eq = sq->cq.mcq.eq;
7ca560b5
EBE		 4138 u32 eqe_count;
4139
7ca560b5 4140 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
7b2117bb 4141 eq->eqn, eq->cons_index, eq->irqn);
7ca560b5
EBE		 4142
4143 eqe_count = mlx5_eq_poll_irq_disabled(eq);
4144 if (!eqe_count)
4145 return false;
4146
4147 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
05909bab 4148 sq->channel->stats->eq_rearm++;
7ca560b5
EBE		 4149 return true;
4150}
4151
bfc647d5 4152static void mlx5e_tx_timeout_work(struct work_struct *work)
3947ca18 4153{
bfc647d5
EBE		 4154 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4155 tx_timeout_work);
4156 struct net_device *dev = priv->netdev;
7ca560b5 4157 bool reopen_channels = false;
bfc647d5 4158 int i, err;
3947ca18 4159
bfc647d5
EBE		 4160 rtnl_lock();
4161 mutex_lock(&priv->state_lock);
4162
4163 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4164 goto unlock;
3947ca18 4165
6a9764ef 4166 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
84990945 4167 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
acc6c595 4168 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 4169
84990945 4170 if (!netif_xmit_stopped(dev_queue))
3947ca18 4171 continue;
bfc647d5
EBE		 4172
4173 netdev_err(dev,
4174 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
84990945
EBE		 4175 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4176 jiffies_to_usecs(jiffies - dev_queue->trans_start));
3a32b26a 4177
7ca560b5
EBE		 4178 /* If we recover a lost interrupt, most likely TX timeout will
4179 * be resolved, skip reopening channels
4180 */
4181 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4182 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4183 reopen_channels = true;
4184 }
3947ca18
DJ		 4185 }
4186
bfc647d5
EBE		 4187 if (!reopen_channels)
4188 goto unlock;
4189
4190 mlx5e_close_locked(dev);
4191 err = mlx5e_open_locked(dev);
4192 if (err)
4193 netdev_err(priv->netdev,
4194 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4195 err);
4196
4197unlock:
4198 mutex_unlock(&priv->state_lock);
4199 rtnl_unlock();
4200}
4201
4202static void mlx5e_tx_timeout(struct net_device *dev)
4203{
4204 struct mlx5e_priv *priv = netdev_priv(dev);
4205
4206 netdev_err(dev, "TX timeout detected\n");
4207 queue_work(priv->wq, &priv->tx_timeout_work);
3947ca18
DJ		 4208}
4209
a26a5bdf 4210static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
0ec13877
TT		 4211{
4212 struct net_device *netdev = priv->netdev;
a26a5bdf 4213 struct mlx5e_channels new_channels = {};
0ec13877
TT		 4214
4215 if (priv->channels.params.lro_en) {
4216 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4217 return -EINVAL;
4218 }
4219
4220 if (MLX5_IPSEC_DEV(priv->mdev)) {
4221 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4222 return -EINVAL;
4223 }
4224
a26a5bdf
TT		 4225 new_channels.params = priv->channels.params;
4226 new_channels.params.xdp_prog = prog;
4227
4228 if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4229 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4230 new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4231 return -EINVAL;
4232 }
4233
0ec13877
TT		 4234 return 0;
4235}
4236
86994156
RS		 4237static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4238{
4239 struct mlx5e_priv *priv = netdev_priv(netdev);
4240 struct bpf_prog *old_prog;
86994156 4241 bool reset, was_opened;
96d39502 4242 int err = 0;
86994156
RS		 4243 int i;
4244
4245 mutex_lock(&priv->state_lock);
4246
0ec13877 4247 if (prog) {
a26a5bdf 4248 err = mlx5e_xdp_allowed(priv, prog);
0ec13877
TT		 4249 if (err)
4250 goto unlock;
547eede0
IT		 4251 }
4252
86994156
RS		 4253 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4254 /* no need for full reset when exchanging programs */
6a9764ef 4255 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 4256
4257 if (was_opened && reset)
4258 mlx5e_close_locked(netdev);
c54c0629
DB		 4259 if (was_opened && !reset) {
4260 /* num_channels is invariant here, so we can take the
4261 * batched reference right upfront.
4262 */
6a9764ef 4263 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 4264 if (IS_ERR(prog)) {
4265 err = PTR_ERR(prog);
4266 goto unlock;
4267 }
4268 }
86994156 4269
c54c0629
DB		 4270 /* exchange programs, extra prog reference we got from caller
4271 * as long as we don't fail from this point onwards.
4272 */
6a9764ef 4273 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 4274 if (old_prog)
4275 bpf_prog_put(old_prog);
4276
4277 if (reset) /* change RQ type according to priv->xdp_prog */
2a0f561b 4278 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
86994156
RS		 4279
4280 if (was_opened && reset)
4281 mlx5e_open_locked(netdev);
4282
4283 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4284 goto unlock;
4285
4286 /* exchanging programs w/o reset, we update ref counts on behalf
4287 * of the channels RQs here.
4288 */
ff9c852f
SM		 4289 for (i = 0; i < priv->channels.num; i++) {
4290 struct mlx5e_channel *c = priv->channels.c[i];
86994156 4291
c0f1147d 4292 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 4293 napi_synchronize(&c->napi);
4294 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4295
4296 old_prog = xchg(&c->rq.xdp_prog, prog);
4297
c0f1147d 4298 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 4299 /* napi_schedule in case we have missed anything */
86994156
RS		 4300 napi_schedule(&c->napi);
4301
4302 if (old_prog)
4303 bpf_prog_put(old_prog);
4304 }
4305
4306unlock:
4307 mutex_unlock(&priv->state_lock);
4308 return err;
4309}
4310
821b2e29 4311static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 4312{
4313 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 4314 const struct bpf_prog *xdp_prog;
4315 u32 prog_id = 0;
86994156 4316
821b2e29
MKL		 4317 mutex_lock(&priv->state_lock);
4318 xdp_prog = priv->channels.params.xdp_prog;
4319 if (xdp_prog)
4320 prog_id = xdp_prog->aux->id;
4321 mutex_unlock(&priv->state_lock);
4322
4323 return prog_id;
86994156
RS		 4324}
4325
f4e63525 4326static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 4327{
4328 switch (xdp->command) {
4329 case XDP_SETUP_PROG:
4330 return mlx5e_xdp_set(dev, xdp->prog);
4331 case XDP_QUERY_PROG:
821b2e29 4332 xdp->prog_id = mlx5e_xdp_query(dev);
86994156
RS		 4333 return 0;
4334 default:
4335 return -EINVAL;
4336 }
4337}
4338
4d8fcf21 4339const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 4340 .ndo_open = mlx5e_open,
4341 .ndo_stop = mlx5e_close,
4342 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 4343 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 4344 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 4345 .ndo_get_stats64 = mlx5e_get_stats,
4346 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4347 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 4348 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4349 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 4350 .ndo_set_features = mlx5e_set_features,
7d92d580 4351 .ndo_fix_features = mlx5e_fix_features,
250a42b6 4352 .ndo_change_mtu = mlx5e_change_nic_mtu,
b0eed40e 4353 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 4354 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 4355 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4356 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4357 .ndo_features_check = mlx5e_features_check,
3947ca18 4358 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 4359 .ndo_bpf = mlx5e_xdp,
58b99ee3 4360 .ndo_xdp_xmit = mlx5e_xdp_xmit,
ec080045
SM		 4361#ifdef CONFIG_MLX5_EN_ARFS
4362 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4363#endif
e80541ec 4364#ifdef CONFIG_MLX5_ESWITCH
706b3583 4365 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 4366 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4367 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 4368 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 4369 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 4370 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 4371 .ndo_get_vf_config = mlx5e_get_vf_config,
4372 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4373 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 4374 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4375 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 4376#endif
f62b8bb8
AV		 4377};
4378
4379static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4380{
4381 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 4382 return -EOPNOTSUPP;
f62b8bb8
AV		 4383 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4384 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4385 !MLX5_CAP_ETH(mdev, csum_cap) ||
4386 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4387 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 4388 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4389 MLX5_CAP_FLOWTABLE(mdev,
4390 flow_table_properties_nic_receive.max_ft_level)
4391 < 3) {
f62b8bb8
AV		 4392 mlx5_core_warn(mdev,
4393 "Not creating net device, some required device capabilities are missing\n");
9eb78923 4394 return -EOPNOTSUPP;
f62b8bb8 4395 }
66189961
TT		 4396 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4397 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 4398 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 4399 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 4400
f62b8bb8
AV		 4401 return 0;
4402}
4403
d4b6c488 4404void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 4405 int num_channels)
4406{
4407 int i;
4408
4409 for (i = 0; i < len; i++)
4410 indirection_rqt[i] = i % num_channels;
4411}
4412
0608d4db 4413static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
b797a684 4414{
0608d4db
TT		 4415 u32 link_speed = 0;
4416 u32 pci_bw = 0;
b797a684 4417
2c81bfd5 4418 mlx5e_port_max_linkspeed(mdev, &link_speed);
3c0d551e 4419 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
0608d4db
TT		 4420 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4421 link_speed, pci_bw);
4422
4423#define MLX5E_SLOW_PCI_RATIO (2)
4424
4425 return link_speed && pci_bw &&
4426 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
0f6e4cf6
EBE		 4427}
4428
cbce4f44 4429static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
0088cbbc 4430{
cbce4f44
TG		 4431 struct net_dim_cq_moder moder;
4432
4433 moder.cq_period_mode = cq_period_mode;
4434 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4435 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4436 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4437 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4438
4439 return moder;
4440}
0088cbbc 4441
cbce4f44
TG		 4442static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4443{
4444 struct net_dim_cq_moder moder;
0088cbbc 4445
cbce4f44
TG		 4446 moder.cq_period_mode = cq_period_mode;
4447 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4448 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
0088cbbc 4449 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
cbce4f44
TG		 4450 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4451
4452 return moder;
4453}
4454
4455static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4456{
4457 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4458 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4459 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4460}
4461
4462void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4463{
4464 if (params->tx_dim_enabled) {
4465 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4466
4467 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4468 } else {
4469 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4470 }
0088cbbc
TG		 4471
4472 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4473 params->tx_cq_moderation.cq_period_mode ==
4474 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4475}
4476
9908aa29
TT		 4477void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4478{
9a317425 4479 if (params->rx_dim_enabled) {
cbce4f44
TG		 4480 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4481
4482 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4483 } else {
4484 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
9a317425 4485 }
457fcd8a 4486
6a9764ef 4487 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 4488 params->rx_cq_moderation.cq_period_mode ==
4489 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 4490}
4491
707129dc 4492static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
2b029556
SM		 4493{
4494 int i;
4495
4496 /* The supported periods are organized in ascending order */
4497 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4498 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4499 break;
4500
4501 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4502}
4503
749359f4
GT		 4504void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4505 struct mlx5e_params *params)
4506{
4507 /* Prefer Striding RQ, unless any of the following holds:
4508 * - Striding RQ configuration is not possible/supported.
4509 * - Slow PCI heuristic.
4510 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4511 */
4512 if (!slow_pci_heuristic(mdev) &&
4513 mlx5e_striding_rq_possible(mdev, params) &&
4514 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4515 !mlx5e_rx_is_linear_skb(mdev, params)))
4516 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4517 mlx5e_set_rq_type(mdev, params);
4518 mlx5e_init_rq_type_params(mdev, params);
4519}
4520
3edc0159
GT		 4521void mlx5e_build_rss_params(struct mlx5e_params *params)
4522{
4523 params->rss_hfunc = ETH_RSS_HASH_XOR;
4524 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4525 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4526 MLX5E_INDIR_RQT_SIZE, params->num_channels);
4527}
4528
8f493ffd
SM		 4529void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4530 struct mlx5e_params *params,
472a1e44 4531 u16 max_channels, u16 mtu)
f62b8bb8 4532{
48bfc397 4533 u8 rx_cq_period_mode;
2fc4bfb7 4534
472a1e44
TT		 4535 params->sw_mtu = mtu;
4536 params->hard_mtu = MLX5E_ETH_HARD_MTU;
6a9764ef
SM		 4537 params->num_channels = max_channels;
4538 params->num_tc = 1;
2b029556 4539
6a9764ef
SM		 4540 /* SQ */
4541 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 4542 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4543 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 4544
b797a684 4545 /* set CQE compression */
6a9764ef 4546 params->rx_cqe_compress_def = false;
b797a684 4547 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4548 MLX5_CAP_GEN(mdev, vport_group_manager))
0608d4db 4549 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
0f6e4cf6 4550
6a9764ef 4551 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
b856df28 4552 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
6a9764ef
SM		 4553
4554 /* RQ */
749359f4 4555 mlx5e_build_rq_params(mdev, params);
b797a684 4556
6a9764ef 4557 /* HW LRO */
c139dbfd 4558
5426a0b2 4559 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4560 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
619a8f2a
TT		 4561 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4562 params->lro_en = !slow_pci_heuristic(mdev);
6a9764ef 4563 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4564
6a9764ef 4565 /* CQ moderation params */
48bfc397 4566 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
6a9764ef
SM		 4567 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4568 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
9a317425 4569 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
cbce4f44 4570 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
48bfc397
TG		 4571 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4572 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
9908aa29 4573
6a9764ef 4574 /* TX inline */
fbcb127e 4575 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4576
6a9764ef 4577 /* RSS */
3edc0159 4578 mlx5e_build_rss_params(params);
6a9764ef 4579}
f62b8bb8 4580
f62b8bb8
AV		 4581static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4582{
4583 struct mlx5e_priv *priv = netdev_priv(netdev);
4584
e1d7d349 4585 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4586 if (is_zero_ether_addr(netdev->dev_addr) &&
4587 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4588 eth_hw_addr_random(netdev);
4589 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4590 }
f62b8bb8
AV		 4591}
4592
f125376b 4593#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4594static const struct switchdev_ops mlx5e_switchdev_ops = {
4595 .switchdev_port_attr_get = mlx5e_attr_get,
4596};
e80541ec 4597#endif
cb67b832 4598
6bfd390b 4599static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4600{
4601 struct mlx5e_priv *priv = netdev_priv(netdev);
4602 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4603 bool fcs_supported;
4604 bool fcs_enabled;
f62b8bb8
AV		 4605
4606 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4607
e80541ec
SM		 4608 netdev->netdev_ops = &mlx5e_netdev_ops;
4609
08fb1dac 4610#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4611 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4612 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4613#endif
66e49ded 4614
f62b8bb8
AV		 4615 netdev->watchdog_timeo = 15 * HZ;
4616
4617 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4618
12be4b21 4619 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4620 netdev->vlan_features |= NETIF_F_IP_CSUM;
4621 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4622 netdev->vlan_features |= NETIF_F_GRO;
4623 netdev->vlan_features |= NETIF_F_TSO;
4624 netdev->vlan_features |= NETIF_F_TSO6;
4625 netdev->vlan_features |= NETIF_F_RXCSUM;
4626 netdev->vlan_features |= NETIF_F_RXHASH;
4627
71186172
AH		 4628 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4629 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4630
6c3a823e
TT		 4631 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4632 mlx5e_check_fragmented_striding_rq_cap(mdev))
f62b8bb8
AV		 4633 netdev->vlan_features |= NETIF_F_LRO;
4634
4635 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4636 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4637 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4638 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4639 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4640
358aa5ce 4641 if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
b3f63c3d 4642 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4643 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4644 netdev->hw_enc_features |= NETIF_F_TSO;
4645 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4646 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4647 }
4648
358aa5ce 4649 if (mlx5_vxlan_allowed(mdev->vxlan)) {
27299841
GP		 4650 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4651 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4652 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4653 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4654 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4655 }
4656
27299841
GP		 4657 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4658 netdev->hw_features |= NETIF_F_GSO_GRE |
4659 NETIF_F_GSO_GRE_CSUM;
4660 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4661 NETIF_F_GSO_GRE_CSUM;
4662 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4663 NETIF_F_GSO_GRE_CSUM;
4664 }
4665
3f44899e
BP		 4666 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4667 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4668 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4669 netdev->features |= NETIF_F_GSO_UDP_L4;
4670
94cb1ebb
EBE		 4671 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4672
4673 if (fcs_supported)
4674 netdev->hw_features |= NETIF_F_RXALL;
4675
102722fc
GE		 4676 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4677 netdev->hw_features |= NETIF_F_RXFCS;
4678
f62b8bb8 4679 netdev->features = netdev->hw_features;
6a9764ef 4680 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4681 netdev->features &= ~NETIF_F_LRO;
4682
94cb1ebb
EBE		 4683 if (fcs_enabled)
4684 netdev->features &= ~NETIF_F_RXALL;
4685
102722fc
GE		 4686 if (!priv->channels.params.scatter_fcs_en)
4687 netdev->features &= ~NETIF_F_RXFCS;
4688
e8f887ac
AV		 4689#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4690 if (FT_CAP(flow_modify_en) &&
4691 FT_CAP(modify_root) &&
4692 FT_CAP(identified_miss_table_mode) &&
1cabe6b0 4693 FT_CAP(flow_table_modify)) {
077ecd78 4694#ifdef CONFIG_MLX5_ESWITCH
1cabe6b0 4695 netdev->hw_features |= NETIF_F_HW_TC;
077ecd78 4696#endif
ec080045 4697#ifdef CONFIG_MLX5_EN_ARFS
1cabe6b0
MG		 4698 netdev->hw_features |= NETIF_F_NTUPLE;
4699#endif
4700 }
e8f887ac 4701
f62b8bb8 4702 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4703 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4704
4705 netdev->priv_flags |= IFF_UNICAST_FLT;
4706
4707 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4708
f125376b 4709#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
733d3e54 4710 if (MLX5_ESWITCH_MANAGER(mdev))
cb67b832
HHZ		 4711 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4712#endif
547eede0
IT		 4713
4714 mlx5e_ipsec_build_netdev(priv);
c83294b9 4715 mlx5e_tls_build_netdev(priv);
f62b8bb8
AV		 4716}
4717
1462e48d 4718void mlx5e_create_q_counters(struct mlx5e_priv *priv)
593cf338
RS		 4719{
4720 struct mlx5_core_dev *mdev = priv->mdev;
4721 int err;
4722
4723 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4724 if (err) {
4725 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4726 priv->q_counter = 0;
4727 }
7cbaf9a3
MS		 4728
4729 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4730 if (err) {
4731 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4732 priv->drop_rq_q_counter = 0;
4733 }
593cf338
RS		 4734}
4735
1462e48d 4736void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
593cf338 4737{
7cbaf9a3
MS		 4738 if (priv->q_counter)
4739 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
593cf338 4740
7cbaf9a3
MS		 4741 if (priv->drop_rq_q_counter)
4742 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
593cf338
RS		 4743}
4744
182570b2
FD		 4745static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4746 struct net_device *netdev,
4747 const struct mlx5e_profile *profile,
4748 void *ppriv)
6bfd390b
HHZ		 4749{
4750 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4751 int err;
6bfd390b 4752
519a0bf5 4753 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
182570b2
FD		 4754 if (err)
4755 return err;
4756
519a0bf5 4757 mlx5e_build_nic_params(mdev, &priv->channels.params,
779d986d 4758 mlx5e_get_netdev_max_channels(netdev), netdev->mtu);
519a0bf5
SM		 4759
4760 mlx5e_timestamp_init(priv);
4761
547eede0
IT		 4762 err = mlx5e_ipsec_init(priv);
4763 if (err)
4764 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
43585a41
IL		 4765 err = mlx5e_tls_init(priv);
4766 if (err)
4767 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
6bfd390b 4768 mlx5e_build_nic_netdev(netdev);
8bfaf07f 4769 mlx5e_build_tc2txq_maps(priv);
182570b2
FD		 4770
4771 return 0;
6bfd390b
HHZ		 4772}
4773
4774static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4775{
43585a41 4776 mlx5e_tls_cleanup(priv);
547eede0 4777 mlx5e_ipsec_cleanup(priv);
182570b2 4778 mlx5e_netdev_cleanup(priv->netdev, priv);
6bfd390b
HHZ		 4779}
4780
4781static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4782{
4783 struct mlx5_core_dev *mdev = priv->mdev;
4784 int err;
6bfd390b 4785
1462e48d
RD		 4786 mlx5e_create_q_counters(priv);
4787
4788 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4789 if (err) {
4790 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4791 goto err_destroy_q_counters;
4792 }
4793
8f493ffd
SM		 4794 err = mlx5e_create_indirect_rqt(priv);
4795 if (err)
1462e48d 4796 goto err_close_drop_rq;
6bfd390b
HHZ		 4797
4798 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4799 if (err)
6bfd390b 4800 goto err_destroy_indirect_rqts;
6bfd390b 4801
46dc933c 4802 err = mlx5e_create_indirect_tirs(priv, true);
8f493ffd 4803 if (err)
6bfd390b 4804 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4805
4806 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4807 if (err)
6bfd390b 4808 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4809
4810 err = mlx5e_create_flow_steering(priv);
4811 if (err) {
4812 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4813 goto err_destroy_direct_tirs;
4814 }
4815
655dc3d2 4816 err = mlx5e_tc_nic_init(priv);
6bfd390b
HHZ		 4817 if (err)
4818 goto err_destroy_flow_steering;
4819
4820 return 0;
4821
4822err_destroy_flow_steering:
4823 mlx5e_destroy_flow_steering(priv);
4824err_destroy_direct_tirs:
4825 mlx5e_destroy_direct_tirs(priv);
4826err_destroy_indirect_tirs:
46dc933c 4827 mlx5e_destroy_indirect_tirs(priv, true);
6bfd390b 4828err_destroy_direct_rqts:
8f493ffd 4829 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4830err_destroy_indirect_rqts:
4831 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d
RD		 4832err_close_drop_rq:
4833 mlx5e_close_drop_rq(&priv->drop_rq);
4834err_destroy_q_counters:
4835 mlx5e_destroy_q_counters(priv);
6bfd390b
HHZ		 4836 return err;
4837}
4838
4839static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4840{
655dc3d2 4841 mlx5e_tc_nic_cleanup(priv);
6bfd390b
HHZ		 4842 mlx5e_destroy_flow_steering(priv);
4843 mlx5e_destroy_direct_tirs(priv);
46dc933c 4844 mlx5e_destroy_indirect_tirs(priv, true);
8f493ffd 4845 mlx5e_destroy_direct_rqts(priv);
6bfd390b 4846 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d
RD		 4847 mlx5e_close_drop_rq(&priv->drop_rq);
4848 mlx5e_destroy_q_counters(priv);
6bfd390b
HHZ		 4849}
4850
4851static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4852{
4853 int err;
4854
4855 err = mlx5e_create_tises(priv);
4856 if (err) {
4857 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4858 return err;
4859 }
4860
4861#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4862 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4863#endif
4864 return 0;
4865}
4866
4867static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4868{
4869 struct net_device *netdev = priv->netdev;
4870 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4871 u16 max_mtu;
4872
4873 mlx5e_init_l2_addr(priv);
4874
63bfd399
EBE		 4875 /* Marking the link as currently not needed by the Driver */
4876 if (!netif_running(netdev))
4877 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4878
2c3b5bee
SM		 4879 /* MTU range: 68 - hw-specific max */
4880 netdev->min_mtu = ETH_MIN_MTU;
4881 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
472a1e44 4882 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
2c3b5bee 4883 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4884
7907f23a
AH		 4885 mlx5_lag_add(mdev, netdev);
4886
6bfd390b 4887 mlx5e_enable_async_events(priv);
127ea380 4888
733d3e54 4889 if (MLX5_ESWITCH_MANAGER(priv->mdev))
1d447a39 4890 mlx5e_register_vport_reps(priv);
2c3b5bee 4891
610e89e0
SM		 4892 if (netdev->reg_state != NETREG_REGISTERED)
4893 return;
2a5e7a13
HN		 4894#ifdef CONFIG_MLX5_CORE_EN_DCB
4895 mlx5e_dcbnl_init_app(priv);
4896#endif
610e89e0
SM		 4897
4898 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4899
4900 rtnl_lock();
4901 if (netif_running(netdev))
4902 mlx5e_open(netdev);
4903 netif_device_attach(netdev);
4904 rtnl_unlock();
6bfd390b
HHZ		 4905}
4906
4907static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4908{
3deef8ce 4909 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4910
2a5e7a13
HN		 4911#ifdef CONFIG_MLX5_CORE_EN_DCB
4912 if (priv->netdev->reg_state == NETREG_REGISTERED)
4913 mlx5e_dcbnl_delete_app(priv);
4914#endif
4915
2c3b5bee
SM		 4916 rtnl_lock();
4917 if (netif_running(priv->netdev))
4918 mlx5e_close(priv->netdev);
4919 netif_device_detach(priv->netdev);
4920 rtnl_unlock();
4921
6bfd390b 4922 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4923
733d3e54 4924 if (MLX5_ESWITCH_MANAGER(priv->mdev))
1d447a39
SM		 4925 mlx5e_unregister_vport_reps(priv);
4926
6bfd390b 4927 mlx5e_disable_async_events(priv);
3deef8ce 4928 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4929}
4930
4931static const struct mlx5e_profile mlx5e_nic_profile = {
4932 .init = mlx5e_nic_init,
4933 .cleanup = mlx5e_nic_cleanup,
4934 .init_rx = mlx5e_init_nic_rx,
4935 .cleanup_rx = mlx5e_cleanup_nic_rx,
4936 .init_tx = mlx5e_init_nic_tx,
4937 .cleanup_tx = mlx5e_cleanup_nic_tx,
4938 .enable = mlx5e_nic_enable,
4939 .disable = mlx5e_nic_disable,
3834a5e6 4940 .update_stats = mlx5e_update_ndo_stats,
7ca42c80 4941 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4942 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4943 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4944 .max_tc = MLX5E_MAX_NUM_TC,
4945};
4946
2c3b5bee
SM		 4947/* mlx5e generic netdev management API (move to en_common.c) */
4948
182570b2 4949/* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
519a0bf5
SM		 4950int mlx5e_netdev_init(struct net_device *netdev,
4951 struct mlx5e_priv *priv,
4952 struct mlx5_core_dev *mdev,
4953 const struct mlx5e_profile *profile,
4954 void *ppriv)
182570b2 4955{
519a0bf5
SM		 4956 /* priv init */
4957 priv->mdev = mdev;
4958 priv->netdev = netdev;
4959 priv->profile = profile;
4960 priv->ppriv = ppriv;
4961 priv->msglevel = MLX5E_MSG_LEVEL;
4962 priv->max_opened_tc = 1;
182570b2 4963
519a0bf5
SM		 4964 mutex_init(&priv->state_lock);
4965 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4966 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4967 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
cdeef2b1 4968 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
303211b4 4969
182570b2
FD		 4970 priv->wq = create_singlethread_workqueue("mlx5e");
4971 if (!priv->wq)
4972 return -ENOMEM;
4973
519a0bf5
SM		 4974 /* netdev init */
4975 netif_carrier_off(netdev);
4976
4977#ifdef CONFIG_MLX5_EN_ARFS
4978 netdev->rx_cpu_rmap = mdev->rmap;
4979#endif
4980
182570b2
FD		 4981 return 0;
4982}
4983
4984void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
4985{
4986 destroy_workqueue(priv->wq);
4987}
4988
26e59d80
MHY		 4989struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4990 const struct mlx5e_profile *profile,
779d986d 4991 int nch,
26e59d80 4992 void *ppriv)
f62b8bb8
AV		 4993{
4994 struct net_device *netdev;
182570b2 4995 int err;
f62b8bb8 4996
08fb1dac 4997 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4998 nch * profile->max_tc,
08fb1dac 4999 nch);
f62b8bb8
AV		 5000 if (!netdev) {
5001 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5002 return NULL;
5003 }
5004
182570b2
FD		 5005 err = profile->init(mdev, netdev, profile, ppriv);
5006 if (err) {
5007 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5008 goto err_free_netdev;
5009 }
26e59d80
MHY		 5010
5011 return netdev;
5012
182570b2 5013err_free_netdev:
26e59d80
MHY		 5014 free_netdev(netdev);
5015
5016 return NULL;
5017}
5018
2c3b5bee 5019int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80
MHY		 5020{
5021 const struct mlx5e_profile *profile;
a1f240f1 5022 int max_nch;
26e59d80
MHY		 5023 int err;
5024
26e59d80
MHY		 5025 profile = priv->profile;
5026 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 5027
a1f240f1
YA		 5028 /* max number of channels may have changed */
5029 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5030 if (priv->channels.params.num_channels > max_nch) {
5031 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5032 priv->channels.params.num_channels = max_nch;
5033 mlx5e_build_default_indir_rqt(priv->channels.params.indirection_rqt,
5034 MLX5E_INDIR_RQT_SIZE, max_nch);
5035 }
5036
6bfd390b
HHZ		 5037 err = profile->init_tx(priv);
5038 if (err)
ec8b9981 5039 goto out;
5c50368f 5040
6bfd390b
HHZ		 5041 err = profile->init_rx(priv);
5042 if (err)
1462e48d 5043 goto err_cleanup_tx;
5c50368f 5044
6bfd390b
HHZ		 5045 if (profile->enable)
5046 profile->enable(priv);
f62b8bb8 5047
26e59d80 5048 return 0;
5c50368f 5049
1462e48d 5050err_cleanup_tx:
6bfd390b 5051 profile->cleanup_tx(priv);
5c50368f 5052
26e59d80
MHY		 5053out:
5054 return err;
f62b8bb8
AV		 5055}
5056
2c3b5bee 5057void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 5058{
26e59d80
MHY		 5059 const struct mlx5e_profile *profile = priv->profile;
5060
5061 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 5062
37f304d1
SM		 5063 if (profile->disable)
5064 profile->disable(priv);
5065 flush_workqueue(priv->wq);
5066
26e59d80 5067 profile->cleanup_rx(priv);
26e59d80 5068 profile->cleanup_tx(priv);
cdeef2b1 5069 cancel_work_sync(&priv->update_stats_work);
26e59d80
MHY		 5070}
5071
2c3b5bee
SM		 5072void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5073{
5074 const struct mlx5e_profile *profile = priv->profile;
5075 struct net_device *netdev = priv->netdev;
5076
2c3b5bee
SM		 5077 if (profile->cleanup)
5078 profile->cleanup(priv);
5079 free_netdev(netdev);
5080}
5081
26e59d80
MHY		 5082/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5083 * hardware contexts and to connect it to the current netdev.
5084 */
5085static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5086{
5087 struct mlx5e_priv *priv = vpriv;
5088 struct net_device *netdev = priv->netdev;
5089 int err;
5090
5091 if (netif_device_present(netdev))
5092 return 0;
5093
5094 err = mlx5e_create_mdev_resources(mdev);
5095 if (err)
5096 return err;
5097
2c3b5bee 5098 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 5099 if (err) {
5100 mlx5e_destroy_mdev_resources(mdev);
5101 return err;
5102 }
5103
5104 return 0;
5105}
5106
5107static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5108{
5109 struct mlx5e_priv *priv = vpriv;
5110 struct net_device *netdev = priv->netdev;
5111
5112 if (!netif_device_present(netdev))
5113 return;
5114
2c3b5bee 5115 mlx5e_detach_netdev(priv);
26e59d80
MHY		 5116 mlx5e_destroy_mdev_resources(mdev);
5117}
5118
b50d292b
HHZ		 5119static void *mlx5e_add(struct mlx5_core_dev *mdev)
5120{
07c9f1e5
SM		 5121 struct net_device *netdev;
5122 void *rpriv = NULL;
26e59d80 5123 void *priv;
26e59d80 5124 int err;
779d986d 5125 int nch;
b50d292b 5126
26e59d80
MHY		 5127 err = mlx5e_check_required_hca_cap(mdev);
5128 if (err)
b50d292b
HHZ		 5129 return NULL;
5130
e80541ec 5131#ifdef CONFIG_MLX5_ESWITCH
733d3e54 5132 if (MLX5_ESWITCH_MANAGER(mdev)) {
07c9f1e5 5133 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 5134 if (!rpriv) {
07c9f1e5 5135 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 5136 return NULL;
5137 }
1d447a39 5138 }
e80541ec 5139#endif
127ea380 5140
779d986d
FD		 5141 nch = mlx5e_get_max_num_channels(mdev);
5142 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, rpriv);
26e59d80
MHY		 5143 if (!netdev) {
5144 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 5145 goto err_free_rpriv;
26e59d80
MHY		 5146 }
5147
5148 priv = netdev_priv(netdev);
5149
5150 err = mlx5e_attach(mdev, priv);
5151 if (err) {
5152 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5153 goto err_destroy_netdev;
5154 }
5155
5156 err = register_netdev(netdev);
5157 if (err) {
5158 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5159 goto err_detach;
b50d292b 5160 }
26e59d80 5161
2a5e7a13
HN		 5162#ifdef CONFIG_MLX5_CORE_EN_DCB
5163 mlx5e_dcbnl_init_app(priv);
5164#endif
26e59d80
MHY		 5165 return priv;
5166
5167err_detach:
5168 mlx5e_detach(mdev, priv);
26e59d80 5169err_destroy_netdev:
2c3b5bee 5170 mlx5e_destroy_netdev(priv);
07c9f1e5 5171err_free_rpriv:
1d447a39 5172 kfree(rpriv);
26e59d80 5173 return NULL;
b50d292b
HHZ		 5174}
5175
b50d292b
HHZ		 5176static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5177{
5178 struct mlx5e_priv *priv = vpriv;
1d447a39 5179 void *ppriv = priv->ppriv;
127ea380 5180
2a5e7a13
HN		 5181#ifdef CONFIG_MLX5_CORE_EN_DCB
5182 mlx5e_dcbnl_delete_app(priv);
5183#endif
5e1e93c7 5184 unregister_netdev(priv->netdev);
26e59d80 5185 mlx5e_detach(mdev, vpriv);
2c3b5bee 5186 mlx5e_destroy_netdev(priv);
1d447a39 5187 kfree(ppriv);
b50d292b
HHZ		 5188}
5189
f62b8bb8
AV		 5190static void *mlx5e_get_netdev(void *vpriv)
5191{
5192 struct mlx5e_priv *priv = vpriv;
5193
5194 return priv->netdev;
5195}
5196
5197static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 5198 .add = mlx5e_add,
5199 .remove = mlx5e_remove,
26e59d80
MHY		 5200 .attach = mlx5e_attach,
5201 .detach = mlx5e_detach,
f62b8bb8
AV		 5202 .event = mlx5e_async_event,
5203 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5204 .get_dev = mlx5e_get_netdev,
5205};
5206
5207void mlx5e_init(void)
5208{
2ac9cfe7 5209 mlx5e_ipsec_build_inverse_table();
665bc539 5210 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 5211 mlx5_register_interface(&mlx5e_interface);
5212}
5213
5214void mlx5e_cleanup(void)
5215{
5216 mlx5_unregister_interface(&mlx5e_interface);
5217}
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