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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / mtd / nand / raw / atmel / nand-controller.c
CommitLineData
f88fc122
BB		 1/*
2 * Copyright 2017 ATMEL
3 * Copyright 2017 Free Electrons
4 *
5 * Author: Boris Brezillon <[email protected]>
6 *
7 * Derived from the atmel_nand.c driver which contained the following
8 * copyrights:
9 *
10 * Copyright 2003 Rick Bronson
11 *
187c5448 12 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
f88fc122
BB		 13 * Copyright 2001 Thomas Gleixner ([email protected])
14 *
187c5448 15 * Derived from drivers/mtd/spia.c (removed in v3.8)
f88fc122
BB		 16 * Copyright 2000 Steven J. Hill ([email protected])
17 *
18 *
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20 * Richard Genoud ([email protected]), Adeneo Copyright 2007
21 *
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
25 *
26 * Add Programmable Multibit ECC support for various AT91 SoC
27 * Copyright 2012 ATMEL, Hong Xu
28 *
29 * Add Nand Flash Controller support for SAMA5 SoC
30 * Copyright 2013 ATMEL, Josh Wu ([email protected])
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
35 *
36 * A few words about the naming convention in this file. This convention
37 * applies to structure and function names.
38 *
39 * Prefixes:
40 *
41 * - atmel_nand_: all generic structures/functions
42 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43 * (at91sam9 and avr32 SoCs)
44 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45 * (sama5 SoCs and later)
46 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47 * that is available in the HSMC block
48 * - <soc>_nand_: all SoC specific structures/functions
49 */
50
51#include <linux/clk.h>
52#include <linux/dma-mapping.h>
53#include <linux/dmaengine.h>
54#include <linux/genalloc.h>
f88fc122
BB		 55#include <linux/gpio/consumer.h>
56#include <linux/interrupt.h>
57#include <linux/mfd/syscon.h>
58#include <linux/mfd/syscon/atmel-matrix.h>
f9ce2edd 59#include <linux/mfd/syscon/atmel-smc.h>
f88fc122 60#include <linux/module.h>
d4092d76 61#include <linux/mtd/rawnand.h>
f88fc122
BB		 62#include <linux/of_address.h>
63#include <linux/of_irq.h>
64#include <linux/of_platform.h>
65#include <linux/iopoll.h>
66#include <linux/platform_device.h>
f88fc122
BB		 67#include <linux/regmap.h>
68
69#include "pmecc.h"
70
71#define ATMEL_HSMC_NFC_CFG 0x0
72#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
73#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
74#define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
75#define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
76#define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
77#define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
78#define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
79#define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
80#define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
81#define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
82
83#define ATMEL_HSMC_NFC_CTRL 0x4
84#define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
85#define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
86
87#define ATMEL_HSMC_NFC_SR 0x8
88#define ATMEL_HSMC_NFC_IER 0xc
89#define ATMEL_HSMC_NFC_IDR 0x10
90#define ATMEL_HSMC_NFC_IMR 0x14
91#define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
92#define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
93#define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
94#define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
95#define ATMEL_HSMC_NFC_SR_WR BIT(11)
96#define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
97#define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
98#define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
99#define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
100#define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
101#define ATMEL_HSMC_NFC_SR_AWB BIT(22)
102#define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
103#define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
104 ATMEL_HSMC_NFC_SR_UNDEF | \
105 ATMEL_HSMC_NFC_SR_AWB | \
106 ATMEL_HSMC_NFC_SR_NFCASE)
107#define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
108
109#define ATMEL_HSMC_NFC_ADDR 0x18
110#define ATMEL_HSMC_NFC_BANK 0x1c
111
112#define ATMEL_NFC_MAX_RB_ID 7
113
114#define ATMEL_NFC_SRAM_SIZE 0x2400
115
116#define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
117#define ATMEL_NFC_VCMD2 BIT(18)
118#define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
119#define ATMEL_NFC_CSID(cs) ((cs) << 22)
120#define ATMEL_NFC_DATAEN BIT(25)
121#define ATMEL_NFC_NFCWR BIT(26)
122
123#define ATMEL_NFC_MAX_ADDR_CYCLES 5
124
125#define ATMEL_NAND_ALE_OFFSET BIT(21)
126#define ATMEL_NAND_CLE_OFFSET BIT(22)
127
128#define DEFAULT_TIMEOUT_MS 1000
129#define MIN_DMA_LEN 128
130
efc6362c
PR		 131static bool atmel_nand_avoid_dma __read_mostly;
132
133MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
134module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
135
f88fc122
BB		 136enum atmel_nand_rb_type {
137 ATMEL_NAND_NO_RB,
138 ATMEL_NAND_NATIVE_RB,
139 ATMEL_NAND_GPIO_RB,
140};
141
142struct atmel_nand_rb {
143 enum atmel_nand_rb_type type;
144 union {
145 struct gpio_desc *gpio;
146 int id;
147 };
148};
149
150struct atmel_nand_cs {
151 int id;
152 struct atmel_nand_rb rb;
153 struct gpio_desc *csgpio;
154 struct {
155 void __iomem *virt;
156 dma_addr_t dma;
157 } io;
f9ce2edd
BB		 158
159 struct atmel_smc_cs_conf smcconf;
f88fc122
BB		 160};
161
162struct atmel_nand {
163 struct list_head node;
164 struct device *dev;
165 struct nand_chip base;
166 struct atmel_nand_cs *activecs;
167 struct atmel_pmecc_user *pmecc;
168 struct gpio_desc *cdgpio;
169 int numcs;
170 struct atmel_nand_cs cs[];
171};
172
173static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
174{
175 return container_of(chip, struct atmel_nand, base);
176}
177
178enum atmel_nfc_data_xfer {
179 ATMEL_NFC_NO_DATA,
180 ATMEL_NFC_READ_DATA,
181 ATMEL_NFC_WRITE_DATA,
182};
183
184struct atmel_nfc_op {
185 u8 cs;
186 u8 ncmds;
187 u8 cmds[2];
188 u8 naddrs;
189 u8 addrs[5];
190 enum atmel_nfc_data_xfer data;
191 u32 wait;
192 u32 errors;
193};
194
195struct atmel_nand_controller;
196struct atmel_nand_controller_caps;
197
198struct atmel_nand_controller_ops {
199 int (*probe)(struct platform_device *pdev,
200 const struct atmel_nand_controller_caps *caps);
201 int (*remove)(struct atmel_nand_controller *nc);
202 void (*nand_init)(struct atmel_nand_controller *nc,
203 struct atmel_nand *nand);
577e010c 204 int (*ecc_init)(struct nand_chip *chip);
f9ce2edd
BB		 205 int (*setup_data_interface)(struct atmel_nand *nand, int csline,
206 const struct nand_data_interface *conf);
f88fc122
BB		 207};
208
209struct atmel_nand_controller_caps {
210 bool has_dma;
211 bool legacy_of_bindings;
212 u32 ale_offs;
213 u32 cle_offs;
214 const struct atmel_nand_controller_ops *ops;
215};
216
217struct atmel_nand_controller {
7da45139 218 struct nand_controller base;
f88fc122
BB		 219 const struct atmel_nand_controller_caps *caps;
220 struct device *dev;
221 struct regmap *smc;
222 struct dma_chan *dmac;
223 struct atmel_pmecc *pmecc;
224 struct list_head chips;
225 struct clk *mck;
226};
227
228static inline struct atmel_nand_controller *
7da45139 229to_nand_controller(struct nand_controller *ctl)
f88fc122
BB		 230{
231 return container_of(ctl, struct atmel_nand_controller, base);
232}
233
234struct atmel_smc_nand_controller {
235 struct atmel_nand_controller base;
236 struct regmap *matrix;
237 unsigned int ebi_csa_offs;
238};
239
240static inline struct atmel_smc_nand_controller *
7da45139 241to_smc_nand_controller(struct nand_controller *ctl)
f88fc122
BB		 242{
243 return container_of(to_nand_controller(ctl),
244 struct atmel_smc_nand_controller, base);
245}
246
247struct atmel_hsmc_nand_controller {
248 struct atmel_nand_controller base;
249 struct {
250 struct gen_pool *pool;
251 void __iomem *virt;
252 dma_addr_t dma;
253 } sram;
b0f3ab20 254 const struct atmel_hsmc_reg_layout *hsmc_layout;
f88fc122
BB		 255 struct regmap *io;
256 struct atmel_nfc_op op;
257 struct completion complete;
258 int irq;
259
260 /* Only used when instantiating from legacy DT bindings. */
261 struct clk *clk;
262};
263
264static inline struct atmel_hsmc_nand_controller *
7da45139 265to_hsmc_nand_controller(struct nand_controller *ctl)
f88fc122
BB		 266{
267 return container_of(to_nand_controller(ctl),
268 struct atmel_hsmc_nand_controller, base);
269}
270
271static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
272{
273 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
274 op->wait ^= status & op->wait;
275
276 return !op->wait || op->errors;
277}
278
279static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
280{
281 struct atmel_hsmc_nand_controller *nc = data;
282 u32 sr, rcvd;
283 bool done;
284
285 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
286
287 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
288 done = atmel_nfc_op_done(&nc->op, sr);
289
290 if (rcvd)
291 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
292
293 if (done)
294 complete(&nc->complete);
295
296 return rcvd ? IRQ_HANDLED : IRQ_NONE;
297}
298
299static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
300 unsigned int timeout_ms)
301{
302 int ret;
303
304 if (!timeout_ms)
305 timeout_ms = DEFAULT_TIMEOUT_MS;
306
307 if (poll) {
308 u32 status;
309
310 ret = regmap_read_poll_timeout(nc->base.smc,
311 ATMEL_HSMC_NFC_SR, status,
312 atmel_nfc_op_done(&nc->op,
313 status),
314 0, timeout_ms * 1000);
315 } else {
316 init_completion(&nc->complete);
317 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
318 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
319 ret = wait_for_completion_timeout(&nc->complete,
320 msecs_to_jiffies(timeout_ms));
321 if (!ret)
322 ret = -ETIMEDOUT;
323 else
324 ret = 0;
325
326 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
327 }
328
329 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
330 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
331 ret = -ETIMEDOUT;
332 }
333
334 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
335 dev_err(nc->base.dev, "Access to an undefined area\n");
336 ret = -EIO;
337 }
338
339 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
340 dev_err(nc->base.dev, "Access while busy\n");
341 ret = -EIO;
342 }
343
344 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
345 dev_err(nc->base.dev, "Wrong access size\n");
346 ret = -EIO;
347 }
348
349 return ret;
350}
351
352static void atmel_nand_dma_transfer_finished(void *data)
353{
354 struct completion *finished = data;
355
356 complete(finished);
357}
358
359static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
360 void *buf, dma_addr_t dev_dma, size_t len,
361 enum dma_data_direction dir)
362{
363 DECLARE_COMPLETION_ONSTACK(finished);
364 dma_addr_t src_dma, dst_dma, buf_dma;
365 struct dma_async_tx_descriptor *tx;
366 dma_cookie_t cookie;
367
368 buf_dma = dma_map_single(nc->dev, buf, len, dir);
369 if (dma_mapping_error(nc->dev, dev_dma)) {
370 dev_err(nc->dev,
371 "Failed to prepare a buffer for DMA access\n");
372 goto err;
373 }
374
375 if (dir == DMA_FROM_DEVICE) {
376 src_dma = dev_dma;
377 dst_dma = buf_dma;
378 } else {
379 src_dma = buf_dma;
380 dst_dma = dev_dma;
381 }
382
383 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
384 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
385 if (!tx) {
386 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
387 goto err_unmap;
388 }
389
390 tx->callback = atmel_nand_dma_transfer_finished;
391 tx->callback_param = &finished;
392
393 cookie = dmaengine_submit(tx);
394 if (dma_submit_error(cookie)) {
395 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
396 goto err_unmap;
397 }
398
399 dma_async_issue_pending(nc->dmac);
400 wait_for_completion(&finished);
401
402 return 0;
403
404err_unmap:
405 dma_unmap_single(nc->dev, buf_dma, len, dir);
406
407err:
408 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
409
410 return -EIO;
411}
412
7e534323 413static u8 atmel_nand_read_byte(struct nand_chip *chip)
f88fc122 414{
f88fc122
BB		 415 struct atmel_nand *nand = to_atmel_nand(chip);
416
417 return ioread8(nand->activecs->io.virt);
418}
419
c0739d85 420static void atmel_nand_write_byte(struct nand_chip *chip, u8 byte)
f88fc122 421{
f88fc122
BB		 422 struct atmel_nand *nand = to_atmel_nand(chip);
423
424 if (chip->options & NAND_BUSWIDTH_16)
425 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
426 else
427 iowrite8(byte, nand->activecs->io.virt);
428}
429
7e534323 430static void atmel_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
f88fc122 431{
f88fc122
BB		 432 struct atmel_nand *nand = to_atmel_nand(chip);
433 struct atmel_nand_controller *nc;
434
435 nc = to_nand_controller(chip->controller);
436
437 /*
438 * If the controller supports DMA, the buffer address is DMA-able and
439 * len is long enough to make DMA transfers profitable, let's trigger
440 * a DMA transfer. If it fails, fallback to PIO mode.
441 */
442 if (nc->dmac && virt_addr_valid(buf) &&
443 len >= MIN_DMA_LEN &&
444 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
445 DMA_FROM_DEVICE))
446 return;
447
448 if (chip->options & NAND_BUSWIDTH_16)
449 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
450 else
451 ioread8_rep(nand->activecs->io.virt, buf, len);
452}
453
c0739d85 454static void atmel_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
f88fc122 455{
f88fc122
BB		 456 struct atmel_nand *nand = to_atmel_nand(chip);
457 struct atmel_nand_controller *nc;
458
459 nc = to_nand_controller(chip->controller);
460
461 /*
462 * If the controller supports DMA, the buffer address is DMA-able and
463 * len is long enough to make DMA transfers profitable, let's trigger
464 * a DMA transfer. If it fails, fallback to PIO mode.
465 */
466 if (nc->dmac && virt_addr_valid(buf) &&
467 len >= MIN_DMA_LEN &&
468 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
469 len, DMA_TO_DEVICE))
470 return;
471
472 if (chip->options & NAND_BUSWIDTH_16)
473 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
474 else
475 iowrite8_rep(nand->activecs->io.virt, buf, len);
476}
477
50a487e7 478static int atmel_nand_dev_ready(struct nand_chip *chip)
f88fc122 479{
f88fc122
BB		 480 struct atmel_nand *nand = to_atmel_nand(chip);
481
482 return gpiod_get_value(nand->activecs->rb.gpio);
483}
484
758b56f5 485static void atmel_nand_select_chip(struct nand_chip *chip, int cs)
f88fc122 486{
f88fc122
BB		 487 struct atmel_nand *nand = to_atmel_nand(chip);
488
489 if (cs < 0 || cs >= nand->numcs) {
490 nand->activecs = NULL;
8395b753 491 chip->legacy.dev_ready = NULL;
f88fc122
BB		 492 return;
493 }
494
495 nand->activecs = &nand->cs[cs];
496
497 if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
8395b753 498 chip->legacy.dev_ready = atmel_nand_dev_ready;
f88fc122
BB		 499}
500
50a487e7 501static int atmel_hsmc_nand_dev_ready(struct nand_chip *chip)
f88fc122 502{
f88fc122
BB		 503 struct atmel_nand *nand = to_atmel_nand(chip);
504 struct atmel_hsmc_nand_controller *nc;
505 u32 status;
506
507 nc = to_hsmc_nand_controller(chip->controller);
508
509 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
510
511 return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
512}
513
758b56f5 514static void atmel_hsmc_nand_select_chip(struct nand_chip *chip, int cs)
f88fc122 515{
758b56f5 516 struct mtd_info *mtd = nand_to_mtd(chip);
f88fc122
BB		 517 struct atmel_nand *nand = to_atmel_nand(chip);
518 struct atmel_hsmc_nand_controller *nc;
519
520 nc = to_hsmc_nand_controller(chip->controller);
521
758b56f5 522 atmel_nand_select_chip(chip, cs);
f88fc122
BB		 523
524 if (!nand->activecs) {
525 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
526 ATMEL_HSMC_NFC_CTRL_DIS);
527 return;
528 }
529
530 if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
8395b753 531 chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready;
f88fc122
BB		 532
533 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
534 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
535 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
536 ATMEL_HSMC_NFC_CFG_RSPARE |
537 ATMEL_HSMC_NFC_CFG_WSPARE,
538 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
539 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
540 ATMEL_HSMC_NFC_CFG_RSPARE);
541 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
542 ATMEL_HSMC_NFC_CTRL_EN);
543}
544
545static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
546{
547 u8 *addrs = nc->op.addrs;
548 unsigned int op = 0;
549 u32 addr, val;
550 int i, ret;
551
552 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
553
554 for (i = 0; i < nc->op.ncmds; i++)
555 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
556
557 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
558 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
559
560 op |= ATMEL_NFC_CSID(nc->op.cs) |
561 ATMEL_NFC_ACYCLE(nc->op.naddrs);
562
563 if (nc->op.ncmds > 1)
564 op |= ATMEL_NFC_VCMD2;
565
566 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
567 (addrs[3] << 24);
568
569 if (nc->op.data != ATMEL_NFC_NO_DATA) {
570 op |= ATMEL_NFC_DATAEN;
571 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
572
573 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
574 op |= ATMEL_NFC_NFCWR;
575 }
576
577 /* Clear all flags. */
578 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
579
580 /* Send the command. */
581 regmap_write(nc->io, op, addr);
582
583 ret = atmel_nfc_wait(nc, poll, 0);
584 if (ret)
585 dev_err(nc->base.dev,
586 "Failed to send NAND command (err = %d)!",
587 ret);
588
589 /* Reset the op state. */
590 memset(&nc->op, 0, sizeof(nc->op));
591
592 return ret;
593}
594
0f808c16 595static void atmel_hsmc_nand_cmd_ctrl(struct nand_chip *chip, int dat,
f88fc122
BB		 596 unsigned int ctrl)
597{
f88fc122
BB		 598 struct atmel_nand *nand = to_atmel_nand(chip);
599 struct atmel_hsmc_nand_controller *nc;
600
601 nc = to_hsmc_nand_controller(chip->controller);
602
603 if (ctrl & NAND_ALE) {
604 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
605 return;
606
607 nc->op.addrs[nc->op.naddrs++] = dat;
608 } else if (ctrl & NAND_CLE) {
609 if (nc->op.ncmds > 1)
610 return;
611
612 nc->op.cmds[nc->op.ncmds++] = dat;
613 }
614
615 if (dat == NAND_CMD_NONE) {
616 nc->op.cs = nand->activecs->id;
617 atmel_nfc_exec_op(nc, true);
618 }
619}
620
0f808c16 621static void atmel_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
f88fc122
BB		 622 unsigned int ctrl)
623{
f88fc122
BB		 624 struct atmel_nand *nand = to_atmel_nand(chip);
625 struct atmel_nand_controller *nc;
626
627 nc = to_nand_controller(chip->controller);
628
629 if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
630 if (ctrl & NAND_NCE)
631 gpiod_set_value(nand->activecs->csgpio, 0);
632 else
633 gpiod_set_value(nand->activecs->csgpio, 1);
634 }
635
636 if (ctrl & NAND_ALE)
637 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
638 else if (ctrl & NAND_CLE)
639 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
640}
641
642static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
643 bool oob_required)
644{
645 struct mtd_info *mtd = nand_to_mtd(chip);
646 struct atmel_hsmc_nand_controller *nc;
647 int ret = -EIO;
648
649 nc = to_hsmc_nand_controller(chip->controller);
650
651 if (nc->base.dmac)
652 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
653 nc->sram.dma, mtd->writesize,
654 DMA_TO_DEVICE);
655
656 /* Falling back to CPU copy. */
657 if (ret)
658 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
659
660 if (oob_required)
661 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
662 mtd->oobsize);
663}
664
665static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
666 bool oob_required)
667{
668 struct mtd_info *mtd = nand_to_mtd(chip);
669 struct atmel_hsmc_nand_controller *nc;
670 int ret = -EIO;
671
672 nc = to_hsmc_nand_controller(chip->controller);
673
674 if (nc->base.dmac)
675 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
676 mtd->writesize, DMA_FROM_DEVICE);
677
678 /* Falling back to CPU copy. */
679 if (ret)
680 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
681
682 if (oob_required)
683 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
684 mtd->oobsize);
685}
686
687static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
688{
689 struct mtd_info *mtd = nand_to_mtd(chip);
690 struct atmel_hsmc_nand_controller *nc;
691
692 nc = to_hsmc_nand_controller(chip->controller);
693
694 if (column >= 0) {
695 nc->op.addrs[nc->op.naddrs++] = column;
696
697 /*
698 * 2 address cycles for the column offset on large page NANDs.
699 */
700 if (mtd->writesize > 512)
701 nc->op.addrs[nc->op.naddrs++] = column >> 8;
702 }
703
704 if (page >= 0) {
705 nc->op.addrs[nc->op.naddrs++] = page;
706 nc->op.addrs[nc->op.naddrs++] = page >> 8;
707
14157f86 708 if (chip->options & NAND_ROW_ADDR_3)
f88fc122
BB		 709 nc->op.addrs[nc->op.naddrs++] = page >> 16;
710 }
711}
712
713static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
714{
715 struct atmel_nand *nand = to_atmel_nand(chip);
716 struct atmel_nand_controller *nc;
717 int ret;
718
719 nc = to_nand_controller(chip->controller);
720
721 if (raw)
722 return 0;
723
724 ret = atmel_pmecc_enable(nand->pmecc, op);
725 if (ret)
726 dev_err(nc->dev,
727 "Failed to enable ECC engine (err = %d)\n", ret);
728
729 return ret;
730}
731
732static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
733{
734 struct atmel_nand *nand = to_atmel_nand(chip);
735
736 if (!raw)
737 atmel_pmecc_disable(nand->pmecc);
738}
739
740static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
741{
742 struct atmel_nand *nand = to_atmel_nand(chip);
743 struct mtd_info *mtd = nand_to_mtd(chip);
744 struct atmel_nand_controller *nc;
745 struct mtd_oob_region oobregion;
746 void *eccbuf;
747 int ret, i;
748
749 nc = to_nand_controller(chip->controller);
750
751 if (raw)
752 return 0;
753
754 ret = atmel_pmecc_wait_rdy(nand->pmecc);
755 if (ret) {
756 dev_err(nc->dev,
757 "Failed to transfer NAND page data (err = %d)\n",
758 ret);
759 return ret;
760 }
761
762 mtd_ooblayout_ecc(mtd, 0, &oobregion);
763 eccbuf = chip->oob_poi + oobregion.offset;
764
765 for (i = 0; i < chip->ecc.steps; i++) {
766 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
767 eccbuf);
768 eccbuf += chip->ecc.bytes;
769 }
770
771 return 0;
772}
773
774static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
775 bool raw)
776{
777 struct atmel_nand *nand = to_atmel_nand(chip);
778 struct mtd_info *mtd = nand_to_mtd(chip);
779 struct atmel_nand_controller *nc;
780 struct mtd_oob_region oobregion;
781 int ret, i, max_bitflips = 0;
782 void *databuf, *eccbuf;
783
784 nc = to_nand_controller(chip->controller);
785
786 if (raw)
787 return 0;
788
789 ret = atmel_pmecc_wait_rdy(nand->pmecc);
790 if (ret) {
791 dev_err(nc->dev,
792 "Failed to read NAND page data (err = %d)\n",
793 ret);
794 return ret;
795 }
796
797 mtd_ooblayout_ecc(mtd, 0, &oobregion);
798 eccbuf = chip->oob_poi + oobregion.offset;
799 databuf = buf;
800
801 for (i = 0; i < chip->ecc.steps; i++) {
802 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
803 eccbuf);
804 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
805 ret = nand_check_erased_ecc_chunk(databuf,
806 chip->ecc.size,
807 eccbuf,
808 chip->ecc.bytes,
809 NULL, 0,
810 chip->ecc.strength);
811
812 if (ret >= 0)
813 max_bitflips = max(ret, max_bitflips);
814 else
815 mtd->ecc_stats.failed++;
816
817 databuf += chip->ecc.size;
818 eccbuf += chip->ecc.bytes;
819 }
820
821 return max_bitflips;
822}
823
824static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
825 bool oob_required, int page, bool raw)
826{
827 struct mtd_info *mtd = nand_to_mtd(chip);
828 struct atmel_nand *nand = to_atmel_nand(chip);
829 int ret;
830
25f815f6
BB		 831 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
832
f88fc122
BB		 833 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
834 if (ret)
835 return ret;
836
c0739d85 837 atmel_nand_write_buf(chip, buf, mtd->writesize);
f88fc122
BB		 838
839 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
840 if (ret) {
841 atmel_pmecc_disable(nand->pmecc);
842 return ret;
843 }
844
845 atmel_nand_pmecc_disable(chip, raw);
846
c0739d85 847 atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
f88fc122 848
25f815f6 849 return nand_prog_page_end_op(chip);
f88fc122
BB		 850}
851
767eb6fb 852static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
f88fc122
BB		 853 int oob_required, int page)
854{
855 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
856}
857
767eb6fb 858static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
f88fc122
BB		 859 const u8 *buf, int oob_required,
860 int page)
861{
862 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
863}
864
865static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
866 bool oob_required, int page, bool raw)
867{
868 struct mtd_info *mtd = nand_to_mtd(chip);
869 int ret;
870
25f815f6
BB		 871 nand_read_page_op(chip, page, 0, NULL, 0);
872
f88fc122
BB		 873 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
874 if (ret)
875 return ret;
876
7e534323
BB		 877 atmel_nand_read_buf(chip, buf, mtd->writesize);
878 atmel_nand_read_buf(chip, chip->oob_poi, mtd->oobsize);
f88fc122
BB		 879
880 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
881
882 atmel_nand_pmecc_disable(chip, raw);
883
884 return ret;
885}
886
b9761687 887static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
f88fc122
BB		 888 int oob_required, int page)
889{
890 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
891}
892
b9761687 893static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
f88fc122
BB		 894 int oob_required, int page)
895{
896 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
897}
898
899static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
900 const u8 *buf, bool oob_required,
901 int page, bool raw)
902{
903 struct mtd_info *mtd = nand_to_mtd(chip);
904 struct atmel_nand *nand = to_atmel_nand(chip);
905 struct atmel_hsmc_nand_controller *nc;
41145649 906 int ret, status;
f88fc122
BB		 907
908 nc = to_hsmc_nand_controller(chip->controller);
909
910 atmel_nfc_copy_to_sram(chip, buf, false);
911
912 nc->op.cmds[0] = NAND_CMD_SEQIN;
913 nc->op.ncmds = 1;
914 atmel_nfc_set_op_addr(chip, page, 0x0);
915 nc->op.cs = nand->activecs->id;
916 nc->op.data = ATMEL_NFC_WRITE_DATA;
917
918 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
919 if (ret)
920 return ret;
921
922 ret = atmel_nfc_exec_op(nc, false);
923 if (ret) {
924 atmel_nand_pmecc_disable(chip, raw);
925 dev_err(nc->base.dev,
926 "Failed to transfer NAND page data (err = %d)\n",
927 ret);
928 return ret;
929 }
930
931 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
932
933 atmel_nand_pmecc_disable(chip, raw);
934
935 if (ret)
936 return ret;
937
c0739d85 938 atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
f88fc122
BB		 939
940 nc->op.cmds[0] = NAND_CMD_PAGEPROG;
941 nc->op.ncmds = 1;
942 nc->op.cs = nand->activecs->id;
943 ret = atmel_nfc_exec_op(nc, false);
944 if (ret)
945 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
946 ret);
947
8395b753 948 status = chip->legacy.waitfunc(chip);
41145649
BB		 949 if (status & NAND_STATUS_FAIL)
950 return -EIO;
951
f88fc122
BB		 952 return ret;
953}
954
767eb6fb 955static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
f88fc122
BB		 956 const u8 *buf, int oob_required,
957 int page)
958{
959 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
960 false);
961}
962
767eb6fb 963static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
f88fc122
BB		 964 const u8 *buf,
965 int oob_required, int page)
966{
967 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
968 true);
969}
970
971static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
972 bool oob_required, int page,
973 bool raw)
974{
975 struct mtd_info *mtd = nand_to_mtd(chip);
976 struct atmel_nand *nand = to_atmel_nand(chip);
977 struct atmel_hsmc_nand_controller *nc;
978 int ret;
979
980 nc = to_hsmc_nand_controller(chip->controller);
981
982 /*
983 * Optimized read page accessors only work when the NAND R/B pin is
984 * connected to a native SoC R/B pin. If that's not the case, fallback
985 * to the non-optimized one.
986 */
987 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
97d90da8 988 nand_read_page_op(chip, page, 0, NULL, 0);
f88fc122
BB		 989
990 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
991 raw);
992 }
993
994 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
995
996 if (mtd->writesize > 512)
997 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
998
999 atmel_nfc_set_op_addr(chip, page, 0x0);
1000 nc->op.cs = nand->activecs->id;
1001 nc->op.data = ATMEL_NFC_READ_DATA;
1002
1003 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1004 if (ret)
1005 return ret;
1006
1007 ret = atmel_nfc_exec_op(nc, false);
1008 if (ret) {
1009 atmel_nand_pmecc_disable(chip, raw);
1010 dev_err(nc->base.dev,
1011 "Failed to load NAND page data (err = %d)\n",
1012 ret);
1013 return ret;
1014 }
1015
1016 atmel_nfc_copy_from_sram(chip, buf, true);
1017
1018 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1019
1020 atmel_nand_pmecc_disable(chip, raw);
1021
1022 return ret;
1023}
1024
b9761687 1025static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
f88fc122
BB		 1026 int oob_required, int page)
1027{
1028 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1029 false);
1030}
1031
b9761687 1032static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
f88fc122
BB		 1033 u8 *buf, int oob_required,
1034 int page)
1035{
1036 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1037 true);
1038}
1039
1040static int atmel_nand_pmecc_init(struct nand_chip *chip)
1041{
1042 struct mtd_info *mtd = nand_to_mtd(chip);
1043 struct atmel_nand *nand = to_atmel_nand(chip);
1044 struct atmel_nand_controller *nc;
1045 struct atmel_pmecc_user_req req;
1046
1047 nc = to_nand_controller(chip->controller);
1048
1049 if (!nc->pmecc) {
1050 dev_err(nc->dev, "HW ECC not supported\n");
1051 return -ENOTSUPP;
1052 }
1053
1054 if (nc->caps->legacy_of_bindings) {
1055 u32 val;
1056
1057 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1058 &val))
1059 chip->ecc.strength = val;
1060
1061 if (!of_property_read_u32(nc->dev->of_node,
1062 "atmel,pmecc-sector-size",
1063 &val))
1064 chip->ecc.size = val;
1065 }
1066
1067 if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1068 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1069 else if (chip->ecc.strength)
1070 req.ecc.strength = chip->ecc.strength;
1071 else if (chip->ecc_strength_ds)
1072 req.ecc.strength = chip->ecc_strength_ds;
1073 else
1074 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1075
1076 if (chip->ecc.size)
1077 req.ecc.sectorsize = chip->ecc.size;
1078 else if (chip->ecc_step_ds)
1079 req.ecc.sectorsize = chip->ecc_step_ds;
1080 else
1081 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1082
1083 req.pagesize = mtd->writesize;
1084 req.oobsize = mtd->oobsize;
1085
1086 if (mtd->writesize <= 512) {
1087 req.ecc.bytes = 4;
1088 req.ecc.ooboffset = 0;
1089 } else {
1090 req.ecc.bytes = mtd->oobsize - 2;
1091 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1092 }
1093
1094 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1095 if (IS_ERR(nand->pmecc))
1096 return PTR_ERR(nand->pmecc);
1097
1098 chip->ecc.algo = NAND_ECC_BCH;
1099 chip->ecc.size = req.ecc.sectorsize;
1100 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1101 chip->ecc.strength = req.ecc.strength;
1102
1103 chip->options |= NAND_NO_SUBPAGE_WRITE;
1104
1105 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1106
1107 return 0;
1108}
1109
577e010c 1110static int atmel_nand_ecc_init(struct nand_chip *chip)
f88fc122 1111{
f88fc122
BB		 1112 struct atmel_nand_controller *nc;
1113 int ret;
1114
1115 nc = to_nand_controller(chip->controller);
1116
1117 switch (chip->ecc.mode) {
1118 case NAND_ECC_NONE:
1119 case NAND_ECC_SOFT:
1120 /*
1121 * Nothing to do, the core will initialize everything for us.
1122 */
1123 break;
1124
1125 case NAND_ECC_HW:
1126 ret = atmel_nand_pmecc_init(chip);
1127 if (ret)
1128 return ret;
1129
1130 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1131 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1132 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1133 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1134 break;
1135
1136 default:
1137 /* Other modes are not supported. */
1138 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1139 chip->ecc.mode);
1140 return -ENOTSUPP;
1141 }
1142
1143 return 0;
1144}
1145
577e010c 1146static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
f88fc122 1147{
f88fc122
BB		 1148 int ret;
1149
577e010c 1150 ret = atmel_nand_ecc_init(chip);
f88fc122
BB		 1151 if (ret)
1152 return ret;
1153
1154 if (chip->ecc.mode != NAND_ECC_HW)
1155 return 0;
1156
1157 /* Adjust the ECC operations for the HSMC IP. */
1158 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1159 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1160 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1161 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
f88fc122
BB		 1162
1163 return 0;
1164}
1165
f9ce2edd
BB		 1166static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1167 const struct nand_data_interface *conf,
1168 struct atmel_smc_cs_conf *smcconf)
1169{
1170 u32 ncycles, totalcycles, timeps, mckperiodps;
1171 struct atmel_nand_controller *nc;
1172 int ret;
1173
1174 nc = to_nand_controller(nand->base.controller);
1175
1176 /* DDR interface not supported. */
1177 if (conf->type != NAND_SDR_IFACE)
1178 return -ENOTSUPP;
1179
1180 /*
1181 * tRC < 30ns implies EDO mode. This controller does not support this
1182 * mode.
1183 */
ee02f73e 1184 if (conf->timings.sdr.tRC_min < 30000)
f9ce2edd
BB		 1185 return -ENOTSUPP;
1186
1187 atmel_smc_cs_conf_init(smcconf);
1188
1189 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1190 mckperiodps *= 1000;
1191
1192 /*
1193 * Set write pulse timing. This one is easy to extract:
1194 *
1195 * NWE_PULSE = tWP
1196 */
1197 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1198 totalcycles = ncycles;
1199 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1200 ncycles);
1201 if (ret)
1202 return ret;
1203
1204 /*
1205 * The write setup timing depends on the operation done on the NAND.
1206 * All operations goes through the same data bus, but the operation
1207 * type depends on the address we are writing to (ALE/CLE address
1208 * lines).
1209 * Since we have no way to differentiate the different operations at
1210 * the SMC level, we must consider the worst case (the biggest setup
1211 * time among all operation types):
1212 *
1213 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1214 */
1215 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1216 conf->timings.sdr.tALS_min);
1217 timeps = max(timeps, conf->timings.sdr.tDS_min);
1218 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1219 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1220 totalcycles += ncycles;
1221 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1222 ncycles);
1223 if (ret)
1224 return ret;
1225
1226 /*
1227 * As for the write setup timing, the write hold timing depends on the
1228 * operation done on the NAND:
1229 *
1230 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1231 */
1232 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1233 conf->timings.sdr.tALH_min);
1234 timeps = max3(timeps, conf->timings.sdr.tDH_min,
1235 conf->timings.sdr.tWH_min);
1236 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1237 totalcycles += ncycles;
1238
1239 /*
1240 * The write cycle timing is directly matching tWC, but is also
1241 * dependent on the other timings on the setup and hold timings we
1242 * calculated earlier, which gives:
1243 *
1244 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1245 */
1246 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1247 ncycles = max(totalcycles, ncycles);
1248 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1249 ncycles);
1250 if (ret)
1251 return ret;
1252
1253 /*
1254 * We don't want the CS line to be toggled between each byte/word
1255 * transfer to the NAND. The only way to guarantee that is to have the
1256 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1257 *
1258 * NCS_WR_PULSE = NWE_CYCLE
1259 */
1260 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1261 ncycles);
1262 if (ret)
1263 return ret;
1264
1265 /*
1266 * As for the write setup timing, the read hold timing depends on the
1267 * operation done on the NAND:
1268 *
1269 * NRD_HOLD = max(tREH, tRHOH)
1270 */
1271 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1272 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1273 totalcycles = ncycles;
1274
1275 /*
1276 * TDF = tRHZ - NRD_HOLD
1277 */
1278 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1279 ncycles -= totalcycles;
1280
1281 /*
1282 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1283 * we might end up with a config that does not fit in the TDF field.
1284 * Just take the max value in this case and hope that the NAND is more
1285 * tolerant than advertised.
1286 */
1287 if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1288 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1289 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1290 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1291
1292 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1293 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1294
1295 /*
1296 * Read pulse timing directly matches tRP:
1297 *
1298 * NRD_PULSE = tRP
1299 */
1300 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1301 totalcycles += ncycles;
1302 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1303 ncycles);
1304 if (ret)
1305 return ret;
1306
1307 /*
1308 * The write cycle timing is directly matching tWC, but is also
1309 * dependent on the setup and hold timings we calculated earlier,
1310 * which gives:
1311 *
1312 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1313 *
1314 * NRD_SETUP is always 0.
1315 */
1316 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1317 ncycles = max(totalcycles, ncycles);
1318 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1319 ncycles);
1320 if (ret)
1321 return ret;
1322
1323 /*
1324 * We don't want the CS line to be toggled between each byte/word
1325 * transfer from the NAND. The only way to guarantee that is to have
1326 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1327 *
1328 * NCS_RD_PULSE = NRD_CYCLE
1329 */
1330 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1331 ncycles);
1332 if (ret)
1333 return ret;
1334
1335 /* Txxx timings are directly matching tXXX ones. */
1336 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1337 ret = atmel_smc_cs_conf_set_timing(smcconf,
1338 ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1339 ncycles);
1340 if (ret)
1341 return ret;
1342
1343 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1344 ret = atmel_smc_cs_conf_set_timing(smcconf,
1345 ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1346 ncycles);
be3e83e3
BB		 1347 /*
1348 * Version 4 of the ONFI spec mandates that tADL be at least 400
1349 * nanoseconds, but, depending on the master clock rate, 400 ns may not
1350 * fit in the tADL field of the SMC reg. We need to relax the check and
1351 * accept the -ERANGE return code.
1352 *
1353 * Note that previous versions of the ONFI spec had a lower tADL_min
1354 * (100 or 200 ns). It's not clear why this timing constraint got
1355 * increased but it seems most NANDs are fine with values lower than
1356 * 400ns, so we should be safe.
1357 */
1358 if (ret && ret != -ERANGE)
f9ce2edd
BB		 1359 return ret;
1360
1361 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1362 ret = atmel_smc_cs_conf_set_timing(smcconf,
1363 ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1364 ncycles);
1365 if (ret)
1366 return ret;
1367
1368 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1369 ret = atmel_smc_cs_conf_set_timing(smcconf,
1370 ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1371 ncycles);
1372 if (ret)
1373 return ret;
1374
1375 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1376 ret = atmel_smc_cs_conf_set_timing(smcconf,
1377 ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1378 ncycles);
1379 if (ret)
1380 return ret;
1381
1382 /* Attach the CS line to the NFC logic. */
1383 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1384
1385 /* Set the appropriate data bus width. */
1386 if (nand->base.options & NAND_BUSWIDTH_16)
1387 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1388
1389 /* Operate in NRD/NWE READ/WRITEMODE. */
1390 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1391 ATMEL_SMC_MODE_WRITEMODE_NWE;
1392
1393 return 0;
1394}
1395
1396static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1397 int csline,
1398 const struct nand_data_interface *conf)
1399{
1400 struct atmel_nand_controller *nc;
1401 struct atmel_smc_cs_conf smcconf;
1402 struct atmel_nand_cs *cs;
1403 int ret;
1404
1405 nc = to_nand_controller(nand->base.controller);
1406
1407 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1408 if (ret)
1409 return ret;
1410
1411 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1412 return 0;
1413
1414 cs = &nand->cs[csline];
1415 cs->smcconf = smcconf;
1416 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1417
1418 return 0;
1419}
1420
1421static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1422 int csline,
1423 const struct nand_data_interface *conf)
1424{
b0f3ab20 1425 struct atmel_hsmc_nand_controller *nc;
f9ce2edd
BB		 1426 struct atmel_smc_cs_conf smcconf;
1427 struct atmel_nand_cs *cs;
1428 int ret;
1429
b0f3ab20 1430 nc = to_hsmc_nand_controller(nand->base.controller);
f9ce2edd
BB		 1431
1432 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1433 if (ret)
1434 return ret;
1435
1436 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1437 return 0;
1438
1439 cs = &nand->cs[csline];
1440 cs->smcconf = smcconf;
1441
1442 if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1443 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1444
b0f3ab20
LD		 1445 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1446 &cs->smcconf);
f9ce2edd
BB		 1447
1448 return 0;
1449}
1450
858838b8 1451static int atmel_nand_setup_data_interface(struct nand_chip *chip, int csline,
f9ce2edd
BB		 1452 const struct nand_data_interface *conf)
1453{
f9ce2edd
BB		 1454 struct atmel_nand *nand = to_atmel_nand(chip);
1455 struct atmel_nand_controller *nc;
1456
1457 nc = to_nand_controller(nand->base.controller);
1458
1459 if (csline >= nand->numcs ||
1460 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1461 return -EINVAL;
1462
1463 return nc->caps->ops->setup_data_interface(nand, csline, conf);
1464}
1465
f88fc122
BB		 1466static void atmel_nand_init(struct atmel_nand_controller *nc,
1467 struct atmel_nand *nand)
1468{
1469 struct nand_chip *chip = &nand->base;
1470 struct mtd_info *mtd = nand_to_mtd(chip);
1471
1472 mtd->dev.parent = nc->dev;
1473 nand->base.controller = &nc->base;
1474
bf6065c6 1475 chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl;
716bbbab
BB		 1476 chip->legacy.read_byte = atmel_nand_read_byte;
1477 chip->legacy.write_byte = atmel_nand_write_byte;
1478 chip->legacy.read_buf = atmel_nand_read_buf;
1479 chip->legacy.write_buf = atmel_nand_write_buf;
f88fc122
BB		 1480 chip->select_chip = atmel_nand_select_chip;
1481
f9ce2edd
BB		 1482 if (nc->mck && nc->caps->ops->setup_data_interface)
1483 chip->setup_data_interface = atmel_nand_setup_data_interface;
1484
f88fc122 1485 /* Some NANDs require a longer delay than the default one (20us). */
3cece3ab 1486 chip->legacy.chip_delay = 40;
f88fc122
BB		 1487
1488 /*
1489 * Use a bounce buffer when the buffer passed by the MTD user is not
1490 * suitable for DMA.
1491 */
1492 if (nc->dmac)
1493 chip->options |= NAND_USE_BOUNCE_BUFFER;
1494
1495 /* Default to HW ECC if pmecc is available. */
1496 if (nc->pmecc)
1497 chip->ecc.mode = NAND_ECC_HW;
1498}
1499
1500static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1501 struct atmel_nand *nand)
1502{
1503 struct nand_chip *chip = &nand->base;
1504 struct atmel_smc_nand_controller *smc_nc;
1505 int i;
1506
1507 atmel_nand_init(nc, nand);
1508
1509 smc_nc = to_smc_nand_controller(chip->controller);
1510 if (!smc_nc->matrix)
1511 return;
1512
1513 /* Attach the CS to the NAND Flash logic. */
1514 for (i = 0; i < nand->numcs; i++)
1515 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1516 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1517}
1518
1519static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1520 struct atmel_nand *nand)
1521{
1522 struct nand_chip *chip = &nand->base;
1523
1524 atmel_nand_init(nc, nand);
1525
1526 /* Overload some methods for the HSMC controller. */
bf6065c6 1527 chip->legacy.cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
f88fc122
BB		 1528 chip->select_chip = atmel_hsmc_nand_select_chip;
1529}
1530
7928225f 1531static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
f88fc122
BB		 1532{
1533 struct nand_chip *chip = &nand->base;
1534 struct mtd_info *mtd = nand_to_mtd(chip);
1535 int ret;
1536
1537 ret = mtd_device_unregister(mtd);
1538 if (ret)
1539 return ret;
1540
1541 nand_cleanup(chip);
1542 list_del(&nand->node);
1543
1544 return 0;
1545}
1546
f88fc122
BB		 1547static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1548 struct device_node *np,
1549 int reg_cells)
1550{
1551 struct atmel_nand *nand;
1552 struct gpio_desc *gpio;
1553 int numcs, ret, i;
1554
1555 numcs = of_property_count_elems_of_size(np, "reg",
1556 reg_cells * sizeof(u32));
1557 if (numcs < 1) {
1558 dev_err(nc->dev, "Missing or invalid reg property\n");
1559 return ERR_PTR(-EINVAL);
1560 }
1561
2f91eb69 1562 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
f88fc122
BB		 1563 if (!nand) {
1564 dev_err(nc->dev, "Failed to allocate NAND object\n");
1565 return ERR_PTR(-ENOMEM);
1566 }
1567
1568 nand->numcs = numcs;
1569
1570 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1571 &np->fwnode, GPIOD_IN,
1572 "nand-det");
1573 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1574 dev_err(nc->dev,
1575 "Failed to get detect gpio (err = %ld)\n",
1576 PTR_ERR(gpio));
1577 return ERR_CAST(gpio);
1578 }
1579
1580 if (!IS_ERR(gpio))
1581 nand->cdgpio = gpio;
1582
1583 for (i = 0; i < numcs; i++) {
1584 struct resource res;
1585 u32 val;
1586
1587 ret = of_address_to_resource(np, 0, &res);
1588 if (ret) {
1589 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1590 ret);
1591 return ERR_PTR(ret);
1592 }
1593
1594 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1595 &val);
1596 if (ret) {
1597 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1598 ret);
1599 return ERR_PTR(ret);
1600 }
1601
1602 nand->cs[i].id = val;
1603
1604 nand->cs[i].io.dma = res.start;
1605 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1606 if (IS_ERR(nand->cs[i].io.virt))
1607 return ERR_CAST(nand->cs[i].io.virt);
1608
1609 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1610 if (val > ATMEL_NFC_MAX_RB_ID)
1611 return ERR_PTR(-EINVAL);
1612
1613 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1614 nand->cs[i].rb.id = val;
1615 } else {
1616 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1617 "rb", i, &np->fwnode,
1618 GPIOD_IN, "nand-rb");
1619 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1620 dev_err(nc->dev,
1621 "Failed to get R/B gpio (err = %ld)\n",
1622 PTR_ERR(gpio));
1623 return ERR_CAST(gpio);
1624 }
1625
1626 if (!IS_ERR(gpio)) {
1627 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1628 nand->cs[i].rb.gpio = gpio;
1629 }
1630 }
1631
1632 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1633 i, &np->fwnode,
1634 GPIOD_OUT_HIGH,
1635 "nand-cs");
1636 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1637 dev_err(nc->dev,
1638 "Failed to get CS gpio (err = %ld)\n",
1639 PTR_ERR(gpio));
1640 return ERR_CAST(gpio);
1641 }
1642
1643 if (!IS_ERR(gpio))
1644 nand->cs[i].csgpio = gpio;
1645 }
1646
1647 nand_set_flash_node(&nand->base, np);
1648
1649 return nand;
1650}
1651
1652static int
1653atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1654 struct atmel_nand *nand)
1655{
577e010c
MR		 1656 struct nand_chip *chip = &nand->base;
1657 struct mtd_info *mtd = nand_to_mtd(chip);
f88fc122
BB		 1658 int ret;
1659
1660 /* No card inserted, skip this NAND. */
1661 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1662 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1663 return 0;
1664 }
1665
1666 nc->caps->ops->nand_init(nc, nand);
1667
00ad378f 1668 ret = nand_scan(chip, nand->numcs);
7928225f 1669 if (ret) {
577e010c 1670 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
7928225f
MR		 1671 return ret;
1672 }
1673
1674 ret = mtd_device_register(mtd, NULL, 0);
1675 if (ret) {
1676 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1677 nand_cleanup(chip);
1678 return ret;
1679 }
1680
1681 list_add_tail(&nand->node, &nc->chips);
1682
1683 return 0;
f88fc122
BB		 1684}
1685
1686static int
1687atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1688{
1689 struct atmel_nand *nand, *tmp;
1690 int ret;
1691
1692 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
7928225f 1693 ret = atmel_nand_controller_remove_nand(nand);
f88fc122
BB		 1694 if (ret)
1695 return ret;
1696 }
1697
1698 return 0;
1699}
1700
1701static int
1702atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1703{
1704 struct device *dev = nc->dev;
1705 struct platform_device *pdev = to_platform_device(dev);
1706 struct atmel_nand *nand;
1707 struct gpio_desc *gpio;
1708 struct resource *res;
1709
1710 /*
1711 * Legacy bindings only allow connecting a single NAND with a unique CS
1712 * line to the controller.
1713 */
1714 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1715 GFP_KERNEL);
1716 if (!nand)
1717 return -ENOMEM;
1718
1719 nand->numcs = 1;
1720
1721 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1722 nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1723 if (IS_ERR(nand->cs[0].io.virt))
1724 return PTR_ERR(nand->cs[0].io.virt);
1725
1726 nand->cs[0].io.dma = res->start;
1727
1728 /*
1729 * The old driver was hardcoding the CS id to 3 for all sama5
1730 * controllers. Since this id is only meaningful for the sama5
1731 * controller we can safely assign this id to 3 no matter the
1732 * controller.
1733 * If one wants to connect a NAND to a different CS line, he will
1734 * have to use the new bindings.
1735 */
1736 nand->cs[0].id = 3;
1737
1738 /* R/B GPIO. */
1739 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);
1740 if (IS_ERR(gpio)) {
1741 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1742 PTR_ERR(gpio));
1743 return PTR_ERR(gpio);
1744 }
1745
1746 if (gpio) {
1747 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1748 nand->cs[0].rb.gpio = gpio;
1749 }
1750
1751 /* CS GPIO. */
1752 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1753 if (IS_ERR(gpio)) {
1754 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1755 PTR_ERR(gpio));
1756 return PTR_ERR(gpio);
1757 }
1758
1759 nand->cs[0].csgpio = gpio;
1760
1761 /* Card detect GPIO. */
1762 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1763 if (IS_ERR(gpio)) {
1764 dev_err(dev,
1765 "Failed to get detect gpio (err = %ld)\n",
1766 PTR_ERR(gpio));
1767 return PTR_ERR(gpio);
1768 }
1769
1770 nand->cdgpio = gpio;
1771
1772 nand_set_flash_node(&nand->base, nc->dev->of_node);
1773
1774 return atmel_nand_controller_add_nand(nc, nand);
1775}
1776
1777static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1778{
1779 struct device_node *np, *nand_np;
1780 struct device *dev = nc->dev;
1781 int ret, reg_cells;
1782 u32 val;
1783
1784 /* We do not retrieve the SMC syscon when parsing old DTs. */
1785 if (nc->caps->legacy_of_bindings)
1786 return atmel_nand_controller_legacy_add_nands(nc);
1787
1788 np = dev->of_node;
1789
1790 ret = of_property_read_u32(np, "#address-cells", &val);
1791 if (ret) {
1792 dev_err(dev, "missing #address-cells property\n");
1793 return ret;
1794 }
1795
1796 reg_cells = val;
1797
1798 ret = of_property_read_u32(np, "#size-cells", &val);
1799 if (ret) {
1800 dev_err(dev, "missing #address-cells property\n");
1801 return ret;
1802 }
1803
1804 reg_cells += val;
1805
1806 for_each_child_of_node(np, nand_np) {
1807 struct atmel_nand *nand;
1808
1809 nand = atmel_nand_create(nc, nand_np, reg_cells);
1810 if (IS_ERR(nand)) {
1811 ret = PTR_ERR(nand);
1812 goto err;
1813 }
1814
1815 ret = atmel_nand_controller_add_nand(nc, nand);
1816 if (ret)
1817 goto err;
1818 }
1819
1820 return 0;
1821
1822err:
1823 atmel_nand_controller_remove_nands(nc);
1824
1825 return ret;
1826}
1827
1828static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1829{
1830 if (nc->dmac)
1831 dma_release_channel(nc->dmac);
1832
1833 clk_put(nc->mck);
1834}
1835
1836static const struct of_device_id atmel_matrix_of_ids[] = {
1837 {
1838 .compatible = "atmel,at91sam9260-matrix",
1839 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1840 },
1841 {
1842 .compatible = "atmel,at91sam9261-matrix",
1843 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1844 },
1845 {
1846 .compatible = "atmel,at91sam9263-matrix",
1847 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1848 },
1849 {
1850 .compatible = "atmel,at91sam9rl-matrix",
1851 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1852 },
1853 {
1854 .compatible = "atmel,at91sam9g45-matrix",
1855 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1856 },
1857 {
1858 .compatible = "atmel,at91sam9n12-matrix",
1859 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1860 },
1861 {
1862 .compatible = "atmel,at91sam9x5-matrix",
1863 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1864 },
038e8ad6 1865 { /* sentinel */ },
f88fc122
BB		 1866};
1867
577e010c
MR		 1868static int atmel_nand_attach_chip(struct nand_chip *chip)
1869{
1870 struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1871 struct atmel_nand *nand = to_atmel_nand(chip);
1872 struct mtd_info *mtd = nand_to_mtd(chip);
1873 int ret;
1874
1875 ret = nc->caps->ops->ecc_init(chip);
1876 if (ret)
1877 return ret;
1878
1879 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1880 /*
1881 * We keep the MTD name unchanged to avoid breaking platforms
1882 * where the MTD cmdline parser is used and the bootloader
1883 * has not been updated to use the new naming scheme.
1884 */
1885 mtd->name = "atmel_nand";
1886 } else if (!mtd->name) {
1887 /*
1888 * If the new bindings are used and the bootloader has not been
1889 * updated to pass a new mtdparts parameter on the cmdline, you
1890 * should define the following property in your nand node:
1891 *
1892 * label = "atmel_nand";
1893 *
1894 * This way, mtd->name will be set by the core when
1895 * nand_set_flash_node() is called.
1896 */
1897 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1898 "%s:nand.%d", dev_name(nc->dev),
1899 nand->cs[0].id);
1900 if (!mtd->name) {
1901 dev_err(nc->dev, "Failed to allocate mtd->name\n");
1902 return -ENOMEM;
1903 }
1904 }
1905
1906 return 0;
1907}
1908
1909static const struct nand_controller_ops atmel_nand_controller_ops = {
1910 .attach_chip = atmel_nand_attach_chip,
1911};
1912
f88fc122
BB		 1913static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1914 struct platform_device *pdev,
1915 const struct atmel_nand_controller_caps *caps)
1916{
1917 struct device *dev = &pdev->dev;
1918 struct device_node *np = dev->of_node;
1919 int ret;
1920
7da45139 1921 nand_controller_init(&nc->base);
577e010c 1922 nc->base.ops = &atmel_nand_controller_ops;
f88fc122
BB		 1923 INIT_LIST_HEAD(&nc->chips);
1924 nc->dev = dev;
1925 nc->caps = caps;
1926
1927 platform_set_drvdata(pdev, nc);
1928
1929 nc->pmecc = devm_atmel_pmecc_get(dev);
1930 if (IS_ERR(nc->pmecc)) {
1931 ret = PTR_ERR(nc->pmecc);
1932 if (ret != -EPROBE_DEFER)
1933 dev_err(dev, "Could not get PMECC object (err = %d)\n",
1934 ret);
1935 return ret;
1936 }
1937
efc6362c 1938 if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
f88fc122
BB		 1939 dma_cap_mask_t mask;
1940
1941 dma_cap_zero(mask);
1942 dma_cap_set(DMA_MEMCPY, mask);
1943
1944 nc->dmac = dma_request_channel(mask, NULL, NULL);
1945 if (!nc->dmac)
1946 dev_err(nc->dev, "Failed to request DMA channel\n");
1947 }
1948
1949 /* We do not retrieve the SMC syscon when parsing old DTs. */
1950 if (nc->caps->legacy_of_bindings)
1951 return 0;
1952
f9ce2edd
BB		 1953 nc->mck = of_clk_get(dev->parent->of_node, 0);
1954 if (IS_ERR(nc->mck)) {
1955 dev_err(dev, "Failed to retrieve MCK clk\n");
1956 return PTR_ERR(nc->mck);
1957 }
1958
f88fc122
BB		 1959 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1960 if (!np) {
1961 dev_err(dev, "Missing or invalid atmel,smc property\n");
1962 return -EINVAL;
1963 }
1964
1965 nc->smc = syscon_node_to_regmap(np);
1966 of_node_put(np);
1967 if (IS_ERR(nc->smc)) {
70106dda 1968 ret = PTR_ERR(nc->smc);
f88fc122
BB		 1969 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1970 return ret;
1971 }
1972
1973 return 0;
1974}
1975
1976static int
1977atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1978{
1979 struct device *dev = nc->base.dev;
1980 const struct of_device_id *match;
1981 struct device_node *np;
1982 int ret;
1983
1984 /* We do not retrieve the matrix syscon when parsing old DTs. */
1985 if (nc->base.caps->legacy_of_bindings)
1986 return 0;
1987
1988 np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
1989 if (!np)
1990 return 0;
1991
1992 match = of_match_node(atmel_matrix_of_ids, np);
1993 if (!match) {
1994 of_node_put(np);
1995 return 0;
1996 }
1997
1998 nc->matrix = syscon_node_to_regmap(np);
1999 of_node_put(np);
2000 if (IS_ERR(nc->matrix)) {
70106dda 2001 ret = PTR_ERR(nc->matrix);
f88fc122
BB		 2002 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2003 return ret;
2004 }
2005
e6848511 2006 nc->ebi_csa_offs = (uintptr_t)match->data;
f88fc122
BB		 2007
2008 /*
2009 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2010 * add 4 to ->ebi_csa_offs.
2011 */
2012 if (of_device_is_compatible(dev->parent->of_node,
2013 "atmel,at91sam9263-ebi1"))
2014 nc->ebi_csa_offs += 4;
2015
2016 return 0;
2017}
2018
2019static int
2020atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2021{
2022 struct regmap_config regmap_conf = {
2023 .reg_bits = 32,
2024 .val_bits = 32,
2025 .reg_stride = 4,
2026 };
2027
2028 struct device *dev = nc->base.dev;
2029 struct device_node *nand_np, *nfc_np;
2030 void __iomem *iomem;
2031 struct resource res;
2032 int ret;
2033
2034 nand_np = dev->of_node;
5d1e9c22 2035 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
fbed2028
GS		 2036 if (!nfc_np) {
2037 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2038 return -ENODEV;
2039 }
f88fc122
BB		 2040
2041 nc->clk = of_clk_get(nfc_np, 0);
2042 if (IS_ERR(nc->clk)) {
2043 ret = PTR_ERR(nc->clk);
2044 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2045 ret);
2046 goto out;
2047 }
2048
2049 ret = clk_prepare_enable(nc->clk);
2050 if (ret) {
2051 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2052 ret);
2053 goto out;
2054 }
2055
2056 nc->irq = of_irq_get(nand_np, 0);
892dd183
SS		 2057 if (nc->irq <= 0) {
2058 ret = nc->irq ?: -ENXIO;
f88fc122
BB		 2059 if (ret != -EPROBE_DEFER)
2060 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2061 ret);
2062 goto out;
2063 }
2064
2065 ret = of_address_to_resource(nfc_np, 0, &res);
2066 if (ret) {
2067 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2068 ret);
2069 goto out;
2070 }
2071
2072 iomem = devm_ioremap_resource(dev, &res);
2073 if (IS_ERR(iomem)) {
2074 ret = PTR_ERR(iomem);
2075 goto out;
2076 }
2077
2078 regmap_conf.name = "nfc-io";
2079 regmap_conf.max_register = resource_size(&res) - 4;
2080 nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2081 if (IS_ERR(nc->io)) {
2082 ret = PTR_ERR(nc->io);
2083 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2084 ret);
2085 goto out;
2086 }
2087
2088 ret = of_address_to_resource(nfc_np, 1, &res);
2089 if (ret) {
2090 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2091 ret);
2092 goto out;
2093 }
2094
2095 iomem = devm_ioremap_resource(dev, &res);
2096 if (IS_ERR(iomem)) {
2097 ret = PTR_ERR(iomem);
2098 goto out;
2099 }
2100
2101 regmap_conf.name = "smc";
2102 regmap_conf.max_register = resource_size(&res) - 4;
2103 nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2104 if (IS_ERR(nc->base.smc)) {
2105 ret = PTR_ERR(nc->base.smc);
2106 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2107 ret);
2108 goto out;
2109 }
2110
2111 ret = of_address_to_resource(nfc_np, 2, &res);
2112 if (ret) {
2113 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2114 ret);
2115 goto out;
2116 }
2117
2118 nc->sram.virt = devm_ioremap_resource(dev, &res);
2119 if (IS_ERR(nc->sram.virt)) {
2120 ret = PTR_ERR(nc->sram.virt);
2121 goto out;
2122 }
2123
2124 nc->sram.dma = res.start;
2125
2126out:
2127 of_node_put(nfc_np);
2128
2129 return ret;
2130}
2131
2132static int
2133atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2134{
2135 struct device *dev = nc->base.dev;
2136 struct device_node *np;
2137 int ret;
2138
2139 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2140 if (!np) {
2141 dev_err(dev, "Missing or invalid atmel,smc property\n");
2142 return -EINVAL;
2143 }
2144
b0f3ab20
LD		 2145 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2146
f88fc122
BB		 2147 nc->irq = of_irq_get(np, 0);
2148 of_node_put(np);
892dd183
SS		 2149 if (nc->irq <= 0) {
2150 ret = nc->irq ?: -ENXIO;
2151 if (ret != -EPROBE_DEFER)
f88fc122 2152 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
892dd183
SS		 2153 ret);
2154 return ret;
f88fc122
BB		 2155 }
2156
2157 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2158 if (!np) {
2159 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2160 return -EINVAL;
2161 }
2162
2163 nc->io = syscon_node_to_regmap(np);
2164 of_node_put(np);
2165 if (IS_ERR(nc->io)) {
2166 ret = PTR_ERR(nc->io);
2167 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2168 return ret;
2169 }
2170
2171 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2172 "atmel,nfc-sram", 0);
2173 if (!nc->sram.pool) {
2174 dev_err(nc->base.dev, "Missing SRAM\n");
2175 return -ENOMEM;
2176 }
2177
d28395c9
BB		 2178 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2179 ATMEL_NFC_SRAM_SIZE,
2180 &nc->sram.dma);
f88fc122
BB		 2181 if (!nc->sram.virt) {
2182 dev_err(nc->base.dev,
2183 "Could not allocate memory from the NFC SRAM pool\n");
2184 return -ENOMEM;
2185 }
2186
2187 return 0;
2188}
2189
2190static int
2191atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2192{
2193 struct atmel_hsmc_nand_controller *hsmc_nc;
2194 int ret;
2195
2196 ret = atmel_nand_controller_remove_nands(nc);
2197 if (ret)
2198 return ret;
2199
2200 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2201 if (hsmc_nc->sram.pool)
2202 gen_pool_free(hsmc_nc->sram.pool,
2203 (unsigned long)hsmc_nc->sram.virt,
2204 ATMEL_NFC_SRAM_SIZE);
2205
2206 if (hsmc_nc->clk) {
2207 clk_disable_unprepare(hsmc_nc->clk);
2208 clk_put(hsmc_nc->clk);
2209 }
2210
2211 atmel_nand_controller_cleanup(nc);
2212
2213 return 0;
2214}
2215
2216static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2217 const struct atmel_nand_controller_caps *caps)
2218{
2219 struct device *dev = &pdev->dev;
2220 struct atmel_hsmc_nand_controller *nc;
2221 int ret;
2222
2223 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2224 if (!nc)
2225 return -ENOMEM;
2226
2227 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2228 if (ret)
2229 return ret;
2230
2231 if (caps->legacy_of_bindings)
2232 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2233 else
2234 ret = atmel_hsmc_nand_controller_init(nc);
2235
2236 if (ret)
2237 return ret;
2238
2239 /* Make sure all irqs are masked before registering our IRQ handler. */
2240 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2241 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2242 IRQF_SHARED, "nfc", nc);
2243 if (ret) {
2244 dev_err(dev,
2245 "Could not get register NFC interrupt handler (err = %d)\n",
2246 ret);
2247 goto err;
2248 }
2249
2250 /* Initial NFC configuration. */
2251 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2252 ATMEL_HSMC_NFC_CFG_DTO_MAX);
2253
2254 ret = atmel_nand_controller_add_nands(&nc->base);
2255 if (ret)
2256 goto err;
2257
2258 return 0;
2259
2260err:
2261 atmel_hsmc_nand_controller_remove(&nc->base);
2262
2263 return ret;
2264}
2265
2266static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2267 .probe = atmel_hsmc_nand_controller_probe,
2268 .remove = atmel_hsmc_nand_controller_remove,
2269 .ecc_init = atmel_hsmc_nand_ecc_init,
2270 .nand_init = atmel_hsmc_nand_init,
f9ce2edd 2271 .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
f88fc122
BB		 2272};
2273
2274static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2275 .has_dma = true,
2276 .ale_offs = BIT(21),
2277 .cle_offs = BIT(22),
2278 .ops = &atmel_hsmc_nc_ops,
2279};
2280
2281/* Only used to parse old bindings. */
2282static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2283 .has_dma = true,
2284 .ale_offs = BIT(21),
2285 .cle_offs = BIT(22),
2286 .ops = &atmel_hsmc_nc_ops,
2287 .legacy_of_bindings = true,
2288};
2289
2290static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2291 const struct atmel_nand_controller_caps *caps)
2292{
2293 struct device *dev = &pdev->dev;
2294 struct atmel_smc_nand_controller *nc;
2295 int ret;
2296
2297 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2298 if (!nc)
2299 return -ENOMEM;
2300
2301 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2302 if (ret)
2303 return ret;
2304
2305 ret = atmel_smc_nand_controller_init(nc);
2306 if (ret)
2307 return ret;
2308
2309 return atmel_nand_controller_add_nands(&nc->base);
2310}
2311
2312static int
2313atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2314{
2315 int ret;
2316
2317 ret = atmel_nand_controller_remove_nands(nc);
2318 if (ret)
2319 return ret;
2320
2321 atmel_nand_controller_cleanup(nc);
2322
2323 return 0;
2324}
2325
f9ce2edd
BB		 2326/*
2327 * The SMC reg layout of at91rm9200 is completely different which prevents us
2328 * from re-using atmel_smc_nand_setup_data_interface() for the
2329 * ->setup_data_interface() hook.
2330 * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2331 * ->setup_data_interface() unassigned.
2332 */
2333static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
f88fc122
BB		 2334 .probe = atmel_smc_nand_controller_probe,
2335 .remove = atmel_smc_nand_controller_remove,
2336 .ecc_init = atmel_nand_ecc_init,
2337 .nand_init = atmel_smc_nand_init,
2338};
2339
2340static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
f9ce2edd
BB		 2341 .ale_offs = BIT(21),
2342 .cle_offs = BIT(22),
2343 .ops = &at91rm9200_nc_ops,
2344};
2345
2346static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2347 .probe = atmel_smc_nand_controller_probe,
2348 .remove = atmel_smc_nand_controller_remove,
2349 .ecc_init = atmel_nand_ecc_init,
2350 .nand_init = atmel_smc_nand_init,
2351 .setup_data_interface = atmel_smc_nand_setup_data_interface,
2352};
2353
2354static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
f88fc122
BB		 2355 .ale_offs = BIT(21),
2356 .cle_offs = BIT(22),
2357 .ops = &atmel_smc_nc_ops,
2358};
2359
2360static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2361 .ale_offs = BIT(22),
2362 .cle_offs = BIT(21),
2363 .ops = &atmel_smc_nc_ops,
2364};
2365
2366static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2367 .has_dma = true,
2368 .ale_offs = BIT(21),
2369 .cle_offs = BIT(22),
2370 .ops = &atmel_smc_nc_ops,
2371};
2372
2373/* Only used to parse old bindings. */
2374static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2375 .ale_offs = BIT(21),
2376 .cle_offs = BIT(22),
2377 .ops = &atmel_smc_nc_ops,
2378 .legacy_of_bindings = true,
2379};
2380
2381static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2382 .ale_offs = BIT(22),
2383 .cle_offs = BIT(21),
2384 .ops = &atmel_smc_nc_ops,
2385 .legacy_of_bindings = true,
2386};
2387
2388static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2389 .has_dma = true,
2390 .ale_offs = BIT(21),
2391 .cle_offs = BIT(22),
2392 .ops = &atmel_smc_nc_ops,
2393 .legacy_of_bindings = true,
2394};
2395
2396static const struct of_device_id atmel_nand_controller_of_ids[] = {
2397 {
2398 .compatible = "atmel,at91rm9200-nand-controller",
2399 .data = &atmel_rm9200_nc_caps,
2400 },
2401 {
2402 .compatible = "atmel,at91sam9260-nand-controller",
f9ce2edd 2403 .data = &atmel_sam9260_nc_caps,
f88fc122
BB		 2404 },
2405 {
2406 .compatible = "atmel,at91sam9261-nand-controller",
2407 .data = &atmel_sam9261_nc_caps,
2408 },
2409 {
2410 .compatible = "atmel,at91sam9g45-nand-controller",
2411 .data = &atmel_sam9g45_nc_caps,
2412 },
2413 {
2414 .compatible = "atmel,sama5d3-nand-controller",
2415 .data = &atmel_sama5_nc_caps,
2416 },
2417 /* Support for old/deprecated bindings: */
2418 {
2419 .compatible = "atmel,at91rm9200-nand",
2420 .data = &atmel_rm9200_nand_caps,
2421 },
2422 {
2423 .compatible = "atmel,sama5d4-nand",
2424 .data = &atmel_rm9200_nand_caps,
2425 },
2426 {
2427 .compatible = "atmel,sama5d2-nand",
2428 .data = &atmel_rm9200_nand_caps,
2429 },
2430 { /* sentinel */ },
2431};
2432MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2433
2434static int atmel_nand_controller_probe(struct platform_device *pdev)
2435{
2436 const struct atmel_nand_controller_caps *caps;
2437
2438 if (pdev->id_entry)
2439 caps = (void *)pdev->id_entry->driver_data;
2440 else
2441 caps = of_device_get_match_data(&pdev->dev);
2442
2443 if (!caps) {
2444 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2445 return -EINVAL;
2446 }
2447
2448 if (caps->legacy_of_bindings) {
5d1e9c22 2449 struct device_node *nfc_node;
f88fc122
BB		 2450 u32 ale_offs = 21;
2451
2452 /*
2453 * If we are parsing legacy DT props and the DT contains a
2454 * valid NFC node, forward the request to the sama5 logic.
2455 */
5d1e9c22
JH		 2456 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2457 "atmel,sama5d3-nfc");
2458 if (nfc_node) {
f88fc122 2459 caps = &atmel_sama5_nand_caps;
5d1e9c22
JH		 2460 of_node_put(nfc_node);
2461 }
f88fc122
BB		 2462
2463 /*
2464 * Even if the compatible says we are dealing with an
2465 * at91rm9200 controller, the atmel,nand-has-dma specify that
2466 * this controller supports DMA, which means we are in fact
2467 * dealing with an at91sam9g45+ controller.
2468 */
2469 if (!caps->has_dma &&
2470 of_property_read_bool(pdev->dev.of_node,
2471 "atmel,nand-has-dma"))
2472 caps = &atmel_sam9g45_nand_caps;
2473
2474 /*
2475 * All SoCs except the at91sam9261 are assigning ALE to A21 and
2476 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2477 * actually dealing with an at91sam9261 controller.
2478 */
2479 of_property_read_u32(pdev->dev.of_node,
2480 "atmel,nand-addr-offset", &ale_offs);
2481 if (ale_offs != 21)
2482 caps = &atmel_sam9261_nand_caps;
2483 }
2484
2485 return caps->ops->probe(pdev, caps);
2486}
2487
2488static int atmel_nand_controller_remove(struct platform_device *pdev)
2489{
2490 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2491
2492 return nc->caps->ops->remove(nc);
2493}
2494
05b6c231 2495static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
6e532afa
BB		 2496{
2497 struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2498 struct atmel_nand *nand;
2499
143b0ab9
RI		 2500 if (nc->pmecc)
2501 atmel_pmecc_reset(nc->pmecc);
2502
6e532afa
BB		 2503 list_for_each_entry(nand, &nc->chips, node) {
2504 int i;
2505
2506 for (i = 0; i < nand->numcs; i++)
2507 nand_reset(&nand->base, i);
2508 }
2509
2510 return 0;
2511}
2512
2513static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2514 atmel_nand_controller_resume);
2515
f88fc122
BB		 2516static struct platform_driver atmel_nand_controller_driver = {
2517 .driver = {
2518 .name = "atmel-nand-controller",
2519 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
1533bfa6 2520 .pm = &atmel_nand_controller_pm_ops,
f88fc122
BB		 2521 },
2522 .probe = atmel_nand_controller_probe,
2523 .remove = atmel_nand_controller_remove,
2524};
2525module_platform_driver(atmel_nand_controller_driver);
2526
2527MODULE_LICENSE("GPL");
2528MODULE_AUTHOR("Boris Brezillon <[email protected]>");
2529MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2530MODULE_ALIAS("platform:atmel-nand-controller");
Empty description
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