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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
5305ec6a 15#include <linux/bitfield.h>
a72016a4 16#include <linux/string.h>
b8c86fc5
PO		 17#include <linux/delay.h>
18#include <linux/highmem.h>
88b47679 19#include <linux/module.h>
b8c86fc5
PO		 20#include <linux/pci.h>
21#include <linux/dma-mapping.h>
5a0e3ad6 22#include <linux/slab.h>
ccc92c23 23#include <linux/device.h>
b8c86fc5 24#include <linux/mmc/host.h>
e1bfad6d 25#include <linux/mmc/mmc.h>
b177bc91
AP		 26#include <linux/scatterlist.h>
27#include <linux/io.h>
0f201655 28#include <linux/gpio.h>
66fd8ad5 29#include <linux/pm_runtime.h>
ff59c520 30#include <linux/mmc/slot-gpio.h>
52c506f0 31#include <linux/mmc/sdhci-pci-data.h>
3f23df72 32#include <linux/acpi.h>
b8c86fc5 33
8ee82bda
AH		 34#include "cqhci.h"
35
b8c86fc5 36#include "sdhci.h"
522624f9 37#include "sdhci-pci.h"
22606405 38
fee686b7 39static void sdhci_pci_hw_reset(struct sdhci_host *host);
fee686b7 40
30cf2803 41#ifdef CONFIG_PM_SLEEP
5c3c6126
AH		 42static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
43{
44 mmc_pm_flag_t pm_flags = 0;
d56ee1ff 45 bool cap_cd_wake = false;
5c3c6126
AH		 46 int i;
47
48 for (i = 0; i < chip->num_slots; i++) {
49 struct sdhci_pci_slot *slot = chip->slots[i];
50
d56ee1ff 51 if (slot) {
5c3c6126 52 pm_flags |= slot->host->mmc->pm_flags;
d56ee1ff
AH		 53 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
54 cap_cd_wake = true;
55 }
5c3c6126
AH		 56 }
57
d56ee1ff
AH		 58 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
59 return device_wakeup_enable(&chip->pdev->dev);
60 else if (!cap_cd_wake)
61 return device_wakeup_disable(&chip->pdev->dev);
62
63 return 0;
5c3c6126
AH		 64}
65
66static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
30cf2803
AH		 67{
68 int i, ret;
69
5c3c6126
AH		 70 sdhci_pci_init_wakeup(chip);
71
30cf2803
AH		 72 for (i = 0; i < chip->num_slots; i++) {
73 struct sdhci_pci_slot *slot = chip->slots[i];
74 struct sdhci_host *host;
75
76 if (!slot)
77 continue;
78
79 host = slot->host;
80
81 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
82 mmc_retune_needed(host->mmc);
83
84 ret = sdhci_suspend_host(host);
85 if (ret)
86 goto err_pci_suspend;
d56ee1ff
AH		 87
88 if (device_may_wakeup(&chip->pdev->dev))
89 mmc_gpio_set_cd_wake(host->mmc, true);
30cf2803
AH		 90 }
91
92 return 0;
93
94err_pci_suspend:
95 while (--i >= 0)
96 sdhci_resume_host(chip->slots[i]->host);
97 return ret;
98}
99
30cf2803
AH		 100int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
101{
102 struct sdhci_pci_slot *slot;
103 int i, ret;
104
105 for (i = 0; i < chip->num_slots; i++) {
106 slot = chip->slots[i];
107 if (!slot)
108 continue;
109
110 ret = sdhci_resume_host(slot->host);
111 if (ret)
112 return ret;
d56ee1ff
AH		 113
114 mmc_gpio_set_cd_wake(slot->host->mmc, false);
30cf2803
AH		 115 }
116
117 return 0;
118}
8ee82bda
AH		 119
120static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
121{
122 int ret;
123
124 ret = cqhci_suspend(chip->slots[0]->host->mmc);
125 if (ret)
126 return ret;
127
128 return sdhci_pci_suspend_host(chip);
129}
130
131static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
132{
133 int ret;
134
135 ret = sdhci_pci_resume_host(chip);
136 if (ret)
137 return ret;
138
139 return cqhci_resume(chip->slots[0]->host->mmc);
140}
30cf2803
AH		 141#endif
142
966d696a
AH		 143#ifdef CONFIG_PM
144static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
145{
146 struct sdhci_pci_slot *slot;
147 struct sdhci_host *host;
148 int i, ret;
149
150 for (i = 0; i < chip->num_slots; i++) {
151 slot = chip->slots[i];
152 if (!slot)
153 continue;
154
155 host = slot->host;
156
157 ret = sdhci_runtime_suspend_host(host);
158 if (ret)
159 goto err_pci_runtime_suspend;
160
161 if (chip->rpm_retune &&
162 host->tuning_mode != SDHCI_TUNING_MODE_3)
163 mmc_retune_needed(host->mmc);
164 }
165
166 return 0;
167
168err_pci_runtime_suspend:
169 while (--i >= 0)
170 sdhci_runtime_resume_host(chip->slots[i]->host);
171 return ret;
172}
173
174static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
175{
176 struct sdhci_pci_slot *slot;
177 int i, ret;
178
179 for (i = 0; i < chip->num_slots; i++) {
180 slot = chip->slots[i];
181 if (!slot)
182 continue;
183
184 ret = sdhci_runtime_resume_host(slot->host);
185 if (ret)
186 return ret;
187 }
188
189 return 0;
190}
8ee82bda
AH		 191
192static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
193{
194 int ret;
195
196 ret = cqhci_suspend(chip->slots[0]->host->mmc);
197 if (ret)
198 return ret;
199
200 return sdhci_pci_runtime_suspend_host(chip);
201}
202
203static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
204{
205 int ret;
206
207 ret = sdhci_pci_runtime_resume_host(chip);
208 if (ret)
209 return ret;
210
211 return cqhci_resume(chip->slots[0]->host->mmc);
212}
966d696a
AH		 213#endif
214
8ee82bda
AH		 215static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
216{
217 int cmd_error = 0;
218 int data_error = 0;
219
220 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
221 return intmask;
222
223 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
224
225 return 0;
226}
227
228static void sdhci_pci_dumpregs(struct mmc_host *mmc)
229{
230 sdhci_dumpregs(mmc_priv(mmc));
231}
232
22606405
PO		 233/*****************************************************************************\
234 * *
235 * Hardware specific quirk handling *
236 * *
237\*****************************************************************************/
238
239static int ricoh_probe(struct sdhci_pci_chip *chip)
240{
c99436fb
CB		 241 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
242 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 243 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 244 return 0;
245}
246
247static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
248{
249 slot->host->caps =
250 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
251 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 252
ccc92c23
ML		 253 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
254 & SDHCI_CLOCK_BASE_MASK) |
255
256 SDHCI_TIMEOUT_CLK_UNIT |
257 SDHCI_CAN_VDD_330 |
1a1f1f04 258 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 259 SDHCI_CAN_DO_SDMA;
260 return 0;
261}
262
b7813f0f 263#ifdef CONFIG_PM_SLEEP
ccc92c23
ML		 264static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
265{
266 /* Apply a delay to allow controller to settle */
267 /* Otherwise it becomes confused if card state changed
268 during suspend */
269 msleep(500);
30cf2803 270 return sdhci_pci_resume_host(chip);
22606405 271}
b7813f0f 272#endif
22606405
PO		 273
274static const struct sdhci_pci_fixes sdhci_ricoh = {
275 .probe = ricoh_probe,
84938294
VK		 276 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
277 SDHCI_QUIRK_FORCE_DMA |
278 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 279};
280
ccc92c23
ML		 281static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
282 .probe_slot = ricoh_mmc_probe_slot,
b7813f0f 283#ifdef CONFIG_PM_SLEEP
ccc92c23 284 .resume = ricoh_mmc_resume,
b7813f0f 285#endif
ccc92c23
ML		 286 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
287 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
288 SDHCI_QUIRK_NO_CARD_NO_RESET |
289 SDHCI_QUIRK_MISSING_CAPS
290};
291
22606405
PO		 292static const struct sdhci_pci_fixes sdhci_ene_712 = {
293 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
294 SDHCI_QUIRK_BROKEN_DMA,
295};
296
297static const struct sdhci_pci_fixes sdhci_ene_714 = {
298 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
299 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
300 SDHCI_QUIRK_BROKEN_DMA,
301};
302
303static const struct sdhci_pci_fixes sdhci_cafe = {
304 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 305 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 306 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 307 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 308};
309
43e968ce
DB		 310static const struct sdhci_pci_fixes sdhci_intel_qrk = {
311 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
312};
313
68077b02
ML		 314static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
315{
316 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
317 return 0;
318}
319
f9ee3eab
AC		 320/*
321 * ADMA operation is disabled for Moorestown platform due to
322 * hardware bugs.
323 */
35ac6f08 324static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 325{
326 /*
35ac6f08
JP		 327 * slots number is fixed here for MRST as SDIO3/5 are never used and
328 * have hardware bugs.
f9ee3eab
AC		 329 */
330 chip->num_slots = 1;
331 return 0;
332}
333
296e0b03
AS		 334static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
335{
336 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
337 return 0;
338}
339
162d6f98 340#ifdef CONFIG_PM
66fd8ad5 341
c5e027a4 342static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 343{
344 struct sdhci_pci_slot *slot = dev_id;
345 struct sdhci_host *host = slot->host;
346
347 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
348 return IRQ_HANDLED;
349}
350
c5e027a4 351static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 352{
c5e027a4 353 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 354
355 slot->cd_gpio = -EINVAL;
356 slot->cd_irq = -EINVAL;
357
c5e027a4
AH		 358 if (!gpio_is_valid(gpio))
359 return;
360
c10bc372 361 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
66fd8ad5
AH		 362 if (err < 0)
363 goto out;
364
365 err = gpio_direction_input(gpio);
366 if (err < 0)
367 goto out_free;
368
369 irq = gpio_to_irq(gpio);
370 if (irq < 0)
371 goto out_free;
372
c5e027a4 373 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 374 IRQF_TRIGGER_FALLING, "sd_cd", slot);
375 if (err)
376 goto out_free;
377
378 slot->cd_gpio = gpio;
379 slot->cd_irq = irq;
66fd8ad5 380
c5e027a4 381 return;
66fd8ad5
AH		 382
383out_free:
c10bc372 384 devm_gpio_free(&slot->chip->pdev->dev, gpio);
66fd8ad5
AH		 385out:
386 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 387}
388
c5e027a4 389static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 390{
391 if (slot->cd_irq >= 0)
392 free_irq(slot->cd_irq, slot);
66fd8ad5
AH		 393}
394
395#else
396
c5e027a4
AH		 397static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
398{
399}
400
401static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
402{
403}
66fd8ad5
AH		 404
405#endif
406
0d013bcf
AH		 407static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
408{
66fd8ad5 409 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
d2a47176 410 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
0d013bcf
AH		 411 return 0;
412}
413
93933508
AH		 414static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
415{
012e4671 416 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 417 return 0;
418}
419
f9ee3eab
AC		 420static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
421 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 422 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 423};
424
35ac6f08 425static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 426 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 427 .probe = mrst_hc_probe,
f9ee3eab
AC		 428};
429
29229052
XS		 430static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 432 .allow_runtime_pm = true,
77a0122e 433 .own_cd_for_runtime_pm = true,
29229052
XS		 434};
435
0d013bcf
AH		 436static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 438 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 439 .allow_runtime_pm = true,
93933508 440 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 441};
442
443static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 445 .allow_runtime_pm = true,
0d013bcf 446 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 447};
448
296e0b03
AS		 449static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
450 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
451 .probe_slot = pch_hc_probe_slot,
452};
453
c959a6b0
AH		 454enum {
455 INTEL_DSM_FNS = 0,
6ae03368 456 INTEL_DSM_V18_SWITCH = 3,
be17355a 457 INTEL_DSM_V33_SWITCH = 4,
51ced59c 458 INTEL_DSM_DRV_STRENGTH = 9,
c959a6b0
AH		 459 INTEL_DSM_D3_RETUNE = 10,
460};
461
462struct intel_host {
463 u32 dsm_fns;
51ced59c 464 int drv_strength;
c959a6b0 465 bool d3_retune;
5305ec6a
AH		 466 bool rpm_retune_ok;
467 u32 glk_rx_ctrl1;
468 u32 glk_tun_val;
c959a6b0
AH		 469};
470
c37f69ff 471static const guid_t intel_dsm_guid =
94116f81
AS		 472 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
473 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
c959a6b0
AH		 474
475static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
476 unsigned int fn, u32 *result)
477{
478 union acpi_object *obj;
479 int err = 0;
a72016a4 480 size_t len;
c959a6b0 481
94116f81 482 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
c959a6b0
AH		 483 if (!obj)
484 return -EOPNOTSUPP;
485
486 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
487 err = -EINVAL;
488 goto out;
489 }
490
a72016a4
AH		 491 len = min_t(size_t, obj->buffer.length, 4);
492
493 *result = 0;
494 memcpy(result, obj->buffer.pointer, len);
c959a6b0
AH		 495out:
496 ACPI_FREE(obj);
497
498 return err;
499}
500
501static int intel_dsm(struct intel_host *intel_host, struct device *dev,
502 unsigned int fn, u32 *result)
503{
504 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
505 return -EOPNOTSUPP;
506
507 return __intel_dsm(intel_host, dev, fn, result);
508}
509
510static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
511 struct mmc_host *mmc)
512{
513 int err;
514 u32 val;
515
eb701ce1
AH		 516 intel_host->d3_retune = true;
517
c959a6b0
AH		 518 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
519 if (err) {
520 pr_debug("%s: DSM not supported, error %d\n",
521 mmc_hostname(mmc), err);
522 return;
523 }
524
525 pr_debug("%s: DSM function mask %#x\n",
526 mmc_hostname(mmc), intel_host->dsm_fns);
527
51ced59c
AH		 528 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
529 intel_host->drv_strength = err ? 0 : val;
530
c959a6b0
AH		 531 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
532 intel_host->d3_retune = err ? true : !!val;
533}
534
c9faff6c
AH		 535static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
536{
537 u8 reg;
538
539 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
540 reg |= 0x10;
541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
542 /* For eMMC, minimum is 1us but give it 9us for good measure */
543 udelay(9);
544 reg &= ~0x10;
545 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
546 /* For eMMC, minimum is 200us but give it 300us for good measure */
547 usleep_range(300, 1000);
548}
549
51ced59c
AH		 550static int intel_select_drive_strength(struct mmc_card *card,
551 unsigned int max_dtr, int host_drv,
552 int card_drv, int *drv_type)
e1bfad6d 553{
51ced59c
AH		 554 struct sdhci_host *host = mmc_priv(card->host);
555 struct sdhci_pci_slot *slot = sdhci_priv(host);
556 struct intel_host *intel_host = sdhci_pci_priv(slot);
e1bfad6d 557
51ced59c 558 return intel_host->drv_strength;
e1bfad6d
AH		 559}
560
163cbe31
AH		 561static int bxt_get_cd(struct mmc_host *mmc)
562{
563 int gpio_cd = mmc_gpio_get_cd(mmc);
564 struct sdhci_host *host = mmc_priv(mmc);
565 unsigned long flags;
566 int ret = 0;
567
568 if (!gpio_cd)
569 return 0;
570
163cbe31
AH		 571 spin_lock_irqsave(&host->lock, flags);
572
573 if (host->flags & SDHCI_DEVICE_DEAD)
574 goto out;
575
576 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
577out:
578 spin_unlock_irqrestore(&host->lock, flags);
579
163cbe31
AH		 580 return ret;
581}
582
48d685a2
AH		 583#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
584#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
585
586static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
587 unsigned short vdd)
588{
589 int cntr;
590 u8 reg;
591
592 sdhci_set_power(host, mode, vdd);
593
594 if (mode == MMC_POWER_OFF)
595 return;
596
597 /*
598 * Bus power might not enable after D3 -> D0 transition due to the
599 * present state not yet having propagated. Retry for up to 2ms.
600 */
601 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
602 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
603 if (reg & SDHCI_POWER_ON)
604 break;
605 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
606 reg |= SDHCI_POWER_ON;
607 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
608 }
609}
610
bc55dcd8
AH		 611#define INTEL_HS400_ES_REG 0x78
612#define INTEL_HS400_ES_BIT BIT(0)
613
614static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
615 struct mmc_ios *ios)
616{
617 struct sdhci_host *host = mmc_priv(mmc);
618 u32 val;
619
620 val = sdhci_readl(host, INTEL_HS400_ES_REG);
621 if (ios->enhanced_strobe)
622 val |= INTEL_HS400_ES_BIT;
623 else
624 val &= ~INTEL_HS400_ES_BIT;
625 sdhci_writel(host, val, INTEL_HS400_ES_REG);
626}
627
be17355a
AH		 628static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
629 struct mmc_ios *ios)
6ae03368 630{
be17355a
AH		 631 struct device *dev = mmc_dev(mmc);
632 struct sdhci_host *host = mmc_priv(mmc);
6ae03368
AH		 633 struct sdhci_pci_slot *slot = sdhci_priv(host);
634 struct intel_host *intel_host = sdhci_pci_priv(slot);
be17355a 635 unsigned int fn;
6ae03368
AH		 636 u32 result = 0;
637 int err;
638
be17355a
AH		 639 err = sdhci_start_signal_voltage_switch(mmc, ios);
640 if (err)
641 return err;
642
643 switch (ios->signal_voltage) {
644 case MMC_SIGNAL_VOLTAGE_330:
645 fn = INTEL_DSM_V33_SWITCH;
646 break;
647 case MMC_SIGNAL_VOLTAGE_180:
648 fn = INTEL_DSM_V18_SWITCH;
649 break;
650 default:
651 return 0;
652 }
653
654 err = intel_dsm(intel_host, dev, fn, &result);
655 pr_debug("%s: %s DSM fn %u error %d result %u\n",
656 mmc_hostname(mmc), __func__, fn, err, result);
657
658 return 0;
6ae03368
AH		 659}
660
48d685a2
AH		 661static const struct sdhci_ops sdhci_intel_byt_ops = {
662 .set_clock = sdhci_set_clock,
663 .set_power = sdhci_intel_set_power,
664 .enable_dma = sdhci_pci_enable_dma,
adc16398 665 .set_bus_width = sdhci_set_bus_width,
48d685a2
AH		 666 .reset = sdhci_reset,
667 .set_uhs_signaling = sdhci_set_uhs_signaling,
668 .hw_reset = sdhci_pci_hw_reset,
669};
670
8ee82bda
AH		 671static const struct sdhci_ops sdhci_intel_glk_ops = {
672 .set_clock = sdhci_set_clock,
673 .set_power = sdhci_intel_set_power,
674 .enable_dma = sdhci_pci_enable_dma,
675 .set_bus_width = sdhci_set_bus_width,
676 .reset = sdhci_reset,
677 .set_uhs_signaling = sdhci_set_uhs_signaling,
678 .hw_reset = sdhci_pci_hw_reset,
8ee82bda
AH		 679 .irq = sdhci_cqhci_irq,
680};
681
c959a6b0
AH		 682static void byt_read_dsm(struct sdhci_pci_slot *slot)
683{
684 struct intel_host *intel_host = sdhci_pci_priv(slot);
685 struct device *dev = &slot->chip->pdev->dev;
686 struct mmc_host *mmc = slot->host->mmc;
687
688 intel_dsm_init(intel_host, dev, mmc);
689 slot->chip->rpm_retune = intel_host->d3_retune;
690}
691
f8870ae6
AH		 692static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
693{
694 int err = sdhci_execute_tuning(mmc, opcode);
695 struct sdhci_host *host = mmc_priv(mmc);
696
697 if (err)
698 return err;
699
700 /*
701 * Tuning can leave the IP in an active state (Buffer Read Enable bit
702 * set) which prevents the entry to low power states (i.e. S0i3). Data
703 * reset will clear it.
704 */
705 sdhci_reset(host, SDHCI_RESET_DATA);
706
707 return 0;
708}
709
710static void byt_probe_slot(struct sdhci_pci_slot *slot)
728ef3d1 711{
f8870ae6
AH		 712 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
713
c959a6b0 714 byt_read_dsm(slot);
f8870ae6
AH		 715
716 ops->execute_tuning = intel_execute_tuning;
be17355a 717 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
f8870ae6
AH		 718}
719
720static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
721{
722 byt_probe_slot(slot);
c9faff6c 723 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8 724 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
32828857 725 MMC_CAP_CMD_DURING_TFR |
6aab23a8 726 MMC_CAP_WAIT_WHILE_BUSY;
c9faff6c 727 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 728 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
729 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
51ced59c
AH		 730 slot->host->mmc_host_ops.select_drive_strength =
731 intel_select_drive_strength;
728ef3d1
AH		 732 return 0;
733}
734
bc55dcd8
AH		 735static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
736{
737 int ret = byt_emmc_probe_slot(slot);
738
8ee82bda
AH		 739 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
740
bc55dcd8
AH		 741 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
742 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
743 slot->host->mmc_host_ops.hs400_enhanced_strobe =
744 intel_hs400_enhanced_strobe;
8ee82bda 745 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
bc55dcd8
AH		 746 }
747
748 return ret;
749}
750
8ee82bda 751static const struct cqhci_host_ops glk_cqhci_ops = {
7b7d57fd 752 .enable = sdhci_cqe_enable,
8ee82bda
AH		 753 .disable = sdhci_cqe_disable,
754 .dumpregs = sdhci_pci_dumpregs,
755};
756
757static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
758{
759 struct device *dev = &slot->chip->pdev->dev;
760 struct sdhci_host *host = slot->host;
761 struct cqhci_host *cq_host;
762 bool dma64;
763 int ret;
764
765 ret = sdhci_setup_host(host);
766 if (ret)
767 return ret;
768
769 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
770 if (!cq_host) {
771 ret = -ENOMEM;
772 goto cleanup;
773 }
774
775 cq_host->mmio = host->ioaddr + 0x200;
776 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
777 cq_host->ops = &glk_cqhci_ops;
778
779 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
780 if (dma64)
781 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
782
783 ret = cqhci_init(cq_host, host->mmc, dma64);
784 if (ret)
785 goto cleanup;
786
787 ret = __sdhci_add_host(host);
788 if (ret)
789 goto cleanup;
790
791 return 0;
792
793cleanup:
794 sdhci_cleanup_host(host);
795 return ret;
796}
797
5305ec6a
AH		 798#ifdef CONFIG_PM
799#define GLK_RX_CTRL1 0x834
800#define GLK_TUN_VAL 0x840
801#define GLK_PATH_PLL GENMASK(13, 8)
802#define GLK_DLY GENMASK(6, 0)
803/* Workaround firmware failing to restore the tuning value */
804static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
805{
806 struct sdhci_pci_slot *slot = chip->slots[0];
807 struct intel_host *intel_host = sdhci_pci_priv(slot);
808 struct sdhci_host *host = slot->host;
809 u32 glk_rx_ctrl1;
810 u32 glk_tun_val;
811 u32 dly;
812
813 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
814 return;
815
816 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
817 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
818
819 if (susp) {
820 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
821 intel_host->glk_tun_val = glk_tun_val;
822 return;
823 }
824
825 if (!intel_host->glk_tun_val)
826 return;
827
828 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
829 intel_host->rpm_retune_ok = true;
830 return;
831 }
832
833 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
834 (intel_host->glk_tun_val << 1));
835 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
836 return;
837
838 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
839 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
840
841 intel_host->rpm_retune_ok = true;
842 chip->rpm_retune = true;
843 mmc_retune_needed(host->mmc);
844 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
845}
846
847static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
848{
849 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
850 !chip->rpm_retune)
851 glk_rpm_retune_wa(chip, susp);
852}
853
854static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
855{
856 glk_rpm_retune_chk(chip, true);
857
858 return sdhci_cqhci_runtime_suspend(chip);
859}
860
861static int glk_runtime_resume(struct sdhci_pci_chip *chip)
862{
863 glk_rpm_retune_chk(chip, false);
864
865 return sdhci_cqhci_runtime_resume(chip);
866}
867#endif
868
3f23df72
ZB		 869#ifdef CONFIG_ACPI
870static int ni_set_max_freq(struct sdhci_pci_slot *slot)
871{
872 acpi_status status;
873 unsigned long long max_freq;
874
875 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
876 "MXFQ", NULL, &max_freq);
877 if (ACPI_FAILURE(status)) {
878 dev_err(&slot->chip->pdev->dev,
879 "MXFQ not found in acpi table\n");
880 return -EINVAL;
881 }
882
883 slot->host->mmc->f_max = max_freq * 1000000;
884
885 return 0;
886}
887#else
888static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
889{
890 return 0;
891}
892#endif
893
42b06496
ZB		 894static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
895{
3f23df72
ZB		 896 int err;
897
f8870ae6 898 byt_probe_slot(slot);
c959a6b0 899
3f23df72
ZB		 900 err = ni_set_max_freq(slot);
901 if (err)
902 return err;
903
42b06496
ZB		 904 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
905 MMC_CAP_WAIT_WHILE_BUSY;
906 return 0;
907}
908
728ef3d1
AH		 909static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
910{
f8870ae6 911 byt_probe_slot(slot);
6aab23a8 912 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
6aab23a8 913 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 914 return 0;
915}
916
ff59c520
AH		 917static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
918{
f8870ae6 919 byt_probe_slot(slot);
c2c49a2e 920 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
6cf4156c 921 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
ff59c520
AH		 922 slot->cd_idx = 0;
923 slot->cd_override_level = true;
163cbe31 924 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
01d6b2a4 925 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
2d1956d0 926 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
c2c49a2e 927 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
163cbe31
AH		 928 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
929
bb26b841
KR		 930 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
931 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
932 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
933
ff59c520
AH		 934 return 0;
935}
936
728ef3d1
AH		 937static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
938 .allow_runtime_pm = true,
939 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 940 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 941 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 942 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 943 SDHCI_QUIRK2_STOP_WITH_TC,
fee686b7 944 .ops = &sdhci_intel_byt_ops,
c959a6b0 945 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 946};
947
bc55dcd8
AH		 948static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
949 .allow_runtime_pm = true,
950 .probe_slot = glk_emmc_probe_slot,
8ee82bda
AH		 951 .add_host = glk_emmc_add_host,
952#ifdef CONFIG_PM_SLEEP
953 .suspend = sdhci_cqhci_suspend,
954 .resume = sdhci_cqhci_resume,
955#endif
956#ifdef CONFIG_PM
5305ec6a
AH		 957 .runtime_suspend = glk_runtime_suspend,
958 .runtime_resume = glk_runtime_resume,
8ee82bda 959#endif
bc55dcd8
AH		 960 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
961 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
962 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
963 SDHCI_QUIRK2_STOP_WITH_TC,
8ee82bda 964 .ops = &sdhci_intel_glk_ops,
bc55dcd8
AH		 965 .priv_size = sizeof(struct intel_host),
966};
967
42b06496
ZB		 968static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
969 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
970 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
971 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
972 .allow_runtime_pm = true,
973 .probe_slot = ni_byt_sdio_probe_slot,
974 .ops = &sdhci_intel_byt_ops,
c959a6b0 975 .priv_size = sizeof(struct intel_host),
42b06496
ZB		 976};
977
728ef3d1 978static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 979 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 980 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
981 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 982 .allow_runtime_pm = true,
983 .probe_slot = byt_sdio_probe_slot,
fee686b7 984 .ops = &sdhci_intel_byt_ops,
c959a6b0 985 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 986};
987
988static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 989 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 990 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 991 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
992 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 993 .allow_runtime_pm = true,
77a0122e 994 .own_cd_for_runtime_pm = true,
ff59c520 995 .probe_slot = byt_sd_probe_slot,
fee686b7 996 .ops = &sdhci_intel_byt_ops,
c959a6b0 997 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 998};
999
8776a165 1000/* Define Host controllers for Intel Merrifield platform */
1f64cec2
AS		 1001#define INTEL_MRFLD_EMMC_0 0
1002#define INTEL_MRFLD_EMMC_1 1
4674b6c8 1003#define INTEL_MRFLD_SD 2
d5565577 1004#define INTEL_MRFLD_SDIO 3
8776a165 1005
0e39220e
AS		 1006#ifdef CONFIG_ACPI
1007static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1008{
1009 struct acpi_device *device, *child;
1010
1011 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1012 if (!device)
1013 return;
1014
1015 acpi_device_fix_up_power(device);
1016 list_for_each_entry(child, &device->children, node)
1017 if (child->status.present && child->status.enabled)
1018 acpi_device_fix_up_power(child);
1019}
1020#else
1021static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1022#endif
1023
1f64cec2 1024static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
8776a165 1025{
2e57bbe2
AS		 1026 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1027
1028 switch (func) {
1029 case INTEL_MRFLD_EMMC_0:
1030 case INTEL_MRFLD_EMMC_1:
1031 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1032 MMC_CAP_8_BIT_DATA |
1033 MMC_CAP_1_8V_DDR;
1034 break;
4674b6c8
AS		 1035 case INTEL_MRFLD_SD:
1036 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1037 break;
d5565577 1038 case INTEL_MRFLD_SDIO:
2a609abe
AS		 1039 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1040 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
d5565577
AS		 1041 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1042 MMC_CAP_POWER_OFF_CARD;
1043 break;
2e57bbe2 1044 default:
8776a165 1045 return -ENODEV;
2e57bbe2 1046 }
0e39220e
AS		 1047
1048 intel_mrfld_mmc_fix_up_power_slot(slot);
8776a165
DC		 1049 return 0;
1050}
1051
1f64cec2 1052static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
8776a165 1053 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 1054 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1055 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 1056 .allow_runtime_pm = true,
1f64cec2 1057 .probe_slot = intel_mrfld_mmc_probe_slot,
8776a165
DC		 1058};
1059
45211e21
PO		 1060static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1061{
1062 u8 scratch;
1063 int ret;
1064
1065 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1066 if (ret)
1067 return ret;
1068
1069 /*
1070 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1071 * [bit 1:2] and enable over current debouncing [bit 6].
1072 */
1073 if (on)
1074 scratch |= 0x47;
1075 else
1076 scratch &= ~0x47;
1077
7582041f 1078 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 1079}
1080
1081static int jmicron_probe(struct sdhci_pci_chip *chip)
1082{
1083 int ret;
8f230f45 1084 u16 mmcdev = 0;
45211e21 1085
93fc48c7
PO		 1086 if (chip->pdev->revision == 0) {
1087 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1088 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 1089 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 1090 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 1091 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 1092 }
1093
4489428a
PO		 1094 /*
1095 * JMicron chips can have two interfaces to the same hardware
1096 * in order to work around limitations in Microsoft's driver.
1097 * We need to make sure we only bind to one of them.
1098 *
1099 * This code assumes two things:
1100 *
1101 * 1. The PCI code adds subfunctions in order.
1102 *
1103 * 2. The MMC interface has a lower subfunction number
1104 * than the SD interface.
1105 */
8f230f45
TI		 1106 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1107 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1108 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1109 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1110
1111 if (mmcdev) {
4489428a
PO		 1112 struct pci_dev *sd_dev;
1113
1114 sd_dev = NULL;
1115 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 1116 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 1117 if ((PCI_SLOT(chip->pdev->devfn) ==
1118 PCI_SLOT(sd_dev->devfn)) &&
1119 (chip->pdev->bus == sd_dev->bus))
1120 break;
1121 }
1122
1123 if (sd_dev) {
1124 pci_dev_put(sd_dev);
1125 dev_info(&chip->pdev->dev, "Refusing to bind to "
1126 "secondary interface.\n");
1127 return -ENODEV;
1128 }
1129 }
1130
45211e21
PO		 1131 /*
1132 * JMicron chips need a bit of a nudge to enable the power
1133 * output pins.
1134 */
1135 ret = jmicron_pmos(chip, 1);
1136 if (ret) {
1137 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1138 return ret;
1139 }
1140
82b0e23a
TI		 1141 /* quirk for unsable RO-detection on JM388 chips */
1142 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1143 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1144 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1145
45211e21
PO		 1146 return 0;
1147}
1148
4489428a
PO		 1149static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1150{
1151 u8 scratch;
1152
1153 scratch = readb(host->ioaddr + 0xC0);
1154
1155 if (on)
1156 scratch |= 0x01;
1157 else
1158 scratch &= ~0x01;
1159
1160 writeb(scratch, host->ioaddr + 0xC0);
1161}
1162
1163static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1164{
2134a922
PO		 1165 if (slot->chip->pdev->revision == 0) {
1166 u16 version;
1167
1168 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1169 version = (version & SDHCI_VENDOR_VER_MASK) >>
1170 SDHCI_VENDOR_VER_SHIFT;
1171
1172 /*
1173 * Older versions of the chip have lots of nasty glitches
1174 * in the ADMA engine. It's best just to avoid it
1175 * completely.
1176 */
1177 if (version < 0xAC)
1178 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1179 }
1180
8f230f45
TI		 1181 /* JM388 MMC doesn't support 1.8V while SD supports it */
1182 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1183 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1184 MMC_VDD_29_30 | MMC_VDD_30_31 |
1185 MMC_VDD_165_195; /* allow 1.8V */
1186 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1187 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1188 }
1189
4489428a
PO		 1190 /*
1191 * The secondary interface requires a bit set to get the
1192 * interrupts.
1193 */
8f230f45
TI		 1194 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1195 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1196 jmicron_enable_mmc(slot->host, 1);
1197
d75c1084
TI		 1198 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1199
4489428a
PO		 1200 return 0;
1201}
1202
1e72859e 1203static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 1204{
1e72859e
PO		 1205 if (dead)
1206 return;
1207
8f230f45
TI		 1208 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1209 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1210 jmicron_enable_mmc(slot->host, 0);
1211}
1212
b7813f0f 1213#ifdef CONFIG_PM_SLEEP
29495aa0 1214static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a 1215{
30cf2803
AH		 1216 int i, ret;
1217
5c3c6126 1218 ret = sdhci_pci_suspend_host(chip);
30cf2803
AH		 1219 if (ret)
1220 return ret;
4489428a 1221
8f230f45
TI		 1222 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1223 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1224 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1225 jmicron_enable_mmc(chip->slots[i]->host, 0);
1226 }
1227
1228 return 0;
1229}
1230
45211e21
PO		 1231static int jmicron_resume(struct sdhci_pci_chip *chip)
1232{
4489428a
PO		 1233 int ret, i;
1234
8f230f45
TI		 1235 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1236 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1237 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1238 jmicron_enable_mmc(chip->slots[i]->host, 1);
1239 }
45211e21
PO		 1240
1241 ret = jmicron_pmos(chip, 1);
1242 if (ret) {
1243 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1244 return ret;
1245 }
1246
30cf2803 1247 return sdhci_pci_resume_host(chip);
45211e21 1248}
b7813f0f 1249#endif
45211e21 1250
26daa1ed 1251static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 1252 .probe = sdhci_pci_o2_probe,
1253 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
143b648d 1254 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
01acf691 1255 .probe_slot = sdhci_pci_o2_probe_slot,
b7813f0f 1256#ifdef CONFIG_PM_SLEEP
01acf691 1257 .resume = sdhci_pci_o2_resume,
b7813f0f 1258#endif
26daa1ed
JL		 1259};
1260
22606405 1261static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 1262 .probe = jmicron_probe,
1263
4489428a
PO		 1264 .probe_slot = jmicron_probe_slot,
1265 .remove_slot = jmicron_remove_slot,
1266
b7813f0f 1267#ifdef CONFIG_PM_SLEEP
4489428a 1268 .suspend = jmicron_suspend,
45211e21 1269 .resume = jmicron_resume,
b7813f0f 1270#endif
22606405
PO		 1271};
1272
a7a6186c
NP		 1273/* SysKonnect CardBus2SDIO extra registers */
1274#define SYSKT_CTRL 0x200
1275#define SYSKT_RDFIFO_STAT 0x204
1276#define SYSKT_WRFIFO_STAT 0x208
1277#define SYSKT_POWER_DATA 0x20c
1278#define SYSKT_POWER_330 0xef
1279#define SYSKT_POWER_300 0xf8
1280#define SYSKT_POWER_184 0xcc
1281#define SYSKT_POWER_CMD 0x20d
1282#define SYSKT_POWER_START (1 << 7)
1283#define SYSKT_POWER_STATUS 0x20e
1284#define SYSKT_POWER_STATUS_OK (1 << 0)
1285#define SYSKT_BOARD_REV 0x210
1286#define SYSKT_CHIP_REV 0x211
1287#define SYSKT_CONF_DATA 0x212
1288#define SYSKT_CONF_DATA_1V8 (1 << 2)
1289#define SYSKT_CONF_DATA_2V5 (1 << 1)
1290#define SYSKT_CONF_DATA_3V3 (1 << 0)
1291
1292static int syskt_probe(struct sdhci_pci_chip *chip)
1293{
1294 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1295 chip->pdev->class &= ~0x0000FF;
1296 chip->pdev->class |= PCI_SDHCI_IFDMA;
1297 }
1298 return 0;
1299}
1300
1301static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1302{
1303 int tm, ps;
1304
1305 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1306 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1307 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1308 "board rev %d.%d, chip rev %d.%d\n",
1309 board_rev >> 4, board_rev & 0xf,
1310 chip_rev >> 4, chip_rev & 0xf);
1311 if (chip_rev >= 0x20)
1312 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1313
1314 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1315 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1316 udelay(50);
1317 tm = 10; /* Wait max 1 ms */
1318 do {
1319 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1320 if (ps & SYSKT_POWER_STATUS_OK)
1321 break;
1322 udelay(100);
1323 } while (--tm);
1324 if (!tm) {
1325 dev_err(&slot->chip->pdev->dev,
1326 "power regulator never stabilized");
1327 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1328 return -ENODEV;
1329 }
1330
1331 return 0;
1332}
1333
1334static const struct sdhci_pci_fixes sdhci_syskt = {
1335 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1336 .probe = syskt_probe,
1337 .probe_slot = syskt_probe_slot,
1338};
1339
557b0697
HW		 1340static int via_probe(struct sdhci_pci_chip *chip)
1341{
1342 if (chip->pdev->revision == 0x10)
1343 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1344
1345 return 0;
1346}
1347
1348static const struct sdhci_pci_fixes sdhci_via = {
1349 .probe = via_probe,
1350};
1351
9107ebbf
MC		 1352static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1353{
1354 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1355 return 0;
1356}
1357
1358static const struct sdhci_pci_fixes sdhci_rtsx = {
1359 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 1360 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 1361 SDHCI_QUIRK2_BROKEN_DDR50,
1362 .probe_slot = rtsx_probe_slot,
1363};
1364
b5e97d6e
VW		 1365/*AMD chipset generation*/
1366enum amd_chipset_gen {
1367 AMD_CHIPSET_BEFORE_ML,
1368 AMD_CHIPSET_CZ,
1369 AMD_CHIPSET_NL,
1370 AMD_CHIPSET_UNKNOWN,
1371};
1372
c31165d7
SS		 1373/* AMD registers */
1374#define AMD_SD_AUTO_PATTERN 0xB8
1375#define AMD_MSLEEP_DURATION 4
1376#define AMD_SD_MISC_CONTROL 0xD0
1377#define AMD_MAX_TUNE_VALUE 0x0B
1378#define AMD_AUTO_TUNE_SEL 0x10800
1379#define AMD_FIFO_PTR 0x30
1380#define AMD_BIT_MASK 0x1F
1381
1382static void amd_tuning_reset(struct sdhci_host *host)
1383{
1384 unsigned int val;
1385
1386 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1387 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1388 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1389
1390 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1391 val &= ~SDHCI_CTRL_EXEC_TUNING;
1392 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1393}
1394
1395static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1396{
1397 unsigned int val;
1398
1399 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1400 val &= ~AMD_BIT_MASK;
1401 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1402 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1403}
1404
1405static void amd_enable_manual_tuning(struct pci_dev *pdev)
1406{
1407 unsigned int val;
1408
1409 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1410 val |= AMD_FIFO_PTR;
1411 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1412}
1413
300ad899 1414static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
c31165d7
SS		 1415{
1416 struct sdhci_pci_slot *slot = sdhci_priv(host);
1417 struct pci_dev *pdev = slot->chip->pdev;
1418 u8 valid_win = 0;
1419 u8 valid_win_max = 0;
1420 u8 valid_win_end = 0;
1421 u8 ctrl, tune_around;
1422
1423 amd_tuning_reset(host);
1424
1425 for (tune_around = 0; tune_around < 12; tune_around++) {
1426 amd_config_tuning_phase(pdev, tune_around);
1427
1428 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1429 valid_win = 0;
1430 msleep(AMD_MSLEEP_DURATION);
1431 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1432 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1433 } else if (++valid_win > valid_win_max) {
1434 valid_win_max = valid_win;
1435 valid_win_end = tune_around;
1436 }
1437 }
1438
1439 if (!valid_win_max) {
1440 dev_err(&pdev->dev, "no tuning point found\n");
1441 return -EIO;
1442 }
1443
1444 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1445
1446 amd_enable_manual_tuning(pdev);
1447
1448 host->mmc->retune_period = 0;
1449
1450 return 0;
1451}
1452
300ad899
DK		 1453static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1454{
1455 struct sdhci_host *host = mmc_priv(mmc);
1456
1457 /* AMD requires custom HS200 tuning */
1458 if (host->timing == MMC_TIMING_MMC_HS200)
1459 return amd_execute_tuning_hs200(host, opcode);
1460
1461 /* Otherwise perform standard SDHCI tuning */
1462 return sdhci_execute_tuning(mmc, opcode);
1463}
1464
1465static int amd_probe_slot(struct sdhci_pci_slot *slot)
1466{
1467 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1468
1469 ops->execute_tuning = amd_execute_tuning;
1470
1471 return 0;
1472}
1473
d44f88da
VW		 1474static int amd_probe(struct sdhci_pci_chip *chip)
1475{
1476 struct pci_dev *smbus_dev;
b5e97d6e 1477 enum amd_chipset_gen gen;
d44f88da
VW		 1478
1479 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1480 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 1481 if (smbus_dev) {
1482 gen = AMD_CHIPSET_BEFORE_ML;
1483 } else {
1484 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1485 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1486 if (smbus_dev) {
1487 if (smbus_dev->revision < 0x51)
1488 gen = AMD_CHIPSET_CZ;
1489 else
1490 gen = AMD_CHIPSET_NL;
1491 } else {
1492 gen = AMD_CHIPSET_UNKNOWN;
1493 }
1494 }
d44f88da 1495
c31165d7 1496 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
d44f88da
VW		 1497 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1498
1499 return 0;
1500}
1501
c31165d7
SS		 1502static const struct sdhci_ops amd_sdhci_pci_ops = {
1503 .set_clock = sdhci_set_clock,
1504 .enable_dma = sdhci_pci_enable_dma,
adc16398 1505 .set_bus_width = sdhci_set_bus_width,
c31165d7
SS		 1506 .reset = sdhci_reset,
1507 .set_uhs_signaling = sdhci_set_uhs_signaling,
c31165d7
SS		 1508};
1509
d44f88da
VW		 1510static const struct sdhci_pci_fixes sdhci_amd = {
1511 .probe = amd_probe,
c31165d7 1512 .ops = &amd_sdhci_pci_ops,
300ad899 1513 .probe_slot = amd_probe_slot,
d44f88da
VW		 1514};
1515
9647f84d 1516static const struct pci_device_id pci_ids[] = {
c949c907
MK		 1517 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1518 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1519 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1520 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1521 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1522 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1523 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1524 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1525 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1526 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1527 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1528 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1529 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1530 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1531 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1532 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1533 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1534 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1535 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1536 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1537 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1538 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1539 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1540 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1541 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1542 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1543 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1544 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1545 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1546 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1547 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1548 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1549 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1550 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1551 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1552 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1553 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1554 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1555 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1556 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1557 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1558 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1559 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1560 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1561 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
cdaba732 1562 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
c949c907
MK		 1563 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1564 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1565 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1566 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1567 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1568 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1569 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1570 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1571 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
bc55dcd8 1572 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
c949c907
MK		 1573 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1574 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
bc55dcd8
AH		 1575 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1576 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1577 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
5637ffad
AH		 1578 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1579 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
c949c907
MK		 1580 SDHCI_PCI_DEVICE(O2, 8120, o2),
1581 SDHCI_PCI_DEVICE(O2, 8220, o2),
1582 SDHCI_PCI_DEVICE(O2, 8221, o2),
1583 SDHCI_PCI_DEVICE(O2, 8320, o2),
1584 SDHCI_PCI_DEVICE(O2, 8321, o2),
1585 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1586 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1587 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1588 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1589 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
d72d72cd 1590 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
152f8204 1591 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
c949c907
MK		 1592 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1593 /* Generic SD host controller */
1594 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
b8c86fc5
PO		 1595 { /* end: all zeroes */ },
1596};
1597
1598MODULE_DEVICE_TABLE(pci, pci_ids);
1599
b8c86fc5
PO		 1600/*****************************************************************************\
1601 * *
1602 * SDHCI core callbacks *
1603 * *
1604\*****************************************************************************/
1605
d72d72cd 1606int sdhci_pci_enable_dma(struct sdhci_host *host)
b8c86fc5
PO		 1607{
1608 struct sdhci_pci_slot *slot;
1609 struct pci_dev *pdev;
b8c86fc5
PO		 1610
1611 slot = sdhci_priv(host);
1612 pdev = slot->chip->pdev;
1613
1614 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1615 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1616 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1617 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1618 "doesn't fully claim to support it.\n");
1619 }
1620
b8c86fc5
PO		 1621 pci_set_master(pdev);
1622
1623 return 0;
1624}
1625
c9faff6c 1626static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1627{
1628 struct sdhci_pci_slot *slot = sdhci_priv(host);
1629 int rst_n_gpio = slot->rst_n_gpio;
1630
1631 if (!gpio_is_valid(rst_n_gpio))
1632 return;
1633 gpio_set_value_cansleep(rst_n_gpio, 0);
1634 /* For eMMC, minimum is 1us but give it 10us for good measure */
1635 udelay(10);
1636 gpio_set_value_cansleep(rst_n_gpio, 1);
1637 /* For eMMC, minimum is 200us but give it 300us for good measure */
1638 usleep_range(300, 1000);
1639}
1640
c9faff6c
AH		 1641static void sdhci_pci_hw_reset(struct sdhci_host *host)
1642{
1643 struct sdhci_pci_slot *slot = sdhci_priv(host);
1644
1645 if (slot->hw_reset)
1646 slot->hw_reset(host);
1647}
1648
c915568d 1649static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1650 .set_clock = sdhci_set_clock,
b8c86fc5 1651 .enable_dma = sdhci_pci_enable_dma,
adc16398 1652 .set_bus_width = sdhci_set_bus_width,
03231f9b 1653 .reset = sdhci_reset,
96d7b78c 1654 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1655 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1656};
1657
1658/*****************************************************************************\
1659 * *
1660 * Suspend/resume *
1661 * *
1662\*****************************************************************************/
1663
f9900f15 1664#ifdef CONFIG_PM_SLEEP
29495aa0 1665static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1666{
29495aa0 1667 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1668 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1669
b8c86fc5
PO		 1670 if (!chip)
1671 return 0;
1672
30cf2803
AH		 1673 if (chip->fixes && chip->fixes->suspend)
1674 return chip->fixes->suspend(chip);
b8c86fc5 1675
30cf2803 1676 return sdhci_pci_suspend_host(chip);
b8c86fc5
PO		 1677}
1678
29495aa0 1679static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1680{
29495aa0 1681 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1682 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1683
b8c86fc5
PO		 1684 if (!chip)
1685 return 0;
1686
30cf2803
AH		 1687 if (chip->fixes && chip->fixes->resume)
1688 return chip->fixes->resume(chip);
b8c86fc5 1689
30cf2803 1690 return sdhci_pci_resume_host(chip);
b8c86fc5 1691}
f9900f15 1692#endif
b8c86fc5 1693
f9900f15 1694#ifdef CONFIG_PM
66fd8ad5
AH		 1695static int sdhci_pci_runtime_suspend(struct device *dev)
1696{
923a231c 1697 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1698 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1699
66fd8ad5
AH		 1700 if (!chip)
1701 return 0;
1702
966d696a
AH		 1703 if (chip->fixes && chip->fixes->runtime_suspend)
1704 return chip->fixes->runtime_suspend(chip);
66fd8ad5 1705
966d696a 1706 return sdhci_pci_runtime_suspend_host(chip);
66fd8ad5
AH		 1707}
1708
1709static int sdhci_pci_runtime_resume(struct device *dev)
1710{
923a231c 1711 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1712 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1713
66fd8ad5
AH		 1714 if (!chip)
1715 return 0;
1716
966d696a
AH		 1717 if (chip->fixes && chip->fixes->runtime_resume)
1718 return chip->fixes->runtime_resume(chip);
66fd8ad5 1719
966d696a 1720 return sdhci_pci_runtime_resume_host(chip);
66fd8ad5 1721}
f9900f15 1722#endif
66fd8ad5
AH		 1723
1724static const struct dev_pm_ops sdhci_pci_pm_ops = {
f9900f15 1725 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
f3a92b1a 1726 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1727 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1728};
1729
b8c86fc5
PO		 1730/*****************************************************************************\
1731 * *
1732 * Device probing/removal *
1733 * *
1734\*****************************************************************************/
1735
c3be1efd 1736static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1737 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1738 int slotno)
b8c86fc5
PO		 1739{
1740 struct sdhci_pci_slot *slot;
1741 struct sdhci_host *host;
52c506f0 1742 int ret, bar = first_bar + slotno;
ac9f67b5 1743 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
b8c86fc5
PO		 1744
1745 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1746 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1747 return ERR_PTR(-ENODEV);
1748 }
1749
90b3e6c5 1750 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1751 dev_err(&pdev->dev, "Invalid iomem size. You may "
1752 "experience problems.\n");
1753 }
1754
1755 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1756 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1757 return ERR_PTR(-ENODEV);
1758 }
1759
1760 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1761 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1762 return ERR_PTR(-ENODEV);
1763 }
1764
ac9f67b5 1765 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
b8c86fc5 1766 if (IS_ERR(host)) {
c60a32cd 1767 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1768 return ERR_CAST(host);
b8c86fc5
PO		 1769 }
1770
1771 slot = sdhci_priv(host);
1772
1773 slot->chip = chip;
1774 slot->host = host;
0f201655 1775 slot->rst_n_gpio = -EINVAL;
c5e027a4 1776 slot->cd_gpio = -EINVAL;
ff59c520 1777 slot->cd_idx = -1;
b8c86fc5 1778
52c506f0
AH		 1779 /* Retrieve platform data if there is any */
1780 if (*sdhci_pci_get_data)
1781 slot->data = sdhci_pci_get_data(pdev, slotno);
1782
1783 if (slot->data) {
1784 if (slot->data->setup) {
1785 ret = slot->data->setup(slot->data);
1786 if (ret) {
1787 dev_err(&pdev->dev, "platform setup failed\n");
1788 goto free;
1789 }
1790 }
c5e027a4
AH		 1791 slot->rst_n_gpio = slot->data->rst_n_gpio;
1792 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1793 }
1794
b8c86fc5 1795 host->hw_name = "PCI";
6bc09063
AH		 1796 host->ops = chip->fixes && chip->fixes->ops ?
1797 chip->fixes->ops :
1798 &sdhci_pci_ops;
b8c86fc5 1799 host->quirks = chip->quirks;
f3c55a7b 1800 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1801
1802 host->irq = pdev->irq;
1803
c10bc372 1804 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
b8c86fc5
PO		 1805 if (ret) {
1806 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1807 goto cleanup;
b8c86fc5
PO		 1808 }
1809
c10bc372 1810 host->ioaddr = pcim_iomap_table(pdev)[bar];
b8c86fc5 1811
4489428a
PO		 1812 if (chip->fixes && chip->fixes->probe_slot) {
1813 ret = chip->fixes->probe_slot(slot);
1814 if (ret)
c10bc372 1815 goto cleanup;
4489428a
PO		 1816 }
1817
c5e027a4 1818 if (gpio_is_valid(slot->rst_n_gpio)) {
c10bc372 1819 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
c5e027a4
AH		 1820 gpio_direction_output(slot->rst_n_gpio, 1);
1821 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1822 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1823 } else {
1824 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1825 slot->rst_n_gpio = -EINVAL;
1826 }
1827 }
1828
e92cc35d 1829 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
eed222ac 1830 host->mmc->slotno = slotno;
a08b17be 1831 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1832
e92cc35d
AH		 1833 if (device_can_wakeup(&pdev->dev))
1834 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1835
d56ee1ff
AH		 1836 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1837 device_init_wakeup(&pdev->dev, true);
1838
8f743d03 1839 if (slot->cd_idx >= 0) {
cdcefe6b 1840 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
8f743d03 1841 slot->cd_override_level, 0, NULL);
cdcefe6b
RJ		 1842 if (ret && ret != -EPROBE_DEFER)
1843 ret = mmc_gpiod_request_cd(host->mmc, NULL,
1844 slot->cd_idx,
1845 slot->cd_override_level,
1846 0, NULL);
8f743d03
DB		 1847 if (ret == -EPROBE_DEFER)
1848 goto remove;
1849
1850 if (ret) {
1851 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1852 slot->cd_idx = -1;
1853 }
ff59c520
AH		 1854 }
1855
61c951de
AH		 1856 if (chip->fixes && chip->fixes->add_host)
1857 ret = chip->fixes->add_host(slot);
1858 else
1859 ret = sdhci_add_host(host);
b8c86fc5 1860 if (ret)
4489428a 1861 goto remove;
b8c86fc5 1862
c5e027a4
AH		 1863 sdhci_pci_add_own_cd(slot);
1864
77a0122e
AH		 1865 /*
1866 * Check if the chip needs a separate GPIO for card detect to wake up
1867 * from runtime suspend. If it is not there, don't allow runtime PM.
1868 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1869 */
945be38c 1870 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1871 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1872 chip->allow_runtime_pm = false;
1873
b8c86fc5
PO		 1874 return slot;
1875
4489428a
PO		 1876remove:
1877 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1878 chip->fixes->remove_slot(slot, 0);
4489428a 1879
52c506f0
AH		 1880cleanup:
1881 if (slot->data && slot->data->cleanup)
1882 slot->data->cleanup(slot->data);
1883
c60a32cd 1884free:
b8c86fc5
PO		 1885 sdhci_free_host(host);
1886
1887 return ERR_PTR(ret);
1888}
1889
1890static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1891{
1e72859e
PO		 1892 int dead;
1893 u32 scratch;
1894
c5e027a4
AH		 1895 sdhci_pci_remove_own_cd(slot);
1896
1e72859e
PO		 1897 dead = 0;
1898 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1899 if (scratch == (u32)-1)
1900 dead = 1;
1901
1902 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1903
1904 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1905 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1906
52c506f0
AH		 1907 if (slot->data && slot->data->cleanup)
1908 slot->data->cleanup(slot->data);
1909
b8c86fc5
PO		 1910 sdhci_free_host(slot->host);
1911}
1912
c3be1efd 1913static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5 1914{
00884b61 1915 pm_suspend_ignore_children(dev, 1);
66fd8ad5
AH		 1916 pm_runtime_set_autosuspend_delay(dev, 50);
1917 pm_runtime_use_autosuspend(dev);
00884b61
AH		 1918 pm_runtime_allow(dev);
1919 /* Stay active until mmc core scans for a card */
1920 pm_runtime_put_noidle(dev);
66fd8ad5
AH		 1921}
1922
6e0ee714 1923static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1924{
1925 pm_runtime_forbid(dev);
1926 pm_runtime_get_noresume(dev);
1927}
1928
c3be1efd 1929static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1930 const struct pci_device_id *ent)
1931{
1932 struct sdhci_pci_chip *chip;
1933 struct sdhci_pci_slot *slot;
1934
cf5e23e1 1935 u8 slots, first_bar;
b8c86fc5
PO		 1936 int ret, i;
1937
1938 BUG_ON(pdev == NULL);
1939 BUG_ON(ent == NULL);
1940
b8c86fc5 1941 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1942 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1943
1944 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1945 if (ret)
1946 return ret;
1947
1948 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1949 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1950 if (slots == 0)
1951 return -ENODEV;
1952
1953 BUG_ON(slots > MAX_SLOTS);
1954
1955 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1956 if (ret)
1957 return ret;
1958
1959 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1960
1961 if (first_bar > 5) {
1962 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1963 return -ENODEV;
1964 }
1965
52ac7acf 1966 ret = pcim_enable_device(pdev);
b8c86fc5
PO		 1967 if (ret)
1968 return ret;
1969
52ac7acf
AS		 1970 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1971 if (!chip)
1972 return -ENOMEM;
b8c86fc5
PO		 1973
1974 chip->pdev = pdev;
b177bc91 1975 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1976 if (chip->fixes) {
22606405 1977 chip->quirks = chip->fixes->quirks;
f3c55a7b 1978 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1979 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1980 }
b8c86fc5 1981 chip->num_slots = slots;
d38dcad4
AH		 1982 chip->pm_retune = true;
1983 chip->rpm_retune = true;
b8c86fc5
PO		 1984
1985 pci_set_drvdata(pdev, chip);
1986
22606405
PO		 1987 if (chip->fixes && chip->fixes->probe) {
1988 ret = chip->fixes->probe(chip);
1989 if (ret)
52ac7acf 1990 return ret;
22606405
PO		 1991 }
1992
225d85fe
AC		 1993 slots = chip->num_slots; /* Quirk may have changed this */
1994
b177bc91 1995 for (i = 0; i < slots; i++) {
52c506f0 1996 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1997 if (IS_ERR(slot)) {
b177bc91 1998 for (i--; i >= 0; i--)
b8c86fc5 1999 sdhci_pci_remove_slot(chip->slots[i]);
52ac7acf 2000 return PTR_ERR(slot);
b8c86fc5
PO		 2001 }
2002
2003 chip->slots[i] = slot;
2004 }
2005
c43fd774
AH		 2006 if (chip->allow_runtime_pm)
2007 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 2008
b8c86fc5 2009 return 0;
b8c86fc5
PO		 2010}
2011
6e0ee714 2012static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 2013{
2014 int i;
52ac7acf 2015 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
c43fd774 2016
52ac7acf
AS		 2017 if (chip->allow_runtime_pm)
2018 sdhci_pci_runtime_pm_forbid(&pdev->dev);
b8c86fc5 2019
52ac7acf
AS		 2020 for (i = 0; i < chip->num_slots; i++)
2021 sdhci_pci_remove_slot(chip->slots[i]);
b8c86fc5
PO		 2022}
2023
2024static struct pci_driver sdhci_driver = {
b177bc91 2025 .name = "sdhci-pci",
b8c86fc5 2026 .id_table = pci_ids,
b177bc91 2027 .probe = sdhci_pci_probe,
0433c143 2028 .remove = sdhci_pci_remove,
66fd8ad5
AH		 2029 .driver = {
2030 .pm = &sdhci_pci_pm_ops
2031 },
b8c86fc5
PO		 2032};
2033
acc69646 2034module_pci_driver(sdhci_driver);
b8c86fc5 2035
32710e8f 2036MODULE_AUTHOR("Pierre Ossman <[email protected]>");
b8c86fc5
PO		 2037MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2038MODULE_LICENSE("GPL");
Empty description
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