]> Git Repo - linux.git/blame - drivers/media/platform/omap3isp/isp.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / media / platform / omap3isp / isp.c
CommitLineData
448de7e7
SA		 1/*
2 * isp.c
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2006-2010 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <[email protected]>
10 * Sakari Ailus <[email protected]>
11 *
12 * Contributors:
13 * Laurent Pinchart <[email protected]>
14 * Sakari Ailus <[email protected]>
15 * David Cohen <[email protected]>
16 * Stanimir Varbanov <[email protected]>
17 * Vimarsh Zutshi <[email protected]>
18 * Tuukka Toivonen <[email protected]>
19 * Sergio Aguirre <[email protected]>
20 * Antti Koskipaa <[email protected]>
21 * Ivan T. Ivanov <[email protected]>
22 * RaniSuneela <[email protected]>
23 * Atanas Filipov <[email protected]>
24 * Gjorgji Rosikopulos <[email protected]>
25 * Hiroshi DOYU <[email protected]>
26 * Nayden Kanchev <[email protected]>
27 * Phil Carmody <[email protected]>
28 * Artem Bityutskiy <[email protected]>
29 * Dominic Curran <[email protected]>
30 * Ilkka Myllyperkio <[email protected]>
31 * Pallavi Kulkarni <[email protected]>
32 * Vaibhav Hiremath <[email protected]>
33 * Mohit Jalori <[email protected]>
34 * Sameer Venkatraman <[email protected]>
35 * Senthilvadivu Guruswamy <[email protected]>
36 * Thara Gopinath <[email protected]>
37 * Toni Leinonen <[email protected]>
38 * Troy Laramy <[email protected]>
39 *
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
448de7e7
SA		 43 */
44
45#include <asm/cacheflush.h>
46
47#include <linux/clk.h>
9b28ee3c 48#include <linux/clkdev.h>
448de7e7
SA		 49#include <linux/delay.h>
50#include <linux/device.h>
51#include <linux/dma-mapping.h>
52#include <linux/i2c.h>
53#include <linux/interrupt.h>
503596a1 54#include <linux/mfd/syscon.h>
448de7e7 55#include <linux/module.h>
c8d35c84 56#include <linux/omap-iommu.h>
448de7e7 57#include <linux/platform_device.h>
859969b3 58#include <linux/property.h>
448de7e7
SA		 59#include <linux/regulator/consumer.h>
60#include <linux/slab.h>
61#include <linux/sched.h>
62#include <linux/vmalloc.h>
63
24313113 64#ifdef CONFIG_ARM_DMA_USE_IOMMU
2a0a5472 65#include <asm/dma-iommu.h>
24313113 66#endif
2a0a5472 67
448de7e7 68#include <media/v4l2-common.h>
859969b3 69#include <media/v4l2-fwnode.h>
448de7e7 70#include <media/v4l2-device.h>
506a47eb 71#include <media/v4l2-mc.h>
448de7e7
SA		 72
73#include "isp.h"
74#include "ispreg.h"
75#include "ispccdc.h"
76#include "isppreview.h"
77#include "ispresizer.h"
78#include "ispcsi2.h"
79#include "ispccp2.h"
80#include "isph3a.h"
81#include "isphist.h"
82
83static unsigned int autoidle;
84module_param(autoidle, int, 0444);
85MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
86
87static void isp_save_ctx(struct isp_device *isp);
88
89static void isp_restore_ctx(struct isp_device *isp);
90
91static const struct isp_res_mapping isp_res_maps[] = {
92 {
93 .isp_rev = ISP_REVISION_2_0,
8644cdf9
SA		 94 .offset = {
95 /* first MMIO area */
96 0x0000, /* base, len 0x0070 */
97 0x0400, /* ccp2, len 0x01f0 */
98 0x0600, /* ccdc, len 0x00a8 */
99 0x0a00, /* hist, len 0x0048 */
100 0x0c00, /* h3a, len 0x0060 */
101 0x0e00, /* preview, len 0x00a0 */
102 0x1000, /* resizer, len 0x00ac */
103 0x1200, /* sbl, len 0x00fc */
104 /* second MMIO area */
105 0x0000, /* csi2a, len 0x0170 */
106 0x0170, /* csiphy2, len 0x000c */
107 },
503596a1 108 .phy_type = ISP_PHY_TYPE_3430,
448de7e7
SA		 109 },
110 {
111 .isp_rev = ISP_REVISION_15_0,
8644cdf9
SA		 112 .offset = {
113 /* first MMIO area */
114 0x0000, /* base, len 0x0070 */
115 0x0400, /* ccp2, len 0x01f0 */
116 0x0600, /* ccdc, len 0x00a8 */
117 0x0a00, /* hist, len 0x0048 */
118 0x0c00, /* h3a, len 0x0060 */
119 0x0e00, /* preview, len 0x00a0 */
120 0x1000, /* resizer, len 0x00ac */
121 0x1200, /* sbl, len 0x00fc */
122 /* second MMIO area */
123 0x0000, /* csi2a, len 0x0170 (1st area) */
124 0x0170, /* csiphy2, len 0x000c */
125 0x01c0, /* csi2a, len 0x0040 (2nd area) */
126 0x0400, /* csi2c, len 0x0170 (1st area) */
127 0x0570, /* csiphy1, len 0x000c */
128 0x05c0, /* csi2c, len 0x0040 (2nd area) */
129 },
503596a1 130 .phy_type = ISP_PHY_TYPE_3630,
448de7e7
SA		 131 },
132};
133
134/* Structure for saving/restoring ISP module registers */
135static struct isp_reg isp_reg_list[] = {
136 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
137 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
138 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
139 {0, ISP_TOK_TERM, 0}
140};
141
142/*
143 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
144 * @isp: OMAP3 ISP device
145 *
146 * In order to force posting of pending writes, we need to write and
147 * readback the same register, in this case the revision register.
148 *
149 * See this link for reference:
150 * http://www.mail-archive.com/[email protected]/msg08149.html
151 */
152void omap3isp_flush(struct isp_device *isp)
153{
154 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
155 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
156}
157
9b28ee3c
LP		 158/* -----------------------------------------------------------------------------
159 * XCLK
160 */
161
162#define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw)
163
164static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
165{
166 switch (xclk->id) {
167 case ISP_XCLK_A:
168 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
169 ISPTCTRL_CTRL_DIVA_MASK,
170 divider << ISPTCTRL_CTRL_DIVA_SHIFT);
171 break;
172 case ISP_XCLK_B:
173 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
174 ISPTCTRL_CTRL_DIVB_MASK,
175 divider << ISPTCTRL_CTRL_DIVB_SHIFT);
176 break;
177 }
178}
179
180static int isp_xclk_prepare(struct clk_hw *hw)
181{
182 struct isp_xclk *xclk = to_isp_xclk(hw);
183
184 omap3isp_get(xclk->isp);
185
186 return 0;
187}
188
189static void isp_xclk_unprepare(struct clk_hw *hw)
190{
191 struct isp_xclk *xclk = to_isp_xclk(hw);
192
193 omap3isp_put(xclk->isp);
194}
195
196static int isp_xclk_enable(struct clk_hw *hw)
197{
198 struct isp_xclk *xclk = to_isp_xclk(hw);
199 unsigned long flags;
200
201 spin_lock_irqsave(&xclk->lock, flags);
202 isp_xclk_update(xclk, xclk->divider);
203 xclk->enabled = true;
204 spin_unlock_irqrestore(&xclk->lock, flags);
205
206 return 0;
207}
208
209static void isp_xclk_disable(struct clk_hw *hw)
210{
211 struct isp_xclk *xclk = to_isp_xclk(hw);
212 unsigned long flags;
213
214 spin_lock_irqsave(&xclk->lock, flags);
215 isp_xclk_update(xclk, 0);
216 xclk->enabled = false;
217 spin_unlock_irqrestore(&xclk->lock, flags);
218}
219
220static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw,
221 unsigned long parent_rate)
222{
223 struct isp_xclk *xclk = to_isp_xclk(hw);
224
225 return parent_rate / xclk->divider;
226}
227
228static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
229{
230 u32 divider;
231
232 if (*rate >= parent_rate) {
233 *rate = parent_rate;
234 return ISPTCTRL_CTRL_DIV_BYPASS;
235 }
236
aadec012
LP		 237 if (*rate == 0)
238 *rate = 1;
239
9b28ee3c
LP		 240 divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
241 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
242 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
243
244 *rate = parent_rate / divider;
245 return divider;
246}
247
248static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
249 unsigned long *parent_rate)
250{
251 isp_xclk_calc_divider(&rate, *parent_rate);
252 return rate;
253}
254
255static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate,
256 unsigned long parent_rate)
257{
258 struct isp_xclk *xclk = to_isp_xclk(hw);
259 unsigned long flags;
260 u32 divider;
261
262 divider = isp_xclk_calc_divider(&rate, parent_rate);
263
264 spin_lock_irqsave(&xclk->lock, flags);
265
266 xclk->divider = divider;
267 if (xclk->enabled)
268 isp_xclk_update(xclk, divider);
269
270 spin_unlock_irqrestore(&xclk->lock, flags);
271
272 dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n",
273 __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
274 return 0;
275}
276
277static const struct clk_ops isp_xclk_ops = {
278 .prepare = isp_xclk_prepare,
279 .unprepare = isp_xclk_unprepare,
280 .enable = isp_xclk_enable,
281 .disable = isp_xclk_disable,
282 .recalc_rate = isp_xclk_recalc_rate,
283 .round_rate = isp_xclk_round_rate,
284 .set_rate = isp_xclk_set_rate,
285};
286
287static const char *isp_xclk_parent_name = "cam_mclk";
288
64904b57
LP		 289static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data)
290{
291 unsigned int idx = clkspec->args[0];
292 struct isp_device *isp = data;
293
294 if (idx >= ARRAY_SIZE(isp->xclks))
295 return ERR_PTR(-ENOENT);
296
297 return isp->xclks[idx].clk;
298}
299
9b28ee3c
LP		 300static int isp_xclk_init(struct isp_device *isp)
301{
64904b57 302 struct device_node *np = isp->dev->of_node;
6c33d826 303 struct clk_init_data init = {};
9b28ee3c
LP		 304 unsigned int i;
305
f8e2ff26
SN		 306 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i)
307 isp->xclks[i].clk = ERR_PTR(-EINVAL);
308
9b28ee3c
LP		 309 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
310 struct isp_xclk *xclk = &isp->xclks[i];
9b28ee3c
LP		 311
312 xclk->isp = isp;
313 xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B;
314 xclk->divider = 1;
315 spin_lock_init(&xclk->lock);
316
317 init.name = i == 0 ? "cam_xclka" : "cam_xclkb";
318 init.ops = &isp_xclk_ops;
319 init.parent_names = &isp_xclk_parent_name;
320 init.num_parents = 1;
321
322 xclk->hw.init = &init;
f8e2ff26
SN		 323 /*
324 * The first argument is NULL in order to avoid circular
325 * reference, as this driver takes reference on the
326 * sensor subdevice modules and the sensors would take
327 * reference on this module through clk_get().
328 */
329 xclk->clk = clk_register(NULL, &xclk->hw);
330 if (IS_ERR(xclk->clk))
331 return PTR_ERR(xclk->clk);
9b28ee3c
LP		 332 }
333
64904b57
LP		 334 if (np)
335 of_clk_add_provider(np, isp_xclk_src_get, isp);
336
9b28ee3c
LP		 337 return 0;
338}
339
340static void isp_xclk_cleanup(struct isp_device *isp)
341{
64904b57 342 struct device_node *np = isp->dev->of_node;
9b28ee3c
LP		 343 unsigned int i;
344
64904b57
LP		 345 if (np)
346 of_clk_del_provider(np);
347
9b28ee3c
LP		 348 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
349 struct isp_xclk *xclk = &isp->xclks[i];
350
f8e2ff26
SN		 351 if (!IS_ERR(xclk->clk))
352 clk_unregister(xclk->clk);
9b28ee3c
LP		 353 }
354}
355
356/* -----------------------------------------------------------------------------
357 * Interrupts
358 */
359
448de7e7
SA		 360/*
361 * isp_enable_interrupts - Enable ISP interrupts.
362 * @isp: OMAP3 ISP device
363 */
364static void isp_enable_interrupts(struct isp_device *isp)
365{
366 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
367 | IRQ0ENABLE_CSIB_IRQ
368 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
369 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
370 | IRQ0ENABLE_CCDC_VD0_IRQ
371 | IRQ0ENABLE_CCDC_VD1_IRQ
372 | IRQ0ENABLE_HS_VS_IRQ
373 | IRQ0ENABLE_HIST_DONE_IRQ
374 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
375 | IRQ0ENABLE_H3A_AF_DONE_IRQ
376 | IRQ0ENABLE_PRV_DONE_IRQ
377 | IRQ0ENABLE_RSZ_DONE_IRQ;
378
379 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
380 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
381}
382
383/*
384 * isp_disable_interrupts - Disable ISP interrupts.
385 * @isp: OMAP3 ISP device
386 */
387static void isp_disable_interrupts(struct isp_device *isp)
388{
389 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
390}
391
448de7e7 392/*
96d62ae2 393 * isp_core_init - ISP core settings
448de7e7
SA		 394 * @isp: OMAP3 ISP device
395 * @idle: Consider idle state.
396 *
25aeb418 397 * Set the power settings for the ISP and SBL bus and configure the HS/VS
96d62ae2
LP		 398 * interrupt source.
399 *
400 * We need to configure the HS/VS interrupt source before interrupts get
401 * enabled, as the sensor might be free-running and the ISP default setting
402 * (HS edge) would put an unnecessary burden on the CPU.
448de7e7 403 */
96d62ae2 404static void isp_core_init(struct isp_device *isp, int idle)
448de7e7
SA		 405{
406 isp_reg_writel(isp,
407 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
408 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
409 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
410 ((isp->revision == ISP_REVISION_15_0) ?
411 ISP_SYSCONFIG_AUTOIDLE : 0),
412 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
413
96d62ae2
LP		 414 isp_reg_writel(isp,
415 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
416 ISPCTRL_SYNC_DETECT_VSRISE,
417 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
448de7e7
SA		 418}
419
420/*
421 * Configure the bridge and lane shifter. Valid inputs are
422 *
423 * CCDC_INPUT_PARALLEL: Parallel interface
424 * CCDC_INPUT_CSI2A: CSI2a receiver
425 * CCDC_INPUT_CCP2B: CCP2b receiver
426 * CCDC_INPUT_CSI2C: CSI2c receiver
427 *
428 * The bridge and lane shifter are configured according to the selected input
429 * and the ISP platform data.
430 */
431void omap3isp_configure_bridge(struct isp_device *isp,
432 enum ccdc_input_entity input,
68908747 433 const struct isp_parallel_cfg *parcfg,
c51364ca 434 unsigned int shift, unsigned int bridge)
448de7e7
SA		 435{
436 u32 ispctrl_val;
437
438 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
439 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
440 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
441 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
442 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
c51364ca 443 ispctrl_val |= bridge;
448de7e7
SA		 444
445 switch (input) {
446 case CCDC_INPUT_PARALLEL:
447 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
68908747 448 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
74d1e7c0 449 shift += parcfg->data_lane_shift;
448de7e7
SA		 450 break;
451
452 case CCDC_INPUT_CSI2A:
453 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
454 break;
455
456 case CCDC_INPUT_CCP2B:
457 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
458 break;
459
460 case CCDC_INPUT_CSI2C:
461 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
462 break;
463
464 default:
465 return;
466 }
467
c09af044
MJ		 468 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
469
448de7e7
SA		 470 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
471}
472
448de7e7
SA		 473void omap3isp_hist_dma_done(struct isp_device *isp)
474{
475 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
476 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
477 /* Histogram cannot be enabled in this frame anymore */
478 atomic_set(&isp->isp_hist.buf_err, 1);
d26da990
MCC		 479 dev_dbg(isp->dev,
480 "hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
448de7e7
SA		 481 }
482}
483
484static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
485{
486 static const char *name[] = {
487 "CSIA_IRQ",
488 "res1",
489 "res2",
490 "CSIB_LCM_IRQ",
491 "CSIB_IRQ",
492 "res5",
493 "res6",
494 "res7",
495 "CCDC_VD0_IRQ",
496 "CCDC_VD1_IRQ",
497 "CCDC_VD2_IRQ",
498 "CCDC_ERR_IRQ",
499 "H3A_AF_DONE_IRQ",
500 "H3A_AWB_DONE_IRQ",
501 "res14",
502 "res15",
503 "HIST_DONE_IRQ",
504 "CCDC_LSC_DONE",
505 "CCDC_LSC_PREFETCH_COMPLETED",
506 "CCDC_LSC_PREFETCH_ERROR",
507 "PRV_DONE_IRQ",
508 "CBUFF_IRQ",
509 "res22",
510 "res23",
511 "RSZ_DONE_IRQ",
512 "OVF_IRQ",
513 "res26",
514 "res27",
515 "MMU_ERR_IRQ",
516 "OCP_ERR_IRQ",
517 "SEC_ERR_IRQ",
518 "HS_VS_IRQ",
519 };
520 int i;
521
6c20c635 522 dev_dbg(isp->dev, "ISP IRQ: ");
448de7e7
SA		 523
524 for (i = 0; i < ARRAY_SIZE(name); i++) {
525 if ((1 << i) & irqstatus)
526 printk(KERN_CONT "%s ", name[i]);
527 }
528 printk(KERN_CONT "\n");
529}
530
531static void isp_isr_sbl(struct isp_device *isp)
532{
533 struct device *dev = isp->dev;
875e2e3e 534 struct isp_pipeline *pipe;
448de7e7
SA		 535 u32 sbl_pcr;
536
537 /*
538 * Handle shared buffer logic overflows for video buffers.
539 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
540 */
541 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
542 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
543 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
544
545 if (sbl_pcr)
546 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
547
875e2e3e
LP		 548 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
549 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
550 if (pipe != NULL)
551 pipe->error = true;
552 }
553
554 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
555 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
556 if (pipe != NULL)
557 pipe->error = true;
558 }
559
560 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
561 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
562 if (pipe != NULL)
563 pipe->error = true;
448de7e7
SA		 564 }
565
566 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
875e2e3e
LP		 567 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
568 if (pipe != NULL)
569 pipe->error = true;
448de7e7
SA		 570 }
571
572 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
573 | ISPSBL_PCR_RSZ2_WBL_OVF
574 | ISPSBL_PCR_RSZ3_WBL_OVF
875e2e3e
LP		 575 | ISPSBL_PCR_RSZ4_WBL_OVF)) {
576 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
577 if (pipe != NULL)
578 pipe->error = true;
579 }
448de7e7
SA		 580
581 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
582 omap3isp_stat_sbl_overflow(&isp->isp_af);
583
584 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
585 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
586}
587
588/*
589 * isp_isr - Interrupt Service Routine for Camera ISP module.
590 * @irq: Not used currently.
591 * @_isp: Pointer to the OMAP3 ISP device
592 *
593 * Handles the corresponding callback if plugged in.
448de7e7
SA		 594 */
595static irqreturn_t isp_isr(int irq, void *_isp)
596{
597 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
598 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
599 IRQ0STATUS_CCDC_VD0_IRQ |
600 IRQ0STATUS_CCDC_VD1_IRQ |
601 IRQ0STATUS_HS_VS_IRQ;
602 struct isp_device *isp = _isp;
603 u32 irqstatus;
448de7e7
SA		 604
605 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
606 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
607
608 isp_isr_sbl(isp);
609
875e2e3e
LP		 610 if (irqstatus & IRQ0STATUS_CSIA_IRQ)
611 omap3isp_csi2_isr(&isp->isp_csi2a);
448de7e7 612
875e2e3e
LP		 613 if (irqstatus & IRQ0STATUS_CSIB_IRQ)
614 omap3isp_ccp2_isr(&isp->isp_ccp2);
448de7e7
SA		 615
616 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
617 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
618 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
619 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
620 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
621 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
622 omap3isp_stat_isr_frame_sync(&isp->isp_af);
623 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
624 }
625
626 if (irqstatus & ccdc_events)
627 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
628
629 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
630 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
631 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
632 omap3isp_preview_isr(&isp->isp_prev);
633 }
634
635 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
636 omap3isp_resizer_isr(&isp->isp_res);
637
638 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
639 omap3isp_stat_isr(&isp->isp_aewb);
640
641 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
642 omap3isp_stat_isr(&isp->isp_af);
643
644 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
645 omap3isp_stat_isr(&isp->isp_hist);
646
647 omap3isp_flush(isp);
648
649#if defined(DEBUG) && defined(ISP_ISR_DEBUG)
650 isp_isr_dbg(isp, irqstatus);
651#endif
652
653 return IRQ_HANDLED;
654}
655
68429f50
LP		 656static const struct media_device_ops isp_media_ops = {
657 .link_notify = v4l2_pipeline_link_notify,
658};
659
448de7e7
SA		 660/* -----------------------------------------------------------------------------
661 * Pipeline stream management
662 */
663
664/*
665 * isp_pipeline_enable - Enable streaming on a pipeline
666 * @pipe: ISP pipeline
667 * @mode: Stream mode (single shot or continuous)
668 *
669 * Walk the entities chain starting at the pipeline output video node and start
670 * all modules in the chain in the given mode.
671 *
25985edc 672 * Return 0 if successful, or the return value of the failed video::s_stream
448de7e7
SA		 673 * operation otherwise.
674 */
675static int isp_pipeline_enable(struct isp_pipeline *pipe,
676 enum isp_pipeline_stream_state mode)
677{
678 struct isp_device *isp = pipe->output->isp;
679 struct media_entity *entity;
680 struct media_pad *pad;
681 struct v4l2_subdev *subdev;
682 unsigned long flags;
c62e2a19 683 int ret;
448de7e7 684
112eee0c
LP		 685 /* Refuse to start streaming if an entity included in the pipeline has
686 * crashed. This check must be performed before the loop below to avoid
687 * starting entities if the pipeline won't start anyway (those entities
688 * would then likely fail to stop, making the problem worse).
1567bb7d 689 */
17d3d405 690 if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed))
1567bb7d
LP		 691 return -EIO;
692
448de7e7
SA		 693 spin_lock_irqsave(&pipe->lock, flags);
694 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
695 spin_unlock_irqrestore(&pipe->lock, flags);
696
697 pipe->do_propagation = false;
698
699 entity = &pipe->output->video.entity;
700 while (1) {
701 pad = &entity->pads[0];
702 if (!(pad->flags & MEDIA_PAD_FL_SINK))
703 break;
704
1bddf1b3 705 pad = media_entity_remote_pad(pad);
3efdf62c 706 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
448de7e7
SA		 707 break;
708
709 entity = pad->entity;
710 subdev = media_entity_to_v4l2_subdev(entity);
711
712 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
713 if (ret < 0 && ret != -ENOIOCTLCMD)
c62e2a19 714 return ret;
448de7e7
SA		 715
716 if (subdev == &isp->isp_ccdc.subdev) {
717 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
718 s_stream, mode);
719 v4l2_subdev_call(&isp->isp_af.subdev, video,
720 s_stream, mode);
721 v4l2_subdev_call(&isp->isp_hist.subdev, video,
722 s_stream, mode);
723 pipe->do_propagation = true;
724 }
725 }
726
c62e2a19 727 return 0;
448de7e7
SA		 728}
729
730static int isp_pipeline_wait_resizer(struct isp_device *isp)
731{
732 return omap3isp_resizer_busy(&isp->isp_res);
733}
734
735static int isp_pipeline_wait_preview(struct isp_device *isp)
736{
737 return omap3isp_preview_busy(&isp->isp_prev);
738}
739
740static int isp_pipeline_wait_ccdc(struct isp_device *isp)
741{
742 return omap3isp_stat_busy(&isp->isp_af)
743 || omap3isp_stat_busy(&isp->isp_aewb)
744 || omap3isp_stat_busy(&isp->isp_hist)
745 || omap3isp_ccdc_busy(&isp->isp_ccdc);
746}
747
748#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
749
750static int isp_pipeline_wait(struct isp_device *isp,
751 int(*busy)(struct isp_device *isp))
752{
753 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
754
755 while (!time_after(jiffies, timeout)) {
756 if (!busy(isp))
757 return 0;
758 }
759
760 return 1;
761}
762
763/*
764 * isp_pipeline_disable - Disable streaming on a pipeline
765 * @pipe: ISP pipeline
766 *
767 * Walk the entities chain starting at the pipeline output video node and stop
768 * all modules in the chain. Wait synchronously for the modules to be stopped if
769 * necessary.
770 *
771 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
772 * can't be stopped (in which case a software reset of the ISP is probably
773 * necessary).
774 */
775static int isp_pipeline_disable(struct isp_pipeline *pipe)
776{
777 struct isp_device *isp = pipe->output->isp;
778 struct media_entity *entity;
779 struct media_pad *pad;
780 struct v4l2_subdev *subdev;
781 int failure = 0;
782 int ret;
783
784 /*
785 * We need to stop all the modules after CCDC first or they'll
786 * never stop since they may not get a full frame from CCDC.
787 */
788 entity = &pipe->output->video.entity;
789 while (1) {
790 pad = &entity->pads[0];
791 if (!(pad->flags & MEDIA_PAD_FL_SINK))
792 break;
793
1bddf1b3 794 pad = media_entity_remote_pad(pad);
3efdf62c 795 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
448de7e7
SA		 796 break;
797
798 entity = pad->entity;
799 subdev = media_entity_to_v4l2_subdev(entity);
800
801 if (subdev == &isp->isp_ccdc.subdev) {
802 v4l2_subdev_call(&isp->isp_aewb.subdev,
803 video, s_stream, 0);
804 v4l2_subdev_call(&isp->isp_af.subdev,
805 video, s_stream, 0);
806 v4l2_subdev_call(&isp->isp_hist.subdev,
807 video, s_stream, 0);
808 }
809
eb228e89 810 ret = v4l2_subdev_call(subdev, video, s_stream, 0);
448de7e7
SA		 811
812 if (subdev == &isp->isp_res.subdev)
eb228e89 813 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
448de7e7 814 else if (subdev == &isp->isp_prev.subdev)
eb228e89 815 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview);
448de7e7 816 else if (subdev == &isp->isp_ccdc.subdev)
eb228e89 817 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
448de7e7 818
112eee0c
LP		 819 /* Handle stop failures. An entity that fails to stop can
820 * usually just be restarted. Flag the stop failure nonetheless
821 * to trigger an ISP reset the next time the device is released,
822 * just in case.
823 *
824 * The preview engine is a special case. A failure to stop can
825 * mean a hardware crash. When that happens the preview engine
826 * won't respond to read/write operations on the L4 bus anymore,
827 * resulting in a bus fault and a kernel oops next time it gets
828 * accessed. Mark it as crashed to prevent pipelines including
829 * it from being started.
830 */
448de7e7
SA		 831 if (ret) {
832 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
112eee0c 833 isp->stop_failure = true;
17d3d405
SA		 834 if (subdev == &isp->isp_prev.subdev)
835 media_entity_enum_set(&isp->crashed,
836 &subdev->entity);
448de7e7
SA		 837 failure = -ETIMEDOUT;
838 }
839 }
840
841 return failure;
842}
843
844/*
845 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
846 * @pipe: ISP pipeline
847 * @state: Stream state (stopped, single shot or continuous)
848 *
849 * Set the pipeline to the given stream state. Pipelines can be started in
850 * single-shot or continuous mode.
851 *
25985edc 852 * Return 0 if successful, or the return value of the failed video::s_stream
994d5375
LP		 853 * operation otherwise. The pipeline state is not updated when the operation
854 * fails, except when stopping the pipeline.
448de7e7
SA		 855 */
856int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
857 enum isp_pipeline_stream_state state)
858{
859 int ret;
860
861 if (state == ISP_PIPELINE_STREAM_STOPPED)
862 ret = isp_pipeline_disable(pipe);
863 else
864 ret = isp_pipeline_enable(pipe, state);
994d5375
LP		 865
866 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
867 pipe->stream_state = state;
448de7e7
SA		 868
869 return ret;
870}
871
661112cb
LP		 872/*
873 * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline
874 * @pipe: ISP pipeline
875 *
876 * Cancelling a stream mark all buffers on all video nodes in the pipeline as
877 * erroneous and makes sure no new buffer can be queued. This function is called
878 * when a fatal error that prevents any further operation on the pipeline
879 * occurs.
880 */
881void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe)
882{
883 if (pipe->input)
884 omap3isp_video_cancel_stream(pipe->input);
885 if (pipe->output)
886 omap3isp_video_cancel_stream(pipe->output);
887}
888
448de7e7
SA		 889/*
890 * isp_pipeline_resume - Resume streaming on a pipeline
891 * @pipe: ISP pipeline
892 *
893 * Resume video output and input and re-enable pipeline.
894 */
895static void isp_pipeline_resume(struct isp_pipeline *pipe)
896{
897 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
898
899 omap3isp_video_resume(pipe->output, !singleshot);
900 if (singleshot)
901 omap3isp_video_resume(pipe->input, 0);
902 isp_pipeline_enable(pipe, pipe->stream_state);
903}
904
905/*
906 * isp_pipeline_suspend - Suspend streaming on a pipeline
907 * @pipe: ISP pipeline
908 *
909 * Suspend pipeline.
910 */
911static void isp_pipeline_suspend(struct isp_pipeline *pipe)
912{
913 isp_pipeline_disable(pipe);
914}
915
916/*
917 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
4a3fad70 918 * video node
448de7e7
SA		 919 * @me: ISP module's media entity
920 *
921 * Returns 1 if the entity has an enabled link to the output video node or 0
922 * otherwise. It's true only while pipeline can have no more than one output
923 * node.
924 */
925static int isp_pipeline_is_last(struct media_entity *me)
926{
927 struct isp_pipeline *pipe;
928 struct media_pad *pad;
929
930 if (!me->pipe)
931 return 0;
932 pipe = to_isp_pipeline(me);
933 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
934 return 0;
1bddf1b3 935 pad = media_entity_remote_pad(&pipe->output->pad);
448de7e7
SA		 936 return pad->entity == me;
937}
938
939/*
940 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
941 * @me: ISP module's media entity
942 *
943 * Suspend the whole pipeline if module's entity has an enabled link to the
944 * output video node. It works only while pipeline can have no more than one
945 * output node.
946 */
947static void isp_suspend_module_pipeline(struct media_entity *me)
948{
949 if (isp_pipeline_is_last(me))
950 isp_pipeline_suspend(to_isp_pipeline(me));
951}
952
953/*
954 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
955 * @me: ISP module's media entity
956 *
957 * Resume the whole pipeline if module's entity has an enabled link to the
958 * output video node. It works only while pipeline can have no more than one
959 * output node.
960 */
961static void isp_resume_module_pipeline(struct media_entity *me)
962{
963 if (isp_pipeline_is_last(me))
964 isp_pipeline_resume(to_isp_pipeline(me));
965}
966
967/*
968 * isp_suspend_modules - Suspend ISP submodules.
969 * @isp: OMAP3 ISP device
970 *
971 * Returns 0 if suspend left in idle state all the submodules properly,
972 * or returns 1 if a general Reset is required to suspend the submodules.
973 */
6f3de838 974static int __maybe_unused isp_suspend_modules(struct isp_device *isp)
448de7e7
SA		 975{
976 unsigned long timeout;
977
978 omap3isp_stat_suspend(&isp->isp_aewb);
979 omap3isp_stat_suspend(&isp->isp_af);
980 omap3isp_stat_suspend(&isp->isp_hist);
981 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
982 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
983 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
984 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
985 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
986
987 timeout = jiffies + ISP_STOP_TIMEOUT;
988 while (omap3isp_stat_busy(&isp->isp_af)
989 || omap3isp_stat_busy(&isp->isp_aewb)
990 || omap3isp_stat_busy(&isp->isp_hist)
991 || omap3isp_preview_busy(&isp->isp_prev)
992 || omap3isp_resizer_busy(&isp->isp_res)
993 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
994 if (time_after(jiffies, timeout)) {
995 dev_info(isp->dev, "can't stop modules.\n");
996 return 1;
997 }
998 msleep(1);
999 }
1000
1001 return 0;
1002}
1003
1004/*
1005 * isp_resume_modules - Resume ISP submodules.
1006 * @isp: OMAP3 ISP device
1007 */
6f3de838 1008static void __maybe_unused isp_resume_modules(struct isp_device *isp)
448de7e7
SA		 1009{
1010 omap3isp_stat_resume(&isp->isp_aewb);
1011 omap3isp_stat_resume(&isp->isp_af);
1012 omap3isp_stat_resume(&isp->isp_hist);
1013 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1014 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1015 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1016 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1017 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1018}
1019
1020/*
1021 * isp_reset - Reset ISP with a timeout wait for idle.
1022 * @isp: OMAP3 ISP device
1023 */
1024static int isp_reset(struct isp_device *isp)
1025{
1026 unsigned long timeout = 0;
1027
1028 isp_reg_writel(isp,
1029 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1030 | ISP_SYSCONFIG_SOFTRESET,
1031 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1032 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1033 ISP_SYSSTATUS) & 0x1)) {
1034 if (timeout++ > 10000) {
1035 dev_alert(isp->dev, "cannot reset ISP\n");
1036 return -ETIMEDOUT;
1037 }
1038 udelay(1);
1039 }
1040
112eee0c 1041 isp->stop_failure = false;
17d3d405 1042 media_entity_enum_zero(&isp->crashed);
448de7e7
SA		 1043 return 0;
1044}
1045
1046/*
1047 * isp_save_context - Saves the values of the ISP module registers.
1048 * @isp: OMAP3 ISP device
1049 * @reg_list: Structure containing pairs of register address and value to
1050 * modify on OMAP.
1051 */
1052static void
1053isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1054{
1055 struct isp_reg *next = reg_list;
1056
1057 for (; next->reg != ISP_TOK_TERM; next++)
1058 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1059}
1060
1061/*
1062 * isp_restore_context - Restores the values of the ISP module registers.
1063 * @isp: OMAP3 ISP device
1064 * @reg_list: Structure containing pairs of register address and value to
1065 * modify on OMAP.
1066 */
1067static void
1068isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1069{
1070 struct isp_reg *next = reg_list;
1071
1072 for (; next->reg != ISP_TOK_TERM; next++)
1073 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1074}
1075
1076/*
1077 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1078 * @isp: OMAP3 ISP device
1079 *
1080 * Routine for saving the context of each module in the ISP.
1081 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1082 */
1083static void isp_save_ctx(struct isp_device *isp)
1084{
1085 isp_save_context(isp, isp_reg_list);
fabdbca8 1086 omap_iommu_save_ctx(isp->dev);
448de7e7
SA		 1087}
1088
1089/*
1090 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1091 * @isp: OMAP3 ISP device
1092 *
1093 * Routine for restoring the context of each module in the ISP.
1094 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1095 */
1096static void isp_restore_ctx(struct isp_device *isp)
1097{
1098 isp_restore_context(isp, isp_reg_list);
fabdbca8 1099 omap_iommu_restore_ctx(isp->dev);
448de7e7
SA		 1100 omap3isp_ccdc_restore_context(isp);
1101 omap3isp_preview_restore_context(isp);
1102}
1103
1104/* -----------------------------------------------------------------------------
1105 * SBL resources management
1106 */
1107#define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1108 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1109 OMAP3_ISP_SBL_PREVIEW_READ | \
1110 OMAP3_ISP_SBL_RESIZER_READ)
1111#define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1112 OMAP3_ISP_SBL_CSI2A_WRITE | \
1113 OMAP3_ISP_SBL_CSI2C_WRITE | \
1114 OMAP3_ISP_SBL_CCDC_WRITE | \
1115 OMAP3_ISP_SBL_PREVIEW_WRITE)
1116
1117void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1118{
1119 u32 sbl = 0;
1120
1121 isp->sbl_resources |= res;
1122
1123 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1124 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1125
1126 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1127 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1128
1129 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1130 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1131
1132 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1133 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1134
1135 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1136 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1137
1138 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1139 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1140
1141 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1142}
1143
1144void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1145{
1146 u32 sbl = 0;
1147
1148 isp->sbl_resources &= ~res;
1149
1150 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1151 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1152
1153 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1154 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1155
1156 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1157 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1158
1159 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1160 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1161
1162 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1163 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1164
1165 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1166 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1167
1168 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1169}
1170
1171/*
1172 * isp_module_sync_idle - Helper to sync module with its idle state
1173 * @me: ISP submodule's media entity
1174 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1175 * @stopping: flag which tells module wants to stop
1176 *
1177 * This function checks if ISP submodule needs to wait for next interrupt. If
1178 * yes, makes the caller to sleep while waiting for such event.
1179 */
1180int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1181 atomic_t *stopping)
1182{
1183 struct isp_pipeline *pipe = to_isp_pipeline(me);
1184
1185 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1186 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1187 !isp_pipeline_ready(pipe)))
1188 return 0;
1189
1190 /*
1191 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1192 * scenario. We'll call it here to avoid race conditions.
1193 */
1194 atomic_set(stopping, 1);
1195 smp_mb();
1196
1197 /*
1198 * If module is the last one, it's writing to memory. In this case,
1199 * it's necessary to check if the module is already paused due to
1200 * DMA queue underrun or if it has to wait for next interrupt to be
1201 * idle.
1202 * If it isn't the last one, the function won't sleep but *stopping
1203 * will still be set to warn next submodule caller's interrupt the
1204 * module wants to be idle.
1205 */
1206 if (isp_pipeline_is_last(me)) {
1207 struct isp_video *video = pipe->output;
1208 unsigned long flags;
e8feb876 1209 spin_lock_irqsave(&video->irqlock, flags);
448de7e7 1210 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
e8feb876 1211 spin_unlock_irqrestore(&video->irqlock, flags);
448de7e7
SA		 1212 atomic_set(stopping, 0);
1213 smp_mb();
1214 return 0;
1215 }
e8feb876 1216 spin_unlock_irqrestore(&video->irqlock, flags);
448de7e7
SA		 1217 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1218 msecs_to_jiffies(1000))) {
1219 atomic_set(stopping, 0);
1220 smp_mb();
1221 return -ETIMEDOUT;
1222 }
1223 }
1224
1225 return 0;
1226}
1227
1228/*
1e9c4d49 1229 * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping
448de7e7
SA		 1230 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1231 * @stopping: flag which tells module wants to stop
1232 *
1233 * This function checks if ISP submodule was stopping. In case of yes, it
1234 * notices the caller by setting stopping to 0 and waking up the wait queue.
1235 * Returns 1 if it was stopping or 0 otherwise.
1236 */
1237int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1238 atomic_t *stopping)
1239{
1240 if (atomic_cmpxchg(stopping, 1, 0)) {
1241 wake_up(wait);
1242 return 1;
1243 }
1244
1245 return 0;
1246}
1247
1248/* --------------------------------------------------------------------------
1249 * Clock management
1250 */
1251
1252#define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1253 ISPCTRL_HIST_CLK_EN | \
1254 ISPCTRL_RSZ_CLK_EN | \
1255 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1256 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1257
1258static void __isp_subclk_update(struct isp_device *isp)
1259{
1260 u32 clk = 0;
1261
be9a1b98
LP		 1262 /* AEWB and AF share the same clock. */
1263 if (isp->subclk_resources &
1264 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
448de7e7
SA		 1265 clk |= ISPCTRL_H3A_CLK_EN;
1266
1267 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1268 clk |= ISPCTRL_HIST_CLK_EN;
1269
1270 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1271 clk |= ISPCTRL_RSZ_CLK_EN;
1272
1273 /* NOTE: For CCDC & Preview submodules, we need to affect internal
25985edc 1274 * RAM as well.
448de7e7
SA		 1275 */
1276 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1277 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1278
1279 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1280 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1281
1282 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1283 ISPCTRL_CLKS_MASK, clk);
1284}
1285
1286void omap3isp_subclk_enable(struct isp_device *isp,
1287 enum isp_subclk_resource res)
1288{
1289 isp->subclk_resources |= res;
1290
1291 __isp_subclk_update(isp);
1292}
1293
1294void omap3isp_subclk_disable(struct isp_device *isp,
1295 enum isp_subclk_resource res)
1296{
1297 isp->subclk_resources &= ~res;
1298
1299 __isp_subclk_update(isp);
1300}
1301
1302/*
1303 * isp_enable_clocks - Enable ISP clocks
1304 * @isp: OMAP3 ISP device
1305 *
b057c3c3
LP		 1306 * Return 0 if successful, or clk_prepare_enable return value if any of them
1307 * fails.
448de7e7
SA		 1308 */
1309static int isp_enable_clocks(struct isp_device *isp)
1310{
1311 int r;
1312 unsigned long rate;
448de7e7 1313
b057c3c3 1314 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7 1315 if (r) {
b057c3c3 1316 dev_err(isp->dev, "failed to enable cam_ick clock\n");
448de7e7
SA		 1317 goto out_clk_enable_ick;
1318 }
6d1aa02f 1319 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
448de7e7 1320 if (r) {
6d1aa02f 1321 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
448de7e7
SA		 1322 goto out_clk_enable_mclk;
1323 }
b057c3c3 1324 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1325 if (r) {
b057c3c3 1326 dev_err(isp->dev, "failed to enable cam_mclk clock\n");
448de7e7
SA		 1327 goto out_clk_enable_mclk;
1328 }
1329 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1330 if (rate != CM_CAM_MCLK_HZ)
1331 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1332 " expected : %d\n"
1333 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
b057c3c3 1334 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7 1335 if (r) {
b057c3c3 1336 dev_err(isp->dev, "failed to enable csi2_fck clock\n");
448de7e7
SA		 1337 goto out_clk_enable_csi2_fclk;
1338 }
1339 return 0;
1340
1341out_clk_enable_csi2_fclk:
b057c3c3 1342 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1343out_clk_enable_mclk:
b057c3c3 1344 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7
SA		 1345out_clk_enable_ick:
1346 return r;
1347}
1348
1349/*
1350 * isp_disable_clocks - Disable ISP clocks
1351 * @isp: OMAP3 ISP device
1352 */
1353static void isp_disable_clocks(struct isp_device *isp)
1354{
b057c3c3
LP		 1355 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1356 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1357 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7
SA		 1358}
1359
1360static const char *isp_clocks[] = {
1361 "cam_ick",
1362 "cam_mclk",
448de7e7
SA		 1363 "csi2_96m_fck",
1364 "l3_ick",
1365};
1366
448de7e7
SA		 1367static int isp_get_clocks(struct isp_device *isp)
1368{
1369 struct clk *clk;
1370 unsigned int i;
1371
1372 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
cf2b4cf6 1373 clk = devm_clk_get(isp->dev, isp_clocks[i]);
448de7e7
SA		 1374 if (IS_ERR(clk)) {
1375 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
448de7e7
SA		 1376 return PTR_ERR(clk);
1377 }
1378
1379 isp->clock[i] = clk;
1380 }
1381
1382 return 0;
1383}
1384
1385/*
1386 * omap3isp_get - Acquire the ISP resource.
1387 *
1388 * Initializes the clocks for the first acquire.
1389 *
1390 * Increment the reference count on the ISP. If the first reference is taken,
1391 * enable clocks and power-up all submodules.
1392 *
25985edc 1393 * Return a pointer to the ISP device structure, or NULL if an error occurred.
448de7e7 1394 */
96d62ae2 1395static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
448de7e7
SA		 1396{
1397 struct isp_device *__isp = isp;
1398
1399 if (isp == NULL)
1400 return NULL;
1401
1402 mutex_lock(&isp->isp_mutex);
1403 if (isp->ref_count > 0)
1404 goto out;
1405
1406 if (isp_enable_clocks(isp) < 0) {
1407 __isp = NULL;
1408 goto out;
1409 }
1410
1411 /* We don't want to restore context before saving it! */
1412 if (isp->has_context)
1413 isp_restore_ctx(isp);
448de7e7 1414
96d62ae2
LP		 1415 if (irq)
1416 isp_enable_interrupts(isp);
448de7e7
SA		 1417
1418out:
1419 if (__isp != NULL)
1420 isp->ref_count++;
1421 mutex_unlock(&isp->isp_mutex);
1422
1423 return __isp;
1424}
1425
96d62ae2
LP		 1426struct isp_device *omap3isp_get(struct isp_device *isp)
1427{
1428 return __omap3isp_get(isp, true);
1429}
1430
448de7e7
SA		 1431/*
1432 * omap3isp_put - Release the ISP
1433 *
1434 * Decrement the reference count on the ISP. If the last reference is released,
1435 * power-down all submodules, disable clocks and free temporary buffers.
1436 */
2a0a5472 1437static void __omap3isp_put(struct isp_device *isp, bool save_ctx)
448de7e7
SA		 1438{
1439 if (isp == NULL)
1440 return;
1441
1442 mutex_lock(&isp->isp_mutex);
1443 BUG_ON(isp->ref_count == 0);
1444 if (--isp->ref_count == 0) {
1445 isp_disable_interrupts(isp);
2a0a5472 1446 if (save_ctx) {
a32f2f90 1447 isp_save_ctx(isp);
96d62ae2
LP		 1448 isp->has_context = 1;
1449 }
1567bb7d
LP		 1450 /* Reset the ISP if an entity has failed to stop. This is the
1451 * only way to recover from such conditions.
1452 */
17d3d405
SA		 1453 if (!media_entity_enum_empty(&isp->crashed) ||
1454 isp->stop_failure)
994d5375 1455 isp_reset(isp);
448de7e7
SA		 1456 isp_disable_clocks(isp);
1457 }
1458 mutex_unlock(&isp->isp_mutex);
1459}
1460
2a0a5472
LP		 1461void omap3isp_put(struct isp_device *isp)
1462{
1463 __omap3isp_put(isp, true);
1464}
1465
448de7e7
SA		 1466/* --------------------------------------------------------------------------
1467 * Platform device driver
1468 */
1469
1470/*
1471 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1472 * @isp: OMAP3 ISP device
1473 */
1474#define ISP_PRINT_REGISTER(isp, name)\
1475 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1476 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1477#define SBL_PRINT_REGISTER(isp, name)\
1478 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1479 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1480
1481void omap3isp_print_status(struct isp_device *isp)
1482{
1483 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1484
1485 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1486 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1487 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1488 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1489 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1490 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1491 ISP_PRINT_REGISTER(isp, CTRL);
1492 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1493 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1494 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1495 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1496 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1497 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1498 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1499 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1500
1501 SBL_PRINT_REGISTER(isp, PCR);
1502 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1503
1504 dev_dbg(isp->dev, "--------------------------------------------\n");
1505}
1506
1507#ifdef CONFIG_PM
1508
1509/*
1510 * Power management support.
1511 *
1512 * As the ISP can't properly handle an input video stream interruption on a non
1513 * frame boundary, the ISP pipelines need to be stopped before sensors get
1514 * suspended. However, as suspending the sensors can require a running clock,
1515 * which can be provided by the ISP, the ISP can't be completely suspended
1516 * before the sensor.
1517 *
1518 * To solve this problem power management support is split into prepare/complete
1519 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1520 * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
1521 * resume(), and the the pipelines are restarted in complete().
1522 *
39c1cb2b 1523 * TODO: PM dependencies between the ISP and sensors are not modelled explicitly
448de7e7
SA		 1524 * yet.
1525 */
1526static int isp_pm_prepare(struct device *dev)
1527{
1528 struct isp_device *isp = dev_get_drvdata(dev);
1529 int reset;
1530
1531 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1532
1533 if (isp->ref_count == 0)
1534 return 0;
1535
1536 reset = isp_suspend_modules(isp);
1537 isp_disable_interrupts(isp);
1538 isp_save_ctx(isp);
1539 if (reset)
1540 isp_reset(isp);
1541
1542 return 0;
1543}
1544
1545static int isp_pm_suspend(struct device *dev)
1546{
1547 struct isp_device *isp = dev_get_drvdata(dev);
1548
1549 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1550
1551 if (isp->ref_count)
1552 isp_disable_clocks(isp);
1553
1554 return 0;
1555}
1556
1557static int isp_pm_resume(struct device *dev)
1558{
1559 struct isp_device *isp = dev_get_drvdata(dev);
1560
1561 if (isp->ref_count == 0)
1562 return 0;
1563
1564 return isp_enable_clocks(isp);
1565}
1566
1567static void isp_pm_complete(struct device *dev)
1568{
1569 struct isp_device *isp = dev_get_drvdata(dev);
1570
1571 if (isp->ref_count == 0)
1572 return;
1573
1574 isp_restore_ctx(isp);
1575 isp_enable_interrupts(isp);
1576 isp_resume_modules(isp);
1577}
1578
1579#else
1580
1581#define isp_pm_prepare NULL
1582#define isp_pm_suspend NULL
1583#define isp_pm_resume NULL
1584#define isp_pm_complete NULL
1585
1586#endif /* CONFIG_PM */
1587
1588static void isp_unregister_entities(struct isp_device *isp)
1589{
30efae3d
SA		 1590 media_device_unregister(&isp->media_dev);
1591
448de7e7
SA		 1592 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1593 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1594 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1595 omap3isp_preview_unregister_entities(&isp->isp_prev);
1596 omap3isp_resizer_unregister_entities(&isp->isp_res);
1597 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1598 omap3isp_stat_unregister_entities(&isp->isp_af);
1599 omap3isp_stat_unregister_entities(&isp->isp_hist);
1600
1601 v4l2_device_unregister(&isp->v4l2_dev);
9832e155 1602 media_device_cleanup(&isp->media_dev);
448de7e7
SA		 1603}
1604
703e6f62
SA		 1605static int isp_link_entity(
1606 struct isp_device *isp, struct media_entity *entity,
1607 enum isp_interface_type interface)
1608{
1609 struct media_entity *input;
1610 unsigned int flags;
1611 unsigned int pad;
1612 unsigned int i;
1613
1614 /* Connect the sensor to the correct interface module.
1615 * Parallel sensors are connected directly to the CCDC, while
1616 * serial sensors are connected to the CSI2a, CCP2b or CSI2c
1617 * receiver through CSIPHY1 or CSIPHY2.
1618 */
1619 switch (interface) {
1620 case ISP_INTERFACE_PARALLEL:
1621 input = &isp->isp_ccdc.subdev.entity;
1622 pad = CCDC_PAD_SINK;
1623 flags = 0;
1624 break;
1625
1626 case ISP_INTERFACE_CSI2A_PHY2:
1627 input = &isp->isp_csi2a.subdev.entity;
1628 pad = CSI2_PAD_SINK;
1629 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1630 break;
1631
1632 case ISP_INTERFACE_CCP2B_PHY1:
1633 case ISP_INTERFACE_CCP2B_PHY2:
1634 input = &isp->isp_ccp2.subdev.entity;
1635 pad = CCP2_PAD_SINK;
1636 flags = 0;
1637 break;
1638
1639 case ISP_INTERFACE_CSI2C_PHY1:
1640 input = &isp->isp_csi2c.subdev.entity;
1641 pad = CSI2_PAD_SINK;
1642 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1643 break;
1644
1645 default:
1646 dev_err(isp->dev, "%s: invalid interface type %u\n", __func__,
1647 interface);
1648 return -EINVAL;
1649 }
1650
1651 /*
1652 * Not all interfaces are available on all revisions of the
1653 * ISP. The sub-devices of those interfaces aren't initialised
1654 * in such a case. Check this by ensuring the num_pads is
1655 * non-zero.
1656 */
1657 if (!input->num_pads) {
1658 dev_err(isp->dev, "%s: invalid input %u\n", entity->name,
1659 interface);
1660 return -EINVAL;
1661 }
1662
1663 for (i = 0; i < entity->num_pads; i++) {
1664 if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1665 break;
1666 }
1667 if (i == entity->num_pads) {
bce9e317
SA		 1668 dev_err(isp->dev, "%s: no source pad in external entity %s\n",
1669 __func__, entity->name);
703e6f62
SA		 1670 return -EINVAL;
1671 }
1672
8df00a15 1673 return media_create_pad_link(entity, i, input, pad, flags);
703e6f62
SA		 1674}
1675
448de7e7
SA		 1676static int isp_register_entities(struct isp_device *isp)
1677{
448de7e7
SA		 1678 int ret;
1679
1680 isp->media_dev.dev = isp->dev;
c0decac1 1681 strscpy(isp->media_dev.model, "TI OMAP3 ISP",
448de7e7 1682 sizeof(isp->media_dev.model));
083eb078 1683 isp->media_dev.hw_revision = isp->revision;
68429f50 1684 isp->media_dev.ops = &isp_media_ops;
9832e155 1685 media_device_init(&isp->media_dev);
448de7e7
SA		 1686
1687 isp->v4l2_dev.mdev = &isp->media_dev;
1688 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1689 if (ret < 0) {
4feca39b 1690 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
448de7e7
SA		 1691 __func__, ret);
1692 goto done;
1693 }
1694
1695 /* Register internal entities */
1696 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1697 if (ret < 0)
1698 goto done;
1699
1700 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1701 if (ret < 0)
1702 goto done;
1703
1704 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1705 if (ret < 0)
1706 goto done;
1707
1708 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1709 &isp->v4l2_dev);
1710 if (ret < 0)
1711 goto done;
1712
1713 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1714 if (ret < 0)
1715 goto done;
1716
1717 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1718 if (ret < 0)
1719 goto done;
1720
1721 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1722 if (ret < 0)
1723 goto done;
1724
1725 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1726 if (ret < 0)
1727 goto done;
1728
448de7e7 1729done:
5d479386 1730 if (ret < 0)
448de7e7
SA		 1731 isp_unregister_entities(isp);
1732
1733 return ret;
1734}
1735
f2f6da0d 1736/*
b285d5af 1737 * isp_create_links() - Create links for internal and external ISP entities
f2f6da0d 1738 * @isp : Pointer to ISP device
b285d5af
JMC		 1739 *
1740 * This function creates all links between ISP internal and external entities.
1741 *
1742 * Return: A negative error code on failure or zero on success. Possible error
1743 * codes are those returned by media_create_pad_link().
f2f6da0d 1744 */
b285d5af 1745static int isp_create_links(struct isp_device *isp)
f2f6da0d
JMC		 1746{
1747 int ret;
1748
b5f6df06
JMC		 1749 /* Create links between entities and video nodes. */
1750 ret = media_create_pad_link(
1751 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1752 &isp->isp_csi2a.video_out.video.entity, 0, 0);
1753 if (ret < 0)
f2f6da0d 1754 return ret;
f2f6da0d 1755
b5f6df06
JMC		 1756 ret = media_create_pad_link(
1757 &isp->isp_ccp2.video_in.video.entity, 0,
1758 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0);
1759 if (ret < 0)
f2f6da0d 1760 return ret;
f2f6da0d 1761
b5f6df06
JMC		 1762 ret = media_create_pad_link(
1763 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1764 &isp->isp_ccdc.video_out.video.entity, 0, 0);
1765 if (ret < 0)
f2f6da0d 1766 return ret;
f2f6da0d 1767
b5f6df06
JMC		 1768 ret = media_create_pad_link(
1769 &isp->isp_prev.video_in.video.entity, 0,
1770 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1771 if (ret < 0)
f2f6da0d 1772 return ret;
f2f6da0d 1773
b5f6df06
JMC		 1774 ret = media_create_pad_link(
1775 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1776 &isp->isp_prev.video_out.video.entity, 0, 0);
1777 if (ret < 0)
1778 return ret;
1779
1780 ret = media_create_pad_link(
1781 &isp->isp_res.video_in.video.entity, 0,
1782 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1783 if (ret < 0)
1784 return ret;
1785
1786 ret = media_create_pad_link(
1787 &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE,
1788 &isp->isp_res.video_out.video.entity, 0, 0);
1789
1790 if (ret < 0)
f2f6da0d 1791 return ret;
f2f6da0d 1792
b5f6df06 1793 /* Create links between entities. */
f2f6da0d
JMC		 1794 ret = media_create_pad_link(
1795 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1796 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1797 if (ret < 0)
1798 return ret;
1799
1800 ret = media_create_pad_link(
1801 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1802 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1803 if (ret < 0)
1804 return ret;
1805
1806 ret = media_create_pad_link(
1807 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1808 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1809 if (ret < 0)
1810 return ret;
1811
1812 ret = media_create_pad_link(
1813 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1814 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1815 if (ret < 0)
1816 return ret;
1817
1818 ret = media_create_pad_link(
1819 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1820 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1821 if (ret < 0)
1822 return ret;
1823
1824 ret = media_create_pad_link(
1825 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1826 &isp->isp_aewb.subdev.entity, 0,
1827 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1828 if (ret < 0)
1829 return ret;
1830
1831 ret = media_create_pad_link(
1832 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1833 &isp->isp_af.subdev.entity, 0,
1834 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1835 if (ret < 0)
1836 return ret;
1837
1838 ret = media_create_pad_link(
1839 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1840 &isp->isp_hist.subdev.entity, 0,
1841 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1842 if (ret < 0)
1843 return ret;
1844
1845 return 0;
1846}
1847
448de7e7
SA		 1848static void isp_cleanup_modules(struct isp_device *isp)
1849{
1850 omap3isp_h3a_aewb_cleanup(isp);
1851 omap3isp_h3a_af_cleanup(isp);
1852 omap3isp_hist_cleanup(isp);
1853 omap3isp_resizer_cleanup(isp);
1854 omap3isp_preview_cleanup(isp);
1855 omap3isp_ccdc_cleanup(isp);
1856 omap3isp_ccp2_cleanup(isp);
1857 omap3isp_csi2_cleanup(isp);
838a6c56 1858 omap3isp_csiphy_cleanup(isp);
448de7e7
SA		 1859}
1860
1861static int isp_initialize_modules(struct isp_device *isp)
1862{
1863 int ret;
1864
1865 ret = omap3isp_csiphy_init(isp);
1866 if (ret < 0) {
1867 dev_err(isp->dev, "CSI PHY initialization failed\n");
838a6c56 1868 return ret;
448de7e7
SA		 1869 }
1870
1871 ret = omap3isp_csi2_init(isp);
1872 if (ret < 0) {
1873 dev_err(isp->dev, "CSI2 initialization failed\n");
1874 goto error_csi2;
1875 }
1876
1877 ret = omap3isp_ccp2_init(isp);
1878 if (ret < 0) {
a4573084
PM		 1879 if (ret != -EPROBE_DEFER)
1880 dev_err(isp->dev, "CCP2 initialization failed\n");
448de7e7
SA		 1881 goto error_ccp2;
1882 }
1883
1884 ret = omap3isp_ccdc_init(isp);
1885 if (ret < 0) {
1886 dev_err(isp->dev, "CCDC initialization failed\n");
1887 goto error_ccdc;
1888 }
1889
1890 ret = omap3isp_preview_init(isp);
1891 if (ret < 0) {
1892 dev_err(isp->dev, "Preview initialization failed\n");
1893 goto error_preview;
1894 }
1895
1896 ret = omap3isp_resizer_init(isp);
1897 if (ret < 0) {
1898 dev_err(isp->dev, "Resizer initialization failed\n");
1899 goto error_resizer;
1900 }
1901
1902 ret = omap3isp_hist_init(isp);
1903 if (ret < 0) {
1904 dev_err(isp->dev, "Histogram initialization failed\n");
1905 goto error_hist;
1906 }
1907
1908 ret = omap3isp_h3a_aewb_init(isp);
1909 if (ret < 0) {
1910 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1911 goto error_h3a_aewb;
1912 }
1913
1914 ret = omap3isp_h3a_af_init(isp);
1915 if (ret < 0) {
1916 dev_err(isp->dev, "H3A AF initialization failed\n");
1917 goto error_h3a_af;
1918 }
1919
448de7e7
SA		 1920 return 0;
1921
448de7e7
SA		 1922error_h3a_af:
1923 omap3isp_h3a_aewb_cleanup(isp);
1924error_h3a_aewb:
1925 omap3isp_hist_cleanup(isp);
1926error_hist:
1927 omap3isp_resizer_cleanup(isp);
1928error_resizer:
1929 omap3isp_preview_cleanup(isp);
1930error_preview:
1931 omap3isp_ccdc_cleanup(isp);
1932error_ccdc:
1933 omap3isp_ccp2_cleanup(isp);
1934error_ccp2:
1935 omap3isp_csi2_cleanup(isp);
1936error_csi2:
838a6c56
SA		 1937 omap3isp_csiphy_cleanup(isp);
1938
448de7e7
SA		 1939 return ret;
1940}
1941
2a0a5472
LP		 1942static void isp_detach_iommu(struct isp_device *isp)
1943{
24313113 1944#ifdef CONFIG_ARM_DMA_USE_IOMMU
b7e1e685 1945 arm_iommu_detach_device(isp->dev);
2a0a5472
LP		 1946 arm_iommu_release_mapping(isp->mapping);
1947 isp->mapping = NULL;
24313113 1948#endif
2a0a5472
LP		 1949}
1950
1951static int isp_attach_iommu(struct isp_device *isp)
1952{
24313113 1953#ifdef CONFIG_ARM_DMA_USE_IOMMU
2a0a5472 1954 struct dma_iommu_mapping *mapping;
2a0a5472
LP		 1955 int ret;
1956
2a0a5472
LP		 1957 /*
1958 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
1959 * VAs. This will allocate a corresponding IOMMU domain.
1960 */
1961 mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
1962 if (IS_ERR(mapping)) {
1963 dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
b7e1e685 1964 return PTR_ERR(mapping);
2a0a5472
LP		 1965 }
1966
1967 isp->mapping = mapping;
1968
1969 /* Attach the ARM VA mapping to the device. */
1970 ret = arm_iommu_attach_device(isp->dev, mapping);
1971 if (ret < 0) {
1972 dev_err(isp->dev, "failed to attach device to VA mapping\n");
1973 goto error;
1974 }
1975
1976 return 0;
1977
1978error:
b7e1e685
SA		 1979 arm_iommu_release_mapping(isp->mapping);
1980 isp->mapping = NULL;
2a0a5472 1981 return ret;
24313113
AB		 1982#else
1983 return -ENODEV;
1984#endif
2a0a5472
LP		 1985}
1986
448de7e7
SA		 1987/*
1988 * isp_remove - Remove ISP platform device
1989 * @pdev: Pointer to ISP platform device
1990 *
1991 * Always returns 0.
1992 */
4c62e976 1993static int isp_remove(struct platform_device *pdev)
448de7e7
SA		 1994{
1995 struct isp_device *isp = platform_get_drvdata(pdev);
448de7e7 1996
da7f3843 1997 v4l2_async_notifier_unregister(&isp->notifier);
448de7e7
SA		 1998 isp_unregister_entities(isp);
1999 isp_cleanup_modules(isp);
9b28ee3c 2000 isp_xclk_cleanup(isp);
448de7e7 2001
96d62ae2 2002 __omap3isp_get(isp, false);
2a0a5472
LP		 2003 isp_detach_iommu(isp);
2004 __omap3isp_put(isp, false);
448de7e7 2005
17d3d405 2006 media_entity_enum_cleanup(&isp->crashed);
df497566 2007 v4l2_async_notifier_cleanup(&isp->notifier);
17d3d405 2008
448de7e7
SA		 2009 return 0;
2010}
2011
da7f3843
SA		 2012enum isp_of_phy {
2013 ISP_OF_PHY_PARALLEL = 0,
2014 ISP_OF_PHY_CSIPHY1,
2015 ISP_OF_PHY_CSIPHY2,
2016};
2017
df497566
SA		 2018static int isp_fwnode_parse(struct device *dev,
2019 struct v4l2_fwnode_endpoint *vep,
2020 struct v4l2_async_subdev *asd)
da7f3843 2021{
df497566
SA		 2022 struct isp_async_subdev *isd =
2023 container_of(asd, struct isp_async_subdev, asd);
da7f3843 2024 struct isp_bus_cfg *buscfg = &isd->bus;
9211434b 2025 bool csi1 = false;
df497566 2026 unsigned int i;
da7f3843 2027
68d9c47b 2028 dev_dbg(dev, "parsing endpoint %pOF, interface %u\n",
df497566 2029 to_of_node(vep->base.local_fwnode), vep->base.port);
da7f3843 2030
df497566 2031 switch (vep->base.port) {
da7f3843
SA		 2032 case ISP_OF_PHY_PARALLEL:
2033 buscfg->interface = ISP_INTERFACE_PARALLEL;
2034 buscfg->bus.parallel.data_lane_shift =
df497566 2035 vep->bus.parallel.data_shift;
da7f3843 2036 buscfg->bus.parallel.clk_pol =
df497566 2037 !!(vep->bus.parallel.flags
da7f3843
SA		 2038 & V4L2_MBUS_PCLK_SAMPLE_FALLING);
2039 buscfg->bus.parallel.hs_pol =
df497566 2040 !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
da7f3843 2041 buscfg->bus.parallel.vs_pol =
df497566 2042 !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
da7f3843 2043 buscfg->bus.parallel.fld_pol =
df497566 2044 !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW);
da7f3843 2045 buscfg->bus.parallel.data_pol =
df497566
SA		 2046 !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW);
2047 buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656;
da7f3843
SA		 2048 break;
2049
2050 case ISP_OF_PHY_CSIPHY1:
2051 case ISP_OF_PHY_CSIPHY2:
df497566 2052 switch (vep->bus_type) {
9211434b
PM		 2053 case V4L2_MBUS_CCP2:
2054 case V4L2_MBUS_CSI1:
2055 dev_dbg(dev, "CSI-1/CCP-2 configuration\n");
2056 csi1 = true;
2057 break;
2d95e7ed 2058 case V4L2_MBUS_CSI2_DPHY:
9211434b
PM		 2059 dev_dbg(dev, "CSI-2 configuration\n");
2060 csi1 = false;
2061 break;
2062 default:
2063 dev_err(dev, "unsupported bus type %u\n",
df497566 2064 vep->bus_type);
9211434b
PM		 2065 return -EINVAL;
2066 }
2067
df497566 2068 switch (vep->base.port) {
da7f3843 2069 case ISP_OF_PHY_CSIPHY1:
9211434b
PM		 2070 if (csi1)
2071 buscfg->interface = ISP_INTERFACE_CCP2B_PHY1;
2072 else
2073 buscfg->interface = ISP_INTERFACE_CSI2C_PHY1;
da7f3843
SA		 2074 break;
2075 case ISP_OF_PHY_CSIPHY2:
9211434b
PM		 2076 if (csi1)
2077 buscfg->interface = ISP_INTERFACE_CCP2B_PHY2;
2078 else
2079 buscfg->interface = ISP_INTERFACE_CSI2A_PHY2;
da7f3843
SA		 2080 break;
2081 }
9211434b
PM		 2082 if (csi1) {
2083 buscfg->bus.ccp2.lanecfg.clk.pos =
df497566 2084 vep->bus.mipi_csi1.clock_lane;
9211434b 2085 buscfg->bus.ccp2.lanecfg.clk.pol =
df497566 2086 vep->bus.mipi_csi1.lane_polarity[0];
9211434b
PM		 2087 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2088 buscfg->bus.ccp2.lanecfg.clk.pol,
2089 buscfg->bus.ccp2.lanecfg.clk.pos);
2090
2091 buscfg->bus.ccp2.lanecfg.data[0].pos =
df497566 2092 vep->bus.mipi_csi1.data_lane;
9211434b 2093 buscfg->bus.ccp2.lanecfg.data[0].pol =
df497566 2094 vep->bus.mipi_csi1.lane_polarity[1];
9211434b 2095
5160fb4b 2096 dev_dbg(dev, "data lane polarity %u, pos %u\n",
9211434b
PM		 2097 buscfg->bus.ccp2.lanecfg.data[0].pol,
2098 buscfg->bus.ccp2.lanecfg.data[0].pos);
2099
2100 buscfg->bus.ccp2.strobe_clk_pol =
df497566
SA		 2101 vep->bus.mipi_csi1.clock_inv;
2102 buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe;
9211434b 2103 buscfg->bus.ccp2.ccp2_mode =
df497566 2104 vep->bus_type == V4L2_MBUS_CCP2;
9211434b
PM		 2105 buscfg->bus.ccp2.vp_clk_pol = 1;
2106
2107 buscfg->bus.ccp2.crc = 1;
2108 } else {
2109 buscfg->bus.csi2.lanecfg.clk.pos =
df497566 2110 vep->bus.mipi_csi2.clock_lane;
9211434b 2111 buscfg->bus.csi2.lanecfg.clk.pol =
df497566 2112 vep->bus.mipi_csi2.lane_polarities[0];
9211434b
PM		 2113 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2114 buscfg->bus.csi2.lanecfg.clk.pol,
2115 buscfg->bus.csi2.lanecfg.clk.pos);
2116
2117 buscfg->bus.csi2.num_data_lanes =
df497566 2118 vep->bus.mipi_csi2.num_data_lanes;
9211434b
PM		 2119
2120 for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) {
2121 buscfg->bus.csi2.lanecfg.data[i].pos =
df497566 2122 vep->bus.mipi_csi2.data_lanes[i];
9211434b 2123 buscfg->bus.csi2.lanecfg.data[i].pol =
df497566 2124 vep->bus.mipi_csi2.lane_polarities[i + 1];
9211434b
PM		 2125 dev_dbg(dev,
2126 "data lane %u polarity %u, pos %u\n", i,
2127 buscfg->bus.csi2.lanecfg.data[i].pol,
2128 buscfg->bus.csi2.lanecfg.data[i].pos);
2129 }
2130 /*
2131 * FIXME: now we assume the CRC is always there.
2132 * Implement a way to obtain this information from the
2133 * sensor. Frame descriptors, perhaps?
2134 */
2135 buscfg->bus.csi2.crc = 1;
da7f3843 2136 }
da7f3843
SA		 2137 break;
2138
2139 default:
68d9c47b 2140 dev_warn(dev, "%pOF: invalid interface %u\n",
df497566 2141 to_of_node(vep->base.local_fwnode), vep->base.port);
831f3494 2142 return -EINVAL;
da7f3843
SA		 2143 }
2144
2145 return 0;
2146}
2147
da7f3843
SA		 2148static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
2149{
2150 struct isp_device *isp = container_of(async, struct isp_device,
2151 notifier);
68a57fa9
JMC		 2152 struct v4l2_device *v4l2_dev = &isp->v4l2_dev;
2153 struct v4l2_subdev *sd;
68a57fa9
JMC		 2154 int ret;
2155
17d3d405
SA		 2156 ret = media_entity_enum_init(&isp->crashed, &isp->media_dev);
2157 if (ret)
2158 return ret;
2159
68a57fa9 2160 list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
eae4cf8f 2161 if (sd->notifier != &isp->notifier)
02b1ce92
SA		 2162 continue;
2163
2164 ret = isp_link_entity(isp, &sd->entity,
2165 v4l2_subdev_to_bus_cfg(sd)->interface);
2166 if (ret < 0)
2167 return ret;
68a57fa9 2168 }
da7f3843 2169
9832e155
JMC		 2170 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
2171 if (ret < 0)
2172 return ret;
2173
2174 return media_device_register(&isp->media_dev);
da7f3843
SA		 2175}
2176
b6ee3f0d
LP		 2177static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
2178 .complete = isp_subdev_notifier_complete,
2179};
2180
448de7e7
SA		 2181/*
2182 * isp_probe - Probe ISP platform device
2183 * @pdev: Pointer to ISP platform device
2184 *
2185 * Returns 0 if successful,
2186 * -ENOMEM if no memory available,
2187 * -ENODEV if no platform device resources found
2188 * or no space for remapping registers,
2189 * -EINVAL if couldn't install ISR,
2190 * or clk_get return error value.
2191 */
4c62e976 2192static int isp_probe(struct platform_device *pdev)
448de7e7 2193{
448de7e7 2194 struct isp_device *isp;
8644cdf9 2195 struct resource *mem;
448de7e7
SA		 2196 int ret;
2197 int i, m;
2198
cf2b4cf6 2199 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
448de7e7
SA		 2200 if (!isp) {
2201 dev_err(&pdev->dev, "could not allocate memory\n");
2202 return -ENOMEM;
2203 }
2204
859969b3
SA		 2205 ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node),
2206 "ti,phy-type", &isp->phy_type);
78c66fbc
LP		 2207 if (ret)
2208 return ret;
da7f3843 2209
78c66fbc
LP		 2210 isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2211 "syscon");
2212 if (IS_ERR(isp->syscon))
2213 return PTR_ERR(isp->syscon);
da7f3843 2214
859969b3
SA		 2215 ret = of_property_read_u32_index(pdev->dev.of_node,
2216 "syscon", 1, &isp->syscon_offset);
78c66fbc
LP		 2217 if (ret)
2218 return ret;
da7f3843 2219
448de7e7 2220 isp->autoidle = autoidle;
448de7e7
SA		 2221
2222 mutex_init(&isp->isp_mutex);
2223 spin_lock_init(&isp->stat_lock);
eae2aed1 2224 v4l2_async_notifier_init(&isp->notifier);
448de7e7 2225
df497566
SA		 2226 ret = v4l2_async_notifier_parse_fwnode_endpoints(
2227 &pdev->dev, &isp->notifier, sizeof(struct isp_async_subdev),
2228 isp_fwnode_parse);
2229 if (ret < 0)
2230 goto error;
2231
448de7e7 2232 isp->dev = &pdev->dev;
448de7e7
SA		 2233 isp->ref_count = 0;
2234
224ddca0
RK		 2235 ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32));
2236 if (ret)
697cca21 2237 goto error;
448de7e7
SA		 2238
2239 platform_set_drvdata(pdev, isp);
2240
2241 /* Regulators */
3494bb05
SA		 2242 isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1");
2243 isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2");
448de7e7 2244
d8658bca
LP		 2245 /* Clocks
2246 *
2247 * The ISP clock tree is revision-dependent. We thus need to enable ICLK
2248 * manually to read the revision before calling __omap3isp_get().
8644cdf9
SA		 2249 *
2250 * Start by mapping the ISP MMIO area, which is in two pieces.
2251 * The ISP IOMMU is in between. Map both now, and fill in the
2252 * ISP revision specific portions a little later in the
2253 * function.
d8658bca 2254 */
8644cdf9
SA		 2255 for (i = 0; i < 2; i++) {
2256 unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
2257
2258 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
2259 isp->mmio_base[map_idx] =
2260 devm_ioremap_resource(isp->dev, mem);
2261 if (IS_ERR(isp->mmio_base[map_idx]))
2262 return PTR_ERR(isp->mmio_base[map_idx]);
2263 }
448de7e7
SA		 2264
2265 ret = isp_get_clocks(isp);
2266 if (ret < 0)
2267 goto error;
2268
d8658bca
LP		 2269 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
2270 if (ret < 0)
2271 goto error;
2272
2273 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2274 dev_info(isp->dev, "Revision %d.%d found\n",
2275 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2276
2277 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
2278
0bd0dbee
PST		 2279 if (__omap3isp_get(isp, false) == NULL) {
2280 ret = -ENODEV;
448de7e7 2281 goto error;
0bd0dbee 2282 }
448de7e7
SA		 2283
2284 ret = isp_reset(isp);
2285 if (ret < 0)
2286 goto error_isp;
2287
9b28ee3c
LP		 2288 ret = isp_xclk_init(isp);
2289 if (ret < 0)
2290 goto error_isp;
2291
448de7e7 2292 /* Memory resources */
448de7e7
SA		 2293 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2294 if (isp->revision == isp_res_maps[m].isp_rev)
2295 break;
2296
2297 if (m == ARRAY_SIZE(isp_res_maps)) {
2298 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2299 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2300 ret = -ENODEV;
2301 goto error_isp;
2302 }
2303
8644cdf9
SA		 2304 for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
2305 isp->mmio_base[i] =
2306 isp->mmio_base[0] + isp_res_maps[m].offset[i];
2307
2308 for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
2309 isp->mmio_base[i] =
2310 isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
2311 + isp_res_maps[m].offset[i];
2312
2313 isp->mmio_hist_base_phys =
2314 mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
448de7e7 2315
2a0a5472
LP		 2316 /* IOMMU */
2317 ret = isp_attach_iommu(isp);
2318 if (ret < 0) {
2319 dev_err(&pdev->dev, "unable to attach to IOMMU\n");
f626b52d
OBC		 2320 goto error_isp;
2321 }
2322
448de7e7 2323 /* Interrupt */
514580f9
AH		 2324 ret = platform_get_irq(pdev, 0);
2325 if (ret <= 0) {
448de7e7
SA		 2326 dev_err(isp->dev, "No IRQ resource\n");
2327 ret = -ENODEV;
2a0a5472 2328 goto error_iommu;
448de7e7 2329 }
514580f9 2330 isp->irq_num = ret;
448de7e7 2331
cf2b4cf6
LP		 2332 if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED,
2333 "OMAP3 ISP", isp)) {
448de7e7
SA		 2334 dev_err(isp->dev, "Unable to request IRQ\n");
2335 ret = -EINVAL;
2a0a5472 2336 goto error_iommu;
448de7e7
SA		 2337 }
2338
2339 /* Entities */
2340 ret = isp_initialize_modules(isp);
2341 if (ret < 0)
2a0a5472 2342 goto error_iommu;
448de7e7
SA		 2343
2344 ret = isp_register_entities(isp);
2345 if (ret < 0)
2346 goto error_modules;
2347
b285d5af 2348 ret = isp_create_links(isp);
f2f6da0d
JMC		 2349 if (ret < 0)
2350 goto error_register_entities;
2351
b6ee3f0d 2352 isp->notifier.ops = &isp_subdev_notifier_ops;
5d479386 2353
78c66fbc
LP		 2354 ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
2355 if (ret)
2356 goto error_register_entities;
5d479386 2357
96d62ae2 2358 isp_core_init(isp, 1);
448de7e7
SA		 2359 omap3isp_put(isp);
2360
2361 return 0;
2362
5d479386
SA		 2363error_register_entities:
2364 isp_unregister_entities(isp);
448de7e7
SA		 2365error_modules:
2366 isp_cleanup_modules(isp);
2a0a5472
LP		 2367error_iommu:
2368 isp_detach_iommu(isp);
448de7e7 2369error_isp:
9b28ee3c 2370 isp_xclk_cleanup(isp);
2a0a5472 2371 __omap3isp_put(isp, false);
448de7e7 2372error:
df497566 2373 v4l2_async_notifier_cleanup(&isp->notifier);
ed33ac8e 2374 mutex_destroy(&isp->isp_mutex);
448de7e7
SA		 2375
2376 return ret;
2377}
2378
2379static const struct dev_pm_ops omap3isp_pm_ops = {
2380 .prepare = isp_pm_prepare,
2381 .suspend = isp_pm_suspend,
2382 .resume = isp_pm_resume,
2383 .complete = isp_pm_complete,
2384};
2385
2386static struct platform_device_id omap3isp_id_table[] = {
2387 { "omap3isp", 0 },
2388 { },
2389};
2390MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2391
da7f3843
SA		 2392static const struct of_device_id omap3isp_of_table[] = {
2393 { .compatible = "ti,omap3-isp" },
2394 { },
2395};
8163ec29 2396MODULE_DEVICE_TABLE(of, omap3isp_of_table);
da7f3843 2397
448de7e7
SA		 2398static struct platform_driver omap3isp_driver = {
2399 .probe = isp_probe,
4c62e976 2400 .remove = isp_remove,
448de7e7
SA		 2401 .id_table = omap3isp_id_table,
2402 .driver = {
448de7e7
SA		 2403 .name = "omap3isp",
2404 .pm = &omap3isp_pm_ops,
da7f3843 2405 .of_match_table = omap3isp_of_table,
448de7e7
SA		 2406 },
2407};
2408
1d6629b1 2409module_platform_driver(omap3isp_driver);
448de7e7
SA		 2410
2411MODULE_AUTHOR("Nokia Corporation");
2412MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2413MODULE_LICENSE("GPL");
64dc3c1a 2414MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);
Empty description
This page took 0.941926 seconds and 4 git commands to generate.