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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / media / i2c / tc358743.c
CommitLineData
55e5927e 1// SPDX-License-Identifier: GPL-2.0-only
d32d9864
MR		 2/*
3 * tc358743 - Toshiba HDMI to CSI-2 bridge
4 *
5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
6 * reserved.
d32d9864
MR		 7 */
8
9/*
10 * References (c = chapter, p = page):
11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/slab.h>
18#include <linux/i2c.h>
25614824 19#include <linux/clk.h>
d32d9864 20#include <linux/delay.h>
25614824 21#include <linux/gpio/consumer.h>
d747b806 22#include <linux/interrupt.h>
4e66a52a 23#include <linux/timer.h>
859969b3 24#include <linux/of_graph.h>
d32d9864
MR		 25#include <linux/videodev2.h>
26#include <linux/workqueue.h>
27#include <linux/v4l2-dv-timings.h>
28#include <linux/hdmi.h>
a0ec8d1d 29#include <media/cec.h>
d32d9864
MR		 30#include <media/v4l2-dv-timings.h>
31#include <media/v4l2-device.h>
32#include <media/v4l2-ctrls.h>
1140f919 33#include <media/v4l2-event.h>
859969b3 34#include <media/v4l2-fwnode.h>
b5dcee22 35#include <media/i2c/tc358743.h>
d32d9864
MR		 36
37#include "tc358743_regs.h"
38
39static int debug;
40module_param(debug, int, 0644);
41MODULE_PARM_DESC(debug, "debug level (0-3)");
42
43MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
44MODULE_AUTHOR("Ramakrishnan Muthukrishnan <[email protected]>");
45MODULE_AUTHOR("Mikhail Khelik <[email protected]>");
46MODULE_AUTHOR("Mats Randgaard <[email protected]>");
47MODULE_LICENSE("GPL");
48
49#define EDID_NUM_BLOCKS_MAX 8
50#define EDID_BLOCK_SIZE 128
51
fcae73fa 52#define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
1d88f831 53
a0ec8d1d 54#define POLL_INTERVAL_CEC_MS 10
4e66a52a
DS		 55#define POLL_INTERVAL_MS 1000
56
d32d9864
MR		 57static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
58 .type = V4L2_DV_BT_656_1120,
59 /* keep this initialization for compatibility with GCC < 4.4.6 */
60 .reserved = { 0 },
61 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
62 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
63 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
64 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
65 V4L2_DV_BT_CAP_PROGRESSIVE |
66 V4L2_DV_BT_CAP_REDUCED_BLANKING |
67 V4L2_DV_BT_CAP_CUSTOM)
68};
69
70struct tc358743_state {
71 struct tc358743_platform_data pdata;
859969b3 72 struct v4l2_fwnode_bus_mipi_csi2 bus;
d32d9864
MR		 73 struct v4l2_subdev sd;
74 struct media_pad pad;
75 struct v4l2_ctrl_handler hdl;
76 struct i2c_client *i2c_client;
77 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
78 struct mutex confctl_mutex;
79
80 /* controls */
81 struct v4l2_ctrl *detect_tx_5v_ctrl;
82 struct v4l2_ctrl *audio_sampling_rate_ctrl;
83 struct v4l2_ctrl *audio_present_ctrl;
84
d32d9864
MR		 85 struct delayed_work delayed_work_enable_hotplug;
86
4e66a52a
DS		 87 struct timer_list timer;
88 struct work_struct work_i2c_poll;
89
d32d9864
MR		 90 /* edid */
91 u8 edid_blocks_written;
92
93 struct v4l2_dv_timings timings;
94 u32 mbus_fmt_code;
59e34ba8 95 u8 csi_lanes_in_use;
25614824
PZ		 96
97 struct gpio_desc *reset_gpio;
a0ec8d1d
HV		 98
99 struct cec_adapter *cec_adap;
d32d9864
MR		 100};
101
102static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
103 bool cable_connected);
104static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
105
106static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
107{
108 return container_of(sd, struct tc358743_state, sd);
109}
110
111/* --------------- I2C --------------- */
112
113static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
114{
115 struct tc358743_state *state = to_state(sd);
116 struct i2c_client *client = state->i2c_client;
117 int err;
118 u8 buf[2] = { reg >> 8, reg & 0xff };
119 struct i2c_msg msgs[] = {
120 {
121 .addr = client->addr,
122 .flags = 0,
123 .len = 2,
124 .buf = buf,
125 },
126 {
127 .addr = client->addr,
128 .flags = I2C_M_RD,
129 .len = n,
130 .buf = values,
131 },
132 };
133
134 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
135 if (err != ARRAY_SIZE(msgs)) {
136 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
137 __func__, reg, client->addr);
138 }
139}
140
141static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
142{
143 struct tc358743_state *state = to_state(sd);
144 struct i2c_client *client = state->i2c_client;
145 int err, i;
146 struct i2c_msg msg;
fcae73fa 147 u8 data[I2C_MAX_XFER_SIZE];
1d88f831 148
fcae73fa
MR		 149 if ((2 + n) > I2C_MAX_XFER_SIZE) {
150 n = I2C_MAX_XFER_SIZE - 2;
1d88f831
MCC		 151 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
152 reg, 2 + n);
fcae73fa 153 }
d32d9864
MR		 154
155 msg.addr = client->addr;
156 msg.buf = data;
157 msg.len = 2 + n;
158 msg.flags = 0;
159
160 data[0] = reg >> 8;
161 data[1] = reg & 0xff;
162
163 for (i = 0; i < n; i++)
164 data[2 + i] = values[i];
165
166 err = i2c_transfer(client->adapter, &msg, 1);
167 if (err != 1) {
168 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
169 __func__, reg, client->addr);
170 return;
171 }
172
173 if (debug < 3)
174 return;
175
176 switch (n) {
177 case 1:
178 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
179 reg, data[2]);
180 break;
181 case 2:
182 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
183 reg, data[3], data[2]);
184 break;
185 case 4:
186 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
187 reg, data[5], data[4], data[3], data[2]);
188 break;
189 default:
190 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
191 n, reg);
192 }
193}
194
3538aa6e 195static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
d32d9864 196{
3538aa6e 197 __le32 val = 0;
d32d9864 198
3538aa6e 199 i2c_rd(sd, reg, (u8 __force *)&val, n);
d32d9864 200
3538aa6e
AB		 201 return le32_to_cpu(val);
202}
203
204static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
205{
206 __le32 raw = cpu_to_le32(val);
207
208 i2c_wr(sd, reg, (u8 __force *)&raw, n);
209}
210
211static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
212{
213 return i2c_rdreg(sd, reg, 1);
d32d9864
MR		 214}
215
216static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
217{
3538aa6e 218 i2c_wrreg(sd, reg, val, 1);
d32d9864
MR		 219}
220
221static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
222 u8 mask, u8 val)
223{
f2c61f98 224 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
d32d9864
MR		 225}
226
227static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
228{
3538aa6e 229 return i2c_rdreg(sd, reg, 2);
d32d9864
MR		 230}
231
232static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
233{
3538aa6e 234 i2c_wrreg(sd, reg, val, 2);
d32d9864
MR		 235}
236
237static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
238{
3538aa6e 239 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
d32d9864
MR		 240}
241
242static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
243{
3538aa6e 244 return i2c_rdreg(sd, reg, 4);
d32d9864
MR		 245}
246
247static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
248{
3538aa6e 249 i2c_wrreg(sd, reg, val, 4);
d32d9864
MR		 250}
251
252/* --------------- STATUS --------------- */
253
254static inline bool is_hdmi(struct v4l2_subdev *sd)
255{
256 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
257}
258
259static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
260{
261 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
262}
263
264static inline bool no_signal(struct v4l2_subdev *sd)
265{
266 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
267}
268
269static inline bool no_sync(struct v4l2_subdev *sd)
270{
271 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
272}
273
274static inline bool audio_present(struct v4l2_subdev *sd)
275{
276 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
277}
278
279static int get_audio_sampling_rate(struct v4l2_subdev *sd)
280{
281 static const int code_to_rate[] = {
282 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
283 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
284 };
285
286 /* Register FS_SET is not cleared when the cable is disconnected */
287 if (no_signal(sd))
288 return 0;
289
290 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
291}
292
d32d9864
MR		 293/* --------------- TIMINGS --------------- */
294
295static inline unsigned fps(const struct v4l2_bt_timings *t)
296{
297 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
298 return 0;
299
300 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
301 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
302}
303
304static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
305 struct v4l2_dv_timings *timings)
306{
307 struct v4l2_bt_timings *bt = &timings->bt;
308 unsigned width, height, frame_width, frame_height, frame_interval, fps;
309
310 memset(timings, 0, sizeof(struct v4l2_dv_timings));
311
312 if (no_signal(sd)) {
313 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
314 return -ENOLINK;
315 }
316 if (no_sync(sd)) {
317 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
318 return -ENOLCK;
319 }
320
321 timings->type = V4L2_DV_BT_656_1120;
322 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
323 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
324
325 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
326 i2c_rd8(sd, DE_WIDTH_H_LO);
327 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
328 i2c_rd8(sd, DE_WIDTH_V_LO);
329 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
330 i2c_rd8(sd, H_SIZE_LO);
331 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
332 i2c_rd8(sd, V_SIZE_LO)) / 2;
333 /* frame interval in milliseconds * 10
334 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
335 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
336 i2c_rd8(sd, FV_CNT_LO);
337 fps = (frame_interval > 0) ?
338 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
339
340 bt->width = width;
341 bt->height = height;
342 bt->vsync = frame_height - height;
343 bt->hsync = frame_width - width;
344 bt->pixelclock = frame_width * frame_height * fps;
345 if (bt->interlaced == V4L2_DV_INTERLACED) {
346 bt->height *= 2;
347 bt->il_vsync = bt->vsync + 1;
348 bt->pixelclock /= 2;
349 }
350
351 return 0;
352}
353
354/* --------------- HOTPLUG / HDCP / EDID --------------- */
355
356static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
357{
358 struct delayed_work *dwork = to_delayed_work(work);
359 struct tc358743_state *state = container_of(dwork,
360 struct tc358743_state, delayed_work_enable_hotplug);
361 struct v4l2_subdev *sd = &state->sd;
362
363 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
364
365 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
366}
367
368static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
369{
370 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
371 "enable" : "disable");
372
0a1f0850
MR		 373 if (enable) {
374 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
375
376 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
377
378 i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
379 MASK_AUTH_UNAUTH_SEL_16_FRAMES |
380 MASK_AUTH_UNAUTH_AUTO);
381
382 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
383 SET_AUTO_P3_RESET_FRAMES(0x0f));
384 } else {
385 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
386 MASK_MANUAL_AUTHENTICATION);
387 }
d32d9864
MR		 388}
389
390static void tc358743_disable_edid(struct v4l2_subdev *sd)
391{
392 struct tc358743_state *state = to_state(sd);
393
394 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
395
396 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
397
398 /* DDC access to EDID is also disabled when hotplug is disabled. See
399 * register DDC_CTL */
400 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
401}
402
403static void tc358743_enable_edid(struct v4l2_subdev *sd)
404{
405 struct tc358743_state *state = to_state(sd);
406
407 if (state->edid_blocks_written == 0) {
408 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
676c002a 409 tc358743_s_ctrl_detect_tx_5v(sd);
d32d9864
MR		 410 return;
411 }
412
413 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
414
415 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
416 * hotplug is enabled. See register DDC_CTL */
1ce39546 417 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
d32d9864
MR		 418
419 tc358743_enable_interrupts(sd, true);
420 tc358743_s_ctrl_detect_tx_5v(sd);
421}
422
423static void tc358743_erase_bksv(struct v4l2_subdev *sd)
424{
425 int i;
426
427 for (i = 0; i < 5; i++)
428 i2c_wr8(sd, BKSV + i, 0);
429}
430
431/* --------------- AVI infoframe --------------- */
432
433static void print_avi_infoframe(struct v4l2_subdev *sd)
434{
435 struct i2c_client *client = v4l2_get_subdevdata(sd);
436 struct device *dev = &client->dev;
437 union hdmi_infoframe frame;
438 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
439
440 if (!is_hdmi(sd)) {
441 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
442 return;
443 }
444
445 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
446
447 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
448 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
449 return;
450 }
451
452 hdmi_infoframe_log(KERN_INFO, dev, &frame);
453}
454
455/* --------------- CTRLS --------------- */
456
457static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
458{
459 struct tc358743_state *state = to_state(sd);
460
461 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
462 tx_5v_power_present(sd));
463}
464
465static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
466{
467 struct tc358743_state *state = to_state(sd);
468
469 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
470 get_audio_sampling_rate(sd));
471}
472
473static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
474{
475 struct tc358743_state *state = to_state(sd);
476
477 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
478 audio_present(sd));
479}
480
481static int tc358743_update_controls(struct v4l2_subdev *sd)
482{
483 int ret = 0;
484
485 ret |= tc358743_s_ctrl_detect_tx_5v(sd);
486 ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
487 ret |= tc358743_s_ctrl_audio_present(sd);
488
489 return ret;
490}
491
492/* --------------- INIT --------------- */
493
494static void tc358743_reset_phy(struct v4l2_subdev *sd)
495{
496 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
497
498 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
499 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
500}
501
502static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
503{
504 u16 sysctl = i2c_rd16(sd, SYSCTL);
505
506 i2c_wr16(sd, SYSCTL, sysctl | mask);
507 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
508}
509
510static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
511{
512 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
513 enable ? MASK_SLEEP : 0);
514}
515
516static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
517{
518 struct tc358743_state *state = to_state(sd);
519
520 v4l2_dbg(3, debug, sd, "%s: %sable\n",
521 __func__, enable ? "en" : "dis");
522
523 if (enable) {
524 /* It is critical for CSI receiver to see lane transition
525 * LP11->HS. Set to non-continuous mode to enable clock lane
526 * LP11 state. */
527 i2c_wr32(sd, TXOPTIONCNTRL, 0);
528 /* Set to continuous mode to trigger LP11->HS transition */
529 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
530 /* Unmute video */
531 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
532 } else {
533 /* Mute video so that all data lanes go to LSP11 state.
534 * No data is output to CSI Tx block. */
535 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
536 }
537
538 mutex_lock(&state->confctl_mutex);
539 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
540 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
541 mutex_unlock(&state->confctl_mutex);
542}
543
544static void tc358743_set_pll(struct v4l2_subdev *sd)
545{
546 struct tc358743_state *state = to_state(sd);
547 struct tc358743_platform_data *pdata = &state->pdata;
548 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
549 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
550 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
551 SET_PLL_FBD(pdata->pll_fbd);
552 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
553
554 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
555
556 /* Only rewrite when needed (new value or disabled), since rewriting
557 * triggers another format change event. */
558 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
559 u16 pll_frs;
560
561 if (hsck > 500000000)
562 pll_frs = 0x0;
563 else if (hsck > 250000000)
564 pll_frs = 0x1;
565 else if (hsck > 125000000)
566 pll_frs = 0x2;
567 else
568 pll_frs = 0x3;
569
570 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
571 tc358743_sleep_mode(sd, true);
572 i2c_wr16(sd, PLLCTL0, pllctl0_new);
573 i2c_wr16_and_or(sd, PLLCTL1,
574 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
575 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
576 MASK_PLL_EN));
577 udelay(10); /* REF_02, Sheet "Source HDMI" */
578 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
579 tc358743_sleep_mode(sd, false);
580 }
581}
582
583static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
584{
585 struct tc358743_state *state = to_state(sd);
586 struct tc358743_platform_data *pdata = &state->pdata;
587 u32 sys_freq;
588 u32 lockdet_ref;
a0ec8d1d 589 u32 cec_freq;
d32d9864
MR		 590 u16 fh_min;
591 u16 fh_max;
592
593 BUG_ON(!(pdata->refclk_hz == 26000000 ||
594 pdata->refclk_hz == 27000000 ||
595 pdata->refclk_hz == 42000000));
596
597 sys_freq = pdata->refclk_hz / 10000;
598 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
599 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
600
601 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
602 (pdata->refclk_hz == 42000000) ?
603 MASK_PHY_SYSCLK_IND : 0x0);
604
605 fh_min = pdata->refclk_hz / 100000;
606 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
607 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
608
609 fh_max = (fh_min * 66) / 10;
610 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
611 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
612
613 lockdet_ref = pdata->refclk_hz / 100;
614 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
615 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
616 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
617
618 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
619 (pdata->refclk_hz == 27000000) ?
620 MASK_NCO_F0_MOD_27MHZ : 0x0);
a0ec8d1d
HV		 621
622 /*
623 * Trial and error suggests that the default register value
624 * of 656 is for a 42 MHz reference clock. Use that to derive
625 * a new value based on the actual reference clock.
626 */
627 cec_freq = (656 * sys_freq) / 4200;
628 i2c_wr16(sd, CECHCLK, cec_freq);
629 i2c_wr16(sd, CECLCLK, cec_freq);
d32d9864
MR		 630}
631
632static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
633{
634 struct tc358743_state *state = to_state(sd);
635
636 switch (state->mbus_fmt_code) {
637 case MEDIA_BUS_FMT_UYVY8_1X16:
638 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
639 i2c_wr8_and_or(sd, VOUT_SET2,
640 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
641 MASK_SEL422 | MASK_VOUT_422FIL_100);
642 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
643 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
644 mutex_lock(&state->confctl_mutex);
645 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
646 MASK_YCBCRFMT_422_8_BIT);
647 mutex_unlock(&state->confctl_mutex);
648 break;
649 case MEDIA_BUS_FMT_RGB888_1X24:
650 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
651 i2c_wr8_and_or(sd, VOUT_SET2,
652 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
653 0x00);
654 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
655 MASK_VOUT_COLOR_RGB_FULL);
656 mutex_lock(&state->confctl_mutex);
657 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
658 mutex_unlock(&state->confctl_mutex);
659 break;
660 default:
661 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
662 __func__, state->mbus_fmt_code);
663 }
664}
665
666static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
667{
668 struct tc358743_state *state = to_state(sd);
669 struct v4l2_bt_timings *bt = &state->timings.bt;
670 struct tc358743_platform_data *pdata = &state->pdata;
671 u32 bits_pr_pixel =
672 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
673 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
674 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
675
676 return DIV_ROUND_UP(bps, bps_pr_lane);
677}
678
679static void tc358743_set_csi(struct v4l2_subdev *sd)
680{
681 struct tc358743_state *state = to_state(sd);
682 struct tc358743_platform_data *pdata = &state->pdata;
683 unsigned lanes = tc358743_num_csi_lanes_needed(sd);
684
685 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
686
59e34ba8
MR		 687 state->csi_lanes_in_use = lanes;
688
d32d9864
MR		 689 tc358743_reset(sd, MASK_CTXRST);
690
691 if (lanes < 1)
692 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
693 if (lanes < 1)
694 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
695 if (lanes < 2)
696 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
697 if (lanes < 3)
698 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
699 if (lanes < 4)
700 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
701
702 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
703 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
704 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
705 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
706 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
707 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
708 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
709 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
710 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
711
712 i2c_wr32(sd, HSTXVREGEN,
713 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
714 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
715 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
716 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
717 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
718
25614824
PZ		 719 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
720 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
d32d9864
MR		 721 i2c_wr32(sd, STARTCNTRL, MASK_START);
722 i2c_wr32(sd, CSI_START, MASK_STRT);
723
724 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
725 MASK_ADDRESS_CSI_CONTROL |
726 MASK_CSI_MODE |
727 MASK_TXHSMD |
728 ((lanes == 4) ? MASK_NOL_4 :
729 (lanes == 3) ? MASK_NOL_3 :
730 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
731
732 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
733 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
734 MASK_WCER | MASK_INER);
735
736 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
737 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
738
739 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
740 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
741}
742
743static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
744{
745 struct tc358743_state *state = to_state(sd);
746 struct tc358743_platform_data *pdata = &state->pdata;
747
748 /* Default settings from REF_02, sheet "Source HDMI"
749 * and custom settings as platform data */
750 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
751 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
752 SET_FREQ_RANGE_MODE_CYCLES(1));
753 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
754 (pdata->hdmi_phy_auto_reset_tmds_detected ?
755 MASK_PHY_AUTO_RST2 : 0) |
756 (pdata->hdmi_phy_auto_reset_tmds_in_range ?
757 MASK_PHY_AUTO_RST3 : 0) |
758 (pdata->hdmi_phy_auto_reset_tmds_valid ?
759 MASK_PHY_AUTO_RST4 : 0));
760 i2c_wr8(sd, PHY_BIAS, 0x40);
761 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
762 i2c_wr8(sd, AVM_CTL, 45);
763 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
764 pdata->hdmi_detection_delay << 4);
765 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
766 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
767 MASK_H_PI_RST : 0) |
768 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
769 MASK_V_PI_RST : 0));
770 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
771}
772
773static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
774{
775 struct tc358743_state *state = to_state(sd);
776
777 /* Default settings from REF_02, sheet "Source HDMI" */
778 i2c_wr8(sd, FORCE_MUTE, 0x00);
779 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
780 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
781 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
782 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
783 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
784 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
785 i2c_wr8(sd, FS_MUTE, 0x00);
786 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
787 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
788 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
789 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
790 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
791 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
792
793 mutex_lock(&state->confctl_mutex);
794 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
795 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
796 mutex_unlock(&state->confctl_mutex);
797}
798
799static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
800{
801 /* Default settings from REF_02, sheet "Source HDMI" */
802 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
803 MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
804 MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
805 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
806 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
807 i2c_wr8(sd, NO_PKT_CLR, 0x53);
808 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
809 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
810 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
811}
812
813static void tc358743_initial_setup(struct v4l2_subdev *sd)
814{
815 struct tc358743_state *state = to_state(sd);
816 struct tc358743_platform_data *pdata = &state->pdata;
817
a0ec8d1d
HV		 818 /*
819 * IR is not supported by this driver.
820 * CEC is only enabled if needed.
821 */
822 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
823 (MASK_IRRST | MASK_CECRST));
d32d9864
MR		 824
825 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
a0ec8d1d
HV		 826#ifdef CONFIG_VIDEO_TC358743_CEC
827 tc358743_reset(sd, MASK_CECRST);
828#endif
d32d9864
MR		 829 tc358743_sleep_mode(sd, false);
830
831 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
832
833 tc358743_set_ref_clk(sd);
834
835 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
836 pdata->ddc5v_delay & MASK_DDC5V_MODE);
837 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
838
839 tc358743_set_hdmi_phy(sd);
840 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
841 tc358743_set_hdmi_audio(sd);
842 tc358743_set_hdmi_info_frame_mode(sd);
843
844 /* All CE and IT formats are detected as RGB full range in DVI mode */
845 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
846
847 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
848 MASK_VOUTCOLORMODE_AUTO);
849 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
850}
851
a0ec8d1d
HV		 852/* --------------- CEC --------------- */
853
854#ifdef CONFIG_VIDEO_TC358743_CEC
855static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable)
856{
857 struct tc358743_state *state = adap->priv;
858 struct v4l2_subdev *sd = &state->sd;
859
860 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
861 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
862 i2c_wr32(sd, CECEN, enable);
863 if (enable)
864 i2c_wr32(sd, CECREN, MASK_CECREN);
865 return 0;
866}
867
868static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap,
869 bool enable)
870{
871 struct tc358743_state *state = adap->priv;
872 struct v4l2_subdev *sd = &state->sd;
873 u32 reg;
874
875 reg = i2c_rd32(sd, CECRCTL1);
876 if (enable)
877 reg |= MASK_CECOTH;
878 else
879 reg &= ~MASK_CECOTH;
880 i2c_wr32(sd, CECRCTL1, reg);
881 return 0;
882}
883
884static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
885{
886 struct tc358743_state *state = adap->priv;
887 struct v4l2_subdev *sd = &state->sd;
888 unsigned int la = 0;
889
890 if (log_addr != CEC_LOG_ADDR_INVALID) {
891 la = i2c_rd32(sd, CECADD);
892 la |= 1 << log_addr;
893 }
894 i2c_wr32(sd, CECADD, la);
895 return 0;
896}
897
898static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
899 u32 signal_free_time, struct cec_msg *msg)
900{
901 struct tc358743_state *state = adap->priv;
902 struct v4l2_subdev *sd = &state->sd;
903 unsigned int i;
904
905 i2c_wr32(sd, CECTCTL,
906 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) |
907 (signal_free_time - 1));
908 for (i = 0; i < msg->len; i++)
909 i2c_wr32(sd, CECTBUF1 + i * 4,
910 msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0));
911 i2c_wr32(sd, CECTEN, MASK_CECTEN);
912 return 0;
913}
914
915static const struct cec_adap_ops tc358743_cec_adap_ops = {
916 .adap_enable = tc358743_cec_adap_enable,
917 .adap_log_addr = tc358743_cec_adap_log_addr,
918 .adap_transmit = tc358743_cec_adap_transmit,
919 .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable,
920};
921
922static void tc358743_cec_isr(struct v4l2_subdev *sd, u16 intstatus,
923 bool *handled)
924{
925 struct tc358743_state *state = to_state(sd);
926 unsigned int cec_rxint, cec_txint;
927 unsigned int clr = 0;
928
929 cec_rxint = i2c_rd32(sd, CECRSTAT);
930 cec_txint = i2c_rd32(sd, CECTSTAT);
931
932 if (intstatus & MASK_CEC_RINT)
933 clr |= MASK_CECRICLR;
934 if (intstatus & MASK_CEC_TINT)
935 clr |= MASK_CECTICLR;
936 i2c_wr32(sd, CECICLR, clr);
937
938 if ((intstatus & MASK_CEC_TINT) && cec_txint) {
939 if (cec_txint & MASK_CECTIEND)
940 cec_transmit_attempt_done(state->cec_adap,
941 CEC_TX_STATUS_OK);
942 else if (cec_txint & MASK_CECTIAL)
943 cec_transmit_attempt_done(state->cec_adap,
944 CEC_TX_STATUS_ARB_LOST);
945 else if (cec_txint & MASK_CECTIACK)
946 cec_transmit_attempt_done(state->cec_adap,
947 CEC_TX_STATUS_NACK);
948 else if (cec_txint & MASK_CECTIUR) {
949 /*
950 * Not sure when this bit is set. Treat
951 * it as an error for now.
952 */
953 cec_transmit_attempt_done(state->cec_adap,
954 CEC_TX_STATUS_ERROR);
955 }
956 *handled = true;
957 }
958 if ((intstatus & MASK_CEC_RINT) &&
959 (cec_rxint & MASK_CECRIEND)) {
960 struct cec_msg msg = {};
961 unsigned int i;
962 unsigned int v;
963
964 v = i2c_rd32(sd, CECRCTR);
965 msg.len = v & 0x1f;
966 for (i = 0; i < msg.len; i++) {
967 v = i2c_rd32(sd, CECRBUF1 + i * 4);
968 msg.msg[i] = v & 0xff;
969 }
970 cec_received_msg(state->cec_adap, &msg);
971 *handled = true;
972 }
973 i2c_wr16(sd, INTSTATUS,
974 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
975}
976
977#endif
978
d32d9864
MR		 979/* --------------- IRQ --------------- */
980
981static void tc358743_format_change(struct v4l2_subdev *sd)
982{
983 struct tc358743_state *state = to_state(sd);
984 struct v4l2_dv_timings timings;
985 const struct v4l2_event tc358743_ev_fmt = {
986 .type = V4L2_EVENT_SOURCE_CHANGE,
987 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
988 };
989
990 if (tc358743_get_detected_timings(sd, &timings)) {
991 enable_stream(sd, false);
992
2874bf3e 993 v4l2_dbg(1, debug, sd, "%s: No signal\n",
d32d9864
MR		 994 __func__);
995 } else {
85f9e06c 996 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
d32d9864
MR		 997 enable_stream(sd, false);
998
2874bf3e
MR		 999 if (debug)
1000 v4l2_print_dv_timings(sd->name,
1001 "tc358743_format_change: New format: ",
1002 &timings, false);
d32d9864
MR		 1003 }
1004
abeaca0f
PZ		 1005 if (sd->devnode)
1006 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
d32d9864
MR		 1007}
1008
1009static void tc358743_init_interrupts(struct v4l2_subdev *sd)
1010{
1011 u16 i;
1012
1013 /* clear interrupt status registers */
1014 for (i = SYS_INT; i <= KEY_INT; i++)
1015 i2c_wr8(sd, i, 0xff);
1016
1017 i2c_wr16(sd, INTSTATUS, 0xffff);
1018}
1019
1020static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
1021 bool cable_connected)
1022{
1023 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1024 cable_connected);
1025
1026 if (cable_connected) {
1027 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
1028 MASK_M_HDMI_DET) & 0xff);
1029 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
1030 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
1031 MASK_M_AF_UNLOCK) & 0xff);
1032 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
1033 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
1034 } else {
1035 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
1036 i2c_wr8(sd, CLK_INTM, 0xff);
1037 i2c_wr8(sd, CBIT_INTM, 0xff);
1038 i2c_wr8(sd, AUDIO_INTM, 0xff);
1039 i2c_wr8(sd, MISC_INTM, 0xff);
1040 }
1041}
1042
1043static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1044 bool *handled)
1045{
1046 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1047 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1048
1049 i2c_wr8(sd, AUDIO_INT, audio_int);
1050
1051 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1052
1053 tc358743_s_ctrl_audio_sampling_rate(sd);
1054 tc358743_s_ctrl_audio_present(sd);
1055}
1056
1057static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
1058{
1059 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
1060
1061 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
1062}
1063
1064static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1065 bool *handled)
1066{
1067 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1068 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1069
1070 i2c_wr8(sd, MISC_INT, misc_int);
1071
1072 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1073
1074 if (misc_int & MASK_I_SYNC_CHG) {
1075 /* Reset the HDMI PHY to try to trigger proper lock on the
1076 * incoming video format. Erase BKSV to prevent that old keys
1077 * are used when a new source is connected. */
1078 if (no_sync(sd) || no_signal(sd)) {
1079 tc358743_reset_phy(sd);
1080 tc358743_erase_bksv(sd);
1081 }
1082
1083 tc358743_format_change(sd);
1084
1085 misc_int &= ~MASK_I_SYNC_CHG;
1086 if (handled)
1087 *handled = true;
1088 }
1089
1090 if (misc_int) {
1091 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1092 __func__, misc_int);
1093 }
1094}
1095
1096static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1097 bool *handled)
1098{
1099 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1100 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1101
1102 i2c_wr8(sd, CBIT_INT, cbit_int);
1103
1104 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1105
1106 if (cbit_int & MASK_I_CBIT_FS) {
1107
1108 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1109 __func__);
1110 tc358743_s_ctrl_audio_sampling_rate(sd);
1111
1112 cbit_int &= ~MASK_I_CBIT_FS;
1113 if (handled)
1114 *handled = true;
1115 }
1116
1117 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
1118
1119 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1120 __func__);
1121 tc358743_s_ctrl_audio_present(sd);
1122
1123 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
1124 if (handled)
1125 *handled = true;
1126 }
1127
1128 if (cbit_int) {
1129 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1130 __func__, cbit_int);
1131 }
1132}
1133
1134static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1135{
1136 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1137 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1138
1139 /* Bit 7 and bit 6 are set even when they are masked */
1140 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1141
1142 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1143
1144 if (clk_int & (MASK_I_IN_DE_CHG)) {
1145
1146 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1147 __func__);
1148
1149 /* If the source switch to a new resolution with the same pixel
1150 * frequency as the existing (e.g. 1080p25 -> 720p50), the
1151 * I_SYNC_CHG interrupt is not always triggered, while the
1152 * I_IN_DE_CHG interrupt seems to work fine. Format change
1153 * notifications are only sent when the signal is stable to
1154 * reduce the number of notifications. */
1155 if (!no_signal(sd) && !no_sync(sd))
1156 tc358743_format_change(sd);
1157
1158 clk_int &= ~(MASK_I_IN_DE_CHG);
1159 if (handled)
1160 *handled = true;
1161 }
1162
1163 if (clk_int) {
1164 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1165 __func__, clk_int);
1166 }
1167}
1168
1169static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1170{
1171 struct tc358743_state *state = to_state(sd);
1172 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1173 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1174
1175 i2c_wr8(sd, SYS_INT, sys_int);
1176
1177 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1178
1179 if (sys_int & MASK_I_DDC) {
1180 bool tx_5v = tx_5v_power_present(sd);
1181
1182 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1183 __func__, tx_5v ? "yes" : "no");
1184
1185 if (tx_5v) {
1186 tc358743_enable_edid(sd);
1187 } else {
1188 tc358743_enable_interrupts(sd, false);
1189 tc358743_disable_edid(sd);
1190 memset(&state->timings, 0, sizeof(state->timings));
1191 tc358743_erase_bksv(sd);
1192 tc358743_update_controls(sd);
1193 }
1194
1195 sys_int &= ~MASK_I_DDC;
1196 if (handled)
1197 *handled = true;
1198 }
1199
1200 if (sys_int & MASK_I_DVI) {
1201 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1202 __func__);
1203
1204 /* Reset the HDMI PHY to try to trigger proper lock on the
1205 * incoming video format. Erase BKSV to prevent that old keys
1206 * are used when a new source is connected. */
1207 if (no_sync(sd) || no_signal(sd)) {
1208 tc358743_reset_phy(sd);
1209 tc358743_erase_bksv(sd);
1210 }
1211
1212 sys_int &= ~MASK_I_DVI;
1213 if (handled)
1214 *handled = true;
1215 }
1216
1217 if (sys_int & MASK_I_HDMI) {
1218 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1219 __func__);
1220
1221 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1222 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1223
1224 sys_int &= ~MASK_I_HDMI;
1225 if (handled)
1226 *handled = true;
1227 }
1228
1229 if (sys_int) {
1230 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1231 __func__, sys_int);
1232 }
1233}
1234
1235/* --------------- CORE OPS --------------- */
1236
1237static int tc358743_log_status(struct v4l2_subdev *sd)
1238{
1239 struct tc358743_state *state = to_state(sd);
1240 struct v4l2_dv_timings timings;
1241 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1242 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1243 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1244 const int deep_color_mode[4] = { 8, 10, 12, 16 };
1245 static const char * const input_color_space[] = {
db034018 1246 "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)",
d32d9864 1247 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
db034018 1248 "NA(10)", "NA(11)", "NA(12)", "opYCC 601"};
d32d9864
MR		 1249
1250 v4l2_info(sd, "-----Chip status-----\n");
1251 v4l2_info(sd, "Chip ID: 0x%02x\n",
1252 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1253 v4l2_info(sd, "Chip revision: 0x%02x\n",
1254 i2c_rd16(sd, CHIPID) & MASK_REVID);
1255 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1256 !!(sysctl & MASK_IRRST),
1257 !!(sysctl & MASK_CECRST),
1258 !!(sysctl & MASK_CTXRST),
1259 !!(sysctl & MASK_HDMIRST));
1260 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1261 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1262 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1263 v4l2_info(sd, "DDC lines enabled: %s\n",
1264 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1265 "yes" : "no");
1266 v4l2_info(sd, "Hotplug enabled: %s\n",
1267 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1268 "yes" : "no");
1269 v4l2_info(sd, "CEC enabled: %s\n",
1270 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1271 v4l2_info(sd, "-----Signal status-----\n");
1272 v4l2_info(sd, "TMDS signal detected: %s\n",
1273 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1274 v4l2_info(sd, "Stable sync signal: %s\n",
1275 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1276 v4l2_info(sd, "PHY PLL locked: %s\n",
1277 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1278 v4l2_info(sd, "PHY DE detected: %s\n",
1279 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1280
1281 if (tc358743_get_detected_timings(sd, &timings)) {
1282 v4l2_info(sd, "No video detected\n");
1283 } else {
1284 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1285 true);
1286 }
1287 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1288 true);
1289
1290 v4l2_info(sd, "-----CSI-TX status-----\n");
1291 v4l2_info(sd, "Lanes needed: %d\n",
1292 tc358743_num_csi_lanes_needed(sd));
1293 v4l2_info(sd, "Lanes in use: %d\n",
59e34ba8 1294 state->csi_lanes_in_use);
d32d9864
MR		 1295 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1296 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1297 "yes" : "no");
1298 v4l2_info(sd, "Transmit mode: %s\n",
1299 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1300 "yes" : "no");
1301 v4l2_info(sd, "Receive mode: %s\n",
1302 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1303 "yes" : "no");
1304 v4l2_info(sd, "Stopped: %s\n",
1305 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1306 "yes" : "no");
1307 v4l2_info(sd, "Color space: %s\n",
1308 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1309 "YCbCr 422 16-bit" :
1310 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1311 "RGB 888 24-bit" : "Unsupported");
1312
1313 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1314 v4l2_info(sd, "HDCP encrypted content: %s\n",
1315 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1316 v4l2_info(sd, "Input color space: %s %s range\n",
1317 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1318 (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1319 if (!is_hdmi(sd))
1320 return 0;
1321 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1322 "off");
1323 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1324 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1325 MASK_S_DEEPCOLOR) >> 2]);
1326 print_avi_infoframe(sd);
1327
1328 return 0;
1329}
1330
1331#ifdef CONFIG_VIDEO_ADV_DEBUG
1332static void tc358743_print_register_map(struct v4l2_subdev *sd)
1333{
85e510a1
HV		 1334 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1335 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1336 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1337 v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1338 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1339 v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1340 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1341 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1342 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1343 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1344 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1345 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1346 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1347 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1348 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
d32d9864
MR		 1349 v4l2_info(sd, "0x9300- : Reserved\n");
1350}
1351
1352static int tc358743_get_reg_size(u16 address)
1353{
1354 /* REF_01 p. 66-72 */
1355 if (address <= 0x00ff)
1356 return 2;
1357 else if ((address >= 0x0100) && (address <= 0x06FF))
1358 return 4;
1359 else if ((address >= 0x0700) && (address <= 0x84ff))
1360 return 2;
1361 else
1362 return 1;
1363}
1364
1365static int tc358743_g_register(struct v4l2_subdev *sd,
1366 struct v4l2_dbg_register *reg)
1367{
1368 if (reg->reg > 0xffff) {
1369 tc358743_print_register_map(sd);
1370 return -EINVAL;
1371 }
1372
1373 reg->size = tc358743_get_reg_size(reg->reg);
1374
3538aa6e 1375 reg->val = i2c_rdreg(sd, reg->reg, reg->size);
d32d9864
MR		 1376
1377 return 0;
1378}
1379
1380static int tc358743_s_register(struct v4l2_subdev *sd,
1381 const struct v4l2_dbg_register *reg)
1382{
1383 if (reg->reg > 0xffff) {
1384 tc358743_print_register_map(sd);
1385 return -EINVAL;
1386 }
1387
1388 /* It should not be possible for the user to enable HDCP with a simple
1389 * v4l2-dbg command.
1390 *
1391 * DO NOT REMOVE THIS unless all other issues with HDCP have been
1392 * resolved.
1393 */
1394 if (reg->reg == HDCP_MODE ||
1395 reg->reg == HDCP_REG1 ||
1396 reg->reg == HDCP_REG2 ||
1397 reg->reg == HDCP_REG3 ||
1398 reg->reg == BCAPS)
1399 return 0;
1400
3538aa6e 1401 i2c_wrreg(sd, (u16)reg->reg, reg->val,
d32d9864
MR		 1402 tc358743_get_reg_size(reg->reg));
1403
1404 return 0;
1405}
1406#endif
1407
1408static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1409{
1410 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1411
1412 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1413
1414 if (intstatus & MASK_HDMI_INT) {
1415 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1416 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1417
1418 if (hdmi_int0 & MASK_I_MISC)
1419 tc358743_hdmi_misc_int_handler(sd, handled);
1420 if (hdmi_int1 & MASK_I_CBIT)
1421 tc358743_hdmi_cbit_int_handler(sd, handled);
1422 if (hdmi_int1 & MASK_I_CLK)
1423 tc358743_hdmi_clk_int_handler(sd, handled);
1424 if (hdmi_int1 & MASK_I_SYS)
1425 tc358743_hdmi_sys_int_handler(sd, handled);
1426 if (hdmi_int1 & MASK_I_AUD)
1427 tc358743_hdmi_audio_int_handler(sd, handled);
1428
1429 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1430 intstatus &= ~MASK_HDMI_INT;
1431 }
1432
a0ec8d1d
HV		 1433#ifdef CONFIG_VIDEO_TC358743_CEC
1434 if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) {
1435 tc358743_cec_isr(sd, intstatus, handled);
1436 i2c_wr16(sd, INTSTATUS,
1437 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
1438 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT);
1439 }
1440#endif
1441
d32d9864
MR		 1442 if (intstatus & MASK_CSI_INT) {
1443 u32 csi_int = i2c_rd32(sd, CSI_INT);
1444
1445 if (csi_int & MASK_INTER)
1446 tc358743_csi_err_int_handler(sd, handled);
1447
1448 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
d32d9864
MR		 1449 }
1450
1451 intstatus = i2c_rd16(sd, INTSTATUS);
1452 if (intstatus) {
1453 v4l2_dbg(1, debug, sd,
1454 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1455 __func__, intstatus);
1456 }
1457
1458 return 0;
1459}
1460
d747b806
PZ		 1461static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1462{
1463 struct tc358743_state *state = dev_id;
1464 bool handled;
1465
1466 tc358743_isr(&state->sd, 0, &handled);
1467
1468 return handled ? IRQ_HANDLED : IRQ_NONE;
1469}
1470
a88cd60f 1471static void tc358743_irq_poll_timer(struct timer_list *t)
4e66a52a 1472{
a88cd60f 1473 struct tc358743_state *state = from_timer(state, t, timer);
a0ec8d1d 1474 unsigned int msecs;
4e66a52a
DS		 1475
1476 schedule_work(&state->work_i2c_poll);
a0ec8d1d
HV		 1477 /*
1478 * If CEC is present, then we need to poll more frequently,
1479 * otherwise we will miss CEC messages.
1480 */
1481 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
1482 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
4e66a52a
DS		 1483}
1484
1485static void tc358743_work_i2c_poll(struct work_struct *work)
1486{
1487 struct tc358743_state *state = container_of(work,
1488 struct tc358743_state, work_i2c_poll);
1489 bool handled;
1490
1491 tc358743_isr(&state->sd, 0, &handled);
1492}
1493
1140f919
PZ		 1494static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1495 struct v4l2_event_subscription *sub)
1496{
1497 switch (sub->type) {
1498 case V4L2_EVENT_SOURCE_CHANGE:
1499 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1500 case V4L2_EVENT_CTRL:
1501 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1502 default:
1503 return -EINVAL;
1504 }
1505}
1506
d32d9864
MR		 1507/* --------------- VIDEO OPS --------------- */
1508
1509static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1510{
1511 *status = 0;
1512 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1513 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1514
1515 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1516
1517 return 0;
1518}
1519
1520static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1521 struct v4l2_dv_timings *timings)
1522{
1523 struct tc358743_state *state = to_state(sd);
d32d9864
MR		 1524
1525 if (!timings)
1526 return -EINVAL;
1527
1528 if (debug)
1529 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1530 timings, false);
1531
85f9e06c 1532 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
d32d9864
MR		 1533 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1534 return 0;
1535 }
1536
d32d9864
MR		 1537 if (!v4l2_valid_dv_timings(timings,
1538 &tc358743_timings_cap, NULL, NULL)) {
1539 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1540 return -ERANGE;
1541 }
1542
1543 state->timings = *timings;
1544
1545 enable_stream(sd, false);
1546 tc358743_set_pll(sd);
1547 tc358743_set_csi(sd);
1548
1549 return 0;
1550}
1551
1552static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1553 struct v4l2_dv_timings *timings)
1554{
1555 struct tc358743_state *state = to_state(sd);
1556
1557 *timings = state->timings;
1558
1559 return 0;
1560}
1561
1562static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1563 struct v4l2_enum_dv_timings *timings)
1564{
1565 if (timings->pad != 0)
1566 return -EINVAL;
1567
1568 return v4l2_enum_dv_timings_cap(timings,
1569 &tc358743_timings_cap, NULL, NULL);
1570}
1571
1572static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1573 struct v4l2_dv_timings *timings)
1574{
1575 int ret;
1576
1577 ret = tc358743_get_detected_timings(sd, timings);
1578 if (ret)
1579 return ret;
1580
1581 if (debug)
1582 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1583 timings, false);
1584
1585 if (!v4l2_valid_dv_timings(timings,
1586 &tc358743_timings_cap, NULL, NULL)) {
1587 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1588 return -ERANGE;
1589 }
1590
1591 return 0;
1592}
1593
1594static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1595 struct v4l2_dv_timings_cap *cap)
1596{
1597 if (cap->pad != 0)
1598 return -EINVAL;
1599
1600 *cap = tc358743_timings_cap;
1601
1602 return 0;
1603}
1604
1605static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1606 struct v4l2_mbus_config *cfg)
1607{
59e34ba8
MR		 1608 struct tc358743_state *state = to_state(sd);
1609
2d95e7ed 1610 cfg->type = V4L2_MBUS_CSI2_DPHY;
d32d9864
MR		 1611
1612 /* Support for non-continuous CSI-2 clock is missing in the driver */
1613 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1614
59e34ba8 1615 switch (state->csi_lanes_in_use) {
d32d9864
MR		 1616 case 1:
1617 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1618 break;
1619 case 2:
1620 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1621 break;
1622 case 3:
1623 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1624 break;
1625 case 4:
1626 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1627 break;
1628 default:
1629 return -EINVAL;
1630 }
1631
1632 return 0;
1633}
1634
1635static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1636{
1637 enable_stream(sd, enable);
fbd4676c 1638 if (!enable) {
3863d4bb 1639 /* Put all lanes in LP-11 state (STOPSTATE) */
fbd4676c
PZ		 1640 tc358743_set_csi(sd);
1641 }
d32d9864
MR		 1642
1643 return 0;
1644}
1645
1646/* --------------- PAD OPS --------------- */
1647
3cb0fe6f
DS		 1648static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
1649 struct v4l2_subdev_pad_config *cfg,
1650 struct v4l2_subdev_mbus_code_enum *code)
1651{
1652 switch (code->index) {
1653 case 0:
1654 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1655 break;
1656 case 1:
1657 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1658 break;
1659 default:
1660 return -EINVAL;
1661 }
1662 return 0;
1663}
1664
d32d9864
MR		 1665static int tc358743_get_fmt(struct v4l2_subdev *sd,
1666 struct v4l2_subdev_pad_config *cfg,
1667 struct v4l2_subdev_format *format)
1668{
1669 struct tc358743_state *state = to_state(sd);
1670 u8 vi_rep = i2c_rd8(sd, VI_REP);
1671
1672 if (format->pad != 0)
1673 return -EINVAL;
1674
1675 format->format.code = state->mbus_fmt_code;
1676 format->format.width = state->timings.bt.width;
1677 format->format.height = state->timings.bt.height;
1678 format->format.field = V4L2_FIELD_NONE;
1679
1680 switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1681 case MASK_VOUT_COLOR_RGB_FULL:
1682 case MASK_VOUT_COLOR_RGB_LIMITED:
1683 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1684 break;
1685 case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1686 case MASK_VOUT_COLOR_601_YCBCR_FULL:
1687 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1688 break;
1689 case MASK_VOUT_COLOR_709_YCBCR_FULL:
1690 case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1691 format->format.colorspace = V4L2_COLORSPACE_REC709;
1692 break;
1693 default:
1694 format->format.colorspace = 0;
1695 break;
1696 }
1697
1698 return 0;
1699}
1700
1701static int tc358743_set_fmt(struct v4l2_subdev *sd,
1702 struct v4l2_subdev_pad_config *cfg,
1703 struct v4l2_subdev_format *format)
1704{
1705 struct tc358743_state *state = to_state(sd);
1706
1707 u32 code = format->format.code; /* is overwritten by get_fmt */
1708 int ret = tc358743_get_fmt(sd, cfg, format);
1709
1710 format->format.code = code;
1711
1712 if (ret)
1713 return ret;
1714
1715 switch (code) {
1716 case MEDIA_BUS_FMT_RGB888_1X24:
1717 case MEDIA_BUS_FMT_UYVY8_1X16:
1718 break;
1719 default:
1720 return -EINVAL;
1721 }
1722
1723 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1724 return 0;
1725
1726 state->mbus_fmt_code = format->format.code;
1727
1728 enable_stream(sd, false);
1729 tc358743_set_pll(sd);
1730 tc358743_set_csi(sd);
1731 tc358743_set_csi_color_space(sd);
1732
1733 return 0;
1734}
1735
1736static int tc358743_g_edid(struct v4l2_subdev *sd,
1737 struct v4l2_subdev_edid *edid)
1738{
1739 struct tc358743_state *state = to_state(sd);
1740
72777724
HV		 1741 memset(edid->reserved, 0, sizeof(edid->reserved));
1742
d32d9864
MR		 1743 if (edid->pad != 0)
1744 return -EINVAL;
1745
1746 if (edid->start_block == 0 && edid->blocks == 0) {
1747 edid->blocks = state->edid_blocks_written;
1748 return 0;
1749 }
1750
1751 if (state->edid_blocks_written == 0)
1752 return -ENODATA;
1753
1754 if (edid->start_block >= state->edid_blocks_written ||
1755 edid->blocks == 0)
1756 return -EINVAL;
1757
1758 if (edid->start_block + edid->blocks > state->edid_blocks_written)
1759 edid->blocks = state->edid_blocks_written - edid->start_block;
1760
1761 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1762 edid->blocks * EDID_BLOCK_SIZE);
1763
1764 return 0;
1765}
1766
1767static int tc358743_s_edid(struct v4l2_subdev *sd,
1768 struct v4l2_subdev_edid *edid)
1769{
1770 struct tc358743_state *state = to_state(sd);
1771 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
a0ec8d1d
HV		 1772 u16 pa;
1773 int err;
fcae73fa 1774 int i;
d32d9864
MR		 1775
1776 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1777 __func__, edid->pad, edid->start_block, edid->blocks);
1778
72777724
HV		 1779 memset(edid->reserved, 0, sizeof(edid->reserved));
1780
d32d9864
MR		 1781 if (edid->pad != 0)
1782 return -EINVAL;
1783
1784 if (edid->start_block != 0)
1785 return -EINVAL;
1786
1787 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1788 edid->blocks = EDID_NUM_BLOCKS_MAX;
1789 return -E2BIG;
1790 }
a0ec8d1d 1791 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL);
9cfd2753 1792 err = v4l2_phys_addr_validate(pa, &pa, NULL);
a0ec8d1d
HV		 1793 if (err)
1794 return err;
1795
1796 cec_phys_addr_invalidate(state->cec_adap);
d32d9864
MR		 1797
1798 tc358743_disable_edid(sd);
1799
1800 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1801 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1802
1803 if (edid->blocks == 0) {
1804 state->edid_blocks_written = 0;
1805 return 0;
1806 }
1807
fcae73fa
MR		 1808 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1809 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
d32d9864
MR		 1810
1811 state->edid_blocks_written = edid->blocks;
1812
a0ec8d1d
HV		 1813 cec_s_phys_addr(state->cec_adap, pa, false);
1814
d32d9864
MR		 1815 if (tx_5v_power_present(sd))
1816 tc358743_enable_edid(sd);
1817
1818 return 0;
1819}
1820
1821/* -------------------------------------------------------------------------- */
1822
1823static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1824 .log_status = tc358743_log_status,
1825#ifdef CONFIG_VIDEO_ADV_DEBUG
1826 .g_register = tc358743_g_register,
1827 .s_register = tc358743_s_register,
1828#endif
1829 .interrupt_service_routine = tc358743_isr,
1140f919
PZ		 1830 .subscribe_event = tc358743_subscribe_event,
1831 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
d32d9864
MR		 1832};
1833
1834static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1835 .g_input_status = tc358743_g_input_status,
1836 .s_dv_timings = tc358743_s_dv_timings,
1837 .g_dv_timings = tc358743_g_dv_timings,
1838 .query_dv_timings = tc358743_query_dv_timings,
1839 .g_mbus_config = tc358743_g_mbus_config,
1840 .s_stream = tc358743_s_stream,
1841};
1842
1843static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
3cb0fe6f 1844 .enum_mbus_code = tc358743_enum_mbus_code,
d32d9864
MR		 1845 .set_fmt = tc358743_set_fmt,
1846 .get_fmt = tc358743_get_fmt,
1847 .get_edid = tc358743_g_edid,
1848 .set_edid = tc358743_s_edid,
1849 .enum_dv_timings = tc358743_enum_dv_timings,
1850 .dv_timings_cap = tc358743_dv_timings_cap,
1851};
1852
1853static const struct v4l2_subdev_ops tc358743_ops = {
1854 .core = &tc358743_core_ops,
1855 .video = &tc358743_video_ops,
1856 .pad = &tc358743_pad_ops,
1857};
1858
1859/* --------------- CUSTOM CTRLS --------------- */
1860
1861static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1862 .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1863 .name = "Audio sampling rate",
1864 .type = V4L2_CTRL_TYPE_INTEGER,
1865 .min = 0,
1866 .max = 768000,
1867 .step = 1,
1868 .def = 0,
1869 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1870};
1871
1872static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1873 .id = TC358743_CID_AUDIO_PRESENT,
1874 .name = "Audio present",
1875 .type = V4L2_CTRL_TYPE_BOOLEAN,
1876 .min = 0,
1877 .max = 1,
1878 .step = 1,
1879 .def = 0,
1880 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1881};
1882
1883/* --------------- PROBE / REMOVE --------------- */
1884
25614824
PZ		 1885#ifdef CONFIG_OF
1886static void tc358743_gpio_reset(struct tc358743_state *state)
1887{
25614824
PZ		 1888 usleep_range(5000, 10000);
1889 gpiod_set_value(state->reset_gpio, 1);
1890 usleep_range(1000, 2000);
1891 gpiod_set_value(state->reset_gpio, 0);
1892 msleep(20);
1893}
1894
1895static int tc358743_probe_of(struct tc358743_state *state)
1896{
1897 struct device *dev = &state->i2c_client->dev;
6970d37c 1898 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
25614824
PZ		 1899 struct device_node *ep;
1900 struct clk *refclk;
1901 u32 bps_pr_lane;
6970d37c 1902 int ret;
25614824
PZ		 1903
1904 refclk = devm_clk_get(dev, "refclk");
1905 if (IS_ERR(refclk)) {
1906 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1907 dev_err(dev, "failed to get refclk: %ld\n",
1908 PTR_ERR(refclk));
1909 return PTR_ERR(refclk);
1910 }
1911
1912 ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1913 if (!ep) {
1914 dev_err(dev, "missing endpoint node\n");
1915 return -EINVAL;
1916 }
1917
6970d37c
SA		 1918 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
1919 if (ret) {
25614824 1920 dev_err(dev, "failed to parse endpoint\n");
64bac691 1921 goto put_node;
25614824
PZ		 1922 }
1923
6970d37c
SA		 1924 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
1925 endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
1926 endpoint.nr_of_link_frequencies == 0) {
25614824 1927 dev_err(dev, "missing CSI-2 properties in endpoint\n");
6970d37c 1928 ret = -EINVAL;
25614824
PZ		 1929 goto free_endpoint;
1930 }
1931
6970d37c 1932 if (endpoint.bus.mipi_csi2.num_data_lanes > 4) {
9d39e46b 1933 dev_err(dev, "invalid number of lanes\n");
6970d37c 1934 ret = -EINVAL;
9d39e46b
PZ		 1935 goto free_endpoint;
1936 }
1937
6970d37c 1938 state->bus = endpoint.bus.mipi_csi2;
25614824 1939
43b288ba
AY		 1940 ret = clk_prepare_enable(refclk);
1941 if (ret) {
1942 dev_err(dev, "Failed! to enable clock\n");
1943 goto free_endpoint;
1944 }
25614824
PZ		 1945
1946 state->pdata.refclk_hz = clk_get_rate(refclk);
1947 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1948 state->pdata.enable_hdcp = false;
1949 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1950 state->pdata.fifo_level = 16;
1951 /*
1952 * The PLL input clock is obtained by dividing refclk by pll_prd.
1953 * It must be between 6 MHz and 40 MHz, lower frequency is better.
1954 */
1955 switch (state->pdata.refclk_hz) {
1956 case 26000000:
1957 case 27000000:
1958 case 42000000:
1959 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1960 break;
1961 default:
1962 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1963 state->pdata.refclk_hz);
1964 goto disable_clk;
1965 }
1966
1967 /*
1968 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1969 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1970 */
6970d37c 1971 bps_pr_lane = 2 * endpoint.link_frequencies[0];
25614824
PZ		 1972 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1973 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1974 goto disable_clk;
1975 }
1976
1977 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1978 state->pdata.pll_fbd = bps_pr_lane /
1979 state->pdata.refclk_hz * state->pdata.pll_prd;
1980
1981 /*
1982 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1983 * link frequency). In principle it should be possible to calculate
1984 * them based on link frequency and resolution.
1985 */
1986 if (bps_pr_lane != 594000000U)
1987 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1988 state->pdata.lineinitcnt = 0xe80;
1989 state->pdata.lptxtimecnt = 0x003;
1990 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1991 state->pdata.tclk_headercnt = 0x1403;
1992 state->pdata.tclk_trailcnt = 0x00;
1993 /* ths-preparecnt: 3, ths-zerocnt: 1 */
1994 state->pdata.ths_headercnt = 0x0103;
1995 state->pdata.twakeup = 0x4882;
1996 state->pdata.tclk_postcnt = 0x008;
1997 state->pdata.ths_trailcnt = 0x2;
1998 state->pdata.hstxvregcnt = 0;
1999
1e137d92
UKK		 2000 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
2001 GPIOD_OUT_LOW);
25614824
PZ		 2002 if (IS_ERR(state->reset_gpio)) {
2003 dev_err(dev, "failed to get reset gpio\n");
2004 ret = PTR_ERR(state->reset_gpio);
2005 goto disable_clk;
2006 }
2007
1e137d92
UKK		 2008 if (state->reset_gpio)
2009 tc358743_gpio_reset(state);
25614824
PZ		 2010
2011 ret = 0;
2012 goto free_endpoint;
2013
2014disable_clk:
2015 clk_disable_unprepare(refclk);
2016free_endpoint:
6970d37c 2017 v4l2_fwnode_endpoint_free(&endpoint);
64bac691
AK		 2018put_node:
2019 of_node_put(ep);
25614824
PZ		 2020 return ret;
2021}
2022#else
2023static inline int tc358743_probe_of(struct tc358743_state *state)
2024{
2025 return -ENODEV;
2026}
2027#endif
2028
d32d9864
MR		 2029static int tc358743_probe(struct i2c_client *client,
2030 const struct i2c_device_id *id)
2031{
2032 static struct v4l2_dv_timings default_timing =
2033 V4L2_DV_BT_CEA_640X480P59_94;
2034 struct tc358743_state *state;
2035 struct tc358743_platform_data *pdata = client->dev.platform_data;
2036 struct v4l2_subdev *sd;
a0ec8d1d 2037 u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
d32d9864
MR		 2038 int err;
2039
2040 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2041 return -EIO;
2042 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
2043 client->addr << 1, client->adapter->name);
2044
2045 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
2046 GFP_KERNEL);
2047 if (!state)
2048 return -ENOMEM;
2049
25614824
PZ		 2050 state->i2c_client = client;
2051
d32d9864 2052 /* platform data */
25614824
PZ		 2053 if (pdata) {
2054 state->pdata = *pdata;
2055 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2056 } else {
2057 err = tc358743_probe_of(state);
2058 if (err == -ENODEV)
2059 v4l_err(client, "No platform data!\n");
2060 if (err)
2061 return err;
d32d9864 2062 }
d32d9864 2063
d32d9864
MR		 2064 sd = &state->sd;
2065 v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
8ec23da7 2066 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
d32d9864
MR		 2067
2068 /* i2c access */
2069 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
2070 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
2071 client->addr << 1);
2072 return -ENODEV;
2073 }
2074
2075 /* control handlers */
2076 v4l2_ctrl_handler_init(&state->hdl, 3);
2077
d32d9864
MR		 2078 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
2079 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2080
2081 /* custom controls */
2082 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2083 &tc358743_ctrl_audio_sampling_rate, NULL);
2084
2085 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2086 &tc358743_ctrl_audio_present, NULL);
2087
2088 sd->ctrl_handler = &state->hdl;
2089 if (state->hdl.error) {
2090 err = state->hdl.error;
2091 goto err_hdl;
2092 }
2093
2094 if (tc358743_update_controls(sd)) {
2095 err = -ENODEV;
2096 goto err_hdl;
2097 }
2098
4c5211a1 2099 state->pad.flags = MEDIA_PAD_FL_SOURCE;
f7480ad0 2100 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
ab22e77c 2101 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
4c5211a1
PZ		 2102 if (err < 0)
2103 goto err_hdl;
2104
2da2391c
DS		 2105 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
2106
4c5211a1
PZ		 2107 sd->dev = &client->dev;
2108 err = v4l2_async_register_subdev(sd);
2109 if (err < 0)
2110 goto err_hdl;
2111
d32d9864
MR		 2112 mutex_init(&state->confctl_mutex);
2113
2114 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2115 tc358743_delayed_work_enable_hotplug);
2116
a0ec8d1d
HV		 2117#ifdef CONFIG_VIDEO_TC358743_CEC
2118 state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops,
2119 state, dev_name(&client->dev),
2120 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS);
2121 if (IS_ERR(state->cec_adap)) {
7996e5c4 2122 err = PTR_ERR(state->cec_adap);
a0ec8d1d
HV		 2123 goto err_hdl;
2124 }
2125 irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK;
2126#endif
2127
d32d9864
MR		 2128 tc358743_initial_setup(sd);
2129
2130 tc358743_s_dv_timings(sd, &default_timing);
2131
d32d9864
MR		 2132 tc358743_set_csi_color_space(sd);
2133
2134 tc358743_init_interrupts(sd);
d747b806
PZ		 2135
2136 if (state->i2c_client->irq) {
2137 err = devm_request_threaded_irq(&client->dev,
2138 state->i2c_client->irq,
2139 NULL, tc358743_irq_handler,
2140 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2141 "tc358743", state);
2142 if (err)
2143 goto err_work_queues;
4e66a52a
DS		 2144 } else {
2145 INIT_WORK(&state->work_i2c_poll,
2146 tc358743_work_i2c_poll);
a88cd60f 2147 timer_setup(&state->timer, tc358743_irq_poll_timer, 0);
4e66a52a
DS		 2148 state->timer.expires = jiffies +
2149 msecs_to_jiffies(POLL_INTERVAL_MS);
2150 add_timer(&state->timer);
d747b806
PZ		 2151 }
2152
a0ec8d1d
HV		 2153 err = cec_register_adapter(state->cec_adap, &client->dev);
2154 if (err < 0) {
2155 pr_err("%s: failed to register the cec device\n", __func__);
2156 cec_delete_adapter(state->cec_adap);
2157 state->cec_adap = NULL;
2158 goto err_work_queues;
2159 }
2160
d32d9864 2161 tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
a0ec8d1d 2162 i2c_wr16(sd, INTMASK, ~irq_mask);
d32d9864
MR		 2163
2164 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
2165 if (err)
2166 goto err_work_queues;
2167
2168 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2169 client->addr << 1, client->adapter->name);
2170
2171 return 0;
2172
2173err_work_queues:
a0ec8d1d 2174 cec_unregister_adapter(state->cec_adap);
4e66a52a
DS		 2175 if (!state->i2c_client->irq)
2176 flush_work(&state->work_i2c_poll);
d32d9864 2177 cancel_delayed_work(&state->delayed_work_enable_hotplug);
d32d9864
MR		 2178 mutex_destroy(&state->confctl_mutex);
2179err_hdl:
4c5211a1 2180 media_entity_cleanup(&sd->entity);
d32d9864
MR		 2181 v4l2_ctrl_handler_free(&state->hdl);
2182 return err;
2183}
2184
2185static int tc358743_remove(struct i2c_client *client)
2186{
2187 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2188 struct tc358743_state *state = to_state(sd);
2189
4e66a52a
DS		 2190 if (!state->i2c_client->irq) {
2191 del_timer_sync(&state->timer);
2192 flush_work(&state->work_i2c_poll);
2193 }
d32d9864 2194 cancel_delayed_work(&state->delayed_work_enable_hotplug);
a0ec8d1d 2195 cec_unregister_adapter(state->cec_adap);
4c5211a1 2196 v4l2_async_unregister_subdev(sd);
d32d9864
MR		 2197 v4l2_device_unregister_subdev(sd);
2198 mutex_destroy(&state->confctl_mutex);
4c5211a1 2199 media_entity_cleanup(&sd->entity);
d32d9864
MR		 2200 v4l2_ctrl_handler_free(&state->hdl);
2201
2202 return 0;
2203}
2204
2f8dfed8 2205static const struct i2c_device_id tc358743_id[] = {
d32d9864
MR		 2206 {"tc358743", 0},
2207 {}
2208};
2209
2210MODULE_DEVICE_TABLE(i2c, tc358743_id);
2211
c0746c1a
JMC		 2212#if IS_ENABLED(CONFIG_OF)
2213static const struct of_device_id tc358743_of_match[] = {
2214 { .compatible = "toshiba,tc358743" },
2215 {},
2216};
2217MODULE_DEVICE_TABLE(of, tc358743_of_match);
2218#endif
2219
d32d9864
MR		 2220static struct i2c_driver tc358743_driver = {
2221 .driver = {
d32d9864 2222 .name = "tc358743",
c0746c1a 2223 .of_match_table = of_match_ptr(tc358743_of_match),
d32d9864
MR		 2224 },
2225 .probe = tc358743_probe,
2226 .remove = tc358743_remove,
2227 .id_table = tc358743_id,
2228};
2229
2230module_i2c_driver(tc358743_driver);
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