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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / gpu / drm / omapdrm / dss / venc.c
CommitLineData
b2886273 1/*
b2886273 2 * Copyright (C) 2009 Nokia Corporation
6505d75c 3 * Author: Tomi Valkeinen <[email protected]>
b2886273
TV		 4 *
5 * VENC settings from TI's DSS driver
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "VENC"
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/clk.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/mutex.h>
28#include <linux/completion.h>
29#include <linux/delay.h>
30#include <linux/string.h>
31#include <linux/seq_file.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
4fbafaf3 34#include <linux/pm_runtime.h>
a2207021 35#include <linux/of.h>
09bffa6e 36#include <linux/of_graph.h>
736e60dd 37#include <linux/component.h>
34dfb85f 38#include <linux/sys_soc.h>
b2886273 39
32043da7 40#include "omapdss.h"
b2886273
TV		 41#include "dss.h"
42
b2886273
TV		 43/* Venc registers */
44#define VENC_REV_ID 0x00
45#define VENC_STATUS 0x04
46#define VENC_F_CONTROL 0x08
47#define VENC_VIDOUT_CTRL 0x10
48#define VENC_SYNC_CTRL 0x14
49#define VENC_LLEN 0x1C
50#define VENC_FLENS 0x20
51#define VENC_HFLTR_CTRL 0x24
52#define VENC_CC_CARR_WSS_CARR 0x28
53#define VENC_C_PHASE 0x2C
54#define VENC_GAIN_U 0x30
55#define VENC_GAIN_V 0x34
56#define VENC_GAIN_Y 0x38
57#define VENC_BLACK_LEVEL 0x3C
58#define VENC_BLANK_LEVEL 0x40
59#define VENC_X_COLOR 0x44
60#define VENC_M_CONTROL 0x48
61#define VENC_BSTAMP_WSS_DATA 0x4C
62#define VENC_S_CARR 0x50
63#define VENC_LINE21 0x54
64#define VENC_LN_SEL 0x58
65#define VENC_L21__WC_CTL 0x5C
66#define VENC_HTRIGGER_VTRIGGER 0x60
67#define VENC_SAVID__EAVID 0x64
68#define VENC_FLEN__FAL 0x68
69#define VENC_LAL__PHASE_RESET 0x6C
70#define VENC_HS_INT_START_STOP_X 0x70
71#define VENC_HS_EXT_START_STOP_X 0x74
72#define VENC_VS_INT_START_X 0x78
73#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
74#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
75#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
76#define VENC_VS_EXT_STOP_Y 0x88
77#define VENC_AVID_START_STOP_X 0x90
78#define VENC_AVID_START_STOP_Y 0x94
79#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
80#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
81#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
82#define VENC_TVDETGP_INT_START_STOP_X 0xB0
83#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
84#define VENC_GEN_CTRL 0xB8
85#define VENC_OUTPUT_CONTROL 0xC4
86#define VENC_OUTPUT_TEST 0xC8
87#define VENC_DAC_B__DAC_C 0xC8
88
89struct venc_config {
90 u32 f_control;
91 u32 vidout_ctrl;
92 u32 sync_ctrl;
93 u32 llen;
94 u32 flens;
95 u32 hfltr_ctrl;
96 u32 cc_carr_wss_carr;
97 u32 c_phase;
98 u32 gain_u;
99 u32 gain_v;
100 u32 gain_y;
101 u32 black_level;
102 u32 blank_level;
103 u32 x_color;
104 u32 m_control;
105 u32 bstamp_wss_data;
106 u32 s_carr;
107 u32 line21;
108 u32 ln_sel;
109 u32 l21__wc_ctl;
110 u32 htrigger_vtrigger;
111 u32 savid__eavid;
112 u32 flen__fal;
113 u32 lal__phase_reset;
114 u32 hs_int_start_stop_x;
115 u32 hs_ext_start_stop_x;
116 u32 vs_int_start_x;
117 u32 vs_int_stop_x__vs_int_start_y;
118 u32 vs_int_stop_y__vs_ext_start_x;
119 u32 vs_ext_stop_x__vs_ext_start_y;
120 u32 vs_ext_stop_y;
121 u32 avid_start_stop_x;
122 u32 avid_start_stop_y;
123 u32 fid_int_start_x__fid_int_start_y;
124 u32 fid_int_offset_y__fid_ext_start_x;
125 u32 fid_ext_start_y__fid_ext_offset_y;
126 u32 tvdetgp_int_start_stop_x;
127 u32 tvdetgp_int_start_stop_y;
128 u32 gen_ctrl;
129};
130
131/* from TRM */
132static const struct venc_config venc_config_pal_trm = {
133 .f_control = 0,
134 .vidout_ctrl = 1,
135 .sync_ctrl = 0x40,
136 .llen = 0x35F, /* 863 */
137 .flens = 0x270, /* 624 */
138 .hfltr_ctrl = 0,
139 .cc_carr_wss_carr = 0x2F7225ED,
140 .c_phase = 0,
141 .gain_u = 0x111,
142 .gain_v = 0x181,
143 .gain_y = 0x140,
144 .black_level = 0x3B,
145 .blank_level = 0x3B,
146 .x_color = 0x7,
147 .m_control = 0x2,
148 .bstamp_wss_data = 0x3F,
149 .s_carr = 0x2A098ACB,
150 .line21 = 0,
151 .ln_sel = 0x01290015,
152 .l21__wc_ctl = 0x0000F603,
153 .htrigger_vtrigger = 0,
154
155 .savid__eavid = 0x06A70108,
156 .flen__fal = 0x00180270,
157 .lal__phase_reset = 0x00040135,
158 .hs_int_start_stop_x = 0x00880358,
159 .hs_ext_start_stop_x = 0x000F035F,
160 .vs_int_start_x = 0x01A70000,
161 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
164 .vs_ext_stop_y = 0x00000025,
165 .avid_start_stop_x = 0x03530083,
166 .avid_start_stop_y = 0x026C002E,
167 .fid_int_start_x__fid_int_start_y = 0x0001008A,
168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
170
171 .tvdetgp_int_start_stop_x = 0x00140001,
172 .tvdetgp_int_start_stop_y = 0x00010001,
173 .gen_ctrl = 0x00FF0000,
174};
175
176/* from TRM */
177static const struct venc_config venc_config_ntsc_trm = {
178 .f_control = 0,
179 .vidout_ctrl = 1,
180 .sync_ctrl = 0x8040,
181 .llen = 0x359,
182 .flens = 0x20C,
183 .hfltr_ctrl = 0,
184 .cc_carr_wss_carr = 0x043F2631,
185 .c_phase = 0,
186 .gain_u = 0x102,
187 .gain_v = 0x16C,
188 .gain_y = 0x12F,
189 .black_level = 0x43,
190 .blank_level = 0x38,
191 .x_color = 0x7,
192 .m_control = 0x1,
193 .bstamp_wss_data = 0x38,
194 .s_carr = 0x21F07C1F,
195 .line21 = 0,
196 .ln_sel = 0x01310011,
197 .l21__wc_ctl = 0x0000F003,
198 .htrigger_vtrigger = 0,
199
200 .savid__eavid = 0x069300F4,
201 .flen__fal = 0x0016020C,
202 .lal__phase_reset = 0x00060107,
203 .hs_int_start_stop_x = 0x008E0350,
204 .hs_ext_start_stop_x = 0x000F0359,
205 .vs_int_start_x = 0x01A00000,
206 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
209 .vs_ext_stop_y = 0x00000006,
210 .avid_start_stop_x = 0x03480078,
211 .avid_start_stop_y = 0x02060024,
212 .fid_int_start_x__fid_int_start_y = 0x0001008A,
213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
215
216 .tvdetgp_int_start_stop_x = 0x00140001,
217 .tvdetgp_int_start_stop_y = 0x00010001,
218 .gen_ctrl = 0x00F90000,
219};
220
221static const struct venc_config venc_config_pal_bdghi = {
222 .f_control = 0,
223 .vidout_ctrl = 0,
224 .sync_ctrl = 0,
225 .hfltr_ctrl = 0,
226 .x_color = 0,
227 .line21 = 0,
228 .ln_sel = 21,
229 .htrigger_vtrigger = 0,
230 .tvdetgp_int_start_stop_x = 0x00140001,
231 .tvdetgp_int_start_stop_y = 0x00010001,
232 .gen_ctrl = 0x00FB0000,
233
234 .llen = 864-1,
235 .flens = 625-1,
236 .cc_carr_wss_carr = 0x2F7625ED,
237 .c_phase = 0xDF,
238 .gain_u = 0x111,
239 .gain_v = 0x181,
240 .gain_y = 0x140,
241 .black_level = 0x3e,
242 .blank_level = 0x3e,
243 .m_control = 0<<2 | 1<<1,
244 .bstamp_wss_data = 0x42,
245 .s_carr = 0x2a098acb,
246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
247 .savid__eavid = 0x06A70108,
248 .flen__fal = 23<<16 | 624<<0,
249 .lal__phase_reset = 2<<17 | 310<<0,
250 .hs_int_start_stop_x = 0x00920358,
251 .hs_ext_start_stop_x = 0x000F035F,
252 .vs_int_start_x = 0x1a7<<16,
253 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
256 .vs_ext_stop_y = 0x05,
257 .avid_start_stop_x = 0x03530082,
258 .avid_start_stop_y = 0x0270002E,
259 .fid_int_start_x__fid_int_start_y = 0x0005008A,
260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
262};
263
beea6214
TV		 264enum venc_videomode {
265 VENC_MODE_UNKNOWN,
266 VENC_MODE_PAL,
267 VENC_MODE_NTSC,
268};
269
d6964307 270static const struct videomode omap_dss_pal_vm = {
81899060 271 .hactive = 720,
fb7f3c43 272 .vactive = 574,
d8d78941 273 .pixelclock = 13500000,
4dc2250d 274 .hsync_len = 64,
0a30e150 275 .hfront_porch = 12,
a85f4a80 276 .hback_porch = 68,
d5bcf0aa 277 .vsync_len = 5,
0996c68e 278 .vfront_porch = 5,
458540c6 279 .vback_porch = 41,
23c8f88e 280
6b44cd27 281 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
f149e17a 282 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
d34afb73
PU		 283 DISPLAY_FLAGS_PIXDATA_POSEDGE |
284 DISPLAY_FLAGS_SYNC_NEGEDGE,
b2886273 285};
b2886273 286
d6964307 287static const struct videomode omap_dss_ntsc_vm = {
81899060 288 .hactive = 720,
fb7f3c43 289 .vactive = 482,
d8d78941 290 .pixelclock = 13500000,
4dc2250d 291 .hsync_len = 64,
0a30e150 292 .hfront_porch = 16,
a85f4a80 293 .hback_porch = 58,
d5bcf0aa 294 .vsync_len = 6,
0996c68e 295 .vfront_porch = 6,
458540c6 296 .vback_porch = 31,
23c8f88e 297
6b44cd27 298 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
f149e17a 299 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
d34afb73
PU		 300 DISPLAY_FLAGS_PIXDATA_POSEDGE |
301 DISPLAY_FLAGS_SYNC_NEGEDGE,
b2886273 302};
b2886273 303
beea6214
TV		 304static enum venc_videomode venc_get_videomode(const struct videomode *vm)
305{
306 if (!(vm->flags & DISPLAY_FLAGS_INTERLACED))
307 return VENC_MODE_UNKNOWN;
308
309 if (vm->pixelclock == omap_dss_pal_vm.pixelclock &&
310 vm->hactive == omap_dss_pal_vm.hactive &&
311 vm->vactive == omap_dss_pal_vm.vactive)
312 return VENC_MODE_PAL;
313
314 if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock &&
315 vm->hactive == omap_dss_ntsc_vm.hactive &&
316 vm->vactive == omap_dss_ntsc_vm.vactive)
317 return VENC_MODE_NTSC;
318
319 return VENC_MODE_UNKNOWN;
320}
321
663ac57b 322struct venc_device {
30ea50c9 323 struct platform_device *pdev;
b2886273
TV		 324 void __iomem *base;
325 struct mutex venc_lock;
326 u32 wss_data;
327 struct regulator *vdda_dac_reg;
1ef904e1 328 struct dss_device *dss;
4fbafaf3 329
f33656e1
LP		 330 struct dss_debugfs_entry *debugfs;
331
4fbafaf3 332 struct clk *tv_dac_clk;
a5abf472 333
da11bbbb 334 struct videomode vm;
febe2905 335 enum omap_dss_venc_type type;
89e71956 336 bool invert_polarity;
34dfb85f 337 bool requires_tv_dac_clk;
81b87f51 338
1f68d9c4 339 struct omap_dss_device output;
663ac57b
LP		 340};
341
342#define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output)
b2886273 343
663ac57b 344static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
b2886273 345{
663ac57b 346 __raw_writel(val, venc->base + idx);
b2886273
TV		 347}
348
663ac57b 349static inline u32 venc_read_reg(struct venc_device *venc, int idx)
b2886273 350{
663ac57b 351 u32 l = __raw_readl(venc->base + idx);
b2886273
TV		 352 return l;
353}
354
663ac57b
LP		 355static void venc_write_config(struct venc_device *venc,
356 const struct venc_config *config)
b2886273
TV		 357{
358 DSSDBG("write venc conf\n");
359
663ac57b
LP		 360 venc_write_reg(venc, VENC_LLEN, config->llen);
361 venc_write_reg(venc, VENC_FLENS, config->flens);
362 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
363 venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
364 venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
365 venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
366 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
367 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
368 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
369 venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
370 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
371 venc->wss_data);
372 venc_write_reg(venc, VENC_S_CARR, config->s_carr);
373 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
374 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
375 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
376 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
377 venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
378 config->hs_int_start_stop_x);
379 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
380 config->hs_ext_start_stop_x);
381 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
382 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
b2886273 383 config->vs_int_stop_x__vs_int_start_y);
663ac57b 384 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
b2886273 385 config->vs_int_stop_y__vs_ext_start_x);
663ac57b 386 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
b2886273 387 config->vs_ext_stop_x__vs_ext_start_y);
663ac57b
LP		 388 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
389 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
390 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
391 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
b2886273 392 config->fid_int_start_x__fid_int_start_y);
663ac57b 393 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
b2886273 394 config->fid_int_offset_y__fid_ext_start_x);
663ac57b 395 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
b2886273
TV		 396 config->fid_ext_start_y__fid_ext_offset_y);
397
663ac57b
LP		 398 venc_write_reg(venc, VENC_DAC_B__DAC_C,
399 venc_read_reg(venc, VENC_DAC_B__DAC_C));
400 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
401 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
402 venc_write_reg(venc, VENC_X_COLOR, config->x_color);
403 venc_write_reg(venc, VENC_LINE21, config->line21);
404 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
405 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
406 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
b2886273 407 config->tvdetgp_int_start_stop_x);
663ac57b 408 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
b2886273 409 config->tvdetgp_int_start_stop_y);
663ac57b
LP		 410 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
411 venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
412 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
b2886273
TV		 413}
414
663ac57b 415static void venc_reset(struct venc_device *venc)
b2886273
TV		 416{
417 int t = 1000;
418
663ac57b
LP		 419 venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
420 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
b2886273
TV		 421 if (--t == 0) {
422 DSSERR("Failed to reset venc\n");
423 return;
424 }
425 }
426
c6f65e1a 427#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
b2886273 428 /* the magical sleep that makes things work */
c6f65e1a 429 /* XXX more info? What bug this circumvents? */
b2886273 430 msleep(20);
c6f65e1a 431#endif
b2886273
TV		 432}
433
663ac57b 434static int venc_runtime_get(struct venc_device *venc)
b2886273 435{
4fbafaf3
TV		 436 int r;
437
438 DSSDBG("venc_runtime_get\n");
439
663ac57b 440 r = pm_runtime_get_sync(&venc->pdev->dev);
4fbafaf3
TV		 441 WARN_ON(r < 0);
442 return r < 0 ? r : 0;
443}
444
663ac57b 445static void venc_runtime_put(struct venc_device *venc)
4fbafaf3
TV		 446{
447 int r;
448
449 DSSDBG("venc_runtime_put\n");
450
663ac57b 451 r = pm_runtime_put_sync(&venc->pdev->dev);
5be3aebd 452 WARN_ON(r < 0 && r != -ENOSYS);
b2886273
TV		 453}
454
a730ce99 455static const struct venc_config *venc_timings_to_config(const struct videomode *vm)
b2886273 456{
beea6214
TV		 457 switch (venc_get_videomode(vm)) {
458 default:
459 WARN_ON_ONCE(1);
460 case VENC_MODE_PAL:
b2886273 461 return &venc_config_pal_trm;
beea6214 462 case VENC_MODE_NTSC:
b2886273 463 return &venc_config_ntsc_trm;
beea6214 464 }
b2886273
TV		 465}
466
663ac57b 467static int venc_power_on(struct venc_device *venc)
37ac60e4
TV		 468{
469 u32 l;
33ca237f 470 int r;
37ac60e4 471
663ac57b 472 r = venc_runtime_get(venc);
156fd99e
AT		 473 if (r)
474 goto err0;
475
663ac57b
LP		 476 venc_reset(venc);
477 venc_write_config(venc, venc_timings_to_config(&venc->vm));
37ac60e4 478
663ac57b
LP		 479 dss_set_venc_output(venc->dss, venc->type);
480 dss_set_dac_pwrdn_bgz(venc->dss, 1);
37ac60e4
TV		 481
482 l = 0;
483
663ac57b 484 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
37ac60e4
TV		 485 l |= 1 << 1;
486 else /* S-Video */
487 l |= (1 << 0) | (1 << 2);
488
663ac57b 489 if (venc->invert_polarity == false)
37ac60e4
TV		 490 l |= 1 << 3;
491
663ac57b 492 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
37ac60e4 493
663ac57b 494 r = regulator_enable(venc->vdda_dac_reg);
ec874107 495 if (r)
156fd99e 496 goto err1;
37ac60e4 497
663ac57b 498 r = dss_mgr_enable(&venc->output);
33ca237f 499 if (r)
156fd99e 500 goto err2;
33ca237f
TV		 501
502 return 0;
503
156fd99e 504err2:
663ac57b 505 regulator_disable(venc->vdda_dac_reg);
156fd99e 506err1:
663ac57b
LP		 507 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
508 dss_set_dac_pwrdn_bgz(venc->dss, 0);
33ca237f 509
663ac57b 510 venc_runtime_put(venc);
156fd99e 511err0:
33ca237f 512 return r;
37ac60e4
TV		 513}
514
663ac57b 515static void venc_power_off(struct venc_device *venc)
37ac60e4 516{
663ac57b
LP		 517 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
518 dss_set_dac_pwrdn_bgz(venc->dss, 0);
37ac60e4 519
663ac57b 520 dss_mgr_disable(&venc->output);
37ac60e4 521
663ac57b 522 regulator_disable(venc->vdda_dac_reg);
156fd99e 523
663ac57b 524 venc_runtime_put(venc);
37ac60e4
TV		 525}
526
09d2e7cd 527static int venc_display_enable(struct omap_dss_device *dssdev)
0aca3c63 528{
663ac57b 529 struct venc_device *venc = dssdev_to_venc(dssdev);
156fd99e 530 int r;
0aca3c63 531
156fd99e 532 DSSDBG("venc_display_enable\n");
0aca3c63 533
663ac57b 534 mutex_lock(&venc->venc_lock);
0aca3c63 535
663ac57b 536 if (!dssdev->dispc_channel_connected) {
8f1f736c 537 DSSERR("Failed to enable display: no output/manager\n");
156fd99e
AT		 538 r = -ENODEV;
539 goto err0;
0aca3c63
GI		 540 }
541
663ac57b 542 r = venc_power_on(venc);
33ca237f 543 if (r)
d3923933 544 goto err0;
37ac60e4 545
663ac57b 546 venc->wss_data = 0;
37ac60e4 547
663ac57b 548 mutex_unlock(&venc->venc_lock);
156fd99e 549
14572c63 550 return 0;
14572c63 551err0:
663ac57b 552 mutex_unlock(&venc->venc_lock);
b2886273
TV		 553 return r;
554}
555
09d2e7cd 556static void venc_display_disable(struct omap_dss_device *dssdev)
b2886273 557{
663ac57b
LP		 558 struct venc_device *venc = dssdev_to_venc(dssdev);
559
156fd99e 560 DSSDBG("venc_display_disable\n");
b2886273 561
663ac57b 562 mutex_lock(&venc->venc_lock);
37ac60e4 563
663ac57b 564 venc_power_off(venc);
37ac60e4 565
663ac57b 566 mutex_unlock(&venc->venc_lock);
b2886273
TV		 567}
568
35d944cb
LP		 569static void venc_get_timings(struct omap_dss_device *dssdev,
570 struct videomode *vm)
571{
572 struct venc_device *venc = dssdev_to_venc(dssdev);
573
574 mutex_lock(&venc->venc_lock);
575 *vm = venc->vm;
576 mutex_unlock(&venc->venc_lock);
577}
578
09d2e7cd 579static void venc_set_timings(struct omap_dss_device *dssdev,
8fe1d361 580 const struct videomode *vm)
69b2048f 581{
663ac57b 582 struct venc_device *venc = dssdev_to_venc(dssdev);
beea6214 583
69b2048f
TV		 584 DSSDBG("venc_set_timings\n");
585
663ac57b 586 mutex_lock(&venc->venc_lock);
156fd99e 587
69b2048f 588 /* Reset WSS data when the TV standard changes. */
a730ce99 589 if (memcmp(&venc->vm, vm, sizeof(*vm)))
663ac57b 590 venc->wss_data = 0;
69b2048f 591
a730ce99 592 venc->vm = *vm;
156fd99e 593
663ac57b 594 dispc_set_tv_pclk(venc->dss->dispc, 13500000);
5391e87d 595
663ac57b 596 mutex_unlock(&venc->venc_lock);
69b2048f
TV		 597}
598
09d2e7cd 599static int venc_check_timings(struct omap_dss_device *dssdev,
da11bbbb 600 struct videomode *vm)
69b2048f
TV		 601{
602 DSSDBG("venc_check_timings\n");
603
beea6214
TV		 604 switch (venc_get_videomode(vm)) {
605 case VENC_MODE_PAL:
a730ce99
LP		 606 *vm = omap_dss_pal_vm;
607 return 0;
608
beea6214 609 case VENC_MODE_NTSC:
a730ce99 610 *vm = omap_dss_ntsc_vm;
69b2048f 611 return 0;
a730ce99 612
beea6214
TV		 613 default:
614 return -EINVAL;
615 }
69b2048f
TV		 616}
617
f33656e1 618static int venc_dump_regs(struct seq_file *s, void *p)
b2886273 619{
663ac57b
LP		 620 struct venc_device *venc = s->private;
621
622#define DUMPREG(venc, r) \
623 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
b2886273 624
663ac57b 625 if (venc_runtime_get(venc))
f33656e1 626 return 0;
b2886273 627
663ac57b
LP		 628 DUMPREG(venc, VENC_F_CONTROL);
629 DUMPREG(venc, VENC_VIDOUT_CTRL);
630 DUMPREG(venc, VENC_SYNC_CTRL);
631 DUMPREG(venc, VENC_LLEN);
632 DUMPREG(venc, VENC_FLENS);
633 DUMPREG(venc, VENC_HFLTR_CTRL);
634 DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
635 DUMPREG(venc, VENC_C_PHASE);
636 DUMPREG(venc, VENC_GAIN_U);
637 DUMPREG(venc, VENC_GAIN_V);
638 DUMPREG(venc, VENC_GAIN_Y);
639 DUMPREG(venc, VENC_BLACK_LEVEL);
640 DUMPREG(venc, VENC_BLANK_LEVEL);
641 DUMPREG(venc, VENC_X_COLOR);
642 DUMPREG(venc, VENC_M_CONTROL);
643 DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
644 DUMPREG(venc, VENC_S_CARR);
645 DUMPREG(venc, VENC_LINE21);
646 DUMPREG(venc, VENC_LN_SEL);
647 DUMPREG(venc, VENC_L21__WC_CTL);
648 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
649 DUMPREG(venc, VENC_SAVID__EAVID);
650 DUMPREG(venc, VENC_FLEN__FAL);
651 DUMPREG(venc, VENC_LAL__PHASE_RESET);
652 DUMPREG(venc, VENC_HS_INT_START_STOP_X);
653 DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
654 DUMPREG(venc, VENC_VS_INT_START_X);
655 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
656 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
657 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
658 DUMPREG(venc, VENC_VS_EXT_STOP_Y);
659 DUMPREG(venc, VENC_AVID_START_STOP_X);
660 DUMPREG(venc, VENC_AVID_START_STOP_Y);
661 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
662 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
663 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
664 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
665 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
666 DUMPREG(venc, VENC_GEN_CTRL);
667 DUMPREG(venc, VENC_OUTPUT_CONTROL);
668 DUMPREG(venc, VENC_OUTPUT_TEST);
669
670 venc_runtime_put(venc);
b2886273
TV		 671
672#undef DUMPREG
f33656e1 673 return 0;
b2886273 674}
30ea50c9 675
663ac57b 676static int venc_get_clocks(struct venc_device *venc)
4fbafaf3
TV		 677{
678 struct clk *clk;
679
663ac57b
LP		 680 if (venc->requires_tv_dac_clk) {
681 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
4fbafaf3
TV		 682 if (IS_ERR(clk)) {
683 DSSERR("can't get tv_dac_clk\n");
4fbafaf3
TV		 684 return PTR_ERR(clk);
685 }
686 } else {
687 clk = NULL;
688 }
689
663ac57b 690 venc->tv_dac_clk = clk;
4fbafaf3
TV		 691
692 return 0;
693}
694
511afb44
LP		 695static int venc_connect(struct omap_dss_device *src,
696 struct omap_dss_device *dst)
fb8efa49 697{
fb8efa49
TV		 698 int r;
699
71316556 700 r = omapdss_device_connect(dst->dss, dst, dst->next);
43f7078f 701 if (r)
71316556 702 return r;
fb8efa49 703
0f37938c 704 dst->dispc_channel_connected = true;
fb8efa49
TV		 705 return 0;
706}
707
511afb44
LP		 708static void venc_disconnect(struct omap_dss_device *src,
709 struct omap_dss_device *dst)
fb8efa49 710{
0f37938c
LP		 711 dst->dispc_channel_connected = false;
712
511afb44 713 omapdss_device_disconnect(dst, dst->next);
fb8efa49
TV		 714}
715
b93109d7 716static const struct omap_dss_device_ops venc_ops = {
fb8efa49
TV		 717 .connect = venc_connect,
718 .disconnect = venc_disconnect,
719
09d2e7cd
TV		 720 .enable = venc_display_enable,
721 .disable = venc_display_disable,
fb8efa49 722
09d2e7cd 723 .check_timings = venc_check_timings,
35d944cb 724 .get_timings = venc_get_timings,
09d2e7cd 725 .set_timings = venc_set_timings,
fb8efa49
TV		 726};
727
c8719326
LP		 728/* -----------------------------------------------------------------------------
729 * Component Bind & Unbind
730 */
731
732static int venc_bind(struct device *dev, struct device *master, void *data)
733{
734 struct dss_device *dss = dss_get_device(master);
735 struct venc_device *venc = dev_get_drvdata(dev);
736 u8 rev_id;
737 int r;
738
739 venc->dss = dss;
740
741 r = venc_runtime_get(venc);
742 if (r)
743 return r;
744
745 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
746 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id);
747
748 venc_runtime_put(venc);
749
750 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
751 venc);
752
753 return 0;
754}
755
756static void venc_unbind(struct device *dev, struct device *master, void *data)
757{
758 struct venc_device *venc = dev_get_drvdata(dev);
759
760 dss_debugfs_remove_file(venc->debugfs);
761}
762
763static const struct component_ops venc_component_ops = {
764 .bind = venc_bind,
765 .unbind = venc_unbind,
766};
767
768/* -----------------------------------------------------------------------------
769 * Probe & Remove, Suspend & Resume
770 */
771
27d62452 772static int venc_init_output(struct venc_device *venc)
81b87f51 773{
663ac57b 774 struct omap_dss_device *out = &venc->output;
71316556 775 int r;
81b87f51 776
663ac57b 777 out->dev = &venc->pdev->dev;
81b87f51 778 out->id = OMAP_DSS_OUTPUT_VENC;
1f68d9c4 779 out->output_type = OMAP_DISPLAY_TYPE_VENC;
7286a08f 780 out->name = "venc.0";
2eea5ae6 781 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
b93109d7 782 out->ops = &venc_ops;
b7328e14 783 out->owner = THIS_MODULE;
4e20bda6 784 out->of_ports = BIT(0);
81b87f51 785
27d62452
LP		 786 out->next = omapdss_of_find_connected_device(out->dev->of_node, 0);
787 if (IS_ERR(out->next)) {
788 if (PTR_ERR(out->next) != -EPROBE_DEFER)
789 dev_err(out->dev, "failed to find video sink\n");
790 return PTR_ERR(out->next);
791 }
792
71316556
LP		 793 r = omapdss_output_validate(out);
794 if (r) {
795 omapdss_device_put(out->next);
796 out->next = NULL;
797 return r;
798 }
799
de57e9db 800 omapdss_device_register(out);
27d62452
LP		 801
802 return 0;
81b87f51
AT		 803}
804
663ac57b 805static void venc_uninit_output(struct venc_device *venc)
81b87f51 806{
27d62452
LP		 807 if (venc->output.next)
808 omapdss_device_put(venc->output.next);
de57e9db 809 omapdss_device_unregister(&venc->output);
81b87f51
AT		 810}
811
663ac57b 812static int venc_probe_of(struct venc_device *venc)
a2207021 813{
663ac57b 814 struct device_node *node = venc->pdev->dev.of_node;
a2207021
TV		 815 struct device_node *ep;
816 u32 channels;
817 int r;
818
09bffa6e 819 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
a2207021
TV		 820 if (!ep)
821 return 0;
822
663ac57b 823 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
a2207021
TV		 824
825 r = of_property_read_u32(ep, "ti,channels", &channels);
826 if (r) {
663ac57b 827 dev_err(&venc->pdev->dev,
a2207021
TV		 828 "failed to read property 'ti,channels': %d\n", r);
829 goto err;
830 }
831
832 switch (channels) {
833 case 1:
663ac57b 834 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
a2207021
TV		 835 break;
836 case 2:
663ac57b 837 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
a2207021
TV		 838 break;
839 default:
663ac57b
LP		 840 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
841 channels);
a2207021
TV		 842 r = -EINVAL;
843 goto err;
844 }
845
846 of_node_put(ep);
847
848 return 0;
18cbe723 849
a2207021
TV		 850err:
851 of_node_put(ep);
18cbe723 852 return r;
a2207021
TV		 853}
854
34dfb85f
LP		 855static const struct soc_device_attribute venc_soc_devices[] = {
856 { .machine = "OMAP3[45]*" },
857 { .machine = "AM35*" },
858 { /* sentinel */ }
859};
860
c8719326 861static int venc_probe(struct platform_device *pdev)
30ea50c9 862{
663ac57b 863 struct venc_device *venc;
ea9da36a 864 struct resource *venc_mem;
38f3daf6 865 int r;
ea9da36a 866
663ac57b
LP		 867 venc = kzalloc(sizeof(*venc), GFP_KERNEL);
868 if (!venc)
869 return -ENOMEM;
870
871 venc->pdev = pdev;
c8719326
LP		 872
873 platform_set_drvdata(pdev, venc);
30ea50c9 874
34dfb85f
LP		 875 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
876 if (soc_device_match(venc_soc_devices))
663ac57b 877 venc->requires_tv_dac_clk = true;
34dfb85f 878
663ac57b 879 mutex_init(&venc->venc_lock);
30ea50c9 880
663ac57b 881 venc->wss_data = 0;
35d944cb 882 venc->vm = omap_dss_pal_vm;
30ea50c9 883
663ac57b
LP		 884 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
885 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
886 if (IS_ERR(venc->base)) {
887 r = PTR_ERR(venc->base);
888 goto err_free;
889 }
30ea50c9 890
8a36357a
LP		 891 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
892 if (IS_ERR(venc->vdda_dac_reg)) {
893 r = PTR_ERR(venc->vdda_dac_reg);
894 if (r != -EPROBE_DEFER)
895 DSSERR("can't get VDDA_DAC regulator\n");
896 goto err_free;
897 }
898
663ac57b 899 r = venc_get_clocks(venc);
4fbafaf3 900 if (r)
663ac57b 901 goto err_free;
4fbafaf3 902
663ac57b 903 r = venc_probe_of(venc);
c8719326
LP		 904 if (r)
905 goto err_free;
a2207021 906
c8719326 907 pm_runtime_enable(&pdev->dev);
e40402cf 908
27d62452
LP		 909 r = venc_init_output(venc);
910 if (r)
911 goto err_pm_disable;
81b87f51 912
c8719326
LP		 913 r = component_add(&pdev->dev, &venc_component_ops);
914 if (r)
915 goto err_uninit_output;
916
cd3b3449 917 return 0;
4fbafaf3 918
c8719326
LP		 919err_uninit_output:
920 venc_uninit_output(venc);
27d62452 921err_pm_disable:
4fbafaf3 922 pm_runtime_disable(&pdev->dev);
663ac57b
LP		 923err_free:
924 kfree(venc);
4fbafaf3 925 return r;
30ea50c9
SG		 926}
927
c8719326 928static int venc_remove(struct platform_device *pdev)
30ea50c9 929{
c8719326 930 struct venc_device *venc = platform_get_drvdata(pdev);
736e60dd 931
c8719326 932 component_del(&pdev->dev, &venc_component_ops);
f33656e1 933
663ac57b 934 venc_uninit_output(venc);
81b87f51 935
c8719326 936 pm_runtime_disable(&pdev->dev);
663ac57b
LP		 937
938 kfree(venc);
30ea50c9
SG		 939 return 0;
940}
941
4fbafaf3
TV		 942static int venc_runtime_suspend(struct device *dev)
943{
663ac57b
LP		 944 struct venc_device *venc = dev_get_drvdata(dev);
945
946 if (venc->tv_dac_clk)
947 clk_disable_unprepare(venc->tv_dac_clk);
4fbafaf3 948
4fbafaf3
TV		 949 return 0;
950}
951
952static int venc_runtime_resume(struct device *dev)
953{
663ac57b 954 struct venc_device *venc = dev_get_drvdata(dev);
4fbafaf3 955
663ac57b
LP		 956 if (venc->tv_dac_clk)
957 clk_prepare_enable(venc->tv_dac_clk);
4fbafaf3
TV		 958
959 return 0;
4fbafaf3
TV		 960}
961
962static const struct dev_pm_ops venc_pm_ops = {
963 .runtime_suspend = venc_runtime_suspend,
964 .runtime_resume = venc_runtime_resume,
965};
966
a2207021
TV		 967static const struct of_device_id venc_of_match[] = {
968 { .compatible = "ti,omap2-venc", },
969 { .compatible = "ti,omap3-venc", },
970 { .compatible = "ti,omap4-venc", },
971 {},
972};
973
d66c36a3 974struct platform_driver omap_venchw_driver = {
736e60dd
TV		 975 .probe = venc_probe,
976 .remove = venc_remove,
30ea50c9
SG		 977 .driver = {
978 .name = "omapdss_venc",
4fbafaf3 979 .pm = &venc_pm_ops,
a2207021 980 .of_match_table = venc_of_match,
422ccbd5 981 .suppress_bind_attrs = true,
30ea50c9
SG		 982 },
983};
Empty description
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