]> Git Repo - linux.git/blame - drivers/gpu/drm/meson/meson_venc.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / gpu / drm / meson / meson_venc.c
CommitLineData
bbbe775e
NA		 1/*
2 * Copyright (C) 2016 BayLibre, SAS
3 * Author: Neil Armstrong <[email protected]>
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <drm/drmP.h>
23#include "meson_drv.h"
24#include "meson_venc.h"
25#include "meson_vpp.h"
26#include "meson_vclk.h"
27#include "meson_registers.h"
28
2021d5b7
NA		 29/**
30 * DOC: Video Encoder
31 *
bbbe775e
NA		 32 * VENC Handle the pixels encoding to the output formats.
33 * We handle the following encodings :
2021d5b7 34 *
bbbe775e 35 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
bbbe775e
NA		 36 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
37 * - Setup of more clock rates for HDMI modes
335e3713
NA		 38 *
39 * What is missing :
2021d5b7 40 *
bbbe775e
NA		 41 * - LCD Panel encoding via ENCL
42 * - TV Panel encoding via ENCT
335e3713
NA		 43 *
44 * VENC paths :
2021d5b7
NA		 45 *
46 * .. code::
47 *
48 * _____ _____ ____________________
49 * vd1---| |-| | | VENC /---------|----VDAC
50 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
51 * osd1--| |-| | | \ | X--HDMI-TX
52 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
53 * | | |
54 * | \--ENCL-----------|----LVDS
55 * |____________________|
335e3713
NA		 56 *
57 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
58 * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI.
59 * The ENCP is designed for Progressive encoding but can also generate
60 * 1080i interlaced pixels, and was initialy desined to encode pixels for
61 * VDAC to output RGB ou YUV analog outputs.
62 * It's output is only used through the ENCP_DVI encoder for HDMI.
63 * The ENCL LVDS encoder is not implemented.
64 *
65 * The ENCI and ENCP encoders needs specially defined parameters for each
66 * supported mode and thus cannot be determined from standard video timings.
67 *
68 * The ENCI end ENCP DVI encoders are more generic and can generate any timings
69 * from the pixel data generated by ENCI or ENCP, so can use the standard video
70 * timings are source for HW parameters.
bbbe775e
NA		 71 */
72
0c931a29 73/* HHI Registers */
2bcd3eca 74#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
0c931a29
NA		 75#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
76#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
77#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
78
bbbe775e
NA		 79struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
80 .mode_tag = MESON_VENC_MODE_CVBS_PAL,
81 .hso_begin = 3,
82 .hso_end = 129,
83 .vso_even = 3,
84 .vso_odd = 260,
85 .macv_max_amp = 7,
86 .video_prog_mode = 0xff,
87 .video_mode = 0x13,
88 .sch_adjust = 0x28,
89 .yc_delay = 0x343,
90 .pixel_start = 251,
91 .pixel_end = 1691,
92 .top_field_line_start = 22,
93 .top_field_line_end = 310,
94 .bottom_field_line_start = 23,
95 .bottom_field_line_end = 311,
96 .video_saturation = 9,
97 .video_contrast = 0,
98 .video_brightness = 0,
99 .video_hue = 0,
100 .analog_sync_adj = 0x8080,
101};
102
103struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
104 .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
105 .hso_begin = 5,
106 .hso_end = 129,
107 .vso_even = 3,
108 .vso_odd = 260,
109 .macv_max_amp = 0xb,
110 .video_prog_mode = 0xf0,
111 .video_mode = 0x8,
112 .sch_adjust = 0x20,
113 .yc_delay = 0x333,
114 .pixel_start = 227,
115 .pixel_end = 1667,
116 .top_field_line_start = 18,
117 .top_field_line_end = 258,
118 .bottom_field_line_start = 19,
119 .bottom_field_line_end = 259,
120 .video_saturation = 18,
121 .video_contrast = 3,
122 .video_brightness = 0,
123 .video_hue = 0,
124 .analog_sync_adj = 0x9c00,
125};
126
335e3713
NA		 127union meson_hdmi_venc_mode {
128 struct {
129 unsigned int mode_tag;
130 unsigned int hso_begin;
131 unsigned int hso_end;
132 unsigned int vso_even;
133 unsigned int vso_odd;
134 unsigned int macv_max_amp;
135 unsigned int video_prog_mode;
136 unsigned int video_mode;
137 unsigned int sch_adjust;
138 unsigned int yc_delay;
139 unsigned int pixel_start;
140 unsigned int pixel_end;
141 unsigned int top_field_line_start;
142 unsigned int top_field_line_end;
143 unsigned int bottom_field_line_start;
144 unsigned int bottom_field_line_end;
145 } enci;
146 struct {
147 unsigned int dvi_settings;
148 unsigned int video_mode;
149 unsigned int video_mode_adv;
150 unsigned int video_prog_mode;
151 bool video_prog_mode_present;
152 unsigned int video_sync_mode;
153 bool video_sync_mode_present;
154 unsigned int video_yc_dly;
155 bool video_yc_dly_present;
156 unsigned int video_rgb_ctrl;
157 bool video_rgb_ctrl_present;
158 unsigned int video_filt_ctrl;
159 bool video_filt_ctrl_present;
160 unsigned int video_ofld_voav_ofst;
161 bool video_ofld_voav_ofst_present;
162 unsigned int yfp1_htime;
163 unsigned int yfp2_htime;
164 unsigned int max_pxcnt;
165 unsigned int hspuls_begin;
166 unsigned int hspuls_end;
167 unsigned int hspuls_switch;
168 unsigned int vspuls_begin;
169 unsigned int vspuls_end;
170 unsigned int vspuls_bline;
171 unsigned int vspuls_eline;
172 unsigned int eqpuls_begin;
173 bool eqpuls_begin_present;
174 unsigned int eqpuls_end;
175 bool eqpuls_end_present;
176 unsigned int eqpuls_bline;
177 bool eqpuls_bline_present;
178 unsigned int eqpuls_eline;
179 bool eqpuls_eline_present;
180 unsigned int havon_begin;
181 unsigned int havon_end;
182 unsigned int vavon_bline;
183 unsigned int vavon_eline;
184 unsigned int hso_begin;
185 unsigned int hso_end;
186 unsigned int vso_begin;
187 unsigned int vso_end;
188 unsigned int vso_bline;
189 unsigned int vso_eline;
190 bool vso_eline_present;
191 unsigned int sy_val;
192 bool sy_val_present;
193 unsigned int sy2_val;
194 bool sy2_val_present;
195 unsigned int max_lncnt;
196 } encp;
197};
198
199union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
200 .enci = {
201 .hso_begin = 5,
202 .hso_end = 129,
203 .vso_even = 3,
204 .vso_odd = 260,
205 .macv_max_amp = 0x810b,
206 .video_prog_mode = 0xf0,
207 .video_mode = 0x8,
208 .sch_adjust = 0x20,
209 .yc_delay = 0,
210 .pixel_start = 227,
211 .pixel_end = 1667,
212 .top_field_line_start = 18,
213 .top_field_line_end = 258,
214 .bottom_field_line_start = 19,
215 .bottom_field_line_end = 259,
216 },
217};
218
219union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
220 .enci = {
221 .hso_begin = 3,
222 .hso_end = 129,
223 .vso_even = 3,
224 .vso_odd = 260,
225 .macv_max_amp = 8107,
226 .video_prog_mode = 0xff,
227 .video_mode = 0x13,
228 .sch_adjust = 0x28,
229 .yc_delay = 0x333,
230 .pixel_start = 251,
231 .pixel_end = 1691,
232 .top_field_line_start = 22,
233 .top_field_line_end = 310,
234 .bottom_field_line_start = 23,
235 .bottom_field_line_end = 311,
236 },
237};
238
239union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
240 .encp = {
241 .dvi_settings = 0x21,
242 .video_mode = 0x4000,
243 .video_mode_adv = 0x9,
244 .video_prog_mode = 0,
245 .video_prog_mode_present = true,
246 .video_sync_mode = 7,
247 .video_sync_mode_present = true,
248 /* video_yc_dly */
249 /* video_rgb_ctrl */
250 .video_filt_ctrl = 0x2052,
251 .video_filt_ctrl_present = true,
252 /* video_ofld_voav_ofst */
253 .yfp1_htime = 244,
254 .yfp2_htime = 1630,
255 .max_pxcnt = 1715,
256 .hspuls_begin = 0x22,
257 .hspuls_end = 0xa0,
258 .hspuls_switch = 88,
259 .vspuls_begin = 0,
260 .vspuls_end = 1589,
261 .vspuls_bline = 0,
262 .vspuls_eline = 5,
263 .havon_begin = 249,
264 .havon_end = 1689,
265 .vavon_bline = 42,
266 .vavon_eline = 521,
267 /* eqpuls_begin */
268 /* eqpuls_end */
269 /* eqpuls_bline */
270 /* eqpuls_eline */
271 .hso_begin = 3,
272 .hso_end = 5,
273 .vso_begin = 3,
274 .vso_end = 5,
275 .vso_bline = 0,
276 /* vso_eline */
277 .sy_val = 8,
278 .sy_val_present = true,
279 .sy2_val = 0x1d8,
280 .sy2_val_present = true,
281 .max_lncnt = 524,
282 },
283};
284
285union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
286 .encp = {
287 .dvi_settings = 0x21,
288 .video_mode = 0x4000,
289 .video_mode_adv = 0x9,
290 .video_prog_mode = 0,
291 .video_prog_mode_present = true,
292 .video_sync_mode = 7,
293 .video_sync_mode_present = true,
294 /* video_yc_dly */
295 /* video_rgb_ctrl */
296 .video_filt_ctrl = 0x52,
297 .video_filt_ctrl_present = true,
298 /* video_ofld_voav_ofst */
299 .yfp1_htime = 235,
300 .yfp2_htime = 1674,
301 .max_pxcnt = 1727,
302 .hspuls_begin = 0,
303 .hspuls_end = 0x80,
304 .hspuls_switch = 88,
305 .vspuls_begin = 0,
306 .vspuls_end = 1599,
307 .vspuls_bline = 0,
308 .vspuls_eline = 4,
309 .havon_begin = 235,
310 .havon_end = 1674,
311 .vavon_bline = 44,
312 .vavon_eline = 619,
313 /* eqpuls_begin */
314 /* eqpuls_end */
315 /* eqpuls_bline */
316 /* eqpuls_eline */
317 .hso_begin = 0x80,
318 .hso_end = 0,
319 .vso_begin = 0,
320 .vso_end = 5,
321 .vso_bline = 0,
322 /* vso_eline */
323 .sy_val = 8,
324 .sy_val_present = true,
325 .sy2_val = 0x1d8,
326 .sy2_val_present = true,
327 .max_lncnt = 624,
328 },
329};
330
331union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
332 .encp = {
333 .dvi_settings = 0x2029,
334 .video_mode = 0x4040,
335 .video_mode_adv = 0x19,
336 /* video_prog_mode */
337 /* video_sync_mode */
338 /* video_yc_dly */
339 /* video_rgb_ctrl */
340 /* video_filt_ctrl */
341 /* video_ofld_voav_ofst */
342 .yfp1_htime = 648,
343 .yfp2_htime = 3207,
344 .max_pxcnt = 3299,
345 .hspuls_begin = 80,
346 .hspuls_end = 240,
347 .hspuls_switch = 80,
348 .vspuls_begin = 688,
349 .vspuls_end = 3248,
350 .vspuls_bline = 4,
351 .vspuls_eline = 8,
352 .havon_begin = 648,
353 .havon_end = 3207,
354 .vavon_bline = 29,
355 .vavon_eline = 748,
356 /* eqpuls_begin */
357 /* eqpuls_end */
358 /* eqpuls_bline */
359 /* eqpuls_eline */
360 .hso_begin = 256,
361 .hso_end = 168,
362 .vso_begin = 168,
363 .vso_end = 256,
364 .vso_bline = 0,
365 .vso_eline = 5,
366 .vso_eline_present = true,
367 /* sy_val */
368 /* sy2_val */
369 .max_lncnt = 749,
370 },
371};
372
373union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
374 .encp = {
375 .dvi_settings = 0x202d,
376 .video_mode = 0x4040,
377 .video_mode_adv = 0x19,
378 .video_prog_mode = 0x100,
379 .video_prog_mode_present = true,
380 .video_sync_mode = 0x407,
381 .video_sync_mode_present = true,
382 .video_yc_dly = 0,
383 .video_yc_dly_present = true,
384 /* video_rgb_ctrl */
385 /* video_filt_ctrl */
386 /* video_ofld_voav_ofst */
387 .yfp1_htime = 648,
388 .yfp2_htime = 3207,
389 .max_pxcnt = 3959,
390 .hspuls_begin = 80,
391 .hspuls_end = 240,
392 .hspuls_switch = 80,
393 .vspuls_begin = 688,
394 .vspuls_end = 3248,
395 .vspuls_bline = 4,
396 .vspuls_eline = 8,
397 .havon_begin = 648,
398 .havon_end = 3207,
399 .vavon_bline = 29,
400 .vavon_eline = 748,
401 /* eqpuls_begin */
402 /* eqpuls_end */
403 /* eqpuls_bline */
404 /* eqpuls_eline */
405 .hso_begin = 128,
406 .hso_end = 208,
407 .vso_begin = 128,
408 .vso_end = 128,
409 .vso_bline = 0,
410 .vso_eline = 5,
411 .vso_eline_present = true,
412 /* sy_val */
413 /* sy2_val */
414 .max_lncnt = 749,
415 },
416};
417
418union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
419 .encp = {
420 .dvi_settings = 0x2029,
421 .video_mode = 0x5ffc,
422 .video_mode_adv = 0x19,
423 .video_prog_mode = 0x100,
424 .video_prog_mode_present = true,
425 .video_sync_mode = 0x207,
426 .video_sync_mode_present = true,
427 /* video_yc_dly */
428 /* video_rgb_ctrl */
429 /* video_filt_ctrl */
430 .video_ofld_voav_ofst = 0x11,
431 .video_ofld_voav_ofst_present = true,
432 .yfp1_htime = 516,
433 .yfp2_htime = 4355,
434 .max_pxcnt = 4399,
435 .hspuls_begin = 88,
436 .hspuls_end = 264,
437 .hspuls_switch = 88,
438 .vspuls_begin = 440,
439 .vspuls_end = 2200,
440 .vspuls_bline = 0,
441 .vspuls_eline = 4,
442 .havon_begin = 516,
443 .havon_end = 4355,
444 .vavon_bline = 20,
445 .vavon_eline = 559,
446 .eqpuls_begin = 2288,
447 .eqpuls_begin_present = true,
448 .eqpuls_end = 2464,
449 .eqpuls_end_present = true,
450 .eqpuls_bline = 0,
451 .eqpuls_bline_present = true,
452 .eqpuls_eline = 4,
453 .eqpuls_eline_present = true,
454 .hso_begin = 264,
455 .hso_end = 176,
456 .vso_begin = 88,
457 .vso_end = 88,
458 .vso_bline = 0,
459 .vso_eline = 5,
460 .vso_eline_present = true,
461 /* sy_val */
462 /* sy2_val */
463 .max_lncnt = 1124,
464 },
465};
466
467union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
468 .encp = {
469 .dvi_settings = 0x202d,
470 .video_mode = 0x5ffc,
471 .video_mode_adv = 0x19,
472 .video_prog_mode = 0x100,
473 .video_prog_mode_present = true,
474 .video_sync_mode = 0x7,
475 .video_sync_mode_present = true,
476 /* video_yc_dly */
477 /* video_rgb_ctrl */
478 /* video_filt_ctrl */
479 .video_ofld_voav_ofst = 0x11,
480 .video_ofld_voav_ofst_present = true,
481 .yfp1_htime = 526,
482 .yfp2_htime = 4365,
483 .max_pxcnt = 5279,
484 .hspuls_begin = 88,
485 .hspuls_end = 264,
486 .hspuls_switch = 88,
487 .vspuls_begin = 440,
488 .vspuls_end = 2200,
489 .vspuls_bline = 0,
490 .vspuls_eline = 4,
491 .havon_begin = 526,
492 .havon_end = 4365,
493 .vavon_bline = 20,
494 .vavon_eline = 559,
495 .eqpuls_begin = 2288,
496 .eqpuls_begin_present = true,
497 .eqpuls_end = 2464,
498 .eqpuls_end_present = true,
499 .eqpuls_bline = 0,
500 .eqpuls_bline_present = true,
501 .eqpuls_eline = 4,
502 .eqpuls_eline_present = true,
503 .hso_begin = 142,
504 .hso_end = 230,
505 .vso_begin = 142,
506 .vso_end = 142,
507 .vso_bline = 0,
508 .vso_eline = 5,
509 .vso_eline_present = true,
510 /* sy_val */
511 /* sy2_val */
512 .max_lncnt = 1124,
513 },
514};
515
516union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
517 .encp = {
518 .dvi_settings = 0xd,
519 .video_mode = 0x4040,
520 .video_mode_adv = 0x18,
521 .video_prog_mode = 0x100,
522 .video_prog_mode_present = true,
523 .video_sync_mode = 0x7,
524 .video_sync_mode_present = true,
525 .video_yc_dly = 0,
526 .video_yc_dly_present = true,
527 .video_rgb_ctrl = 2,
528 .video_rgb_ctrl_present = true,
529 .video_filt_ctrl = 0x1052,
530 .video_filt_ctrl_present = true,
531 /* video_ofld_voav_ofst */
532 .yfp1_htime = 271,
533 .yfp2_htime = 2190,
534 .max_pxcnt = 2749,
535 .hspuls_begin = 44,
536 .hspuls_end = 132,
537 .hspuls_switch = 44,
538 .vspuls_begin = 220,
539 .vspuls_end = 2140,
540 .vspuls_bline = 0,
541 .vspuls_eline = 4,
542 .havon_begin = 271,
543 .havon_end = 2190,
544 .vavon_bline = 41,
545 .vavon_eline = 1120,
546 /* eqpuls_begin */
547 /* eqpuls_end */
548 .eqpuls_bline = 0,
549 .eqpuls_bline_present = true,
550 .eqpuls_eline = 4,
551 .eqpuls_eline_present = true,
552 .hso_begin = 79,
553 .hso_end = 123,
554 .vso_begin = 79,
555 .vso_end = 79,
556 .vso_bline = 0,
557 .vso_eline = 5,
558 .vso_eline_present = true,
559 /* sy_val */
560 /* sy2_val */
561 .max_lncnt = 1124,
562 },
563};
564
565union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
566 .encp = {
567 .dvi_settings = 0x1,
568 .video_mode = 0x4040,
569 .video_mode_adv = 0x18,
570 .video_prog_mode = 0x100,
571 .video_prog_mode_present = true,
572 /* video_sync_mode */
573 /* video_yc_dly */
574 /* video_rgb_ctrl */
575 .video_filt_ctrl = 0x1052,
576 .video_filt_ctrl_present = true,
577 /* video_ofld_voav_ofst */
578 .yfp1_htime = 140,
579 .yfp2_htime = 2060,
580 .max_pxcnt = 2199,
581 .hspuls_begin = 2156,
582 .hspuls_end = 44,
583 .hspuls_switch = 44,
584 .vspuls_begin = 140,
585 .vspuls_end = 2059,
586 .vspuls_bline = 0,
587 .vspuls_eline = 4,
588 .havon_begin = 148,
589 .havon_end = 2067,
590 .vavon_bline = 41,
591 .vavon_eline = 1120,
592 /* eqpuls_begin */
593 /* eqpuls_end */
594 /* eqpuls_bline */
595 /* eqpuls_eline */
596 .hso_begin = 44,
597 .hso_end = 2156,
598 .vso_begin = 2100,
599 .vso_end = 2164,
600 .vso_bline = 0,
601 .vso_eline = 5,
602 .vso_eline_present = true,
603 /* sy_val */
604 /* sy2_val */
605 .max_lncnt = 1124,
606 },
607};
608
609union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
610 .encp = {
611 .dvi_settings = 0xd,
612 .video_mode = 0x4040,
613 .video_mode_adv = 0x18,
614 .video_prog_mode = 0x100,
615 .video_prog_mode_present = true,
616 .video_sync_mode = 0x7,
617 .video_sync_mode_present = true,
618 .video_yc_dly = 0,
619 .video_yc_dly_present = true,
620 .video_rgb_ctrl = 2,
621 .video_rgb_ctrl_present = true,
622 /* video_filt_ctrl */
623 /* video_ofld_voav_ofst */
624 .yfp1_htime = 271,
625 .yfp2_htime = 2190,
626 .max_pxcnt = 2639,
627 .hspuls_begin = 44,
628 .hspuls_end = 132,
629 .hspuls_switch = 44,
630 .vspuls_begin = 220,
631 .vspuls_end = 2140,
632 .vspuls_bline = 0,
633 .vspuls_eline = 4,
634 .havon_begin = 271,
635 .havon_end = 2190,
636 .vavon_bline = 41,
637 .vavon_eline = 1120,
638 /* eqpuls_begin */
639 /* eqpuls_end */
640 .eqpuls_bline = 0,
641 .eqpuls_bline_present = true,
642 .eqpuls_eline = 4,
643 .eqpuls_eline_present = true,
644 .hso_begin = 79,
645 .hso_end = 123,
646 .vso_begin = 79,
647 .vso_end = 79,
648 .vso_bline = 0,
649 .vso_eline = 5,
650 .vso_eline_present = true,
651 /* sy_val */
652 /* sy2_val */
653 .max_lncnt = 1124,
654 },
655};
656
657union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
658 .encp = {
659 .dvi_settings = 0x1,
660 .video_mode = 0x4040,
661 .video_mode_adv = 0x18,
662 .video_prog_mode = 0x100,
663 .video_prog_mode_present = true,
664 /* video_sync_mode */
665 /* video_yc_dly */
666 /* video_rgb_ctrl */
667 .video_filt_ctrl = 0x1052,
668 .video_filt_ctrl_present = true,
669 /* video_ofld_voav_ofst */
670 .yfp1_htime = 140,
671 .yfp2_htime = 2060,
672 .max_pxcnt = 2199,
673 .hspuls_begin = 2156,
674 .hspuls_end = 44,
675 .hspuls_switch = 44,
676 .vspuls_begin = 140,
677 .vspuls_end = 2059,
678 .vspuls_bline = 0,
679 .vspuls_eline = 4,
680 .havon_begin = 148,
681 .havon_end = 2067,
682 .vavon_bline = 41,
683 .vavon_eline = 1120,
684 /* eqpuls_begin */
685 /* eqpuls_end */
686 /* eqpuls_bline */
687 /* eqpuls_eline */
688 .hso_begin = 44,
689 .hso_end = 2156,
690 .vso_begin = 2100,
691 .vso_end = 2164,
692 .vso_bline = 0,
693 .vso_eline = 5,
694 .vso_eline_present = true,
695 /* sy_val */
696 /* sy2_val */
697 .max_lncnt = 1124,
698 },
699};
700
701struct meson_hdmi_venc_vic_mode {
702 unsigned int vic;
703 union meson_hdmi_venc_mode *mode;
704} meson_hdmi_venc_vic_modes[] = {
705 { 6, &meson_hdmi_enci_mode_480i },
706 { 7, &meson_hdmi_enci_mode_480i },
707 { 21, &meson_hdmi_enci_mode_576i },
708 { 22, &meson_hdmi_enci_mode_576i },
709 { 2, &meson_hdmi_encp_mode_480p },
710 { 3, &meson_hdmi_encp_mode_480p },
711 { 17, &meson_hdmi_encp_mode_576p },
712 { 18, &meson_hdmi_encp_mode_576p },
713 { 4, &meson_hdmi_encp_mode_720p60 },
714 { 19, &meson_hdmi_encp_mode_720p50 },
715 { 5, &meson_hdmi_encp_mode_1080i60 },
716 { 20, &meson_hdmi_encp_mode_1080i50 },
717 { 32, &meson_hdmi_encp_mode_1080p24 },
31e1ab49 718 { 33, &meson_hdmi_encp_mode_1080p50 },
335e3713
NA		 719 { 34, &meson_hdmi_encp_mode_1080p30 },
720 { 31, &meson_hdmi_encp_mode_1080p50 },
721 { 16, &meson_hdmi_encp_mode_1080p60 },
722 { 0, NULL}, /* sentinel */
723};
724
725static signed int to_signed(unsigned int a)
726{
727 if (a <= 7)
728 return a;
729 else
730 return a - 16;
731}
732
733static unsigned long modulo(unsigned long a, unsigned long b)
734{
735 if (a >= b)
736 return a - b;
737 else
738 return a;
739}
740
3273fc63
NA		 741enum drm_mode_status
742meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
9c936b12 743{
3273fc63
NA		 744 if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
745 DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
746 return MODE_BAD;
9c936b12 747
3273fc63
NA		 748 if (mode->hdisplay < 640 || mode->hdisplay > 1920)
749 return MODE_BAD_HVALUE;
9c936b12 750
3273fc63
NA		 751 if (mode->vdisplay < 480 || mode->vdisplay > 1200)
752 return MODE_BAD_VVALUE;
753
754 return MODE_OK;
9c936b12
NA		 755}
756EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode);
757
335e3713
NA		 758bool meson_venc_hdmi_supported_vic(int vic)
759{
760 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
761
762 while (vmode->vic && vmode->mode) {
763 if (vmode->vic == vic)
764 return true;
765 vmode++;
766 }
767
768 return false;
769}
770EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic);
771
3273fc63
NA		 772void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode,
773 union meson_hdmi_venc_mode *dmt_mode)
9c936b12 774{
3273fc63
NA		 775 memset(dmt_mode, 0, sizeof(*dmt_mode));
776
777 dmt_mode->encp.dvi_settings = 0x21;
778 dmt_mode->encp.video_mode = 0x4040;
779 dmt_mode->encp.video_mode_adv = 0x18;
780 dmt_mode->encp.max_pxcnt = mode->htotal - 1;
781 dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start;
782 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin +
783 mode->hdisplay - 1;
784 dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start;
785 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline +
786 mode->vdisplay - 1;
787 dmt_mode->encp.hso_begin = 0;
788 dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start;
789 dmt_mode->encp.vso_begin = 30;
790 dmt_mode->encp.vso_end = 50;
791 dmt_mode->encp.vso_bline = 0;
792 dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start;
793 dmt_mode->encp.vso_eline_present = true;
794 dmt_mode->encp.max_lncnt = mode->vtotal - 1;
9c936b12
NA		 795}
796
335e3713
NA		 797static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
798{
799 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
800
801 while (vmode->vic && vmode->mode) {
802 if (vmode->vic == vic)
803 return vmode->mode;
804 vmode++;
805 }
806
807 return NULL;
808}
809
810bool meson_venc_hdmi_venc_repeat(int vic)
811{
812 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
813 if (vic == 6 || vic == 7 || /* 480i */
814 vic == 21 || vic == 22 || /* 576i */
815 vic == 17 || vic == 18 || /* 576p */
816 vic == 2 || vic == 3 || /* 480p */
817 vic == 4 || /* 720p60 */
818 vic == 19 || /* 720p50 */
819 vic == 5 || /* 1080i60 */
820 vic == 20) /* 1080i50 */
821 return true;
822
823 return false;
824}
825EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
826
827void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
828 struct drm_display_mode *mode)
829{
830 union meson_hdmi_venc_mode *vmode = NULL;
3273fc63 831 union meson_hdmi_venc_mode vmode_dmt;
335e3713
NA		 832 bool use_enci = false;
833 bool venc_repeat = false;
834 bool hdmi_repeat = false;
835 unsigned int venc_hdmi_latency = 2;
836 unsigned long total_pixels_venc = 0;
837 unsigned long active_pixels_venc = 0;
838 unsigned long front_porch_venc = 0;
839 unsigned long hsync_pixels_venc = 0;
840 unsigned long de_h_begin = 0;
841 unsigned long de_h_end = 0;
842 unsigned long de_v_begin_even = 0;
843 unsigned long de_v_end_even = 0;
844 unsigned long de_v_begin_odd = 0;
845 unsigned long de_v_end_odd = 0;
846 unsigned long hs_begin = 0;
847 unsigned long hs_end = 0;
848 unsigned long vs_adjust = 0;
849 unsigned long vs_bline_evn = 0;
850 unsigned long vs_eline_evn = 0;
851 unsigned long vs_bline_odd = 0;
852 unsigned long vs_eline_odd = 0;
853 unsigned long vso_begin_evn = 0;
854 unsigned long vso_begin_odd = 0;
855 unsigned int eof_lines;
856 unsigned int sof_lines;
857 unsigned int vsync_lines;
858
adf59dd2
JRO		 859 /* Use VENCI for 480i and 576i and double HDMI pixels */
860 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
861 hdmi_repeat = true;
862 use_enci = true;
863 venc_hdmi_latency = 1;
864 }
865
3273fc63 866 if (meson_venc_hdmi_supported_vic(vic)) {
9c936b12 867 vmode = meson_venc_hdmi_get_vic_vmode(vic);
3273fc63
NA		 868 if (!vmode) {
869 dev_err(priv->dev, "%s: Fatal Error, unsupported mode "
870 DRM_MODE_FMT "\n", __func__,
871 DRM_MODE_ARG(mode));
872 return;
873 }
874 } else {
875 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
876 vmode = &vmode_dmt;
adf59dd2 877 use_enci = false;
335e3713
NA		 878 }
879
880 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
881 if (meson_venc_hdmi_venc_repeat(vic))
882 venc_repeat = true;
883
884 eof_lines = mode->vsync_start - mode->vdisplay;
885 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
886 eof_lines /= 2;
887 sof_lines = mode->vtotal - mode->vsync_end;
888 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
889 sof_lines /= 2;
890 vsync_lines = mode->vsync_end - mode->vsync_start;
891 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
892 vsync_lines /= 2;
893
894 total_pixels_venc = mode->htotal;
895 if (hdmi_repeat)
896 total_pixels_venc /= 2;
897 if (venc_repeat)
898 total_pixels_venc *= 2;
899
900 active_pixels_venc = mode->hdisplay;
901 if (hdmi_repeat)
902 active_pixels_venc /= 2;
903 if (venc_repeat)
904 active_pixels_venc *= 2;
905
906 front_porch_venc = (mode->hsync_start - mode->hdisplay);
907 if (hdmi_repeat)
908 front_porch_venc /= 2;
909 if (venc_repeat)
910 front_porch_venc *= 2;
911
912 hsync_pixels_venc = (mode->hsync_end - mode->hsync_start);
913 if (hdmi_repeat)
914 hsync_pixels_venc /= 2;
915 if (venc_repeat)
916 hsync_pixels_venc *= 2;
917
918 /* Disable VDACs */
9c936b12 919 writel_bits_relaxed(0xff, 0xff,
335e3713
NA		 920 priv->io_base + _REG(VENC_VDAC_SETTING));
921
922 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
923 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
924
925 if (use_enci) {
926 unsigned int lines_f0;
927 unsigned int lines_f1;
928
929 /* CVBS Filter settings */
930 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
931 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
932
933 /* Digital Video Select : Interlace, clk27 clk, external */
934 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
935
936 /* Reset Video Mode */
937 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
938 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
939
940 /* Horizontal sync signal output */
941 writel_relaxed(vmode->enci.hso_begin,
942 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
943 writel_relaxed(vmode->enci.hso_end,
944 priv->io_base + _REG(ENCI_SYNC_HSO_END));
945
946 /* Vertical Sync lines */
947 writel_relaxed(vmode->enci.vso_even,
948 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
949 writel_relaxed(vmode->enci.vso_odd,
950 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
951
952 /* Macrovision max amplitude change */
953 writel_relaxed(vmode->enci.macv_max_amp,
954 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
955
956 /* Video mode */
957 writel_relaxed(vmode->enci.video_prog_mode,
958 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
959 writel_relaxed(vmode->enci.video_mode,
960 priv->io_base + _REG(ENCI_VIDEO_MODE));
961
962 /* Advanced Video Mode :
963 * Demux shifting 0x2
964 * Blank line end at line17/22
965 * High bandwidth Luma Filter
966 * Low bandwidth Chroma Filter
967 * Bypass luma low pass filter
968 * No macrovision on CSYNC
969 */
970 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
971
972 writel(vmode->enci.sch_adjust,
973 priv->io_base + _REG(ENCI_VIDEO_SCH));
974
975 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
976 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
977
978 if (vmode->enci.yc_delay)
979 writel_relaxed(vmode->enci.yc_delay,
980 priv->io_base + _REG(ENCI_YC_DELAY));
981
982
983 /* UNreset Interlaced TV Encoder */
984 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
985
986 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
987 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
988
989 /* Timings */
990 writel_relaxed(vmode->enci.pixel_start,
991 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
992 writel_relaxed(vmode->enci.pixel_end,
993 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
994
995 writel_relaxed(vmode->enci.top_field_line_start,
996 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
997 writel_relaxed(vmode->enci.top_field_line_end,
998 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
999
1000 writel_relaxed(vmode->enci.bottom_field_line_start,
1001 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1002 writel_relaxed(vmode->enci.bottom_field_line_end,
1003 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1004
1005 /* Select ENCI for VIU */
1006 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1007
1008 /* Interlace video enable */
1009 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1010
1011 lines_f0 = mode->vtotal >> 1;
1012 lines_f1 = lines_f0 + 1;
1013
1014 de_h_begin = modulo(readl_relaxed(priv->io_base +
1015 _REG(ENCI_VFIFO2VD_PIXEL_START))
1016 + venc_hdmi_latency,
1017 total_pixels_venc);
1018 de_h_end = modulo(de_h_begin + active_pixels_venc,
1019 total_pixels_venc);
1020
1021 writel_relaxed(de_h_begin,
1022 priv->io_base + _REG(ENCI_DE_H_BEGIN));
1023 writel_relaxed(de_h_end,
1024 priv->io_base + _REG(ENCI_DE_H_END));
1025
1026 de_v_begin_even = readl_relaxed(priv->io_base +
1027 _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1028 de_v_end_even = de_v_begin_even + mode->vdisplay;
1029 de_v_begin_odd = readl_relaxed(priv->io_base +
1030 _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1031 de_v_end_odd = de_v_begin_odd + mode->vdisplay;
1032
1033 writel_relaxed(de_v_begin_even,
1034 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
1035 writel_relaxed(de_v_end_even,
1036 priv->io_base + _REG(ENCI_DE_V_END_EVEN));
1037 writel_relaxed(de_v_begin_odd,
1038 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
1039 writel_relaxed(de_v_end_odd,
1040 priv->io_base + _REG(ENCI_DE_V_END_ODD));
1041
1042 /* Program Hsync timing */
1043 hs_begin = de_h_end + front_porch_venc;
1044 if (de_h_end + front_porch_venc >= total_pixels_venc) {
1045 hs_begin -= total_pixels_venc;
1046 vs_adjust = 1;
1047 } else {
1048 hs_begin = de_h_end + front_porch_venc;
1049 vs_adjust = 0;
1050 }
1051
1052 hs_end = modulo(hs_begin + hsync_pixels_venc,
1053 total_pixels_venc);
1054 writel_relaxed(hs_begin,
1055 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
1056 writel_relaxed(hs_end,
1057 priv->io_base + _REG(ENCI_DVI_HSO_END));
1058
1059 /* Program Vsync timing for even field */
1060 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
1061 vs_bline_evn = (de_v_end_odd - 1)
1062 + eof_lines
1063 + vs_adjust
1064 - lines_f1;
1065 vs_eline_evn = vs_bline_evn + vsync_lines;
1066
1067 writel_relaxed(vs_bline_evn,
1068 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1069
1070 writel_relaxed(vs_eline_evn,
1071 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
1072
1073 writel_relaxed(hs_begin,
1074 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1075 writel_relaxed(hs_begin,
1076 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
1077 } else {
1078 vs_bline_odd = (de_v_end_odd - 1)
1079 + eof_lines
1080 + vs_adjust;
1081
1082 writel_relaxed(vs_bline_odd,
1083 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1084
1085 writel_relaxed(hs_begin,
1086 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1087
1088 if ((vs_bline_odd + vsync_lines) >= lines_f1) {
1089 vs_eline_evn = vs_bline_odd
1090 + vsync_lines
1091 - lines_f1;
1092
1093 writel_relaxed(vs_eline_evn, priv->io_base
1094 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1095
1096 writel_relaxed(hs_begin, priv->io_base
1097 + _REG(ENCI_DVI_VSO_END_EVN));
1098 } else {
1099 vs_eline_odd = vs_bline_odd
1100 + vsync_lines;
1101
1102 writel_relaxed(vs_eline_odd, priv->io_base
1103 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1104
1105 writel_relaxed(hs_begin, priv->io_base
1106 + _REG(ENCI_DVI_VSO_END_ODD));
1107 }
1108 }
1109
1110 /* Program Vsync timing for odd field */
1111 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
1112 vs_bline_odd = (de_v_end_even - 1)
1113 + (eof_lines + 1)
1114 - lines_f0;
1115 vs_eline_odd = vs_bline_odd + vsync_lines;
1116
1117 writel_relaxed(vs_bline_odd,
1118 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1119
1120 writel_relaxed(vs_eline_odd,
1121 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
1122
1123 vso_begin_odd = modulo(hs_begin
1124 + (total_pixels_venc >> 1),
1125 total_pixels_venc);
1126
1127 writel_relaxed(vso_begin_odd,
1128 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1129 writel_relaxed(vso_begin_odd,
1130 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
1131 } else {
1132 vs_bline_evn = (de_v_end_even - 1)
1133 + (eof_lines + 1);
1134
1135 writel_relaxed(vs_bline_evn,
1136 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1137
1138 vso_begin_evn = modulo(hs_begin
1139 + (total_pixels_venc >> 1),
1140 total_pixels_venc);
1141
1142 writel_relaxed(vso_begin_evn, priv->io_base
1143 + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1144
1145 if (vs_bline_evn + vsync_lines >= lines_f0) {
1146 vs_eline_odd = vs_bline_evn
1147 + vsync_lines
1148 - lines_f0;
1149
1150 writel_relaxed(vs_eline_odd, priv->io_base
1151 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1152
1153 writel_relaxed(vso_begin_evn, priv->io_base
1154 + _REG(ENCI_DVI_VSO_END_ODD));
1155 } else {
1156 vs_eline_evn = vs_bline_evn + vsync_lines;
1157
1158 writel_relaxed(vs_eline_evn, priv->io_base
1159 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1160
1161 writel_relaxed(vso_begin_evn, priv->io_base
1162 + _REG(ENCI_DVI_VSO_END_EVN));
1163 }
1164 }
1165 } else {
1166 writel_relaxed(vmode->encp.dvi_settings,
1167 priv->io_base + _REG(VENC_DVI_SETTING));
1168 writel_relaxed(vmode->encp.video_mode,
1169 priv->io_base + _REG(ENCP_VIDEO_MODE));
1170 writel_relaxed(vmode->encp.video_mode_adv,
1171 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
1172 if (vmode->encp.video_prog_mode_present)
1173 writel_relaxed(vmode->encp.video_prog_mode,
1174 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1175 if (vmode->encp.video_sync_mode_present)
1176 writel_relaxed(vmode->encp.video_sync_mode,
1177 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
1178 if (vmode->encp.video_yc_dly_present)
1179 writel_relaxed(vmode->encp.video_yc_dly,
1180 priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
1181 if (vmode->encp.video_rgb_ctrl_present)
1182 writel_relaxed(vmode->encp.video_rgb_ctrl,
1183 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
1184 if (vmode->encp.video_filt_ctrl_present)
1185 writel_relaxed(vmode->encp.video_filt_ctrl,
1186 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
1187 if (vmode->encp.video_ofld_voav_ofst_present)
1188 writel_relaxed(vmode->encp.video_ofld_voav_ofst,
1189 priv->io_base
1190 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1191 writel_relaxed(vmode->encp.yfp1_htime,
1192 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
1193 writel_relaxed(vmode->encp.yfp2_htime,
1194 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
1195 writel_relaxed(vmode->encp.max_pxcnt,
1196 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
1197 writel_relaxed(vmode->encp.hspuls_begin,
1198 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
1199 writel_relaxed(vmode->encp.hspuls_end,
1200 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
1201 writel_relaxed(vmode->encp.hspuls_switch,
1202 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
1203 writel_relaxed(vmode->encp.vspuls_begin,
1204 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
1205 writel_relaxed(vmode->encp.vspuls_end,
1206 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
1207 writel_relaxed(vmode->encp.vspuls_bline,
1208 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
1209 writel_relaxed(vmode->encp.vspuls_eline,
1210 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
1211 if (vmode->encp.eqpuls_begin_present)
1212 writel_relaxed(vmode->encp.eqpuls_begin,
1213 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
1214 if (vmode->encp.eqpuls_end_present)
1215 writel_relaxed(vmode->encp.eqpuls_end,
1216 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
1217 if (vmode->encp.eqpuls_bline_present)
1218 writel_relaxed(vmode->encp.eqpuls_bline,
1219 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
1220 if (vmode->encp.eqpuls_eline_present)
1221 writel_relaxed(vmode->encp.eqpuls_eline,
1222 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
1223 writel_relaxed(vmode->encp.havon_begin,
1224 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
1225 writel_relaxed(vmode->encp.havon_end,
1226 priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
1227 writel_relaxed(vmode->encp.vavon_bline,
1228 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
1229 writel_relaxed(vmode->encp.vavon_eline,
1230 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
1231 writel_relaxed(vmode->encp.hso_begin,
1232 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
1233 writel_relaxed(vmode->encp.hso_end,
1234 priv->io_base + _REG(ENCP_VIDEO_HSO_END));
1235 writel_relaxed(vmode->encp.vso_begin,
1236 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
1237 writel_relaxed(vmode->encp.vso_end,
1238 priv->io_base + _REG(ENCP_VIDEO_VSO_END));
1239 writel_relaxed(vmode->encp.vso_bline,
1240 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
1241 if (vmode->encp.vso_eline_present)
1242 writel_relaxed(vmode->encp.vso_eline,
1243 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
1244 if (vmode->encp.sy_val_present)
1245 writel_relaxed(vmode->encp.sy_val,
1246 priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
1247 if (vmode->encp.sy2_val_present)
1248 writel_relaxed(vmode->encp.sy2_val,
1249 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
1250 writel_relaxed(vmode->encp.max_lncnt,
1251 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
1252
1253 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
1254
1255 /* Set DE signal’s polarity is active high */
1256 writel_bits_relaxed(BIT(14), BIT(14),
1257 priv->io_base + _REG(ENCP_VIDEO_MODE));
1258
1259 /* Program DE timing */
1260 de_h_begin = modulo(readl_relaxed(priv->io_base +
1261 _REG(ENCP_VIDEO_HAVON_BEGIN))
1262 + venc_hdmi_latency,
1263 total_pixels_venc);
1264 de_h_end = modulo(de_h_begin + active_pixels_venc,
1265 total_pixels_venc);
1266
1267 writel_relaxed(de_h_begin,
1268 priv->io_base + _REG(ENCP_DE_H_BEGIN));
1269 writel_relaxed(de_h_end,
1270 priv->io_base + _REG(ENCP_DE_H_END));
1271
1272 /* Program DE timing for even field */
1273 de_v_begin_even = readl_relaxed(priv->io_base
1274 + _REG(ENCP_VIDEO_VAVON_BLINE));
1275 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1276 de_v_end_even = de_v_begin_even +
1277 (mode->vdisplay / 2);
1278 else
1279 de_v_end_even = de_v_begin_even + mode->vdisplay;
1280
1281 writel_relaxed(de_v_begin_even,
1282 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
1283 writel_relaxed(de_v_end_even,
1284 priv->io_base + _REG(ENCP_DE_V_END_EVEN));
1285
1286 /* Program DE timing for odd field if needed */
1287 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1288 unsigned int ofld_voav_ofst =
1289 readl_relaxed(priv->io_base +
1290 _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1291 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
1292 + de_v_begin_even
1293 + ((mode->vtotal - 1) / 2);
1294 de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2);
1295
1296 writel_relaxed(de_v_begin_odd,
1297 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
1298 writel_relaxed(de_v_end_odd,
1299 priv->io_base + _REG(ENCP_DE_V_END_ODD));
1300 }
1301
1302 /* Program Hsync timing */
1303 if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
1304 hs_begin = de_h_end
1305 + front_porch_venc
1306 - total_pixels_venc;
1307 vs_adjust = 1;
1308 } else {
1309 hs_begin = de_h_end
1310 + front_porch_venc;
1311 vs_adjust = 0;
1312 }
1313
1314 hs_end = modulo(hs_begin + hsync_pixels_venc,
1315 total_pixels_venc);
1316
1317 writel_relaxed(hs_begin,
1318 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
1319 writel_relaxed(hs_end,
1320 priv->io_base + _REG(ENCP_DVI_HSO_END));
1321
1322 /* Program Vsync timing for even field */
1323 if (de_v_begin_even >=
1324 (sof_lines + vsync_lines + (1 - vs_adjust)))
1325 vs_bline_evn = de_v_begin_even
1326 - sof_lines
1327 - vsync_lines
1328 - (1 - vs_adjust);
1329 else
1330 vs_bline_evn = mode->vtotal
1331 + de_v_begin_even
1332 - sof_lines
1333 - vsync_lines
1334 - (1 - vs_adjust);
1335
1336 vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
1337 mode->vtotal);
1338
1339 writel_relaxed(vs_bline_evn,
1340 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
1341 writel_relaxed(vs_eline_evn,
1342 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
1343
1344 vso_begin_evn = hs_begin;
1345 writel_relaxed(vso_begin_evn,
1346 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
1347 writel_relaxed(vso_begin_evn,
1348 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
1349
1350 /* Program Vsync timing for odd field if needed */
1351 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1352 vs_bline_odd = (de_v_begin_odd - 1)
1353 - sof_lines
1354 - vsync_lines;
1355 vs_eline_odd = (de_v_begin_odd - 1)
1356 - vsync_lines;
1357 vso_begin_odd = modulo(hs_begin
1358 + (total_pixels_venc >> 1),
1359 total_pixels_venc);
1360
1361 writel_relaxed(vs_bline_odd,
1362 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
1363 writel_relaxed(vs_eline_odd,
1364 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
1365 writel_relaxed(vso_begin_odd,
1366 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
1367 writel_relaxed(vso_begin_odd,
1368 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
1369 }
1370
1371 /* Select ENCP for VIU */
1372 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
1373 }
1374
1375 writel_relaxed((use_enci ? 1 : 2) |
1376 (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
1377 (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
1378 4 << 5 |
1379 (venc_repeat ? 1 << 8 : 0) |
1380 (hdmi_repeat ? 1 << 12 : 0),
1381 priv->io_base + _REG(VPU_HDMI_SETTING));
1382
1383 priv->venc.hdmi_repeat = hdmi_repeat;
1384 priv->venc.venc_repeat = venc_repeat;
1385 priv->venc.hdmi_use_enci = use_enci;
1386
1387 priv->venc.current_mode = MESON_VENC_MODE_HDMI;
1388}
1389EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
1390
bbbe775e
NA		 1391void meson_venci_cvbs_mode_set(struct meson_drm *priv,
1392 struct meson_cvbs_enci_mode *mode)
1393{
1394 if (mode->mode_tag == priv->venc.current_mode)
1395 return;
1396
1397 /* CVBS Filter settings */
1398 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1399 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1400
1401 /* Digital Video Select : Interlace, clk27 clk, external */
1402 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1403
1404 /* Reset Video Mode */
1405 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1406 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1407
1408 /* Horizontal sync signal output */
1409 writel_relaxed(mode->hso_begin,
1410 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1411 writel_relaxed(mode->hso_end,
1412 priv->io_base + _REG(ENCI_SYNC_HSO_END));
1413
1414 /* Vertical Sync lines */
1415 writel_relaxed(mode->vso_even,
1416 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1417 writel_relaxed(mode->vso_odd,
1418 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1419
1420 /* Macrovision max amplitude change */
1421 writel_relaxed(0x8100 + mode->macv_max_amp,
1422 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1423
1424 /* Video mode */
1425 writel_relaxed(mode->video_prog_mode,
1426 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1427 writel_relaxed(mode->video_mode,
1428 priv->io_base + _REG(ENCI_VIDEO_MODE));
1429
1430 /* Advanced Video Mode :
1431 * Demux shifting 0x2
1432 * Blank line end at line17/22
1433 * High bandwidth Luma Filter
1434 * Low bandwidth Chroma Filter
1435 * Bypass luma low pass filter
1436 * No macrovision on CSYNC
1437 */
1438 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1439
1440 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
1441
1442 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1443 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1444
1445 /* 0x3 Y, C, and Component Y delay */
1446 writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
1447
1448 /* Timings */
1449 writel_relaxed(mode->pixel_start,
1450 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1451 writel_relaxed(mode->pixel_end,
1452 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1453
1454 writel_relaxed(mode->top_field_line_start,
1455 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1456 writel_relaxed(mode->top_field_line_end,
1457 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1458
1459 writel_relaxed(mode->bottom_field_line_start,
1460 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1461 writel_relaxed(mode->bottom_field_line_end,
1462 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1463
1464 /* Internal Venc, Internal VIU Sync, Internal Vencoder */
1465 writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
1466
1467 /* UNreset Interlaced TV Encoder */
1468 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1469
1470 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1471 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1472
1473 /* Power UP Dacs */
1474 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
1475
1476 /* Video Upsampling */
1477 writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1478 writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1479 writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1480
1481 /* Select Interlace Y DACs */
1482 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
1483 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
1484 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
1485 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
1486 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
1487 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
1488
1489 /* Select ENCI for VIU */
1490 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1491
1492 /* Enable ENCI FIFO */
1493 writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1494
1495 /* Select ENCI DACs 0, 1, 4, and 5 */
1496 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
1497 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
1498
1499 /* Interlace video enable */
1500 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1501
1502 /* Configure Video Saturation / Contrast / Brightness / Hue */
1503 writel_relaxed(mode->video_saturation,
1504 priv->io_base + _REG(ENCI_VIDEO_SAT));
1505 writel_relaxed(mode->video_contrast,
1506 priv->io_base + _REG(ENCI_VIDEO_CONT));
1507 writel_relaxed(mode->video_brightness,
1508 priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
1509 writel_relaxed(mode->video_hue,
1510 priv->io_base + _REG(ENCI_VIDEO_HUE));
1511
1512 /* Enable DAC0 Filter */
1513 writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1514 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
1515
1516 /* 0 in Macrovision register 0 */
1517 writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
1518
1519 /* Analog Synchronization and color burst value adjust */
1520 writel_relaxed(mode->analog_sync_adj,
1521 priv->io_base + _REG(ENCI_SYNC_ADJ));
1522
bbbe775e
NA		 1523 priv->venc.current_mode = mode->mode_tag;
1524}
1525
1526/* Returns the current ENCI field polarity */
1527unsigned int meson_venci_get_field(struct meson_drm *priv)
1528{
1529 return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29);
1530}
1531
1532void meson_venc_enable_vsync(struct meson_drm *priv)
1533{
1534 writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
2bcd3eca 1535 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
bbbe775e
NA		 1536}
1537
1538void meson_venc_disable_vsync(struct meson_drm *priv)
1539{
2bcd3eca 1540 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
bbbe775e
NA		 1541 writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
1542}
1543
1544void meson_venc_init(struct meson_drm *priv)
1545{
0c931a29
NA		 1546 /* Disable CVBS VDAC */
1547 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
1548 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
1549
1550 /* Power Down Dacs */
1551 writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
1552
1553 /* Disable HDMI PHY */
1554 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
1555
1556 /* Disable HDMI */
1557 writel_bits_relaxed(0x3, 0,
1558 priv->io_base + _REG(VPU_HDMI_SETTING));
1559
bbbe775e
NA		 1560 /* Disable all encoders */
1561 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1562 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1563 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
1564
1565 /* Disable VSync IRQ */
1566 meson_venc_disable_vsync(priv);
1567
1568 priv->venc.current_mode = MESON_VENC_MODE_NONE;
1569}
Empty description
This page took 0.39614 seconds and 4 git commands to generate.