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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / gpu / drm / meson / meson_dw_hdmi.c
CommitLineData
3f68be7d
NA		 1/*
2 * Copyright (C) 2016 BayLibre, SAS
3 * Author: Neil Armstrong <[email protected]>
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/component.h>
23#include <linux/of_graph.h>
24#include <linux/reset.h>
25#include <linux/clk.h>
161a803f 26#include <linux/regulator/consumer.h>
3f68be7d
NA		 27
28#include <drm/drmP.h>
29#include <drm/drm_edid.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/drm_atomic_helper.h>
32#include <drm/bridge/dw_hdmi.h>
33
34#include <uapi/linux/media-bus-format.h>
35#include <uapi/linux/videodev2.h>
36
37#include "meson_drv.h"
38#include "meson_venc.h"
39#include "meson_vclk.h"
40#include "meson_dw_hdmi.h"
41#include "meson_registers.h"
42
43#define DRIVER_NAME "meson-dw-hdmi"
44#define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
45
2021d5b7
NA		 46/**
47 * DOC: HDMI Output
48 *
3f68be7d 49 * HDMI Output is composed of :
2021d5b7 50 *
3f68be7d
NA		 51 * - A Synopsys DesignWare HDMI Controller IP
52 * - A TOP control block controlling the Clocks and PHY
53 * - A custom HDMI PHY in order convert video to TMDS signal
2021d5b7
NA		 54 *
55 * .. code::
56 *
57 * ___________________________________
58 * | HDMI TOP |<= HPD
59 * |___________________________________|
60 * | | |
61 * | Synopsys HDMI | HDMI PHY |=> TMDS
62 * | Controller |________________|
63 * |___________________________________|<=> DDC
64 *
3f68be7d
NA		 65 *
66 * The HDMI TOP block only supports HPD sensing.
67 * The Synopsys HDMI Controller interrupt is routed
68 * through the TOP Block interrupt.
69 * Communication to the TOP Block and the Synopsys
70 * HDMI Controller is done a pair of addr+read/write
71 * registers.
72 * The HDMI PHY is configured by registers in the
73 * HHI register block.
74 *
75 * Pixel data arrives in 4:4:4 format from the VENC
76 * block and the VPU HDMI mux selects either the ENCI
77 * encoder for the 576i or 480i formats or the ENCP
78 * encoder for all the other formats including
79 * interlaced HD formats.
80 * The VENC uses a DVI encoder on top of the ENCI
81 * or ENCP encoders to generate DVI timings for the
82 * HDMI controller.
83 *
84 * GXBB, GXL and GXM embeds the Synopsys DesignWare
85 * HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
86 * audio source interfaces.
87 *
88 * We handle the following features :
2021d5b7 89 *
3f68be7d
NA		 90 * - HPD Rise & Fall interrupt
91 * - HDMI Controller Interrupt
92 * - HDMI PHY Init for 480i to 1080p60
93 * - VENC & HDMI Clock setup for 480i to 1080p60
94 * - VENC Mode setup for 480i to 1080p60
95 *
96 * What is missing :
2021d5b7 97 *
3f68be7d
NA		 98 * - PHY, Clock and Mode setup for 2k && 4k modes
99 * - SDDC Scrambling mode for HDMI 2.0a
100 * - HDCP Setup
101 * - CEC Management
102 */
103
104/* TOP Block Communication Channel */
105#define HDMITX_TOP_ADDR_REG 0x0
106#define HDMITX_TOP_DATA_REG 0x4
107#define HDMITX_TOP_CTRL_REG 0x8
108
109/* Controller Communication Channel */
110#define HDMITX_DWC_ADDR_REG 0x10
111#define HDMITX_DWC_DATA_REG 0x14
112#define HDMITX_DWC_CTRL_REG 0x18
113
114/* HHI Registers */
115#define HHI_MEM_PD_REG0 0x100 /* 0x40 */
116#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
117#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
118#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
119#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
120#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
121
122static DEFINE_SPINLOCK(reg_lock);
123
124enum meson_venc_source {
125 MESON_VENC_SOURCE_NONE = 0,
126 MESON_VENC_SOURCE_ENCI = 1,
127 MESON_VENC_SOURCE_ENCP = 2,
128};
129
130struct meson_dw_hdmi {
131 struct drm_encoder encoder;
132 struct dw_hdmi_plat_data dw_plat_data;
133 struct meson_drm *priv;
134 struct device *dev;
135 void __iomem *hdmitx;
136 struct reset_control *hdmitx_apb;
137 struct reset_control *hdmitx_ctrl;
138 struct reset_control *hdmitx_phy;
139 struct clk *hdmi_pclk;
140 struct clk *venci_clk;
161a803f 141 struct regulator *hdmi_supply;
3f68be7d 142 u32 irq_stat;
eea034af 143 struct dw_hdmi *hdmi;
3f68be7d
NA		 144};
145#define encoder_to_meson_dw_hdmi(x) \
146 container_of(x, struct meson_dw_hdmi, encoder)
147
148static inline int dw_hdmi_is_compatible(struct meson_dw_hdmi *dw_hdmi,
149 const char *compat)
150{
151 return of_device_is_compatible(dw_hdmi->dev->of_node, compat);
152}
153
154/* PHY (via TOP bridge) and Controller dedicated register interface */
155
156static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi *dw_hdmi,
157 unsigned int addr)
158{
159 unsigned long flags;
160 unsigned int data;
161
162 spin_lock_irqsave(&reg_lock, flags);
163
164 /* ADDR must be written twice */
165 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
166 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
167
168 /* Read needs a second DATA read */
169 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
170 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
171
172 spin_unlock_irqrestore(&reg_lock, flags);
173
174 return data;
175}
176
177static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi,
178 unsigned int addr, unsigned int data)
179{
180 unsigned long flags;
181
182 spin_lock_irqsave(&reg_lock, flags);
183
184 /* ADDR must be written twice */
185 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
186 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
187
188 /* Write needs single DATA write */
189 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
190
191 spin_unlock_irqrestore(&reg_lock, flags);
192}
193
194/* Helper to change specific bits in PHY registers */
195static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi,
196 unsigned int addr,
197 unsigned int mask,
198 unsigned int val)
199{
200 unsigned int data = dw_hdmi_top_read(dw_hdmi, addr);
201
202 data &= ~mask;
203 data |= val;
204
205 dw_hdmi_top_write(dw_hdmi, addr, data);
206}
207
208static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi,
209 unsigned int addr)
210{
211 unsigned long flags;
212 unsigned int data;
213
214 spin_lock_irqsave(&reg_lock, flags);
215
216 /* ADDR must be written twice */
217 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
218 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
219
220 /* Read needs a second DATA read */
221 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
222 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
223
224 spin_unlock_irqrestore(&reg_lock, flags);
225
226 return data;
227}
228
229static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi,
230 unsigned int addr, unsigned int data)
231{
232 unsigned long flags;
233
234 spin_lock_irqsave(&reg_lock, flags);
235
236 /* ADDR must be written twice */
237 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
238 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
239
240 /* Write needs single DATA write */
241 writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
242
243 spin_unlock_irqrestore(&reg_lock, flags);
244}
245
246/* Helper to change specific bits in controller registers */
247static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi *dw_hdmi,
248 unsigned int addr,
249 unsigned int mask,
250 unsigned int val)
251{
252 unsigned int data = dw_hdmi_dwc_read(dw_hdmi, addr);
253
254 data &= ~mask;
255 data |= val;
256
257 dw_hdmi_dwc_write(dw_hdmi, addr, data);
258}
259
260/* Bridge */
261
262/* Setup PHY bandwidth modes */
263static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
264 struct drm_display_mode *mode)
265{
266 struct meson_drm *priv = dw_hdmi->priv;
267 unsigned int pixel_clock = mode->clock;
268
269 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
270 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) {
271 if (pixel_clock >= 371250) {
272 /* 5.94Gbps, 3.7125Gbps */
273 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282);
274 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b);
275 } else if (pixel_clock >= 297000) {
276 /* 2.97Gbps */
277 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382);
278 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b);
279 } else if (pixel_clock >= 148500) {
280 /* 1.485Gbps */
281 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362);
282 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b);
283 } else {
284 /* 742.5Mbps, and below */
285 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142);
286 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b);
287 }
288 } else if (dw_hdmi_is_compatible(dw_hdmi,
289 "amlogic,meson-gxbb-dw-hdmi")) {
290 if (pixel_clock >= 371250) {
291 /* 5.94Gbps, 3.7125Gbps */
292 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245);
293 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b);
294 } else if (pixel_clock >= 297000) {
295 /* 2.97Gbps */
296 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283);
297 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b);
298 } else {
299 /* 1.485Gbps, and below */
300 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122);
301 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b);
302 }
303 }
304}
305
5765916a 306static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi)
3f68be7d
NA		 307{
308 struct meson_drm *priv = dw_hdmi->priv;
309
310 /* Enable and software reset */
311 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
312
313 mdelay(2);
314
315 /* Enable and unreset */
316 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
317
318 mdelay(2);
319}
320
321static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi,
322 struct drm_display_mode *mode)
323{
324 struct meson_drm *priv = dw_hdmi->priv;
325 int vic = drm_match_cea_mode(mode);
326 unsigned int vclk_freq;
327 unsigned int venc_freq;
328 unsigned int hdmi_freq;
329
330 vclk_freq = mode->clock;
331
3273fc63
NA		 332 if (!vic) {
333 meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq,
334 vclk_freq, vclk_freq, false);
335 return;
336 }
337
3f68be7d
NA		 338 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
339 vclk_freq *= 2;
340
341 venc_freq = vclk_freq;
342 hdmi_freq = vclk_freq;
343
344 if (meson_venc_hdmi_venc_repeat(vic))
345 venc_freq *= 2;
346
347 vclk_freq = max(venc_freq, hdmi_freq);
348
349 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
350 venc_freq /= 2;
351
352 DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n",
353 vclk_freq, venc_freq, hdmi_freq,
354 priv->venc.hdmi_use_enci);
355
356 meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq,
357 venc_freq, hdmi_freq, priv->venc.hdmi_use_enci);
358}
359
360static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
361 struct drm_display_mode *mode)
362{
363 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
364 struct meson_drm *priv = dw_hdmi->priv;
365 unsigned int wr_clk =
366 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
367
368 DRM_DEBUG_DRIVER("%d:\"%s\"\n", mode->base.id, mode->name);
369
370 /* Enable clocks */
371 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
372
373 /* Bring HDMITX MEM output of power down */
374 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
375
376 /* Bring out of reset */
377 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0);
378
379 /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
380 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
381 0x3, 0x3);
382 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
383 0x3 << 4, 0x3 << 4);
384
385 /* Enable normal output to PHY */
386 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
387
388 /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */
389 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
390 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
391
392 /* Load TMDS pattern */
393 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
394 msleep(20);
395 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
396
397 /* Setup PHY parameters */
398 meson_hdmi_phy_setup_mode(dw_hdmi, mode);
399
400 /* Setup PHY */
401 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
402 0xffff << 16, 0x0390 << 16);
403
404 /* BIT_INVERT */
405 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
406 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi"))
407 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
408 BIT(17), 0);
409 else
410 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
411 BIT(17), BIT(17));
412
413 /* Disable clock, fifo, fifo_wr */
414 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
415
416 msleep(100);
417
418 /* Reset PHY 3 times in a row */
5765916a
JS		 419 meson_dw_hdmi_phy_reset(dw_hdmi);
420 meson_dw_hdmi_phy_reset(dw_hdmi);
421 meson_dw_hdmi_phy_reset(dw_hdmi);
3f68be7d
NA		 422
423 /* Temporary Disable VENC video stream */
424 if (priv->venc.hdmi_use_enci)
425 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
426 else
427 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
428
429 /* Temporary Disable HDMI video stream to HDMI-TX */
430 writel_bits_relaxed(0x3, 0,
431 priv->io_base + _REG(VPU_HDMI_SETTING));
432 writel_bits_relaxed(0xf << 8, 0,
433 priv->io_base + _REG(VPU_HDMI_SETTING));
434
435 /* Re-Enable VENC video stream */
436 if (priv->venc.hdmi_use_enci)
437 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
438 else
439 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
440
441 /* Push back HDMI clock settings */
442 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8),
443 priv->io_base + _REG(VPU_HDMI_SETTING));
444
445 /* Enable and Select HDMI video source for HDMI-TX */
446 if (priv->venc.hdmi_use_enci)
447 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI,
448 priv->io_base + _REG(VPU_HDMI_SETTING));
449 else
450 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP,
451 priv->io_base + _REG(VPU_HDMI_SETTING));
452
453 return 0;
454}
455
456static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
457 void *data)
458{
459 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
460 struct meson_drm *priv = dw_hdmi->priv;
461
462 DRM_DEBUG_DRIVER("\n");
463
464 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
465}
466
467static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
468 void *data)
469{
470 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
471
472 return !!dw_hdmi_top_read(dw_hdmi, HDMITX_TOP_STAT0) ?
473 connector_status_connected : connector_status_disconnected;
474}
475
476static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi,
477 void *data)
478{
479 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
480
481 /* Setup HPD Filter */
482 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,
483 (0xa << 12) | 0xa0);
484
485 /* Clear interrupts */
486 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
487 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL);
488
489 /* Unmask interrupts */
490 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_INTR_MASKN,
491 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL,
492 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL);
493}
494
495static const struct dw_hdmi_phy_ops meson_dw_hdmi_phy_ops = {
496 .init = dw_hdmi_phy_init,
497 .disable = dw_hdmi_phy_disable,
498 .read_hpd = dw_hdmi_read_hpd,
499 .setup_hpd = dw_hdmi_setup_hpd,
500};
501
502static irqreturn_t dw_hdmi_top_irq(int irq, void *dev_id)
503{
504 struct meson_dw_hdmi *dw_hdmi = dev_id;
505 u32 stat;
506
507 stat = dw_hdmi_top_read(dw_hdmi, HDMITX_TOP_INTR_STAT);
508 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);
509
510 /* HPD Events, handle in the threaded interrupt handler */
511 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) {
512 dw_hdmi->irq_stat = stat;
513 return IRQ_WAKE_THREAD;
514 }
515
516 /* HDMI Controller Interrupt */
517 if (stat & 1)
518 return IRQ_NONE;
519
520 /* TOFIX Handle HDCP Interrupts */
521
522 return IRQ_HANDLED;
523}
524
525/* Threaded interrupt handler to manage HPD events */
526static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id)
527{
528 struct meson_dw_hdmi *dw_hdmi = dev_id;
529 u32 stat = dw_hdmi->irq_stat;
530
531 /* HPD Events */
532 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) {
533 bool hpd_connected = false;
534
535 if (stat & HDMITX_TOP_INTR_HPD_RISE)
536 hpd_connected = true;
537
c32048d9 538 dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected,
3f68be7d
NA		 539 hpd_connected);
540
541 drm_helper_hpd_irq_event(dw_hdmi->encoder.dev);
542 }
543
544 return IRQ_HANDLED;
545}
546
b0febde7
JA		 547static enum drm_mode_status
548dw_hdmi_mode_valid(struct drm_connector *connector,
549 const struct drm_display_mode *mode)
3f68be7d 550{
3273fc63 551 struct meson_drm *priv = connector->dev->dev_private;
3f68be7d
NA		 552 unsigned int vclk_freq;
553 unsigned int venc_freq;
554 unsigned int hdmi_freq;
555 int vic = drm_match_cea_mode(mode);
3273fc63 556 enum drm_mode_status status;
3f68be7d
NA		 557
558 DRM_DEBUG_DRIVER("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n",
559 mode->base.id, mode->name, mode->vrefresh, mode->clock,
560 mode->hdisplay, mode->hsync_start,
561 mode->hsync_end, mode->htotal,
562 mode->vdisplay, mode->vsync_start,
563 mode->vsync_end, mode->vtotal, mode->type, mode->flags);
564
9c936b12
NA		 565 /* Check against non-VIC supported modes */
566 if (!vic) {
3273fc63
NA		 567 status = meson_venc_hdmi_supported_mode(mode);
568 if (status != MODE_OK)
569 return status;
570
571 return meson_vclk_dmt_supported_freq(priv, mode->clock);
9c936b12
NA		 572 /* Check against supported VIC modes */
573 } else if (!meson_venc_hdmi_supported_vic(vic))
3f68be7d
NA		 574 return MODE_BAD;
575
576 vclk_freq = mode->clock;
577
578 /* 480i/576i needs global pixel doubling */
579 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
580 vclk_freq *= 2;
581
582 venc_freq = vclk_freq;
583 hdmi_freq = vclk_freq;
584
585 /* VENC double pixels for 1080i and 720p modes */
586 if (meson_venc_hdmi_venc_repeat(vic))
587 venc_freq *= 2;
588
589 vclk_freq = max(venc_freq, hdmi_freq);
590
591 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
592 venc_freq /= 2;
593
594 dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__,
595 vclk_freq, venc_freq, hdmi_freq);
596
3273fc63 597 /* Finally filter by configurable vclk frequencies for VIC modes */
3f68be7d
NA		 598 switch (vclk_freq) {
599 case 54000:
600 case 74250:
601 case 148500:
602 case 297000:
603 case 594000:
604 return MODE_OK;
605 }
606
607 return MODE_CLOCK_RANGE;
608}
609
610/* Encoder */
611
612static void meson_venc_hdmi_encoder_destroy(struct drm_encoder *encoder)
613{
614 drm_encoder_cleanup(encoder);
615}
616
617static const struct drm_encoder_funcs meson_venc_hdmi_encoder_funcs = {
618 .destroy = meson_venc_hdmi_encoder_destroy,
619};
620
621static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
622 struct drm_crtc_state *crtc_state,
623 struct drm_connector_state *conn_state)
624{
625 return 0;
626}
627
628static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder)
629{
630 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
631 struct meson_drm *priv = dw_hdmi->priv;
632
633 DRM_DEBUG_DRIVER("\n");
634
635 writel_bits_relaxed(0x3, 0,
636 priv->io_base + _REG(VPU_HDMI_SETTING));
637
638 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
639 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
640}
641
642static void meson_venc_hdmi_encoder_enable(struct drm_encoder *encoder)
643{
644 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
645 struct meson_drm *priv = dw_hdmi->priv;
646
647 DRM_DEBUG_DRIVER("%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP");
648
649 if (priv->venc.hdmi_use_enci)
650 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
651 else
652 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
653}
654
655static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder,
656 struct drm_display_mode *mode,
657 struct drm_display_mode *adjusted_mode)
658{
659 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
660 struct meson_drm *priv = dw_hdmi->priv;
661 int vic = drm_match_cea_mode(mode);
662
663 DRM_DEBUG_DRIVER("%d:\"%s\" vic %d\n",
664 mode->base.id, mode->name, vic);
665
3f68be7d
NA		 666 /* VENC + VENC-DVI Mode setup */
667 meson_venc_hdmi_mode_set(priv, vic, mode);
668
669 /* VCLK Set clock */
670 dw_hdmi_set_vclk(dw_hdmi, mode);
671
672 /* Setup YUV444 to HDMI-TX, no 10bit diphering */
673 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
674}
675
676static const struct drm_encoder_helper_funcs
677 meson_venc_hdmi_encoder_helper_funcs = {
678 .atomic_check = meson_venc_hdmi_encoder_atomic_check,
679 .disable = meson_venc_hdmi_encoder_disable,
680 .enable = meson_venc_hdmi_encoder_enable,
681 .mode_set = meson_venc_hdmi_encoder_mode_set,
682};
683
684/* DW HDMI Regmap */
685
686static int meson_dw_hdmi_reg_read(void *context, unsigned int reg,
687 unsigned int *result)
688{
689 *result = dw_hdmi_dwc_read(context, reg);
690
691 return 0;
692
693}
694
695static int meson_dw_hdmi_reg_write(void *context, unsigned int reg,
696 unsigned int val)
697{
698 dw_hdmi_dwc_write(context, reg, val);
699
700 return 0;
701}
702
703static const struct regmap_config meson_dw_hdmi_regmap_config = {
704 .reg_bits = 32,
705 .val_bits = 8,
706 .reg_read = meson_dw_hdmi_reg_read,
707 .reg_write = meson_dw_hdmi_reg_write,
708 .max_register = 0x10000,
995b278e 709 .fast_io = true,
3f68be7d
NA		 710};
711
712static bool meson_hdmi_connector_is_available(struct device *dev)
713{
714 struct device_node *ep, *remote;
715
716 /* HDMI Connector is on the second port, first endpoint */
717 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, 0);
718 if (!ep)
719 return false;
720
721 /* If the endpoint node exists, consider it enabled */
722 remote = of_graph_get_remote_port(ep);
723 if (remote) {
724 of_node_put(ep);
725 return true;
726 }
727
728 of_node_put(ep);
729 of_node_put(remote);
730
731 return false;
732}
733
734static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
735 void *data)
736{
737 struct platform_device *pdev = to_platform_device(dev);
738 struct meson_dw_hdmi *meson_dw_hdmi;
739 struct drm_device *drm = data;
740 struct meson_drm *priv = drm->dev_private;
741 struct dw_hdmi_plat_data *dw_plat_data;
742 struct drm_encoder *encoder;
743 struct resource *res;
744 int irq;
745 int ret;
746
747 DRM_DEBUG_DRIVER("\n");
748
749 if (!meson_hdmi_connector_is_available(dev)) {
750 dev_info(drm->dev, "HDMI Output connector not available\n");
751 return -ENODEV;
752 }
753
754 meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi),
755 GFP_KERNEL);
756 if (!meson_dw_hdmi)
757 return -ENOMEM;
758
759 meson_dw_hdmi->priv = priv;
760 meson_dw_hdmi->dev = dev;
761 dw_plat_data = &meson_dw_hdmi->dw_plat_data;
762 encoder = &meson_dw_hdmi->encoder;
763
161a803f
NA		 764 meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi");
765 if (IS_ERR(meson_dw_hdmi->hdmi_supply)) {
766 if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER)
767 return -EPROBE_DEFER;
768 meson_dw_hdmi->hdmi_supply = NULL;
769 } else {
770 ret = regulator_enable(meson_dw_hdmi->hdmi_supply);
771 if (ret)
772 return ret;
773 }
774
3f68be7d
NA		 775 meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev,
776 "hdmitx_apb");
777 if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) {
778 dev_err(dev, "Failed to get hdmitx_apb reset\n");
779 return PTR_ERR(meson_dw_hdmi->hdmitx_apb);
780 }
781
782 meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev,
783 "hdmitx");
784 if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) {
785 dev_err(dev, "Failed to get hdmitx reset\n");
786 return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl);
787 }
788
789 meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev,
790 "hdmitx_phy");
791 if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) {
792 dev_err(dev, "Failed to get hdmitx_phy reset\n");
793 return PTR_ERR(meson_dw_hdmi->hdmitx_phy);
794 }
795
796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
797 meson_dw_hdmi->hdmitx = devm_ioremap_resource(dev, res);
798 if (IS_ERR(meson_dw_hdmi->hdmitx))
799 return PTR_ERR(meson_dw_hdmi->hdmitx);
800
801 meson_dw_hdmi->hdmi_pclk = devm_clk_get(dev, "isfr");
802 if (IS_ERR(meson_dw_hdmi->hdmi_pclk)) {
803 dev_err(dev, "Unable to get HDMI pclk\n");
804 return PTR_ERR(meson_dw_hdmi->hdmi_pclk);
805 }
806 clk_prepare_enable(meson_dw_hdmi->hdmi_pclk);
807
808 meson_dw_hdmi->venci_clk = devm_clk_get(dev, "venci");
809 if (IS_ERR(meson_dw_hdmi->venci_clk)) {
810 dev_err(dev, "Unable to get venci clk\n");
811 return PTR_ERR(meson_dw_hdmi->venci_clk);
812 }
813 clk_prepare_enable(meson_dw_hdmi->venci_clk);
814
815 dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi,
816 &meson_dw_hdmi_regmap_config);
817 if (IS_ERR(dw_plat_data->regm))
818 return PTR_ERR(dw_plat_data->regm);
819
820 irq = platform_get_irq(pdev, 0);
821 if (irq < 0) {
822 dev_err(dev, "Failed to get hdmi top irq\n");
823 return irq;
824 }
825
826 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq,
827 dw_hdmi_top_thread_irq, IRQF_SHARED,
828 "dw_hdmi_top_irq", meson_dw_hdmi);
829 if (ret) {
830 dev_err(dev, "Failed to request hdmi top irq\n");
831 return ret;
832 }
833
834 /* Encoder */
835
836 drm_encoder_helper_add(encoder, &meson_venc_hdmi_encoder_helper_funcs);
837
838 ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs,
839 DRM_MODE_ENCODER_TMDS, "meson_hdmi");
840 if (ret) {
841 dev_err(priv->dev, "Failed to init HDMI encoder\n");
842 return ret;
843 }
844
845 encoder->possible_crtcs = BIT(0);
846
847 DRM_DEBUG_DRIVER("encoder initialized\n");
848
849 /* Enable clocks */
850 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
851
852 /* Bring HDMITX MEM output of power down */
853 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
854
855 /* Reset HDMITX APB & TX & PHY */
856 reset_control_reset(meson_dw_hdmi->hdmitx_apb);
857 reset_control_reset(meson_dw_hdmi->hdmitx_ctrl);
858 reset_control_reset(meson_dw_hdmi->hdmitx_phy);
859
860 /* Enable APB3 fail on error */
861 writel_bits_relaxed(BIT(15), BIT(15),
862 meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
863 writel_bits_relaxed(BIT(15), BIT(15),
864 meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);
865
866 /* Bring out of reset */
867 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_SW_RESET, 0);
868
869 msleep(20);
870
871 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_CLK_CNTL, 0xff);
872
873 /* Enable HDMI-TX Interrupt */
874 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
875 HDMITX_TOP_INTR_CORE);
876
877 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,
878 HDMITX_TOP_INTR_CORE);
879
880 /* Bridge / Connector */
881
882 dw_plat_data->mode_valid = dw_hdmi_mode_valid;
883 dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops;
884 dw_plat_data->phy_name = "meson_dw_hdmi_phy";
885 dw_plat_data->phy_data = meson_dw_hdmi;
886 dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
887 dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
888
eea034af
JS		 889 platform_set_drvdata(pdev, meson_dw_hdmi);
890
891 meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder,
892 &meson_dw_hdmi->dw_plat_data);
893 if (IS_ERR(meson_dw_hdmi->hdmi))
894 return PTR_ERR(meson_dw_hdmi->hdmi);
3f68be7d
NA		 895
896 DRM_DEBUG_DRIVER("HDMI controller initialized\n");
897
898 return 0;
899}
900
901static void meson_dw_hdmi_unbind(struct device *dev, struct device *master,
902 void *data)
903{
eea034af
JS		 904 struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);
905
906 dw_hdmi_unbind(meson_dw_hdmi->hdmi);
3f68be7d
NA		 907}
908
909static const struct component_ops meson_dw_hdmi_ops = {
910 .bind = meson_dw_hdmi_bind,
911 .unbind = meson_dw_hdmi_unbind,
912};
913
914static int meson_dw_hdmi_probe(struct platform_device *pdev)
915{
916 return component_add(&pdev->dev, &meson_dw_hdmi_ops);
917}
918
919static int meson_dw_hdmi_remove(struct platform_device *pdev)
920{
921 component_del(&pdev->dev, &meson_dw_hdmi_ops);
922
923 return 0;
924}
925
926static const struct of_device_id meson_dw_hdmi_of_table[] = {
927 { .compatible = "amlogic,meson-gxbb-dw-hdmi" },
928 { .compatible = "amlogic,meson-gxl-dw-hdmi" },
929 { .compatible = "amlogic,meson-gxm-dw-hdmi" },
930 { }
931};
932MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table);
933
934static struct platform_driver meson_dw_hdmi_platform_driver = {
935 .probe = meson_dw_hdmi_probe,
936 .remove = meson_dw_hdmi_remove,
937 .driver = {
938 .name = DRIVER_NAME,
939 .of_match_table = meson_dw_hdmi_of_table,
940 },
941};
942module_platform_driver(meson_dw_hdmi_platform_driver);
943
944MODULE_AUTHOR("Neil Armstrong <[email protected]>");
945MODULE_DESCRIPTION(DRIVER_DESC);
946MODULE_LICENSE("GPL");
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