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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
CommitLineData
9c065a7d
SV		 1/*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <[email protected]>
25 * Daniel Vetter <[email protected]>
26 *
27 */
28
29#include <linux/pm_runtime.h>
30#include <linux/vgaarb.h>
31
32#include "i915_drv.h"
33#include "intel_drv.h"
9c065a7d 34
e4e7684f
SV		 35/**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
5aefb239 52bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
438b8dc4 53 enum i915_power_well_id power_well_id);
5aefb239 54
9895ad03
DS		 55const char *
56intel_display_power_domain_str(enum intel_display_power_domain domain)
57{
58 switch (domain) {
59 case POWER_DOMAIN_PIPE_A:
60 return "PIPE_A";
61 case POWER_DOMAIN_PIPE_B:
62 return "PIPE_B";
63 case POWER_DOMAIN_PIPE_C:
64 return "PIPE_C";
65 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
66 return "PIPE_A_PANEL_FITTER";
67 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
68 return "PIPE_B_PANEL_FITTER";
69 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
70 return "PIPE_C_PANEL_FITTER";
71 case POWER_DOMAIN_TRANSCODER_A:
72 return "TRANSCODER_A";
73 case POWER_DOMAIN_TRANSCODER_B:
74 return "TRANSCODER_B";
75 case POWER_DOMAIN_TRANSCODER_C:
76 return "TRANSCODER_C";
77 case POWER_DOMAIN_TRANSCODER_EDP:
78 return "TRANSCODER_EDP";
4d1de975
JN		 79 case POWER_DOMAIN_TRANSCODER_DSI_A:
80 return "TRANSCODER_DSI_A";
81 case POWER_DOMAIN_TRANSCODER_DSI_C:
82 return "TRANSCODER_DSI_C";
9895ad03
DS		 83 case POWER_DOMAIN_PORT_DDI_A_LANES:
84 return "PORT_DDI_A_LANES";
85 case POWER_DOMAIN_PORT_DDI_B_LANES:
86 return "PORT_DDI_B_LANES";
87 case POWER_DOMAIN_PORT_DDI_C_LANES:
88 return "PORT_DDI_C_LANES";
89 case POWER_DOMAIN_PORT_DDI_D_LANES:
90 return "PORT_DDI_D_LANES";
91 case POWER_DOMAIN_PORT_DDI_E_LANES:
92 return "PORT_DDI_E_LANES";
9787e835
RV		 93 case POWER_DOMAIN_PORT_DDI_F_LANES:
94 return "PORT_DDI_F_LANES";
62b69566
ACO		 95 case POWER_DOMAIN_PORT_DDI_A_IO:
96 return "PORT_DDI_A_IO";
97 case POWER_DOMAIN_PORT_DDI_B_IO:
98 return "PORT_DDI_B_IO";
99 case POWER_DOMAIN_PORT_DDI_C_IO:
100 return "PORT_DDI_C_IO";
101 case POWER_DOMAIN_PORT_DDI_D_IO:
102 return "PORT_DDI_D_IO";
103 case POWER_DOMAIN_PORT_DDI_E_IO:
104 return "PORT_DDI_E_IO";
9787e835
RV		 105 case POWER_DOMAIN_PORT_DDI_F_IO:
106 return "PORT_DDI_F_IO";
9895ad03
DS		 107 case POWER_DOMAIN_PORT_DSI:
108 return "PORT_DSI";
109 case POWER_DOMAIN_PORT_CRT:
110 return "PORT_CRT";
111 case POWER_DOMAIN_PORT_OTHER:
112 return "PORT_OTHER";
113 case POWER_DOMAIN_VGA:
114 return "VGA";
115 case POWER_DOMAIN_AUDIO:
116 return "AUDIO";
117 case POWER_DOMAIN_PLLS:
118 return "PLLS";
119 case POWER_DOMAIN_AUX_A:
120 return "AUX_A";
121 case POWER_DOMAIN_AUX_B:
122 return "AUX_B";
123 case POWER_DOMAIN_AUX_C:
124 return "AUX_C";
125 case POWER_DOMAIN_AUX_D:
126 return "AUX_D";
bb187e93
JA		 127 case POWER_DOMAIN_AUX_E:
128 return "AUX_E";
a324fcac
RV		 129 case POWER_DOMAIN_AUX_F:
130 return "AUX_F";
b891d5e4
DP		 131 case POWER_DOMAIN_AUX_IO_A:
132 return "AUX_IO_A";
67ca07e7
ID		 133 case POWER_DOMAIN_AUX_TBT1:
134 return "AUX_TBT1";
135 case POWER_DOMAIN_AUX_TBT2:
136 return "AUX_TBT2";
137 case POWER_DOMAIN_AUX_TBT3:
138 return "AUX_TBT3";
139 case POWER_DOMAIN_AUX_TBT4:
140 return "AUX_TBT4";
9895ad03
DS		 141 case POWER_DOMAIN_GMBUS:
142 return "GMBUS";
143 case POWER_DOMAIN_INIT:
144 return "INIT";
145 case POWER_DOMAIN_MODESET:
146 return "MODESET";
b6876374
TU		 147 case POWER_DOMAIN_GT_IRQ:
148 return "GT_IRQ";
9895ad03
DS		 149 default:
150 MISSING_CASE(domain);
151 return "?";
152 }
153}
154
e8ca9320
DL		 155static void intel_power_well_enable(struct drm_i915_private *dev_priv,
156 struct i915_power_well *power_well)
157{
f28ec6f4
ID		 158 DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
159 power_well->desc->ops->enable(dev_priv, power_well);
e8ca9320
DL		 160 power_well->hw_enabled = true;
161}
162
dcddab3a
DL		 163static void intel_power_well_disable(struct drm_i915_private *dev_priv,
164 struct i915_power_well *power_well)
165{
f28ec6f4 166 DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);
dcddab3a 167 power_well->hw_enabled = false;
f28ec6f4 168 power_well->desc->ops->disable(dev_priv, power_well);
dcddab3a
DL		 169}
170
b409ca95
ID		 171static void intel_power_well_get(struct drm_i915_private *dev_priv,
172 struct i915_power_well *power_well)
173{
174 if (!power_well->count++)
175 intel_power_well_enable(dev_priv, power_well);
176}
177
178static void intel_power_well_put(struct drm_i915_private *dev_priv,
179 struct i915_power_well *power_well)
180{
181 WARN(!power_well->count, "Use count on power well %s is already zero",
f28ec6f4 182 power_well->desc->name);
b409ca95
ID		 183
184 if (!--power_well->count)
185 intel_power_well_disable(dev_priv, power_well);
186}
187
e4e7684f
SV		 188/**
189 * __intel_display_power_is_enabled - unlocked check for a power domain
190 * @dev_priv: i915 device instance
191 * @domain: power domain to check
192 *
193 * This is the unlocked version of intel_display_power_is_enabled() and should
194 * only be used from error capture and recovery code where deadlocks are
195 * possible.
196 *
197 * Returns:
198 * True when the power domain is enabled, false otherwise.
199 */
f458ebbc
SV		 200bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
201 enum intel_display_power_domain domain)
9c065a7d 202{
9c065a7d
SV		 203 struct i915_power_well *power_well;
204 bool is_enabled;
9c065a7d 205
ad1443f0 206 if (dev_priv->runtime_pm.suspended)
9c065a7d
SV		 207 return false;
208
9c065a7d
SV		 209 is_enabled = true;
210
75ccb2ec 211 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
f28ec6f4 212 if (power_well->desc->always_on)
9c065a7d
SV		 213 continue;
214
215 if (!power_well->hw_enabled) {
216 is_enabled = false;
217 break;
218 }
219 }
220
221 return is_enabled;
222}
223
e4e7684f 224/**
f61ccae3 225 * intel_display_power_is_enabled - check for a power domain
e4e7684f
SV		 226 * @dev_priv: i915 device instance
227 * @domain: power domain to check
228 *
229 * This function can be used to check the hw power domain state. It is mostly
230 * used in hardware state readout functions. Everywhere else code should rely
231 * upon explicit power domain reference counting to ensure that the hardware
232 * block is powered up before accessing it.
233 *
234 * Callers must hold the relevant modesetting locks to ensure that concurrent
235 * threads can't disable the power well while the caller tries to read a few
236 * registers.
237 *
238 * Returns:
239 * True when the power domain is enabled, false otherwise.
240 */
f458ebbc
SV		 241bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
242 enum intel_display_power_domain domain)
9c065a7d
SV		 243{
244 struct i915_power_domains *power_domains;
245 bool ret;
246
247 power_domains = &dev_priv->power_domains;
248
249 mutex_lock(&power_domains->lock);
f458ebbc 250 ret = __intel_display_power_is_enabled(dev_priv, domain);
9c065a7d
SV		 251 mutex_unlock(&power_domains->lock);
252
253 return ret;
254}
255
256/*
257 * Starting with Haswell, we have a "Power Down Well" that can be turned off
258 * when not needed anymore. We have 4 registers that can request the power well
259 * to be enabled, and it will only be disabled if none of the registers is
260 * requesting it to be enabled.
261 */
001bd2cb
ID		 262static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
263 u8 irq_pipe_mask, bool has_vga)
9c065a7d 264{
52a05c30 265 struct pci_dev *pdev = dev_priv->drm.pdev;
9c065a7d
SV		 266
267 /*
268 * After we re-enable the power well, if we touch VGA register 0x3d5
269 * we'll get unclaimed register interrupts. This stops after we write
270 * anything to the VGA MSR register. The vgacon module uses this
271 * register all the time, so if we unbind our driver and, as a
272 * consequence, bind vgacon, we'll get stuck in an infinite loop at
273 * console_unlock(). So make here we touch the VGA MSR register, making
274 * sure vgacon can keep working normally without triggering interrupts
275 * and error messages.
276 */
001bd2cb
ID		 277 if (has_vga) {
278 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
279 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
280 vga_put(pdev, VGA_RSRC_LEGACY_IO);
281 }
9c065a7d 282
001bd2cb
ID		 283 if (irq_pipe_mask)
284 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
9c065a7d
SV		 285}
286
001bd2cb
ID		 287static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
288 u8 irq_pipe_mask)
aae8ba84 289{
001bd2cb
ID		 290 if (irq_pipe_mask)
291 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
aae8ba84
VS		 292}
293
aae8ba84 294
76347c04
ID		 295static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
296 struct i915_power_well *power_well)
42d9366d 297{
75e39688
ID		 298 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
299 int pw_idx = power_well->desc->hsw.idx;
42d9366d
ID		 300
301 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
302 WARN_ON(intel_wait_for_register(dev_priv,
75e39688
ID		 303 regs->driver,
304 HSW_PWR_WELL_CTL_STATE(pw_idx),
305 HSW_PWR_WELL_CTL_STATE(pw_idx),
42d9366d
ID		 306 1));
307}
308
76347c04 309static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
75e39688
ID		 310 const struct i915_power_well_regs *regs,
311 int pw_idx)
42d9366d 312{
75e39688 313 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
42d9366d
ID		 314 u32 ret;
315
75e39688
ID		 316 ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
317 ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
318 if (regs->kvmr.reg)
319 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
320 ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
42d9366d
ID		 321
322 return ret;
323}
324
76347c04
ID		 325static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
326 struct i915_power_well *power_well)
42d9366d 327{
75e39688
ID		 328 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
329 int pw_idx = power_well->desc->hsw.idx;
42d9366d
ID		 330 bool disabled;
331 u32 reqs;
332
333 /*
334 * Bspec doesn't require waiting for PWs to get disabled, but still do
335 * this for paranoia. The known cases where a PW will be forced on:
336 * - a KVMR request on any power well via the KVMR request register
337 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
338 * DEBUG request registers
339 * Skip the wait in case any of the request bits are set and print a
340 * diagnostic message.
341 */
75e39688
ID		 342 wait_for((disabled = !(I915_READ(regs->driver) &
343 HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
344 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
42d9366d
ID		 345 if (disabled)
346 return;
347
348 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
f28ec6f4 349 power_well->desc->name,
42d9366d
ID		 350 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
351}
352
b2891eb2
ID		 353static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
354 enum skl_power_gate pg)
355{
356 /* Timeout 5us for PG#0, for other PGs 1us */
357 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
358 SKL_FUSE_PG_DIST_STATUS(pg),
359 SKL_FUSE_PG_DIST_STATUS(pg), 1));
360}
361
ec46d483
ID		 362static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
363 struct i915_power_well *power_well)
9c065a7d 364{
75e39688
ID		 365 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
366 int pw_idx = power_well->desc->hsw.idx;
f28ec6f4 367 bool wait_fuses = power_well->desc->hsw.has_fuses;
320671f9 368 enum skl_power_gate uninitialized_var(pg);
1af474fe
ID		 369 u32 val;
370
b2891eb2 371 if (wait_fuses) {
75e39688
ID		 372 pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
373 SKL_PW_CTL_IDX_TO_PG(pw_idx);
b2891eb2
ID		 374 /*
375 * For PW1 we have to wait both for the PW0/PG0 fuse state
376 * before enabling the power well and PW1/PG1's own fuse
377 * state after the enabling. For all other power wells with
378 * fuses we only have to wait for that PW/PG's fuse state
379 * after the enabling.
380 */
381 if (pg == SKL_PG1)
382 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
383 }
384
75e39688
ID		 385 val = I915_READ(regs->driver);
386 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
76347c04 387 hsw_wait_for_power_well_enable(dev_priv, power_well);
001bd2cb 388
ddd39e4b
LDM		 389 /* Display WA #1178: cnl */
390 if (IS_CANNONLAKE(dev_priv) &&
75e39688
ID		 391 pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
392 pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
393 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
ddd39e4b 394 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
75e39688 395 I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val);
ddd39e4b
LDM		 396 }
397
b2891eb2
ID		 398 if (wait_fuses)
399 gen9_wait_for_power_well_fuses(dev_priv, pg);
400
f28ec6f4
ID		 401 hsw_power_well_post_enable(dev_priv,
402 power_well->desc->hsw.irq_pipe_mask,
403 power_well->desc->hsw.has_vga);
ec46d483 404}
00742cab 405
ec46d483
ID		 406static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
407 struct i915_power_well *power_well)
408{
75e39688
ID		 409 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
410 int pw_idx = power_well->desc->hsw.idx;
1af474fe
ID		 411 u32 val;
412
f28ec6f4
ID		 413 hsw_power_well_pre_disable(dev_priv,
414 power_well->desc->hsw.irq_pipe_mask);
001bd2cb 415
75e39688
ID		 416 val = I915_READ(regs->driver);
417 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
76347c04 418 hsw_wait_for_power_well_disable(dev_priv, power_well);
9c065a7d
SV		 419}
420
75e39688 421#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
67ca07e7
ID		 422
423static void
424icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
425 struct i915_power_well *power_well)
426{
75e39688
ID		 427 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
428 int pw_idx = power_well->desc->hsw.idx;
429 enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
67ca07e7
ID		 430 u32 val;
431
75e39688
ID		 432 val = I915_READ(regs->driver);
433 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
67ca07e7
ID		 434
435 val = I915_READ(ICL_PORT_CL_DW12(port));
436 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
437
438 hsw_wait_for_power_well_enable(dev_priv, power_well);
439}
440
441static void
442icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
443 struct i915_power_well *power_well)
444{
75e39688
ID		 445 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
446 int pw_idx = power_well->desc->hsw.idx;
447 enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
67ca07e7
ID		 448 u32 val;
449
450 val = I915_READ(ICL_PORT_CL_DW12(port));
451 I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
452
75e39688
ID		 453 val = I915_READ(regs->driver);
454 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
67ca07e7
ID		 455
456 hsw_wait_for_power_well_disable(dev_priv, power_well);
457}
458
d42539ba
ID		 459/*
460 * We should only use the power well if we explicitly asked the hardware to
461 * enable it, so check if it's enabled and also check if we've requested it to
462 * be enabled.
463 */
464static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
465 struct i915_power_well *power_well)
466{
75e39688
ID		 467 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
468 int pw_idx = power_well->desc->hsw.idx;
469 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
470 HSW_PWR_WELL_CTL_STATE(pw_idx);
d42539ba 471
75e39688 472 return (I915_READ(regs->driver) & mask) == mask;
d42539ba
ID		 473}
474
664326f8
SK		 475static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
476{
bfcdabe8
ID		 477 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
478 "DC9 already programmed to be enabled.\n");
479 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
480 "DC5 still not disabled to enable DC9.\n");
75e39688
ID		 481 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
482 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
e8a3a2a3 483 "Power well 2 on.\n");
bfcdabe8
ID		 484 WARN_ONCE(intel_irqs_enabled(dev_priv),
485 "Interrupts not disabled yet.\n");
664326f8
SK		 486
487 /*
488 * TODO: check for the following to verify the conditions to enter DC9
489 * state are satisfied:
490 * 1] Check relevant display engine registers to verify if mode set
491 * disable sequence was followed.
492 * 2] Check if display uninitialize sequence is initialized.
493 */
494}
495
496static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
497{
bfcdabe8
ID		 498 WARN_ONCE(intel_irqs_enabled(dev_priv),
499 "Interrupts not disabled yet.\n");
500 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
501 "DC5 still not disabled.\n");
664326f8
SK		 502
503 /*
504 * TODO: check for the following to verify DC9 state was indeed
505 * entered before programming to disable it:
506 * 1] Check relevant display engine registers to verify if mode
507 * set disable sequence was followed.
508 * 2] Check if display uninitialize sequence is initialized.
509 */
510}
511
779cb5d3
MK		 512static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
513 u32 state)
514{
515 int rewrites = 0;
516 int rereads = 0;
517 u32 v;
518
519 I915_WRITE(DC_STATE_EN, state);
520
521 /* It has been observed that disabling the dc6 state sometimes
522 * doesn't stick and dmc keeps returning old value. Make sure
523 * the write really sticks enough times and also force rewrite until
524 * we are confident that state is exactly what we want.
525 */
526 do {
527 v = I915_READ(DC_STATE_EN);
528
529 if (v != state) {
530 I915_WRITE(DC_STATE_EN, state);
531 rewrites++;
532 rereads = 0;
533 } else if (rereads++ > 5) {
534 break;
535 }
536
537 } while (rewrites < 100);
538
539 if (v != state)
540 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
541 state, v);
542
543 /* Most of the times we need one retry, avoid spam */
544 if (rewrites > 1)
545 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
546 state, rewrites);
547}
548
da2f41d1 549static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
664326f8 550{
da2f41d1 551 u32 mask;
664326f8 552
13ae3a0d 553 mask = DC_STATE_EN_UPTO_DC5;
cc3f90f0 554 if (IS_GEN9_LP(dev_priv))
13ae3a0d
ID		 555 mask |= DC_STATE_EN_DC9;
556 else
557 mask |= DC_STATE_EN_UPTO_DC6;
664326f8 558
da2f41d1
ID		 559 return mask;
560}
561
562void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
563{
564 u32 val;
565
566 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
567
568 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
569 dev_priv->csr.dc_state, val);
570 dev_priv->csr.dc_state = val;
571}
572
13e1592f
ID		 573/**
574 * gen9_set_dc_state - set target display C power state
575 * @dev_priv: i915 device instance
576 * @state: target DC power state
577 * - DC_STATE_DISABLE
578 * - DC_STATE_EN_UPTO_DC5
579 * - DC_STATE_EN_UPTO_DC6
580 * - DC_STATE_EN_DC9
581 *
582 * Signal to DMC firmware/HW the target DC power state passed in @state.
583 * DMC/HW can turn off individual display clocks and power rails when entering
584 * a deeper DC power state (higher in number) and turns these back when exiting
585 * that state to a shallower power state (lower in number). The HW will decide
586 * when to actually enter a given state on an on-demand basis, for instance
587 * depending on the active state of display pipes. The state of display
588 * registers backed by affected power rails are saved/restored as needed.
589 *
590 * Based on the above enabling a deeper DC power state is asynchronous wrt.
591 * enabling it. Disabling a deeper power state is synchronous: for instance
592 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
593 * back on and register state is restored. This is guaranteed by the MMIO write
594 * to DC_STATE_EN blocking until the state is restored.
595 */
da2f41d1
ID		 596static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
597{
598 uint32_t val;
599 uint32_t mask;
600
a37baf3b
ID		 601 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
602 state &= dev_priv->csr.allowed_dc_mask;
443646c7 603
664326f8 604 val = I915_READ(DC_STATE_EN);
da2f41d1 605 mask = gen9_dc_mask(dev_priv);
13ae3a0d
ID		 606 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
607 val & mask, state);
832dba88
PJ		 608
609 /* Check if DMC is ignoring our DC state requests */
610 if ((val & mask) != dev_priv->csr.dc_state)
611 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
612 dev_priv->csr.dc_state, val & mask);
613
13ae3a0d
ID		 614 val &= ~mask;
615 val |= state;
779cb5d3
MK		 616
617 gen9_write_dc_state(dev_priv, val);
832dba88
PJ		 618
619 dev_priv->csr.dc_state = val & mask;
664326f8
SK		 620}
621
13ae3a0d 622void bxt_enable_dc9(struct drm_i915_private *dev_priv)
664326f8 623{
13ae3a0d
ID		 624 assert_can_enable_dc9(dev_priv);
625
626 DRM_DEBUG_KMS("Enabling DC9\n");
664326f8 627
78597996 628 intel_power_sequencer_reset(dev_priv);
13ae3a0d
ID		 629 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
630}
631
632void bxt_disable_dc9(struct drm_i915_private *dev_priv)
633{
664326f8
SK		 634 assert_can_disable_dc9(dev_priv);
635
636 DRM_DEBUG_KMS("Disabling DC9\n");
637
13ae3a0d 638 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
8090ba8c
ID		 639
640 intel_pps_unlock_regs_wa(dev_priv);
664326f8
SK		 641}
642
af5fead2
SV		 643static void assert_csr_loaded(struct drm_i915_private *dev_priv)
644{
645 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
646 "CSR program storage start is NULL\n");
647 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
648 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
649}
650
f7480b2f
PZ		 651static struct i915_power_well *
652lookup_power_well(struct drm_i915_private *dev_priv,
653 enum i915_power_well_id power_well_id)
654{
655 struct i915_power_well *power_well;
656
657 for_each_power_well(dev_priv, power_well)
658 if (power_well->desc->id == power_well_id)
659 return power_well;
660
661 /*
662 * It's not feasible to add error checking code to the callers since
663 * this condition really shouldn't happen and it doesn't even make sense
664 * to abort things like display initialization sequences. Just return
665 * the first power well and hope the WARN gets reported so we can fix
666 * our driver.
667 */
668 WARN(1, "Power well %d not defined for this platform\n", power_well_id);
669 return &dev_priv->power_domains.power_wells[0];
670}
671
5aefb239 672static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
dc174300 673{
5aefb239
SS		 674 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
675 SKL_DISP_PW_2);
676
6ff8ab0d 677 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
5aefb239 678
6ff8ab0d
JB		 679 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
680 "DC5 already programmed to be enabled.\n");
c9b8846a 681 assert_rpm_wakelock_held(dev_priv);
5aefb239
SS		 682
683 assert_csr_loaded(dev_priv);
684}
685
f62c79b3 686void gen9_enable_dc5(struct drm_i915_private *dev_priv)
5aefb239 687{
5aefb239 688 assert_can_enable_dc5(dev_priv);
6b457d31
SK		 689
690 DRM_DEBUG_KMS("Enabling DC5\n");
691
53421c2f
LDM		 692 /* Wa Display #1183: skl,kbl,cfl */
693 if (IS_GEN9_BC(dev_priv))
694 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
695 SKL_SELECT_ALTERNATE_DC_EXIT);
696
13ae3a0d 697 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
dc174300
SS		 698}
699
93c7cb6c 700static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
f75a1985 701{
6ff8ab0d
JB		 702 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
703 "Backlight is not disabled.\n");
704 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
705 "DC6 already programmed to be enabled.\n");
93c7cb6c
SS		 706
707 assert_csr_loaded(dev_priv);
708}
709
c4c25259 710static void skl_enable_dc6(struct drm_i915_private *dev_priv)
93c7cb6c 711{
93c7cb6c 712 assert_can_enable_dc6(dev_priv);
74b4f371
SK		 713
714 DRM_DEBUG_KMS("Enabling DC6\n");
715
b49be662
ID		 716 /* Wa Display #1183: skl,kbl,cfl */
717 if (IS_GEN9_BC(dev_priv))
718 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
719 SKL_SELECT_ALTERNATE_DC_EXIT);
13ae3a0d 720
b49be662 721 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
f75a1985
SS		 722}
723
9c065a7d
SV		 724static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
725 struct i915_power_well *power_well)
726{
75e39688
ID		 727 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
728 int pw_idx = power_well->desc->hsw.idx;
729 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
730 u32 bios_req = I915_READ(regs->bios);
1af474fe 731
16e84914 732 /* Take over the request bit if set by BIOS. */
1af474fe 733 if (bios_req & mask) {
75e39688 734 u32 drv_req = I915_READ(regs->driver);
1af474fe
ID		 735
736 if (!(drv_req & mask))
75e39688
ID		 737 I915_WRITE(regs->driver, drv_req | mask);
738 I915_WRITE(regs->bios, bios_req & ~mask);
16e84914 739 }
9c065a7d
SV		 740}
741
9c8d0b8e
ID		 742static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
743 struct i915_power_well *power_well)
744{
f28ec6f4 745 bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
9c8d0b8e
ID		 746}
747
748static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
749 struct i915_power_well *power_well)
750{
f28ec6f4 751 bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
9c8d0b8e
ID		 752}
753
754static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
755 struct i915_power_well *power_well)
756{
f28ec6f4 757 return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
9c8d0b8e
ID		 758}
759
9c8d0b8e
ID		 760static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
761{
762 struct i915_power_well *power_well;
763
2183b499 764 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
9c8d0b8e 765 if (power_well->count > 0)
f28ec6f4 766 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
9c8d0b8e 767
d9fcdc8d 768 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
9c8d0b8e 769 if (power_well->count > 0)
f28ec6f4 770 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
0a116ce8
ACO		 771
772 if (IS_GEMINILAKE(dev_priv)) {
2183b499
ID		 773 power_well = lookup_power_well(dev_priv,
774 GLK_DISP_PW_DPIO_CMN_C);
0a116ce8 775 if (power_well->count > 0)
f28ec6f4
ID		 776 bxt_ddi_phy_verify_state(dev_priv,
777 power_well->desc->bxt.phy);
0a116ce8 778 }
9c8d0b8e
ID		 779}
780
9f836f90
PJ		 781static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
782 struct i915_power_well *power_well)
783{
784 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
785}
786
18a8067c
VS		 787static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
788{
789 u32 tmp = I915_READ(DBUF_CTL);
790
791 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
792 (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
793 "Unexpected DBuf power power state (0x%08x)\n", tmp);
794}
795
9f836f90
PJ		 796static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
797 struct i915_power_well *power_well)
798{
49cd97a3
VS		 799 struct intel_cdclk_state cdclk_state = {};
800
5b773eb4 801 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
adc7f04b 802
49cd97a3 803 dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
64600bd5
VS		 804 /* Can't read out voltage_level so can't use intel_cdclk_changed() */
805 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
342be926 806
18a8067c
VS		 807 gen9_assert_dbuf_enabled(dev_priv);
808
cc3f90f0 809 if (IS_GEN9_LP(dev_priv))
9c8d0b8e 810 bxt_verify_ddi_phy_power_wells(dev_priv);
9f836f90
PJ		 811}
812
813static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
814 struct i915_power_well *power_well)
815{
f74ed08d
ID		 816 if (!dev_priv->csr.dmc_payload)
817 return;
818
a37baf3b 819 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
9f836f90 820 skl_enable_dc6(dev_priv);
a37baf3b 821 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
9f836f90
PJ		 822 gen9_enable_dc5(dev_priv);
823}
824
3c1b38e6
ID		 825static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
826 struct i915_power_well *power_well)
9f836f90 827{
9f836f90
PJ		 828}
829
9c065a7d
SV		 830static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
831 struct i915_power_well *power_well)
832{
833}
834
835static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
836 struct i915_power_well *power_well)
837{
838 return true;
839}
840
2ee0da16
VS		 841static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
842 struct i915_power_well *power_well)
843{
844 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
845 i830_enable_pipe(dev_priv, PIPE_A);
846 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
847 i830_enable_pipe(dev_priv, PIPE_B);
848}
849
850static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
851 struct i915_power_well *power_well)
852{
853 i830_disable_pipe(dev_priv, PIPE_B);
854 i830_disable_pipe(dev_priv, PIPE_A);
855}
856
857static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
858 struct i915_power_well *power_well)
859{
860 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
861 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
862}
863
864static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
865 struct i915_power_well *power_well)
866{
867 if (power_well->count > 0)
868 i830_pipes_power_well_enable(dev_priv, power_well);
869 else
870 i830_pipes_power_well_disable(dev_priv, power_well);
871}
872
9c065a7d
SV		 873static void vlv_set_power_well(struct drm_i915_private *dev_priv,
874 struct i915_power_well *power_well, bool enable)
875{
d13dd05a 876 int pw_idx = power_well->desc->vlv.idx;
9c065a7d
SV		 877 u32 mask;
878 u32 state;
879 u32 ctrl;
880
d13dd05a
ID		 881 mask = PUNIT_PWRGT_MASK(pw_idx);
882 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
883 PUNIT_PWRGT_PWR_GATE(pw_idx);
9c065a7d 884
9f817501 885 mutex_lock(&dev_priv->pcu_lock);
9c065a7d
SV		 886
887#define COND \
888 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
889
890 if (COND)
891 goto out;
892
893 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
894 ctrl &= ~mask;
895 ctrl |= state;
896 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
897
898 if (wait_for(COND, 100))
7e35ab88 899 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
SV		 900 state,
901 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
902
903#undef COND
904
905out:
9f817501 906 mutex_unlock(&dev_priv->pcu_lock);
9c065a7d
SV		 907}
908
9c065a7d
SV		 909static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
910 struct i915_power_well *power_well)
911{
912 vlv_set_power_well(dev_priv, power_well, true);
913}
914
915static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
916 struct i915_power_well *power_well)
917{
918 vlv_set_power_well(dev_priv, power_well, false);
919}
920
921static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
922 struct i915_power_well *power_well)
923{
d13dd05a 924 int pw_idx = power_well->desc->vlv.idx;
9c065a7d
SV		 925 bool enabled = false;
926 u32 mask;
927 u32 state;
928 u32 ctrl;
929
d13dd05a
ID		 930 mask = PUNIT_PWRGT_MASK(pw_idx);
931 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
9c065a7d 932
9f817501 933 mutex_lock(&dev_priv->pcu_lock);
9c065a7d
SV		 934
935 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
936 /*
937 * We only ever set the power-on and power-gate states, anything
938 * else is unexpected.
939 */
d13dd05a
ID		 940 WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
941 state != PUNIT_PWRGT_PWR_GATE(pw_idx));
9c065a7d
SV		 942 if (state == ctrl)
943 enabled = true;
944
945 /*
946 * A transient state at this point would mean some unexpected party
947 * is poking at the power controls too.
948 */
949 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
950 WARN_ON(ctrl != state);
951
9f817501 952 mutex_unlock(&dev_priv->pcu_lock);
9c065a7d
SV		 953
954 return enabled;
955}
956
766078df
VS		 957static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
958{
721d4845
HG		 959 u32 val;
960
961 /*
962 * On driver load, a pipe may be active and driving a DSI display.
963 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
964 * (and never recovering) in this case. intel_dsi_post_disable() will
965 * clear it when we turn off the display.
966 */
967 val = I915_READ(DSPCLK_GATE_D);
968 val &= DPOUNIT_CLOCK_GATE_DISABLE;
969 val |= VRHUNIT_CLOCK_GATE_DISABLE;
970 I915_WRITE(DSPCLK_GATE_D, val);
766078df
VS		 971
972 /*
973 * Disable trickle feed and enable pnd deadline calculation
974 */
975 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
976 I915_WRITE(CBR1_VLV, 0);
19ab4ed3
VS		 977
978 WARN_ON(dev_priv->rawclk_freq == 0);
979
980 I915_WRITE(RAWCLK_FREQ_VLV,
981 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
766078df
VS		 982}
983
2be7d540 984static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
9c065a7d 985{
9504a892 986 struct intel_encoder *encoder;
5a8fbb7d
VS		 987 enum pipe pipe;
988
989 /*
990 * Enable the CRI clock source so we can get at the
991 * display and the reference clock for VGA
992 * hotplug / manual detection. Supposedly DSI also
993 * needs the ref clock up and running.
994 *
995 * CHV DPLL B/C have some issues if VGA mode is enabled.
996 */
801388cb 997 for_each_pipe(dev_priv, pipe) {
5a8fbb7d
VS		 998 u32 val = I915_READ(DPLL(pipe));
999
1000 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1001 if (pipe != PIPE_A)
1002 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1003
1004 I915_WRITE(DPLL(pipe), val);
1005 }
9c065a7d 1006
766078df
VS		 1007 vlv_init_display_clock_gating(dev_priv);
1008
9c065a7d
SV		 1009 spin_lock_irq(&dev_priv->irq_lock);
1010 valleyview_enable_display_irqs(dev_priv);
1011 spin_unlock_irq(&dev_priv->irq_lock);
1012
1013 /*
1014 * During driver initialization/resume we can avoid restoring the
1015 * part of the HW/SW state that will be inited anyway explicitly.
1016 */
1017 if (dev_priv->power_domains.initializing)
1018 return;
1019
b963291c 1020 intel_hpd_init(dev_priv);
9c065a7d 1021
9504a892
L		 1022 /* Re-enable the ADPA, if we have one */
1023 for_each_intel_encoder(&dev_priv->drm, encoder) {
1024 if (encoder->type == INTEL_OUTPUT_ANALOG)
1025 intel_crt_reset(&encoder->base);
1026 }
1027
29b74b7f 1028 i915_redisable_vga_power_on(dev_priv);
8090ba8c
ID		 1029
1030 intel_pps_unlock_regs_wa(dev_priv);
9c065a7d
SV		 1031}
1032
2be7d540
VS		 1033static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1034{
1035 spin_lock_irq(&dev_priv->irq_lock);
1036 valleyview_disable_display_irqs(dev_priv);
1037 spin_unlock_irq(&dev_priv->irq_lock);
1038
2230fde8 1039 /* make sure we're done processing display irqs */
91c8a326 1040 synchronize_irq(dev_priv->drm.irq);
2230fde8 1041
78597996 1042 intel_power_sequencer_reset(dev_priv);
19625e85 1043
b64b5409
L		 1044 /* Prevent us from re-enabling polling on accident in late suspend */
1045 if (!dev_priv->drm.dev->power.is_suspended)
1046 intel_hpd_poll_init(dev_priv);
2be7d540
VS		 1047}
1048
1049static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1050 struct i915_power_well *power_well)
1051{
2be7d540
VS		 1052 vlv_set_power_well(dev_priv, power_well, true);
1053
1054 vlv_display_power_well_init(dev_priv);
1055}
1056
9c065a7d
SV		 1057static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1058 struct i915_power_well *power_well)
1059{
2be7d540 1060 vlv_display_power_well_deinit(dev_priv);
9c065a7d
SV		 1061
1062 vlv_set_power_well(dev_priv, power_well, false);
9c065a7d
SV		 1063}
1064
1065static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1066 struct i915_power_well *power_well)
1067{
5a8fbb7d 1068 /* since ref/cri clock was enabled */
9c065a7d
SV		 1069 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1070
1071 vlv_set_power_well(dev_priv, power_well, true);
1072
1073 /*
1074 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1075 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1076 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1077 * b. The other bits such as sfr settings / modesel may all
1078 * be set to 0.
1079 *
1080 * This should only be done on init and resume from S3 with
1081 * both PLLs disabled, or we risk losing DPIO and PLL
1082 * synchronization.
1083 */
1084 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1085}
1086
1087static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1088 struct i915_power_well *power_well)
1089{
1090 enum pipe pipe;
1091
9c065a7d
SV		 1092 for_each_pipe(dev_priv, pipe)
1093 assert_pll_disabled(dev_priv, pipe);
1094
1095 /* Assert common reset */
1096 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1097
1098 vlv_set_power_well(dev_priv, power_well, false);
1099}
1100
d8fc70b7 1101#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
30142273 1102
30142273
VS		 1103#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1104
1105static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1106{
1107 struct i915_power_well *cmn_bc =
2183b499 1108 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
30142273 1109 struct i915_power_well *cmn_d =
2183b499 1110 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
30142273
VS		 1111 u32 phy_control = dev_priv->chv_phy_control;
1112 u32 phy_status = 0;
3be60de9 1113 u32 phy_status_mask = 0xffffffff;
30142273 1114
3be60de9
VS		 1115 /*
1116 * The BIOS can leave the PHY is some weird state
1117 * where it doesn't fully power down some parts.
1118 * Disable the asserts until the PHY has been fully
1119 * reset (ie. the power well has been disabled at
1120 * least once).
1121 */
1122 if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1123 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1124 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1125 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1126 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1127 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1128 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1129
1130 if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1131 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1132 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1133 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1134
f28ec6f4 1135 if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
30142273
VS		 1136 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1137
1138 /* this assumes override is only used to enable lanes */
1139 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1140 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1141
1142 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1143 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1144
1145 /* CL1 is on whenever anything is on in either channel */
1146 if (BITS_SET(phy_control,
1147 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1148 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1149 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1150
1151 /*
1152 * The DPLLB check accounts for the pipe B + port A usage
1153 * with CL2 powered up but all the lanes in the second channel
1154 * powered down.
1155 */
1156 if (BITS_SET(phy_control,
1157 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1158 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1159 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1160
1161 if (BITS_SET(phy_control,
1162 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1163 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1164 if (BITS_SET(phy_control,
1165 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1166 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1167
1168 if (BITS_SET(phy_control,
1169 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1170 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1171 if (BITS_SET(phy_control,
1172 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1173 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1174 }
1175
f28ec6f4 1176 if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
30142273
VS		 1177 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1178
1179 /* this assumes override is only used to enable lanes */
1180 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1181 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1182
1183 if (BITS_SET(phy_control,
1184 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1185 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1186
1187 if (BITS_SET(phy_control,
1188 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1189 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1190 if (BITS_SET(phy_control,
1191 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1192 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1193 }
1194
3be60de9
VS		 1195 phy_status &= phy_status_mask;
1196
30142273
VS		 1197 /*
1198 * The PHY may be busy with some initial calibration and whatnot,
1199 * so the power state can take a while to actually change.
1200 */
919fcd51
CW		 1201 if (intel_wait_for_register(dev_priv,
1202 DISPLAY_PHY_STATUS,
1203 phy_status_mask,
1204 phy_status,
1205 10))
1206 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1207 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1208 phy_status, dev_priv->chv_phy_control);
30142273
VS		 1209}
1210
1211#undef BITS_SET
1212
9c065a7d
SV		 1213static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1214 struct i915_power_well *power_well)
1215{
1216 enum dpio_phy phy;
e0fce78f
VS		 1217 enum pipe pipe;
1218 uint32_t tmp;
9c065a7d 1219
2183b499
ID		 1220 WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1221 power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
9c065a7d 1222
2183b499 1223 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
e0fce78f 1224 pipe = PIPE_A;
9c065a7d 1225 phy = DPIO_PHY0;
e0fce78f
VS		 1226 } else {
1227 pipe = PIPE_C;
9c065a7d 1228 phy = DPIO_PHY1;
e0fce78f 1229 }
5a8fbb7d
VS		 1230
1231 /* since ref/cri clock was enabled */
9c065a7d
SV		 1232 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1233 vlv_set_power_well(dev_priv, power_well, true);
1234
1235 /* Poll for phypwrgood signal */
ffebb83b
CW		 1236 if (intel_wait_for_register(dev_priv,
1237 DISPLAY_PHY_STATUS,
1238 PHY_POWERGOOD(phy),
1239 PHY_POWERGOOD(phy),
1240 1))
9c065a7d
SV		 1241 DRM_ERROR("Display PHY %d is not power up\n", phy);
1242
e0fce78f
VS		 1243 mutex_lock(&dev_priv->sb_lock);
1244
1245 /* Enable dynamic power down */
1246 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
ee279218
VS		 1247 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1248 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
e0fce78f
VS		 1249 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1250
2183b499 1251 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
e0fce78f
VS		 1252 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1253 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1254 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
3e288786
VS		 1255 } else {
1256 /*
1257 * Force the non-existing CL2 off. BXT does this
1258 * too, so maybe it saves some power even though
1259 * CL2 doesn't exist?
1260 */
1261 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1262 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1263 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
e0fce78f
VS		 1264 }
1265
1266 mutex_unlock(&dev_priv->sb_lock);
1267
70722468
VS		 1268 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1269 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
e0fce78f
VS		 1270
1271 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1272 phy, dev_priv->chv_phy_control);
30142273
VS		 1273
1274 assert_chv_phy_status(dev_priv);
9c065a7d
SV		 1275}
1276
1277static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1278 struct i915_power_well *power_well)
1279{
1280 enum dpio_phy phy;
1281
2183b499
ID		 1282 WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1283 power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
9c065a7d 1284
2183b499 1285 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
9c065a7d
SV		 1286 phy = DPIO_PHY0;
1287 assert_pll_disabled(dev_priv, PIPE_A);
1288 assert_pll_disabled(dev_priv, PIPE_B);
1289 } else {
1290 phy = DPIO_PHY1;
1291 assert_pll_disabled(dev_priv, PIPE_C);
1292 }
1293
70722468
VS		 1294 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1295 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
9c065a7d
SV		 1296
1297 vlv_set_power_well(dev_priv, power_well, false);
e0fce78f
VS		 1298
1299 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1300 phy, dev_priv->chv_phy_control);
30142273 1301
3be60de9
VS		 1302 /* PHY is fully reset now, so we can enable the PHY state asserts */
1303 dev_priv->chv_phy_assert[phy] = true;
1304
30142273 1305 assert_chv_phy_status(dev_priv);
e0fce78f
VS		 1306}
1307
6669e39f
VS		 1308static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1309 enum dpio_channel ch, bool override, unsigned int mask)
1310{
1311 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1312 u32 reg, val, expected, actual;
1313
3be60de9
VS		 1314 /*
1315 * The BIOS can leave the PHY is some weird state
1316 * where it doesn't fully power down some parts.
1317 * Disable the asserts until the PHY has been fully
1318 * reset (ie. the power well has been disabled at
1319 * least once).
1320 */
1321 if (!dev_priv->chv_phy_assert[phy])
1322 return;
1323
6669e39f
VS		 1324 if (ch == DPIO_CH0)
1325 reg = _CHV_CMN_DW0_CH0;
1326 else
1327 reg = _CHV_CMN_DW6_CH1;
1328
1329 mutex_lock(&dev_priv->sb_lock);
1330 val = vlv_dpio_read(dev_priv, pipe, reg);
1331 mutex_unlock(&dev_priv->sb_lock);
1332
1333 /*
1334 * This assumes !override is only used when the port is disabled.
1335 * All lanes should power down even without the override when
1336 * the port is disabled.
1337 */
1338 if (!override || mask == 0xf) {
1339 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1340 /*
1341 * If CH1 common lane is not active anymore
1342 * (eg. for pipe B DPLL) the entire channel will
1343 * shut down, which causes the common lane registers
1344 * to read as 0. That means we can't actually check
1345 * the lane power down status bits, but as the entire
1346 * register reads as 0 it's a good indication that the
1347 * channel is indeed entirely powered down.
1348 */
1349 if (ch == DPIO_CH1 && val == 0)
1350 expected = 0;
1351 } else if (mask != 0x0) {
1352 expected = DPIO_ANYDL_POWERDOWN;
1353 } else {
1354 expected = 0;
1355 }
1356
1357 if (ch == DPIO_CH0)
1358 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1359 else
1360 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1361 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1362
1363 WARN(actual != expected,
1364 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1365 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1366 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1367 reg, val);
1368}
1369
b0b33846
VS		 1370bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1371 enum dpio_channel ch, bool override)
1372{
1373 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1374 bool was_override;
1375
1376 mutex_lock(&power_domains->lock);
1377
1378 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1379
1380 if (override == was_override)
1381 goto out;
1382
1383 if (override)
1384 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1385 else
1386 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1387
1388 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1389
1390 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1391 phy, ch, dev_priv->chv_phy_control);
1392
30142273
VS		 1393 assert_chv_phy_status(dev_priv);
1394
b0b33846
VS		 1395out:
1396 mutex_unlock(&power_domains->lock);
1397
1398 return was_override;
1399}
1400
e0fce78f
VS		 1401void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1402 bool override, unsigned int mask)
1403{
1404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1405 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1406 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1407 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1408
1409 mutex_lock(&power_domains->lock);
1410
1411 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1412 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1413
1414 if (override)
1415 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1416 else
1417 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1418
1419 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1420
1421 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1422 phy, ch, mask, dev_priv->chv_phy_control);
1423
30142273
VS		 1424 assert_chv_phy_status(dev_priv);
1425
6669e39f
VS		 1426 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1427
e0fce78f 1428 mutex_unlock(&power_domains->lock);
9c065a7d
SV		 1429}
1430
1431static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1432 struct i915_power_well *power_well)
1433{
f49193cd 1434 enum pipe pipe = PIPE_A;
9c065a7d
SV		 1435 bool enabled;
1436 u32 state, ctrl;
1437
9f817501 1438 mutex_lock(&dev_priv->pcu_lock);
9c065a7d
SV		 1439
1440 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1441 /*
1442 * We only ever set the power-on and power-gate states, anything
1443 * else is unexpected.
1444 */
1445 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1446 enabled = state == DP_SSS_PWR_ON(pipe);
1447
1448 /*
1449 * A transient state at this point would mean some unexpected party
1450 * is poking at the power controls too.
1451 */
1452 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1453 WARN_ON(ctrl << 16 != state);
1454
9f817501 1455 mutex_unlock(&dev_priv->pcu_lock);
9c065a7d
SV		 1456
1457 return enabled;
1458}
1459
1460static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1461 struct i915_power_well *power_well,
1462 bool enable)
1463{
f49193cd 1464 enum pipe pipe = PIPE_A;
9c065a7d
SV		 1465 u32 state;
1466 u32 ctrl;
1467
1468 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1469
9f817501 1470 mutex_lock(&dev_priv->pcu_lock);
9c065a7d
SV		 1471
1472#define COND \
1473 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1474
1475 if (COND)
1476 goto out;
1477
1478 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1479 ctrl &= ~DP_SSC_MASK(pipe);
1480 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1481 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1482
1483 if (wait_for(COND, 100))
7e35ab88 1484 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
SV		 1485 state,
1486 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1487
1488#undef COND
1489
1490out:
9f817501 1491 mutex_unlock(&dev_priv->pcu_lock);
9c065a7d
SV		 1492}
1493
9c065a7d
SV		 1494static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1495 struct i915_power_well *power_well)
1496{
9c065a7d 1497 chv_set_pipe_power_well(dev_priv, power_well, true);
afd6275d 1498
2be7d540 1499 vlv_display_power_well_init(dev_priv);
9c065a7d
SV		 1500}
1501
1502static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1503 struct i915_power_well *power_well)
1504{
2be7d540 1505 vlv_display_power_well_deinit(dev_priv);
afd6275d 1506
9c065a7d
SV		 1507 chv_set_pipe_power_well(dev_priv, power_well, false);
1508}
1509
09731280
ID		 1510static void
1511__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1512 enum intel_display_power_domain domain)
1513{
1514 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1515 struct i915_power_well *power_well;
09731280 1516
75ccb2ec 1517 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
b409ca95 1518 intel_power_well_get(dev_priv, power_well);
09731280
ID		 1519
1520 power_domains->domain_use_count[domain]++;
1521}
1522
e4e7684f
SV		 1523/**
1524 * intel_display_power_get - grab a power domain reference
1525 * @dev_priv: i915 device instance
1526 * @domain: power domain to reference
1527 *
1528 * This function grabs a power domain reference for @domain and ensures that the
1529 * power domain and all its parents are powered up. Therefore users should only
1530 * grab a reference to the innermost power domain they need.
1531 *
1532 * Any power domain reference obtained by this function must have a symmetric
1533 * call to intel_display_power_put() to release the reference again.
1534 */
9c065a7d
SV		 1535void intel_display_power_get(struct drm_i915_private *dev_priv,
1536 enum intel_display_power_domain domain)
1537{
09731280 1538 struct i915_power_domains *power_domains = &dev_priv->power_domains;
9c065a7d
SV		 1539
1540 intel_runtime_pm_get(dev_priv);
1541
09731280
ID		 1542 mutex_lock(&power_domains->lock);
1543
1544 __intel_display_power_get_domain(dev_priv, domain);
1545
1546 mutex_unlock(&power_domains->lock);
1547}
1548
1549/**
1550 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1551 * @dev_priv: i915 device instance
1552 * @domain: power domain to reference
1553 *
1554 * This function grabs a power domain reference for @domain and ensures that the
1555 * power domain and all its parents are powered up. Therefore users should only
1556 * grab a reference to the innermost power domain they need.
1557 *
1558 * Any power domain reference obtained by this function must have a symmetric
1559 * call to intel_display_power_put() to release the reference again.
1560 */
1561bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1562 enum intel_display_power_domain domain)
1563{
1564 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1565 bool is_enabled;
1566
1567 if (!intel_runtime_pm_get_if_in_use(dev_priv))
1568 return false;
9c065a7d
SV		 1569
1570 mutex_lock(&power_domains->lock);
1571
09731280
ID		 1572 if (__intel_display_power_is_enabled(dev_priv, domain)) {
1573 __intel_display_power_get_domain(dev_priv, domain);
1574 is_enabled = true;
1575 } else {
1576 is_enabled = false;
9c065a7d
SV		 1577 }
1578
9c065a7d 1579 mutex_unlock(&power_domains->lock);
09731280
ID		 1580
1581 if (!is_enabled)
1582 intel_runtime_pm_put(dev_priv);
1583
1584 return is_enabled;
9c065a7d
SV		 1585}
1586
e4e7684f
SV		 1587/**
1588 * intel_display_power_put - release a power domain reference
1589 * @dev_priv: i915 device instance
1590 * @domain: power domain to reference
1591 *
1592 * This function drops the power domain reference obtained by
1593 * intel_display_power_get() and might power down the corresponding hardware
1594 * block right away if this is the last reference.
1595 */
9c065a7d
SV		 1596void intel_display_power_put(struct drm_i915_private *dev_priv,
1597 enum intel_display_power_domain domain)
1598{
1599 struct i915_power_domains *power_domains;
1600 struct i915_power_well *power_well;
9c065a7d
SV		 1601
1602 power_domains = &dev_priv->power_domains;
1603
1604 mutex_lock(&power_domains->lock);
1605
11c86db8
DS		 1606 WARN(!power_domains->domain_use_count[domain],
1607 "Use count on domain %s is already zero\n",
1608 intel_display_power_domain_str(domain));
9c065a7d
SV		 1609 power_domains->domain_use_count[domain]--;
1610
75ccb2ec 1611 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
b409ca95 1612 intel_power_well_put(dev_priv, power_well);
9c065a7d
SV		 1613
1614 mutex_unlock(&power_domains->lock);
1615
1616 intel_runtime_pm_put(dev_priv);
1617}
1618
965a79ad
ID		 1619#define I830_PIPES_POWER_DOMAINS ( \
1620 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
1621 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1622 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1623 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1624 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1625 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
d8fc70b7 1626 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d 1627
465ac0c6 1628#define VLV_DISPLAY_POWER_DOMAINS ( \
d8fc70b7
ACO		 1629 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
1630 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1631 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1632 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1633 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1634 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1635 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1636 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1637 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
1638 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
1639 BIT_ULL(POWER_DOMAIN_VGA) | \
1640 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1641 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1642 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1643 BIT_ULL(POWER_DOMAIN_GMBUS) | \
1644 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d
SV		 1645
1646#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
d8fc70b7
ACO		 1647 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1648 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1649 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
1650 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1651 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1652 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d
SV		 1653
1654#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
d8fc70b7
ACO		 1655 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1656 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1657 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d
SV		 1658
1659#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
d8fc70b7
ACO		 1660 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1661 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1662 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d
SV		 1663
1664#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
d8fc70b7
ACO		 1665 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1666 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1667 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d
SV		 1668
1669#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
d8fc70b7
ACO		 1670 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1671 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1672 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d 1673
465ac0c6 1674#define CHV_DISPLAY_POWER_DOMAINS ( \
d8fc70b7
ACO		 1675 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
1676 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1677 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1678 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1679 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1680 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1681 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1682 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1683 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1684 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1685 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1686 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1687 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
1688 BIT_ULL(POWER_DOMAIN_VGA) | \
1689 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1690 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1691 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1692 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1693 BIT_ULL(POWER_DOMAIN_GMBUS) | \
1694 BIT_ULL(POWER_DOMAIN_INIT))
465ac0c6 1695
9c065a7d 1696#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
d8fc70b7
ACO		 1697 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1698 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1699 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1700 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1701 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d
SV		 1702
1703#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
d8fc70b7
ACO		 1704 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1705 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1706 BIT_ULL(POWER_DOMAIN_INIT))
9c065a7d 1707
965a79ad
ID		 1708#define HSW_DISPLAY_POWER_DOMAINS ( \
1709 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1710 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1711 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1712 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1713 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1714 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1715 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1716 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1717 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1718 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1719 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1720 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1721 BIT_ULL(POWER_DOMAIN_VGA) | \
1722 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1723 BIT_ULL(POWER_DOMAIN_INIT))
1724
1725#define BDW_DISPLAY_POWER_DOMAINS ( \
1726 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1727 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1728 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1729 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1730 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1731 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1732 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1733 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1734 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1735 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1736 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1737 BIT_ULL(POWER_DOMAIN_VGA) | \
1738 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1739 BIT_ULL(POWER_DOMAIN_INIT))
1740
1741#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1742 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1743 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1744 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1745 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1746 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1747 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1748 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1749 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1750 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1751 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1752 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
1753 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1754 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1755 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1756 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1757 BIT_ULL(POWER_DOMAIN_VGA) | \
1758 BIT_ULL(POWER_DOMAIN_INIT))
1759#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
1760 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
1761 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
1762 BIT_ULL(POWER_DOMAIN_INIT))
1763#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
1764 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
1765 BIT_ULL(POWER_DOMAIN_INIT))
1766#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
1767 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
1768 BIT_ULL(POWER_DOMAIN_INIT))
1769#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
1770 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
1771 BIT_ULL(POWER_DOMAIN_INIT))
1772#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1773 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
b6876374 1774 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
965a79ad
ID		 1775 BIT_ULL(POWER_DOMAIN_MODESET) | \
1776 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1777 BIT_ULL(POWER_DOMAIN_INIT))
1778
1779#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1780 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1781 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1782 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1783 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1784 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1785 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1786 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1787 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1788 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1789 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1790 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1791 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1792 BIT_ULL(POWER_DOMAIN_VGA) | \
965a79ad
ID		 1793 BIT_ULL(POWER_DOMAIN_INIT))
1794#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1795 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
b6876374 1796 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
965a79ad
ID		 1797 BIT_ULL(POWER_DOMAIN_MODESET) | \
1798 BIT_ULL(POWER_DOMAIN_AUX_A) | \
54c105d6 1799 BIT_ULL(POWER_DOMAIN_GMBUS) | \
965a79ad
ID		 1800 BIT_ULL(POWER_DOMAIN_INIT))
1801#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
1802 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1803 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1804 BIT_ULL(POWER_DOMAIN_INIT))
1805#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
1806 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1807 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1808 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1809 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1810 BIT_ULL(POWER_DOMAIN_INIT))
1811
1812#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1813 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1814 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1815 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1816 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1817 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1818 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1819 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1820 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1821 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1822 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1823 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1824 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1825 BIT_ULL(POWER_DOMAIN_VGA) | \
1826 BIT_ULL(POWER_DOMAIN_INIT))
1827#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
1828 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
1829#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
1830 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
1831#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
1832 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
1833#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
1834 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1835 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1836 BIT_ULL(POWER_DOMAIN_INIT))
1837#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
1838 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1839 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1840 BIT_ULL(POWER_DOMAIN_INIT))
1841#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
1842 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1843 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1844 BIT_ULL(POWER_DOMAIN_INIT))
1845#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
1846 BIT_ULL(POWER_DOMAIN_AUX_A) | \
52528055 1847 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
965a79ad
ID		 1848 BIT_ULL(POWER_DOMAIN_INIT))
1849#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
1850 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1851 BIT_ULL(POWER_DOMAIN_INIT))
1852#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
1853 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1854 BIT_ULL(POWER_DOMAIN_INIT))
1855#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1856 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
b6876374 1857 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
965a79ad
ID		 1858 BIT_ULL(POWER_DOMAIN_MODESET) | \
1859 BIT_ULL(POWER_DOMAIN_AUX_A) | \
156961ae 1860 BIT_ULL(POWER_DOMAIN_GMBUS) | \
965a79ad
ID		 1861 BIT_ULL(POWER_DOMAIN_INIT))
1862
1863#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1864 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1865 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1866 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1867 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1868 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1869 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1870 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1871 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1872 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1873 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
9787e835 1874 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
965a79ad
ID		 1875 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1876 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1877 BIT_ULL(POWER_DOMAIN_AUX_D) | \
a324fcac 1878 BIT_ULL(POWER_DOMAIN_AUX_F) | \
965a79ad
ID		 1879 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1880 BIT_ULL(POWER_DOMAIN_VGA) | \
1881 BIT_ULL(POWER_DOMAIN_INIT))
1882#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
1883 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
965a79ad
ID		 1884 BIT_ULL(POWER_DOMAIN_INIT))
1885#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
1886 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
1887 BIT_ULL(POWER_DOMAIN_INIT))
1888#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
1889 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
1890 BIT_ULL(POWER_DOMAIN_INIT))
1891#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
1892 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
1893 BIT_ULL(POWER_DOMAIN_INIT))
1894#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
1895 BIT_ULL(POWER_DOMAIN_AUX_A) | \
b891d5e4 1896 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
965a79ad
ID		 1897 BIT_ULL(POWER_DOMAIN_INIT))
1898#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
1899 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1900 BIT_ULL(POWER_DOMAIN_INIT))
1901#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
1902 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1903 BIT_ULL(POWER_DOMAIN_INIT))
1904#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
1905 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1906 BIT_ULL(POWER_DOMAIN_INIT))
a324fcac
RV		 1907#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
1908 BIT_ULL(POWER_DOMAIN_AUX_F) | \
1909 BIT_ULL(POWER_DOMAIN_INIT))
9787e835
RV		 1910#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
1911 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
1912 BIT_ULL(POWER_DOMAIN_INIT))
965a79ad
ID		 1913#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1914 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
6e7a3f52 1915 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
965a79ad
ID		 1916 BIT_ULL(POWER_DOMAIN_MODESET) | \
1917 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2ee0da16
VS		 1918 BIT_ULL(POWER_DOMAIN_INIT))
1919
67ca07e7
ID		 1920/*
1921 * ICL PW_0/PG_0 domains (HW/DMC control):
1922 * - PCI
1923 * - clocks except port PLL
1924 * - central power except FBC
1925 * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
1926 * ICL PW_1/PG_1 domains (HW/DMC control):
1927 * - DBUF function
1928 * - PIPE_A and its planes, except VGA
1929 * - transcoder EDP + PSR
1930 * - transcoder DSI
1931 * - DDI_A
1932 * - FBC
1933 */
1934#define ICL_PW_4_POWER_DOMAINS ( \
1935 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1936 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1937 BIT_ULL(POWER_DOMAIN_INIT))
1938 /* VDSC/joining */
1939#define ICL_PW_3_POWER_DOMAINS ( \
1940 ICL_PW_4_POWER_DOMAINS | \
1941 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1942 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1943 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1944 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1945 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1946 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1947 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
1948 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1949 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
1950 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1951 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
1952 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
1953 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
1954 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
1955 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
1956 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1957 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1958 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1959 BIT_ULL(POWER_DOMAIN_AUX_E) | \
1960 BIT_ULL(POWER_DOMAIN_AUX_F) | \
1961 BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
1962 BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
1963 BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
1964 BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
1965 BIT_ULL(POWER_DOMAIN_VGA) | \
1966 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1967 BIT_ULL(POWER_DOMAIN_INIT))
1968 /*
1969 * - transcoder WD
1970 * - KVMR (HW control)
1971 */
1972#define ICL_PW_2_POWER_DOMAINS ( \
1973 ICL_PW_3_POWER_DOMAINS | \
1974 BIT_ULL(POWER_DOMAIN_INIT))
1975 /*
1976 * - eDP/DSI VDSC
1977 * - KVMR (HW control)
1978 */
1979#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1980 ICL_PW_2_POWER_DOMAINS | \
1981 BIT_ULL(POWER_DOMAIN_MODESET) | \
1982 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1983 BIT_ULL(POWER_DOMAIN_INIT))
1984
1985#define ICL_DDI_IO_A_POWER_DOMAINS ( \
1986 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
1987#define ICL_DDI_IO_B_POWER_DOMAINS ( \
1988 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
1989#define ICL_DDI_IO_C_POWER_DOMAINS ( \
1990 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
1991#define ICL_DDI_IO_D_POWER_DOMAINS ( \
1992 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
1993#define ICL_DDI_IO_E_POWER_DOMAINS ( \
1994 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
1995#define ICL_DDI_IO_F_POWER_DOMAINS ( \
1996 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
1997
1998#define ICL_AUX_A_IO_POWER_DOMAINS ( \
9e3b5ce9 1999 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
67ca07e7
ID		 2000 BIT_ULL(POWER_DOMAIN_AUX_A))
2001#define ICL_AUX_B_IO_POWER_DOMAINS ( \
2002 BIT_ULL(POWER_DOMAIN_AUX_B))
2003#define ICL_AUX_C_IO_POWER_DOMAINS ( \
2004 BIT_ULL(POWER_DOMAIN_AUX_C))
2005#define ICL_AUX_D_IO_POWER_DOMAINS ( \
2006 BIT_ULL(POWER_DOMAIN_AUX_D))
2007#define ICL_AUX_E_IO_POWER_DOMAINS ( \
2008 BIT_ULL(POWER_DOMAIN_AUX_E))
2009#define ICL_AUX_F_IO_POWER_DOMAINS ( \
2010 BIT_ULL(POWER_DOMAIN_AUX_F))
2011#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
2012 BIT_ULL(POWER_DOMAIN_AUX_TBT1))
2013#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
2014 BIT_ULL(POWER_DOMAIN_AUX_TBT2))
2015#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \
2016 BIT_ULL(POWER_DOMAIN_AUX_TBT3))
2017#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
2018 BIT_ULL(POWER_DOMAIN_AUX_TBT4))
2019
9c065a7d 2020static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
3c1b38e6 2021 .sync_hw = i9xx_power_well_sync_hw_noop,
9c065a7d
SV		 2022 .enable = i9xx_always_on_power_well_noop,
2023 .disable = i9xx_always_on_power_well_noop,
2024 .is_enabled = i9xx_always_on_power_well_enabled,
2025};
2026
2027static const struct i915_power_well_ops chv_pipe_power_well_ops = {
3c1b38e6 2028 .sync_hw = i9xx_power_well_sync_hw_noop,
9c065a7d
SV		 2029 .enable = chv_pipe_power_well_enable,
2030 .disable = chv_pipe_power_well_disable,
2031 .is_enabled = chv_pipe_power_well_enabled,
2032};
2033
2034static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
3c1b38e6 2035 .sync_hw = i9xx_power_well_sync_hw_noop,
9c065a7d
SV		 2036 .enable = chv_dpio_cmn_power_well_enable,
2037 .disable = chv_dpio_cmn_power_well_disable,
2038 .is_enabled = vlv_power_well_enabled,
2039};
2040
f28ec6f4 2041static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
9c065a7d
SV		 2042 {
2043 .name = "always-on",
2044 .always_on = 1,
2045 .domains = POWER_DOMAIN_MASK,
2046 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2047 .id = DISP_PW_ID_NONE,
9c065a7d
SV		 2048 },
2049};
2050
2ee0da16
VS		 2051static const struct i915_power_well_ops i830_pipes_power_well_ops = {
2052 .sync_hw = i830_pipes_power_well_sync_hw,
2053 .enable = i830_pipes_power_well_enable,
2054 .disable = i830_pipes_power_well_disable,
2055 .is_enabled = i830_pipes_power_well_enabled,
2056};
2057
f28ec6f4 2058static const struct i915_power_well_desc i830_power_wells[] = {
2ee0da16
VS		 2059 {
2060 .name = "always-on",
2061 .always_on = 1,
2062 .domains = POWER_DOMAIN_MASK,
2063 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2064 .id = DISP_PW_ID_NONE,
2ee0da16
VS		 2065 },
2066 {
2067 .name = "pipes",
2068 .domains = I830_PIPES_POWER_DOMAINS,
2069 .ops = &i830_pipes_power_well_ops,
4739a9d2 2070 .id = DISP_PW_ID_NONE,
2ee0da16
VS		 2071 },
2072};
2073
9c065a7d
SV		 2074static const struct i915_power_well_ops hsw_power_well_ops = {
2075 .sync_hw = hsw_power_well_sync_hw,
2076 .enable = hsw_power_well_enable,
2077 .disable = hsw_power_well_disable,
2078 .is_enabled = hsw_power_well_enabled,
2079};
2080
9f836f90 2081static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
3c1b38e6 2082 .sync_hw = i9xx_power_well_sync_hw_noop,
9f836f90
PJ		 2083 .enable = gen9_dc_off_power_well_enable,
2084 .disable = gen9_dc_off_power_well_disable,
2085 .is_enabled = gen9_dc_off_power_well_enabled,
2086};
2087
9c8d0b8e 2088static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
3c1b38e6 2089 .sync_hw = i9xx_power_well_sync_hw_noop,
9c8d0b8e
ID		 2090 .enable = bxt_dpio_cmn_power_well_enable,
2091 .disable = bxt_dpio_cmn_power_well_disable,
2092 .is_enabled = bxt_dpio_cmn_power_well_enabled,
2093};
2094
75e39688
ID		 2095static const struct i915_power_well_regs hsw_power_well_regs = {
2096 .bios = HSW_PWR_WELL_CTL1,
2097 .driver = HSW_PWR_WELL_CTL2,
2098 .kvmr = HSW_PWR_WELL_CTL3,
2099 .debug = HSW_PWR_WELL_CTL4,
2100};
2101
f28ec6f4 2102static const struct i915_power_well_desc hsw_power_wells[] = {
9c065a7d
SV		 2103 {
2104 .name = "always-on",
2105 .always_on = 1,
998bd66a 2106 .domains = POWER_DOMAIN_MASK,
9c065a7d 2107 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2108 .id = DISP_PW_ID_NONE,
9c065a7d
SV		 2109 },
2110 {
2111 .name = "display",
2112 .domains = HSW_DISPLAY_POWER_DOMAINS,
2113 .ops = &hsw_power_well_ops,
fb9248e2 2114 .id = HSW_DISP_PW_GLOBAL,
0a445945 2115 {
75e39688
ID		 2116 .hsw.regs = &hsw_power_well_regs,
2117 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
0a445945
ID		 2118 .hsw.has_vga = true,
2119 },
9c065a7d
SV		 2120 },
2121};
2122
f28ec6f4 2123static const struct i915_power_well_desc bdw_power_wells[] = {
9c065a7d
SV		 2124 {
2125 .name = "always-on",
2126 .always_on = 1,
998bd66a 2127 .domains = POWER_DOMAIN_MASK,
9c065a7d 2128 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2129 .id = DISP_PW_ID_NONE,
9c065a7d
SV		 2130 },
2131 {
2132 .name = "display",
2133 .domains = BDW_DISPLAY_POWER_DOMAINS,
2134 .ops = &hsw_power_well_ops,
fb9248e2 2135 .id = HSW_DISP_PW_GLOBAL,
0a445945 2136 {
75e39688
ID		 2137 .hsw.regs = &hsw_power_well_regs,
2138 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
0a445945
ID		 2139 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2140 .hsw.has_vga = true,
2141 },
9c065a7d
SV		 2142 },
2143};
2144
2145static const struct i915_power_well_ops vlv_display_power_well_ops = {
3c1b38e6 2146 .sync_hw = i9xx_power_well_sync_hw_noop,
9c065a7d
SV		 2147 .enable = vlv_display_power_well_enable,
2148 .disable = vlv_display_power_well_disable,
2149 .is_enabled = vlv_power_well_enabled,
2150};
2151
2152static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
3c1b38e6 2153 .sync_hw = i9xx_power_well_sync_hw_noop,
9c065a7d
SV		 2154 .enable = vlv_dpio_cmn_power_well_enable,
2155 .disable = vlv_dpio_cmn_power_well_disable,
2156 .is_enabled = vlv_power_well_enabled,
2157};
2158
2159static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
3c1b38e6 2160 .sync_hw = i9xx_power_well_sync_hw_noop,
9c065a7d
SV		 2161 .enable = vlv_power_well_enable,
2162 .disable = vlv_power_well_disable,
2163 .is_enabled = vlv_power_well_enabled,
2164};
2165
f28ec6f4 2166static const struct i915_power_well_desc vlv_power_wells[] = {
9c065a7d
SV		 2167 {
2168 .name = "always-on",
2169 .always_on = 1,
998bd66a 2170 .domains = POWER_DOMAIN_MASK,
9c065a7d 2171 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2172 .id = DISP_PW_ID_NONE,
9c065a7d
SV		 2173 },
2174 {
2175 .name = "display",
2176 .domains = VLV_DISPLAY_POWER_DOMAINS,
9c065a7d 2177 .ops = &vlv_display_power_well_ops,
2183b499 2178 .id = VLV_DISP_PW_DISP2D,
d13dd05a
ID		 2179 {
2180 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
2181 },
9c065a7d
SV		 2182 },
2183 {
2184 .name = "dpio-tx-b-01",
2185 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2186 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2187 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2188 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2189 .ops = &vlv_dpio_power_well_ops,
4739a9d2 2190 .id = DISP_PW_ID_NONE,
d13dd05a
ID		 2191 {
2192 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
2193 },
9c065a7d
SV		 2194 },
2195 {
2196 .name = "dpio-tx-b-23",
2197 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2198 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2199 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2200 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2201 .ops = &vlv_dpio_power_well_ops,
4739a9d2 2202 .id = DISP_PW_ID_NONE,
d13dd05a
ID		 2203 {
2204 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
2205 },
9c065a7d
SV		 2206 },
2207 {
2208 .name = "dpio-tx-c-01",
2209 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2210 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2211 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2212 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2213 .ops = &vlv_dpio_power_well_ops,
4739a9d2 2214 .id = DISP_PW_ID_NONE,
d13dd05a
ID		 2215 {
2216 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
2217 },
9c065a7d
SV		 2218 },
2219 {
2220 .name = "dpio-tx-c-23",
2221 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2222 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2223 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2224 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2225 .ops = &vlv_dpio_power_well_ops,
4739a9d2 2226 .id = DISP_PW_ID_NONE,
d13dd05a
ID		 2227 {
2228 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
2229 },
9c065a7d
SV		 2230 },
2231 {
2232 .name = "dpio-common",
2233 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
9c065a7d 2234 .ops = &vlv_dpio_cmn_power_well_ops,
2183b499 2235 .id = VLV_DISP_PW_DPIO_CMN_BC,
d13dd05a
ID		 2236 {
2237 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2238 },
9c065a7d
SV		 2239 },
2240};
2241
f28ec6f4 2242static const struct i915_power_well_desc chv_power_wells[] = {
9c065a7d
SV		 2243 {
2244 .name = "always-on",
2245 .always_on = 1,
998bd66a 2246 .domains = POWER_DOMAIN_MASK,
9c065a7d 2247 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2248 .id = DISP_PW_ID_NONE,
9c065a7d 2249 },
9c065a7d
SV		 2250 {
2251 .name = "display",
baa4e575 2252 /*
fde61e4b
VS		 2253 * Pipe A power well is the new disp2d well. Pipe B and C
2254 * power wells don't actually exist. Pipe A power well is
2255 * required for any pipe to work.
baa4e575 2256 */
465ac0c6 2257 .domains = CHV_DISPLAY_POWER_DOMAINS,
9c065a7d 2258 .ops = &chv_pipe_power_well_ops,
4739a9d2 2259 .id = DISP_PW_ID_NONE,
9c065a7d 2260 },
9c065a7d
SV		 2261 {
2262 .name = "dpio-common-bc",
71849b67 2263 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
9c065a7d 2264 .ops = &chv_dpio_cmn_power_well_ops,
2183b499 2265 .id = VLV_DISP_PW_DPIO_CMN_BC,
d13dd05a
ID		 2266 {
2267 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2268 },
9c065a7d
SV		 2269 },
2270 {
2271 .name = "dpio-common-d",
71849b67 2272 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
9c065a7d 2273 .ops = &chv_dpio_cmn_power_well_ops,
2183b499 2274 .id = CHV_DISP_PW_DPIO_CMN_D,
d13dd05a
ID		 2275 {
2276 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
2277 },
9c065a7d 2278 },
9c065a7d
SV		 2279};
2280
5aefb239 2281bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
438b8dc4 2282 enum i915_power_well_id power_well_id)
5aefb239
SS		 2283{
2284 struct i915_power_well *power_well;
2285 bool ret;
2286
2287 power_well = lookup_power_well(dev_priv, power_well_id);
f28ec6f4 2288 ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
5aefb239
SS		 2289
2290 return ret;
2291}
2292
f28ec6f4 2293static const struct i915_power_well_desc skl_power_wells[] = {
94dd5138
S		 2294 {
2295 .name = "always-on",
2296 .always_on = 1,
998bd66a 2297 .domains = POWER_DOMAIN_MASK,
94dd5138 2298 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2299 .id = DISP_PW_ID_NONE,
94dd5138
S		 2300 },
2301 {
2302 .name = "power well 1",
4a76f295
ID		 2303 /* Handled by the DMC firmware */
2304 .domains = 0,
4196b918 2305 .ops = &hsw_power_well_ops,
01c3faa7 2306 .id = SKL_DISP_PW_1,
0a445945 2307 {
75e39688
ID		 2308 .hsw.regs = &hsw_power_well_regs,
2309 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
0a445945
ID		 2310 .hsw.has_fuses = true,
2311 },
94dd5138
S		 2312 },
2313 {
2314 .name = "MISC IO power well",
4a76f295
ID		 2315 /* Handled by the DMC firmware */
2316 .domains = 0,
4196b918 2317 .ops = &hsw_power_well_ops,
01c3faa7 2318 .id = SKL_DISP_PW_MISC_IO,
75e39688
ID		 2319 {
2320 .hsw.regs = &hsw_power_well_regs,
2321 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
2322 },
94dd5138 2323 },
9f836f90
PJ		 2324 {
2325 .name = "DC off",
2326 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2327 .ops = &gen9_dc_off_power_well_ops,
4739a9d2 2328 .id = DISP_PW_ID_NONE,
9f836f90 2329 },
94dd5138
S		 2330 {
2331 .name = "power well 2",
2332 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
4196b918 2333 .ops = &hsw_power_well_ops,
01c3faa7 2334 .id = SKL_DISP_PW_2,
0a445945 2335 {
75e39688
ID		 2336 .hsw.regs = &hsw_power_well_regs,
2337 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
0a445945
ID		 2338 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2339 .hsw.has_vga = true,
2340 .hsw.has_fuses = true,
2341 },
94dd5138
S		 2342 },
2343 {
62b69566
ACO		 2344 .name = "DDI A/E IO power well",
2345 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
4196b918 2346 .ops = &hsw_power_well_ops,
4739a9d2 2347 .id = DISP_PW_ID_NONE,
75e39688
ID		 2348 {
2349 .hsw.regs = &hsw_power_well_regs,
2350 .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
2351 },
94dd5138
S		 2352 },
2353 {
62b69566
ACO		 2354 .name = "DDI B IO power well",
2355 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
4196b918 2356 .ops = &hsw_power_well_ops,
4739a9d2 2357 .id = DISP_PW_ID_NONE,
75e39688
ID		 2358 {
2359 .hsw.regs = &hsw_power_well_regs,
2360 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2361 },
94dd5138
S		 2362 },
2363 {
62b69566
ACO		 2364 .name = "DDI C IO power well",
2365 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
4196b918 2366 .ops = &hsw_power_well_ops,
4739a9d2 2367 .id = DISP_PW_ID_NONE,
75e39688
ID		 2368 {
2369 .hsw.regs = &hsw_power_well_regs,
2370 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2371 },
94dd5138
S		 2372 },
2373 {
62b69566
ACO		 2374 .name = "DDI D IO power well",
2375 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
4196b918 2376 .ops = &hsw_power_well_ops,
4739a9d2 2377 .id = DISP_PW_ID_NONE,
75e39688
ID		 2378 {
2379 .hsw.regs = &hsw_power_well_regs,
2380 .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2381 },
94dd5138
S		 2382 },
2383};
2384
f28ec6f4 2385static const struct i915_power_well_desc bxt_power_wells[] = {
0b4a2a36
S		 2386 {
2387 .name = "always-on",
2388 .always_on = 1,
998bd66a 2389 .domains = POWER_DOMAIN_MASK,
0b4a2a36 2390 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2391 .id = DISP_PW_ID_NONE,
0b4a2a36
S		 2392 },
2393 {
2394 .name = "power well 1",
d7d7c9ee 2395 .domains = 0,
4196b918 2396 .ops = &hsw_power_well_ops,
01c3faa7 2397 .id = SKL_DISP_PW_1,
0a445945 2398 {
75e39688
ID		 2399 .hsw.regs = &hsw_power_well_regs,
2400 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
0a445945
ID		 2401 .hsw.has_fuses = true,
2402 },
0b4a2a36 2403 },
9f836f90
PJ		 2404 {
2405 .name = "DC off",
2406 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2407 .ops = &gen9_dc_off_power_well_ops,
4739a9d2 2408 .id = DISP_PW_ID_NONE,
9f836f90 2409 },
0b4a2a36
S		 2410 {
2411 .name = "power well 2",
2412 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
4196b918 2413 .ops = &hsw_power_well_ops,
01c3faa7 2414 .id = SKL_DISP_PW_2,
0a445945 2415 {
75e39688
ID		 2416 .hsw.regs = &hsw_power_well_regs,
2417 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
0a445945
ID		 2418 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2419 .hsw.has_vga = true,
2420 .hsw.has_fuses = true,
2421 },
9f836f90 2422 },
9c8d0b8e
ID		 2423 {
2424 .name = "dpio-common-a",
2425 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2426 .ops = &bxt_dpio_cmn_power_well_ops,
2183b499 2427 .id = BXT_DISP_PW_DPIO_CMN_A,
0a445945
ID		 2428 {
2429 .bxt.phy = DPIO_PHY1,
2430 },
9c8d0b8e
ID		 2431 },
2432 {
2433 .name = "dpio-common-bc",
2434 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2435 .ops = &bxt_dpio_cmn_power_well_ops,
d9fcdc8d 2436 .id = VLV_DISP_PW_DPIO_CMN_BC,
0a445945
ID		 2437 {
2438 .bxt.phy = DPIO_PHY0,
2439 },
9c8d0b8e 2440 },
0b4a2a36
S		 2441};
2442
f28ec6f4 2443static const struct i915_power_well_desc glk_power_wells[] = {
0d03926d
ACO		 2444 {
2445 .name = "always-on",
2446 .always_on = 1,
2447 .domains = POWER_DOMAIN_MASK,
2448 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2449 .id = DISP_PW_ID_NONE,
0d03926d
ACO		 2450 },
2451 {
2452 .name = "power well 1",
2453 /* Handled by the DMC firmware */
2454 .domains = 0,
4196b918 2455 .ops = &hsw_power_well_ops,
0d03926d 2456 .id = SKL_DISP_PW_1,
0a445945 2457 {
75e39688
ID		 2458 .hsw.regs = &hsw_power_well_regs,
2459 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
0a445945
ID		 2460 .hsw.has_fuses = true,
2461 },
0d03926d
ACO		 2462 },
2463 {
2464 .name = "DC off",
2465 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
2466 .ops = &gen9_dc_off_power_well_ops,
4739a9d2 2467 .id = DISP_PW_ID_NONE,
0d03926d
ACO		 2468 },
2469 {
2470 .name = "power well 2",
2471 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
4196b918 2472 .ops = &hsw_power_well_ops,
0d03926d 2473 .id = SKL_DISP_PW_2,
0a445945 2474 {
75e39688
ID		 2475 .hsw.regs = &hsw_power_well_regs,
2476 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
0a445945
ID		 2477 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2478 .hsw.has_vga = true,
2479 .hsw.has_fuses = true,
2480 },
0d03926d 2481 },
0a116ce8
ACO		 2482 {
2483 .name = "dpio-common-a",
2484 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
2485 .ops = &bxt_dpio_cmn_power_well_ops,
2183b499 2486 .id = BXT_DISP_PW_DPIO_CMN_A,
0a445945
ID		 2487 {
2488 .bxt.phy = DPIO_PHY1,
2489 },
0a116ce8
ACO		 2490 },
2491 {
2492 .name = "dpio-common-b",
2493 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
2494 .ops = &bxt_dpio_cmn_power_well_ops,
d9fcdc8d 2495 .id = VLV_DISP_PW_DPIO_CMN_BC,
0a445945
ID		 2496 {
2497 .bxt.phy = DPIO_PHY0,
2498 },
0a116ce8
ACO		 2499 },
2500 {
2501 .name = "dpio-common-c",
2502 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
2503 .ops = &bxt_dpio_cmn_power_well_ops,
2183b499 2504 .id = GLK_DISP_PW_DPIO_CMN_C,
0a445945
ID		 2505 {
2506 .bxt.phy = DPIO_PHY2,
2507 },
0a116ce8 2508 },
0d03926d
ACO		 2509 {
2510 .name = "AUX A",
2511 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
4196b918 2512 .ops = &hsw_power_well_ops,
4739a9d2 2513 .id = DISP_PW_ID_NONE,
75e39688
ID		 2514 {
2515 .hsw.regs = &hsw_power_well_regs,
2516 .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2517 },
0d03926d
ACO		 2518 },
2519 {
2520 .name = "AUX B",
2521 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
4196b918 2522 .ops = &hsw_power_well_ops,
4739a9d2 2523 .id = DISP_PW_ID_NONE,
75e39688
ID		 2524 {
2525 .hsw.regs = &hsw_power_well_regs,
2526 .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2527 },
0d03926d
ACO		 2528 },
2529 {
2530 .name = "AUX C",
2531 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
4196b918 2532 .ops = &hsw_power_well_ops,
4739a9d2 2533 .id = DISP_PW_ID_NONE,
75e39688
ID		 2534 {
2535 .hsw.regs = &hsw_power_well_regs,
2536 .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2537 },
0d03926d
ACO		 2538 },
2539 {
62b69566
ACO		 2540 .name = "DDI A IO power well",
2541 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
4196b918 2542 .ops = &hsw_power_well_ops,
4739a9d2 2543 .id = DISP_PW_ID_NONE,
75e39688
ID		 2544 {
2545 .hsw.regs = &hsw_power_well_regs,
2546 .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2547 },
0d03926d
ACO		 2548 },
2549 {
62b69566
ACO		 2550 .name = "DDI B IO power well",
2551 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
4196b918 2552 .ops = &hsw_power_well_ops,
4739a9d2 2553 .id = DISP_PW_ID_NONE,
75e39688
ID		 2554 {
2555 .hsw.regs = &hsw_power_well_regs,
2556 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2557 },
0d03926d
ACO		 2558 },
2559 {
62b69566
ACO		 2560 .name = "DDI C IO power well",
2561 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
4196b918 2562 .ops = &hsw_power_well_ops,
4739a9d2 2563 .id = DISP_PW_ID_NONE,
75e39688
ID		 2564 {
2565 .hsw.regs = &hsw_power_well_regs,
2566 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2567 },
0d03926d
ACO		 2568 },
2569};
2570
f28ec6f4 2571static const struct i915_power_well_desc cnl_power_wells[] = {
8bcd3dd4
VS		 2572 {
2573 .name = "always-on",
2574 .always_on = 1,
2575 .domains = POWER_DOMAIN_MASK,
2576 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2577 .id = DISP_PW_ID_NONE,
8bcd3dd4
VS		 2578 },
2579 {
2580 .name = "power well 1",
2581 /* Handled by the DMC firmware */
2582 .domains = 0,
4196b918 2583 .ops = &hsw_power_well_ops,
8bcd3dd4 2584 .id = SKL_DISP_PW_1,
0a445945 2585 {
75e39688
ID		 2586 .hsw.regs = &hsw_power_well_regs,
2587 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
0a445945
ID		 2588 .hsw.has_fuses = true,
2589 },
8bcd3dd4
VS		 2590 },
2591 {
2592 .name = "AUX A",
2593 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
4196b918 2594 .ops = &hsw_power_well_ops,
4739a9d2 2595 .id = DISP_PW_ID_NONE,
75e39688
ID		 2596 {
2597 .hsw.regs = &hsw_power_well_regs,
2598 .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2599 },
8bcd3dd4
VS		 2600 },
2601 {
2602 .name = "AUX B",
2603 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
4196b918 2604 .ops = &hsw_power_well_ops,
4739a9d2 2605 .id = DISP_PW_ID_NONE,
75e39688
ID		 2606 {
2607 .hsw.regs = &hsw_power_well_regs,
2608 .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2609 },
8bcd3dd4
VS		 2610 },
2611 {
2612 .name = "AUX C",
2613 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
4196b918 2614 .ops = &hsw_power_well_ops,
4739a9d2 2615 .id = DISP_PW_ID_NONE,
75e39688
ID		 2616 {
2617 .hsw.regs = &hsw_power_well_regs,
2618 .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2619 },
8bcd3dd4
VS		 2620 },
2621 {
2622 .name = "AUX D",
2623 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
4196b918 2624 .ops = &hsw_power_well_ops,
4739a9d2 2625 .id = DISP_PW_ID_NONE,
75e39688
ID		 2626 {
2627 .hsw.regs = &hsw_power_well_regs,
2628 .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
2629 },
8bcd3dd4
VS		 2630 },
2631 {
2632 .name = "DC off",
2633 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
2634 .ops = &gen9_dc_off_power_well_ops,
4739a9d2 2635 .id = DISP_PW_ID_NONE,
8bcd3dd4
VS		 2636 },
2637 {
2638 .name = "power well 2",
2639 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
4196b918 2640 .ops = &hsw_power_well_ops,
8bcd3dd4 2641 .id = SKL_DISP_PW_2,
0a445945 2642 {
75e39688
ID		 2643 .hsw.regs = &hsw_power_well_regs,
2644 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
0a445945
ID		 2645 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2646 .hsw.has_vga = true,
2647 .hsw.has_fuses = true,
2648 },
8bcd3dd4
VS		 2649 },
2650 {
2651 .name = "DDI A IO power well",
2652 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
4196b918 2653 .ops = &hsw_power_well_ops,
4739a9d2 2654 .id = DISP_PW_ID_NONE,
75e39688
ID		 2655 {
2656 .hsw.regs = &hsw_power_well_regs,
2657 .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2658 },
8bcd3dd4
VS		 2659 },
2660 {
2661 .name = "DDI B IO power well",
2662 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
4196b918 2663 .ops = &hsw_power_well_ops,
4739a9d2 2664 .id = DISP_PW_ID_NONE,
75e39688
ID		 2665 {
2666 .hsw.regs = &hsw_power_well_regs,
2667 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2668 },
8bcd3dd4
VS		 2669 },
2670 {
2671 .name = "DDI C IO power well",
2672 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
4196b918 2673 .ops = &hsw_power_well_ops,
4739a9d2 2674 .id = DISP_PW_ID_NONE,
75e39688
ID		 2675 {
2676 .hsw.regs = &hsw_power_well_regs,
2677 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2678 },
8bcd3dd4
VS		 2679 },
2680 {
2681 .name = "DDI D IO power well",
2682 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
4196b918 2683 .ops = &hsw_power_well_ops,
4739a9d2 2684 .id = DISP_PW_ID_NONE,
75e39688
ID		 2685 {
2686 .hsw.regs = &hsw_power_well_regs,
2687 .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2688 },
8bcd3dd4 2689 },
9787e835
RV		 2690 {
2691 .name = "DDI F IO power well",
2692 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
2693 .ops = &hsw_power_well_ops,
4739a9d2 2694 .id = DISP_PW_ID_NONE,
75e39688
ID		 2695 {
2696 .hsw.regs = &hsw_power_well_regs,
2697 .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
2698 },
9787e835 2699 },
a324fcac
RV		 2700 {
2701 .name = "AUX F",
2702 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
2703 .ops = &hsw_power_well_ops,
4739a9d2 2704 .id = DISP_PW_ID_NONE,
75e39688
ID		 2705 {
2706 .hsw.regs = &hsw_power_well_regs,
2707 .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
2708 },
a324fcac 2709 },
8bcd3dd4
VS		 2710};
2711
67ca07e7
ID		 2712static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
2713 .sync_hw = hsw_power_well_sync_hw,
2714 .enable = icl_combo_phy_aux_power_well_enable,
2715 .disable = icl_combo_phy_aux_power_well_disable,
2716 .is_enabled = hsw_power_well_enabled,
2717};
2718
75e39688
ID		 2719static const struct i915_power_well_regs icl_aux_power_well_regs = {
2720 .bios = ICL_PWR_WELL_CTL_AUX1,
2721 .driver = ICL_PWR_WELL_CTL_AUX2,
2722 .debug = ICL_PWR_WELL_CTL_AUX4,
2723};
2724
2725static const struct i915_power_well_regs icl_ddi_power_well_regs = {
2726 .bios = ICL_PWR_WELL_CTL_DDI1,
2727 .driver = ICL_PWR_WELL_CTL_DDI2,
2728 .debug = ICL_PWR_WELL_CTL_DDI4,
2729};
2730
f28ec6f4 2731static const struct i915_power_well_desc icl_power_wells[] = {
67ca07e7
ID		 2732 {
2733 .name = "always-on",
2734 .always_on = 1,
2735 .domains = POWER_DOMAIN_MASK,
2736 .ops = &i9xx_always_on_power_well_ops,
4739a9d2 2737 .id = DISP_PW_ID_NONE,
67ca07e7
ID		 2738 },
2739 {
2740 .name = "power well 1",
2741 /* Handled by the DMC firmware */
2742 .domains = 0,
2743 .ops = &hsw_power_well_ops,
d9fcdc8d 2744 .id = SKL_DISP_PW_1,
ae9b06ca 2745 {
75e39688
ID		 2746 .hsw.regs = &hsw_power_well_regs,
2747 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
ae9b06ca
ID		 2748 .hsw.has_fuses = true,
2749 },
67ca07e7 2750 },
c4f22407
ID		 2751 {
2752 .name = "DC off",
2753 .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
2754 .ops = &gen9_dc_off_power_well_ops,
2755 .id = DISP_PW_ID_NONE,
2756 },
67ca07e7
ID		 2757 {
2758 .name = "power well 2",
2759 .domains = ICL_PW_2_POWER_DOMAINS,
2760 .ops = &hsw_power_well_ops,
d9fcdc8d 2761 .id = SKL_DISP_PW_2,
ae9b06ca 2762 {
75e39688
ID		 2763 .hsw.regs = &hsw_power_well_regs,
2764 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
ae9b06ca
ID		 2765 .hsw.has_fuses = true,
2766 },
67ca07e7 2767 },
67ca07e7
ID		 2768 {
2769 .name = "power well 3",
2770 .domains = ICL_PW_3_POWER_DOMAINS,
2771 .ops = &hsw_power_well_ops,
4739a9d2 2772 .id = DISP_PW_ID_NONE,
ae9b06ca 2773 {
75e39688
ID		 2774 .hsw.regs = &hsw_power_well_regs,
2775 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
ae9b06ca
ID		 2776 .hsw.irq_pipe_mask = BIT(PIPE_B),
2777 .hsw.has_vga = true,
2778 .hsw.has_fuses = true,
2779 },
67ca07e7
ID		 2780 },
2781 {
2782 .name = "DDI A IO",
2783 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
2784 .ops = &hsw_power_well_ops,
4739a9d2 2785 .id = DISP_PW_ID_NONE,
75e39688
ID		 2786 {
2787 .hsw.regs = &icl_ddi_power_well_regs,
2788 .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
2789 },
67ca07e7
ID		 2790 },
2791 {
2792 .name = "DDI B IO",
2793 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
2794 .ops = &hsw_power_well_ops,
4739a9d2 2795 .id = DISP_PW_ID_NONE,
75e39688
ID		 2796 {
2797 .hsw.regs = &icl_ddi_power_well_regs,
2798 .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
2799 },
67ca07e7
ID		 2800 },
2801 {
2802 .name = "DDI C IO",
2803 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
2804 .ops = &hsw_power_well_ops,
4739a9d2 2805 .id = DISP_PW_ID_NONE,
75e39688
ID		 2806 {
2807 .hsw.regs = &icl_ddi_power_well_regs,
2808 .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
2809 },
67ca07e7
ID		 2810 },
2811 {
2812 .name = "DDI D IO",
2813 .domains = ICL_DDI_IO_D_POWER_DOMAINS,
2814 .ops = &hsw_power_well_ops,
4739a9d2 2815 .id = DISP_PW_ID_NONE,
75e39688
ID		 2816 {
2817 .hsw.regs = &icl_ddi_power_well_regs,
2818 .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
2819 },
67ca07e7
ID		 2820 },
2821 {
2822 .name = "DDI E IO",
2823 .domains = ICL_DDI_IO_E_POWER_DOMAINS,
2824 .ops = &hsw_power_well_ops,
4739a9d2 2825 .id = DISP_PW_ID_NONE,
75e39688
ID		 2826 {
2827 .hsw.regs = &icl_ddi_power_well_regs,
2828 .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
2829 },
67ca07e7
ID		 2830 },
2831 {
2832 .name = "DDI F IO",
2833 .domains = ICL_DDI_IO_F_POWER_DOMAINS,
2834 .ops = &hsw_power_well_ops,
4739a9d2 2835 .id = DISP_PW_ID_NONE,
75e39688
ID		 2836 {
2837 .hsw.regs = &icl_ddi_power_well_regs,
2838 .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
2839 },
67ca07e7
ID		 2840 },
2841 {
2842 .name = "AUX A",
2843 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
2844 .ops = &icl_combo_phy_aux_power_well_ops,
4739a9d2 2845 .id = DISP_PW_ID_NONE,
75e39688
ID		 2846 {
2847 .hsw.regs = &icl_aux_power_well_regs,
2848 .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
2849 },
67ca07e7
ID		 2850 },
2851 {
2852 .name = "AUX B",
2853 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
2854 .ops = &icl_combo_phy_aux_power_well_ops,
4739a9d2 2855 .id = DISP_PW_ID_NONE,
75e39688
ID		 2856 {
2857 .hsw.regs = &icl_aux_power_well_regs,
2858 .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
2859 },
67ca07e7
ID		 2860 },
2861 {
2862 .name = "AUX C",
2863 .domains = ICL_AUX_C_IO_POWER_DOMAINS,
2864 .ops = &hsw_power_well_ops,
4739a9d2 2865 .id = DISP_PW_ID_NONE,
75e39688
ID		 2866 {
2867 .hsw.regs = &icl_aux_power_well_regs,
2868 .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
2869 },
67ca07e7
ID		 2870 },
2871 {
2872 .name = "AUX D",
2873 .domains = ICL_AUX_D_IO_POWER_DOMAINS,
2874 .ops = &hsw_power_well_ops,
4739a9d2 2875 .id = DISP_PW_ID_NONE,
75e39688
ID		 2876 {
2877 .hsw.regs = &icl_aux_power_well_regs,
2878 .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
2879 },
67ca07e7
ID		 2880 },
2881 {
2882 .name = "AUX E",
2883 .domains = ICL_AUX_E_IO_POWER_DOMAINS,
2884 .ops = &hsw_power_well_ops,
4739a9d2 2885 .id = DISP_PW_ID_NONE,
75e39688
ID		 2886 {
2887 .hsw.regs = &icl_aux_power_well_regs,
2888 .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
2889 },
67ca07e7
ID		 2890 },
2891 {
2892 .name = "AUX F",
2893 .domains = ICL_AUX_F_IO_POWER_DOMAINS,
2894 .ops = &hsw_power_well_ops,
4739a9d2 2895 .id = DISP_PW_ID_NONE,
75e39688
ID		 2896 {
2897 .hsw.regs = &icl_aux_power_well_regs,
2898 .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
2899 },
67ca07e7
ID		 2900 },
2901 {
2902 .name = "AUX TBT1",
2903 .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
2904 .ops = &hsw_power_well_ops,
4739a9d2 2905 .id = DISP_PW_ID_NONE,
75e39688
ID		 2906 {
2907 .hsw.regs = &icl_aux_power_well_regs,
2908 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
2909 },
67ca07e7
ID		 2910 },
2911 {
2912 .name = "AUX TBT2",
2913 .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
2914 .ops = &hsw_power_well_ops,
4739a9d2 2915 .id = DISP_PW_ID_NONE,
75e39688
ID		 2916 {
2917 .hsw.regs = &icl_aux_power_well_regs,
2918 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
2919 },
67ca07e7
ID		 2920 },
2921 {
2922 .name = "AUX TBT3",
2923 .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
2924 .ops = &hsw_power_well_ops,
4739a9d2 2925 .id = DISP_PW_ID_NONE,
75e39688
ID		 2926 {
2927 .hsw.regs = &icl_aux_power_well_regs,
2928 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
2929 },
67ca07e7
ID		 2930 },
2931 {
2932 .name = "AUX TBT4",
2933 .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
2934 .ops = &hsw_power_well_ops,
4739a9d2 2935 .id = DISP_PW_ID_NONE,
75e39688
ID		 2936 {
2937 .hsw.regs = &icl_aux_power_well_regs,
2938 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
2939 },
67ca07e7
ID		 2940 },
2941 {
2942 .name = "power well 4",
2943 .domains = ICL_PW_4_POWER_DOMAINS,
2944 .ops = &hsw_power_well_ops,
4739a9d2 2945 .id = DISP_PW_ID_NONE,
ae9b06ca 2946 {
75e39688
ID		 2947 .hsw.regs = &hsw_power_well_regs,
2948 .hsw.idx = ICL_PW_CTL_IDX_PW_4,
ae9b06ca
ID		 2949 .hsw.has_fuses = true,
2950 .hsw.irq_pipe_mask = BIT(PIPE_C),
2951 },
67ca07e7
ID		 2952 },
2953};
2954
1b0e3a04
ID		 2955static int
2956sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2957 int disable_power_well)
2958{
2959 if (disable_power_well >= 0)
2960 return !!disable_power_well;
2961
1b0e3a04
ID		 2962 return 1;
2963}
2964
a37baf3b
ID		 2965static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2966 int enable_dc)
2967{
2968 uint32_t mask;
2969 int requested_dc;
2970 int max_dc;
2971
67ca07e7 2972 if (IS_GEN9_BC(dev_priv) || INTEL_INFO(dev_priv)->gen >= 10) {
a37baf3b
ID		 2973 max_dc = 2;
2974 mask = 0;
cc3f90f0 2975 } else if (IS_GEN9_LP(dev_priv)) {
a37baf3b
ID		 2976 max_dc = 1;
2977 /*
2978 * DC9 has a separate HW flow from the rest of the DC states,
2979 * not depending on the DMC firmware. It's needed by system
2980 * suspend/resume, so allow it unconditionally.
2981 */
2982 mask = DC_STATE_EN_DC9;
2983 } else {
2984 max_dc = 0;
2985 mask = 0;
2986 }
2987
4f044a88 2988 if (!i915_modparams.disable_power_well)
66e2c4c3
ID		 2989 max_dc = 0;
2990
a37baf3b
ID		 2991 if (enable_dc >= 0 && enable_dc <= max_dc) {
2992 requested_dc = enable_dc;
2993 } else if (enable_dc == -1) {
2994 requested_dc = max_dc;
2995 } else if (enable_dc > max_dc && enable_dc <= 2) {
2996 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2997 enable_dc, max_dc);
2998 requested_dc = max_dc;
2999 } else {
3000 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
3001 requested_dc = max_dc;
3002 }
3003
3004 if (requested_dc > 1)
3005 mask |= DC_STATE_EN_UPTO_DC6;
3006 if (requested_dc > 0)
3007 mask |= DC_STATE_EN_UPTO_DC5;
3008
3009 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
3010
3011 return mask;
3012}
3013
f28ec6f4
ID		 3014static int
3015__set_power_wells(struct i915_power_domains *power_domains,
3016 const struct i915_power_well_desc *power_well_descs,
3017 int power_well_count)
21792c60 3018{
f28ec6f4 3019 u64 power_well_ids = 0;
21792c60
ID		 3020 int i;
3021
f28ec6f4
ID		 3022 power_domains->power_well_count = power_well_count;
3023 power_domains->power_wells =
3024 kcalloc(power_well_count,
3025 sizeof(*power_domains->power_wells),
3026 GFP_KERNEL);
3027 if (!power_domains->power_wells)
3028 return -ENOMEM;
3029
3030 for (i = 0; i < power_well_count; i++) {
3031 enum i915_power_well_id id = power_well_descs[i].id;
3032
3033 power_domains->power_wells[i].desc = &power_well_descs[i];
21792c60 3034
4739a9d2
ID		 3035 if (id == DISP_PW_ID_NONE)
3036 continue;
3037
21792c60
ID		 3038 WARN_ON(id >= sizeof(power_well_ids) * 8);
3039 WARN_ON(power_well_ids & BIT_ULL(id));
3040 power_well_ids |= BIT_ULL(id);
3041 }
f28ec6f4
ID		 3042
3043 return 0;
21792c60
ID		 3044}
3045
f28ec6f4
ID		 3046#define set_power_wells(power_domains, __power_well_descs) \
3047 __set_power_wells(power_domains, __power_well_descs, \
3048 ARRAY_SIZE(__power_well_descs))
9c065a7d 3049
e4e7684f
SV		 3050/**
3051 * intel_power_domains_init - initializes the power domain structures
3052 * @dev_priv: i915 device instance
3053 *
3054 * Initializes the power domain structures for @dev_priv depending upon the
3055 * supported platform.
3056 */
9c065a7d
SV		 3057int intel_power_domains_init(struct drm_i915_private *dev_priv)
3058{
3059 struct i915_power_domains *power_domains = &dev_priv->power_domains;
f28ec6f4 3060 int err;
9c065a7d 3061
4f044a88
MW		 3062 i915_modparams.disable_power_well =
3063 sanitize_disable_power_well_option(dev_priv,
3064 i915_modparams.disable_power_well);
3065 dev_priv->csr.allowed_dc_mask =
3066 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
1b0e3a04 3067
d8fc70b7 3068 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
f0ab43e6 3069
9c065a7d
SV		 3070 mutex_init(&power_domains->lock);
3071
3072 /*
3073 * The enabling order will be from lower to higher indexed wells,
3074 * the disabling order is reversed.
3075 */
67ca07e7 3076 if (IS_ICELAKE(dev_priv)) {
f28ec6f4 3077 err = set_power_wells(power_domains, icl_power_wells);
67ca07e7 3078 } else if (IS_HASWELL(dev_priv)) {
f28ec6f4 3079 err = set_power_wells(power_domains, hsw_power_wells);
2d1fe073 3080 } else if (IS_BROADWELL(dev_priv)) {
f28ec6f4 3081 err = set_power_wells(power_domains, bdw_power_wells);
b976dc53 3082 } else if (IS_GEN9_BC(dev_priv)) {
f28ec6f4 3083 err = set_power_wells(power_domains, skl_power_wells);
8bcd3dd4 3084 } else if (IS_CANNONLAKE(dev_priv)) {
f28ec6f4 3085 err = set_power_wells(power_domains, cnl_power_wells);
a324fcac
RV		 3086
3087 /*
9787e835 3088 * DDI and Aux IO are getting enabled for all ports
a324fcac 3089 * regardless the presence or use. So, in order to avoid
9787e835 3090 * timeouts, lets remove them from the list
a324fcac
RV		 3091 * for the SKUs without port F.
3092 */
3093 if (!IS_CNL_WITH_PORT_F(dev_priv))
9787e835 3094 power_domains->power_well_count -= 2;
a324fcac 3095
2d1fe073 3096 } else if (IS_BROXTON(dev_priv)) {
f28ec6f4 3097 err = set_power_wells(power_domains, bxt_power_wells);
0d03926d 3098 } else if (IS_GEMINILAKE(dev_priv)) {
f28ec6f4 3099 err = set_power_wells(power_domains, glk_power_wells);
2d1fe073 3100 } else if (IS_CHERRYVIEW(dev_priv)) {
f28ec6f4 3101 err = set_power_wells(power_domains, chv_power_wells);
2d1fe073 3102 } else if (IS_VALLEYVIEW(dev_priv)) {
f28ec6f4 3103 err = set_power_wells(power_domains, vlv_power_wells);
2ee0da16 3104 } else if (IS_I830(dev_priv)) {
f28ec6f4 3105 err = set_power_wells(power_domains, i830_power_wells);
9c065a7d 3106 } else {
f28ec6f4 3107 err = set_power_wells(power_domains, i9xx_always_on_power_well);
9c065a7d
SV		 3108 }
3109
f28ec6f4
ID		 3110 return err;
3111}
21792c60 3112
f28ec6f4
ID		 3113/**
3114 * intel_power_domains_cleanup - clean up power domains resources
3115 * @dev_priv: i915 device instance
3116 *
3117 * Release any resources acquired by intel_power_domains_init()
3118 */
3119void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
3120{
3121 kfree(dev_priv->power_domains.power_wells);
9c065a7d
SV		 3122}
3123
30eade12 3124static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
9c065a7d
SV		 3125{
3126 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3127 struct i915_power_well *power_well;
9c065a7d
SV		 3128
3129 mutex_lock(&power_domains->lock);
75ccb2ec 3130 for_each_power_well(dev_priv, power_well) {
f28ec6f4
ID		 3131 power_well->desc->ops->sync_hw(dev_priv, power_well);
3132 power_well->hw_enabled =
3133 power_well->desc->ops->is_enabled(dev_priv, power_well);
9c065a7d
SV		 3134 }
3135 mutex_unlock(&power_domains->lock);
3136}
3137
aa9664ff
MK		 3138static inline
3139bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
3140 i915_reg_t reg, bool enable)
70c2c184 3141{
aa9664ff 3142 u32 val, status;
70c2c184 3143
aa9664ff
MK		 3144 val = I915_READ(reg);
3145 val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST);
3146 I915_WRITE(reg, val);
3147 POSTING_READ(reg);
70c2c184
VS		 3148 udelay(10);
3149
aa9664ff
MK		 3150 status = I915_READ(reg) & DBUF_POWER_STATE;
3151 if ((enable && !status) || (!enable && status)) {
3152 DRM_ERROR("DBus power %s timeout!\n",
3153 enable ? "enable" : "disable");
3154 return false;
3155 }
3156 return true;
3157}
3158
3159static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
3160{
3161 intel_dbuf_slice_set(dev_priv, DBUF_CTL, true);
70c2c184
VS		 3162}
3163
3164static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
3165{
aa9664ff
MK		 3166 intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
3167}
70c2c184 3168
aa9664ff
MK		 3169static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
3170{
3171 if (INTEL_GEN(dev_priv) < 11)
3172 return 1;
3173 return 2;
3174}
70c2c184 3175
aa9664ff
MK		 3176void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
3177 u8 req_slices)
3178{
a2261230 3179 const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
aa9664ff
MK		 3180 bool ret;
3181
3182 if (req_slices > intel_dbuf_max_slices(dev_priv)) {
3183 DRM_ERROR("Invalid number of dbuf slices requested\n");
3184 return;
3185 }
3186
3187 if (req_slices == hw_enabled_slices || req_slices == 0)
3188 return;
3189
aa9664ff
MK		 3190 if (req_slices > hw_enabled_slices)
3191 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
3192 else
3193 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
3194
3195 if (ret)
3196 dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
70c2c184
VS		 3197}
3198
746edf8f
MK		 3199static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
3200{
3201 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
3202 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
3203 POSTING_READ(DBUF_CTL_S2);
3204
3205 udelay(10);
3206
3207 if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
3208 !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
3209 DRM_ERROR("DBuf power enable timeout\n");
74bd8004
MK		 3210 else
3211 dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
746edf8f
MK		 3212}
3213
3214static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
3215{
3216 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
3217 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
3218 POSTING_READ(DBUF_CTL_S2);
3219
3220 udelay(10);
3221
3222 if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
3223 (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
3224 DRM_ERROR("DBuf power disable timeout!\n");
74bd8004
MK		 3225 else
3226 dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
746edf8f
MK		 3227}
3228
4cb4585e
MK		 3229static void icl_mbus_init(struct drm_i915_private *dev_priv)
3230{
3231 uint32_t val;
3232
3233 val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
3234 MBUS_ABOX_BT_CREDIT_POOL2(16) |
3235 MBUS_ABOX_B_CREDIT(1) |
3236 MBUS_ABOX_BW_CREDIT(1);
3237
3238 I915_WRITE(MBUS_ABOX_CTL, val);
3239}
3240
73dfc227 3241static void skl_display_core_init(struct drm_i915_private *dev_priv,
443a93ac 3242 bool resume)
73dfc227
ID		 3243{
3244 struct i915_power_domains *power_domains = &dev_priv->power_domains;
443a93ac 3245 struct i915_power_well *well;
73dfc227
ID		 3246 uint32_t val;
3247
d26fa1d5
ID		 3248 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3249
73dfc227
ID		 3250 /* enable PCH reset handshake */
3251 val = I915_READ(HSW_NDE_RSTWRN_OPT);
3252 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
3253
3254 /* enable PG1 and Misc I/O */
3255 mutex_lock(&power_domains->lock);
443a93ac
ID		 3256
3257 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3258 intel_power_well_enable(dev_priv, well);
3259
3260 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
3261 intel_power_well_enable(dev_priv, well);
3262
73dfc227
ID		 3263 mutex_unlock(&power_domains->lock);
3264
73dfc227
ID		 3265 skl_init_cdclk(dev_priv);
3266
70c2c184
VS		 3267 gen9_dbuf_enable(dev_priv);
3268
9f7eb31a 3269 if (resume && dev_priv->csr.dmc_payload)
2abc525b 3270 intel_csr_load_program(dev_priv);
73dfc227
ID		 3271}
3272
3273static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
3274{
3275 struct i915_power_domains *power_domains = &dev_priv->power_domains;
443a93ac 3276 struct i915_power_well *well;
73dfc227 3277
d26fa1d5
ID		 3278 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3279
70c2c184
VS		 3280 gen9_dbuf_disable(dev_priv);
3281
73dfc227
ID		 3282 skl_uninit_cdclk(dev_priv);
3283
3284 /* The spec doesn't call for removing the reset handshake flag */
3285 /* disable PG1 and Misc I/O */
443a93ac 3286
73dfc227 3287 mutex_lock(&power_domains->lock);
443a93ac 3288
edfda8e3
ID		 3289 /*
3290 * BSpec says to keep the MISC IO power well enabled here, only
3291 * remove our request for power well 1.
42d9366d
ID		 3292 * Note that even though the driver's request is removed power well 1
3293 * may stay enabled after this due to DMC's own request on it.
edfda8e3 3294 */
443a93ac
ID		 3295 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3296 intel_power_well_disable(dev_priv, well);
3297
73dfc227 3298 mutex_unlock(&power_domains->lock);
846c6b26
ID		 3299
3300 usleep_range(10, 30); /* 10 us delay per Bspec */
73dfc227
ID		 3301}
3302
d7d7c9ee
ID		 3303void bxt_display_core_init(struct drm_i915_private *dev_priv,
3304 bool resume)
3305{
3306 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3307 struct i915_power_well *well;
3308 uint32_t val;
3309
3310 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3311
3312 /*
3313 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
3314 * or else the reset will hang because there is no PCH to respond.
3315 * Move the handshake programming to initialization sequence.
3316 * Previously was left up to BIOS.
3317 */
3318 val = I915_READ(HSW_NDE_RSTWRN_OPT);
3319 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
3320 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
3321
3322 /* Enable PG1 */
3323 mutex_lock(&power_domains->lock);
3324
3325 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3326 intel_power_well_enable(dev_priv, well);
3327
3328 mutex_unlock(&power_domains->lock);
3329
324513c0 3330 bxt_init_cdclk(dev_priv);
70c2c184
VS		 3331
3332 gen9_dbuf_enable(dev_priv);
3333
d7d7c9ee
ID		 3334 if (resume && dev_priv->csr.dmc_payload)
3335 intel_csr_load_program(dev_priv);
3336}
3337
3338void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
3339{
3340 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3341 struct i915_power_well *well;
3342
3343 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3344
70c2c184
VS		 3345 gen9_dbuf_disable(dev_priv);
3346
324513c0 3347 bxt_uninit_cdclk(dev_priv);
d7d7c9ee
ID		 3348
3349 /* The spec doesn't call for removing the reset handshake flag */
3350
42d9366d
ID		 3351 /*
3352 * Disable PW1 (PG1).
3353 * Note that even though the driver's request is removed power well 1
3354 * may stay enabled after this due to DMC's own request on it.
3355 */
d7d7c9ee
ID		 3356 mutex_lock(&power_domains->lock);
3357
3358 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3359 intel_power_well_disable(dev_priv, well);
3360
3361 mutex_unlock(&power_domains->lock);
846c6b26
ID		 3362
3363 usleep_range(10, 30); /* 10 us delay per Bspec */
d7d7c9ee
ID		 3364}
3365
e0b8acf3
PZ		 3366enum {
3367 PROCMON_0_85V_DOT_0,
3368 PROCMON_0_95V_DOT_0,
3369 PROCMON_0_95V_DOT_1,
3370 PROCMON_1_05V_DOT_0,
3371 PROCMON_1_05V_DOT_1,
3372};
d8d4a512
VS		 3373
3374static const struct cnl_procmon {
3375 u32 dw1, dw9, dw10;
e0b8acf3
PZ		 3376} cnl_procmon_values[] = {
3377 [PROCMON_0_85V_DOT_0] =
3378 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
3379 [PROCMON_0_95V_DOT_0] =
3380 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
3381 [PROCMON_0_95V_DOT_1] =
3382 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
3383 [PROCMON_1_05V_DOT_0] =
3384 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
3385 [PROCMON_1_05V_DOT_1] =
3386 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
d8d4a512
VS		 3387};
3388
62d4a5e1
PZ		 3389/*
3390 * CNL has just one set of registers, while ICL has two sets: one for port A and
3391 * the other for port B. The CNL registers are equivalent to the ICL port A
3392 * registers, that's why we call the ICL macros even though the function has CNL
3393 * on its name.
3394 */
3395static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
3396 enum port port)
d8d4a512 3397{
d8d4a512 3398 const struct cnl_procmon *procmon;
d8d4a512
VS		 3399 u32 val;
3400
62d4a5e1 3401 val = I915_READ(ICL_PORT_COMP_DW3(port));
e0b8acf3
PZ		 3402 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
3403 default:
3404 MISSING_CASE(val);
f0d759f0 3405 /* fall through */
e0b8acf3
PZ		 3406 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
3407 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
3408 break;
3409 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
3410 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
3411 break;
3412 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
3413 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
3414 break;
3415 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
3416 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
3417 break;
3418 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
3419 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
3420 break;
3421 }
d8d4a512 3422
62d4a5e1 3423 val = I915_READ(ICL_PORT_COMP_DW1(port));
d8d4a512
VS		 3424 val &= ~((0xff << 16) | 0xff);
3425 val |= procmon->dw1;
62d4a5e1 3426 I915_WRITE(ICL_PORT_COMP_DW1(port), val);
d8d4a512 3427
62d4a5e1
PZ		 3428 I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
3429 I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
ade5ee7e
PZ		 3430}
3431
3432static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
3433{
3434 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3435 struct i915_power_well *well;
3436 u32 val;
3437
3438 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3439
3440 /* 1. Enable PCH Reset Handshake */
3441 val = I915_READ(HSW_NDE_RSTWRN_OPT);
3442 val |= RESET_PCH_HANDSHAKE_ENABLE;
3443 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
3444
3445 /* 2. Enable Comp */
3446 val = I915_READ(CHICKEN_MISC_2);
3447 val &= ~CNL_COMP_PWR_DOWN;
3448 I915_WRITE(CHICKEN_MISC_2, val);
3449
62d4a5e1
PZ		 3450 /* Dummy PORT_A to get the correct CNL register from the ICL macro */
3451 cnl_set_procmon_ref_values(dev_priv, PORT_A);
d8d4a512
VS		 3452
3453 val = I915_READ(CNL_PORT_COMP_DW0);
3454 val |= COMP_INIT;
3455 I915_WRITE(CNL_PORT_COMP_DW0, val);
3456
3457 /* 3. */
3458 val = I915_READ(CNL_PORT_CL1CM_DW5);
3459 val |= CL_POWER_DOWN_ENABLE;
3460 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
3461
b38131fb
ID		 3462 /*
3463 * 4. Enable Power Well 1 (PG1).
3464 * The AUX IO power wells will be enabled on demand.
3465 */
d8d4a512
VS		 3466 mutex_lock(&power_domains->lock);
3467 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3468 intel_power_well_enable(dev_priv, well);
3469 mutex_unlock(&power_domains->lock);
3470
3471 /* 5. Enable CD clock */
3472 cnl_init_cdclk(dev_priv);
3473
3474 /* 6. Enable DBUF */
3475 gen9_dbuf_enable(dev_priv);
57522c4c
ID		 3476
3477 if (resume && dev_priv->csr.dmc_payload)
3478 intel_csr_load_program(dev_priv);
d8d4a512
VS		 3479}
3480
d8d4a512
VS		 3481static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
3482{
3483 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3484 struct i915_power_well *well;
3485 u32 val;
3486
3487 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3488
3489 /* 1. Disable all display engine functions -> aready done */
3490
3491 /* 2. Disable DBUF */
3492 gen9_dbuf_disable(dev_priv);
3493
3494 /* 3. Disable CD clock */
3495 cnl_uninit_cdclk(dev_priv);
3496
b38131fb
ID		 3497 /*
3498 * 4. Disable Power Well 1 (PG1).
3499 * The AUX IO power wells are toggled on demand, so they are already
3500 * disabled at this point.
3501 */
d8d4a512
VS		 3502 mutex_lock(&power_domains->lock);
3503 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3504 intel_power_well_disable(dev_priv, well);
3505 mutex_unlock(&power_domains->lock);
3506
846c6b26
ID		 3507 usleep_range(10, 30); /* 10 us delay per Bspec */
3508
d8d4a512
VS		 3509 /* 5. Disable Comp */
3510 val = I915_READ(CHICKEN_MISC_2);
746a5173 3511 val |= CNL_COMP_PWR_DOWN;
d8d4a512
VS		 3512 I915_WRITE(CHICKEN_MISC_2, val);
3513}
3514
ad186f3f
PZ		 3515static void icl_display_core_init(struct drm_i915_private *dev_priv,
3516 bool resume)
3517{
67ca07e7
ID		 3518 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3519 struct i915_power_well *well;
ad186f3f
PZ		 3520 enum port port;
3521 u32 val;
3522
3523 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3524
3525 /* 1. Enable PCH reset handshake. */
3526 val = I915_READ(HSW_NDE_RSTWRN_OPT);
3527 val |= RESET_PCH_HANDSHAKE_ENABLE;
3528 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
3529
3530 for (port = PORT_A; port <= PORT_B; port++) {
3531 /* 2. Enable DDI combo PHY comp. */
3532 val = I915_READ(ICL_PHY_MISC(port));
3533 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
3534 I915_WRITE(ICL_PHY_MISC(port), val);
3535
3536 cnl_set_procmon_ref_values(dev_priv, port);
3537
3538 val = I915_READ(ICL_PORT_COMP_DW0(port));
3539 val |= COMP_INIT;
3540 I915_WRITE(ICL_PORT_COMP_DW0(port), val);
3541
3542 /* 3. Set power down enable. */
3543 val = I915_READ(ICL_PORT_CL_DW5(port));
3544 val |= CL_POWER_DOWN_ENABLE;
3545 I915_WRITE(ICL_PORT_CL_DW5(port), val);
3546 }
3547
67ca07e7
ID		 3548 /*
3549 * 4. Enable Power Well 1 (PG1).
3550 * The AUX IO power wells will be enabled on demand.
3551 */
3552 mutex_lock(&power_domains->lock);
d9fcdc8d 3553 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
67ca07e7
ID		 3554 intel_power_well_enable(dev_priv, well);
3555 mutex_unlock(&power_domains->lock);
ad186f3f
PZ		 3556
3557 /* 5. Enable CDCLK. */
3558 icl_init_cdclk(dev_priv);
3559
3560 /* 6. Enable DBUF. */
746edf8f 3561 icl_dbuf_enable(dev_priv);
ad186f3f
PZ		 3562
3563 /* 7. Setup MBUS. */
4cb4585e 3564 icl_mbus_init(dev_priv);
4445930f
AS		 3565
3566 if (resume && dev_priv->csr.dmc_payload)
3567 intel_csr_load_program(dev_priv);
ad186f3f
PZ		 3568}
3569
3570static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
3571{
67ca07e7
ID		 3572 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3573 struct i915_power_well *well;
ad186f3f
PZ		 3574 enum port port;
3575 u32 val;
3576
3577 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3578
3579 /* 1. Disable all display engine functions -> aready done */
3580
3581 /* 2. Disable DBUF */
746edf8f 3582 icl_dbuf_disable(dev_priv);
ad186f3f
PZ		 3583
3584 /* 3. Disable CD clock */
3585 icl_uninit_cdclk(dev_priv);
3586
67ca07e7
ID		 3587 /*
3588 * 4. Disable Power Well 1 (PG1).
3589 * The AUX IO power wells are toggled on demand, so they are already
3590 * disabled at this point.
3591 */
3592 mutex_lock(&power_domains->lock);
d9fcdc8d 3593 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
67ca07e7
ID		 3594 intel_power_well_disable(dev_priv, well);
3595 mutex_unlock(&power_domains->lock);
ad186f3f
PZ		 3596
3597 /* 5. Disable Comp */
3598 for (port = PORT_A; port <= PORT_B; port++) {
3599 val = I915_READ(ICL_PHY_MISC(port));
3600 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
3601 I915_WRITE(ICL_PHY_MISC(port), val);
3602 }
3603}
3604
70722468
VS		 3605static void chv_phy_control_init(struct drm_i915_private *dev_priv)
3606{
3607 struct i915_power_well *cmn_bc =
2183b499 3608 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
70722468 3609 struct i915_power_well *cmn_d =
2183b499 3610 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
70722468
VS		 3611
3612 /*
3613 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
3614 * workaround never ever read DISPLAY_PHY_CONTROL, and
3615 * instead maintain a shadow copy ourselves. Use the actual
e0fce78f
VS		 3616 * power well state and lane status to reconstruct the
3617 * expected initial value.
70722468
VS		 3618 */
3619 dev_priv->chv_phy_control =
bc284542
VS		 3620 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
3621 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
e0fce78f
VS		 3622 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
3623 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
3624 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
3625
3626 /*
3627 * If all lanes are disabled we leave the override disabled
3628 * with all power down bits cleared to match the state we
3629 * would use after disabling the port. Otherwise enable the
3630 * override and set the lane powerdown bits accding to the
3631 * current lane status.
3632 */
f28ec6f4 3633 if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
e0fce78f
VS		 3634 uint32_t status = I915_READ(DPLL(PIPE_A));
3635 unsigned int mask;
3636
3637 mask = status & DPLL_PORTB_READY_MASK;
3638 if (mask == 0xf)
3639 mask = 0x0;
3640 else
3641 dev_priv->chv_phy_control |=
3642 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
3643
3644 dev_priv->chv_phy_control |=
3645 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
3646
3647 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
3648 if (mask == 0xf)
3649 mask = 0x0;
3650 else
3651 dev_priv->chv_phy_control |=
3652 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
3653
3654 dev_priv->chv_phy_control |=
3655 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
3656
70722468 3657 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
3be60de9
VS		 3658
3659 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
3660 } else {
3661 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
e0fce78f
VS		 3662 }
3663
f28ec6f4 3664 if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
e0fce78f
VS		 3665 uint32_t status = I915_READ(DPIO_PHY_STATUS);
3666 unsigned int mask;
3667
3668 mask = status & DPLL_PORTD_READY_MASK;
3669
3670 if (mask == 0xf)
3671 mask = 0x0;
3672 else
3673 dev_priv->chv_phy_control |=
3674 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
3675
3676 dev_priv->chv_phy_control |=
3677 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
3678
70722468 3679 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
3be60de9
VS		 3680
3681 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
3682 } else {
3683 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
e0fce78f
VS		 3684 }
3685
3686 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
3687
3688 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
3689 dev_priv->chv_phy_control);
70722468
VS		 3690}
3691
9c065a7d
SV		 3692static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
3693{
3694 struct i915_power_well *cmn =
2183b499 3695 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
9c065a7d 3696 struct i915_power_well *disp2d =
2183b499 3697 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
9c065a7d 3698
9c065a7d 3699 /* If the display might be already active skip this */
f28ec6f4
ID		 3700 if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
3701 disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
9c065a7d
SV		 3702 I915_READ(DPIO_CTL) & DPIO_CMNRST)
3703 return;
3704
3705 DRM_DEBUG_KMS("toggling display PHY side reset\n");
3706
3707 /* cmnlane needs DPLL registers */
f28ec6f4 3708 disp2d->desc->ops->enable(dev_priv, disp2d);
9c065a7d
SV		 3709
3710 /*
3711 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
3712 * Need to assert and de-assert PHY SB reset by gating the
3713 * common lane power, then un-gating it.
3714 * Simply ungating isn't enough to reset the PHY enough to get
3715 * ports and lanes running.
3716 */
f28ec6f4 3717 cmn->desc->ops->disable(dev_priv, cmn);
9c065a7d
SV		 3718}
3719
6dfc4a8f
ID		 3720static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
3721
e4e7684f
SV		 3722/**
3723 * intel_power_domains_init_hw - initialize hardware power domain state
3724 * @dev_priv: i915 device instance
14bb2c11 3725 * @resume: Called from resume code paths or not
e4e7684f
SV		 3726 *
3727 * This function initializes the hardware power domain state and enables all
8d8c386c 3728 * power wells belonging to the INIT power domain. Power wells in other
d8c5d29f
ID		 3729 * domains (and not in the INIT domain) are referenced or disabled by
3730 * intel_modeset_readout_hw_state(). After that the reference count of each
3731 * power well must match its HW enabled state, see
3732 * intel_power_domains_verify_state().
2cd9a689
ID		 3733 *
3734 * It will return with power domains disabled (to be enabled later by
3735 * intel_power_domains_enable()) and must be paired with
3736 * intel_power_domains_fini_hw().
e4e7684f 3737 */
73dfc227 3738void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
9c065a7d 3739{
9c065a7d
SV		 3740 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3741
3742 power_domains->initializing = true;
3743
ad186f3f
PZ		 3744 if (IS_ICELAKE(dev_priv)) {
3745 icl_display_core_init(dev_priv, resume);
3746 } else if (IS_CANNONLAKE(dev_priv)) {
d8d4a512
VS		 3747 cnl_display_core_init(dev_priv, resume);
3748 } else if (IS_GEN9_BC(dev_priv)) {
73dfc227 3749 skl_display_core_init(dev_priv, resume);
b817c440 3750 } else if (IS_GEN9_LP(dev_priv)) {
d7d7c9ee 3751 bxt_display_core_init(dev_priv, resume);
920a14b2 3752 } else if (IS_CHERRYVIEW(dev_priv)) {
770effb1 3753 mutex_lock(&power_domains->lock);
70722468 3754 chv_phy_control_init(dev_priv);
770effb1 3755 mutex_unlock(&power_domains->lock);
11a914c2 3756 } else if (IS_VALLEYVIEW(dev_priv)) {
9c065a7d
SV		 3757 mutex_lock(&power_domains->lock);
3758 vlv_cmnlane_wa(dev_priv);
3759 mutex_unlock(&power_domains->lock);
3760 }
3761
2cd9a689
ID		 3762 /*
3763 * Keep all power wells enabled for any dependent HW access during
3764 * initialization and to make sure we keep BIOS enabled display HW
3765 * resources powered until display HW readout is complete. We drop
3766 * this reference in intel_power_domains_enable().
3767 */
3768 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
d314cd43 3769 /* Disable power support if the user asked so. */
4f044a88 3770 if (!i915_modparams.disable_power_well)
d314cd43 3771 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
30eade12 3772 intel_power_domains_sync_hw(dev_priv);
6dfc4a8f 3773
d8c5d29f 3774 power_domains->initializing = false;
9c065a7d
SV		 3775}
3776
48a287ed
ID		 3777/**
3778 * intel_power_domains_fini_hw - deinitialize hw power domain state
3779 * @dev_priv: i915 device instance
3780 *
3781 * De-initializes the display power domain HW state. It also ensures that the
3782 * device stays powered up so that the driver can be reloaded.
2cd9a689
ID		 3783 *
3784 * It must be called with power domains already disabled (after a call to
3785 * intel_power_domains_disable()) and must be paired with
3786 * intel_power_domains_init_hw().
48a287ed
ID		 3787 */
3788void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv)
3789{
07d80572
CW		 3790 /* Keep the power well enabled, but cancel its rpm wakeref. */
3791 intel_runtime_pm_put(dev_priv);
48a287ed
ID		 3792
3793 /* Remove the refcount we took to keep power well support disabled. */
3794 if (!i915_modparams.disable_power_well)
3795 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
6dfc4a8f
ID		 3796
3797 intel_power_domains_verify_state(dev_priv);
48a287ed
ID		 3798}
3799
2cd9a689
ID		 3800/**
3801 * intel_power_domains_enable - enable toggling of display power wells
3802 * @dev_priv: i915 device instance
3803 *
3804 * Enable the ondemand enabling/disabling of the display power wells. Note that
3805 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
3806 * only at specific points of the display modeset sequence, thus they are not
3807 * affected by the intel_power_domains_enable()/disable() calls. The purpose
3808 * of these function is to keep the rest of power wells enabled until the end
3809 * of display HW readout (which will acquire the power references reflecting
3810 * the current HW state).
3811 */
3812void intel_power_domains_enable(struct drm_i915_private *dev_priv)
3813{
3814 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
6dfc4a8f
ID		 3815
3816 intel_power_domains_verify_state(dev_priv);
2cd9a689
ID		 3817}
3818
3819/**
3820 * intel_power_domains_disable - disable toggling of display power wells
3821 * @dev_priv: i915 device instance
3822 *
3823 * Disable the ondemand enabling/disabling of the display power wells. See
3824 * intel_power_domains_enable() for which power wells this call controls.
3825 */
3826void intel_power_domains_disable(struct drm_i915_private *dev_priv)
3827{
3828 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
6dfc4a8f
ID		 3829
3830 intel_power_domains_verify_state(dev_priv);
2cd9a689
ID		 3831}
3832
73dfc227
ID		 3833/**
3834 * intel_power_domains_suspend - suspend power domain state
3835 * @dev_priv: i915 device instance
2cd9a689 3836 * @suspend_mode: specifies the target suspend state (idle, mem, hibernation)
73dfc227
ID		 3837 *
3838 * This function prepares the hardware power domain state before entering
2cd9a689
ID		 3839 * system suspend.
3840 *
3841 * It must be called with power domains already disabled (after a call to
3842 * intel_power_domains_disable()) and paired with intel_power_domains_resume().
73dfc227 3843 */
2cd9a689
ID		 3844void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
3845 enum i915_drm_suspend_mode suspend_mode)
73dfc227 3846{
2cd9a689
ID		 3847 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3848
3849 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3850
3851 /*
a61d904f
ID		 3852 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
3853 * support don't manually deinit the power domains. This also means the
3854 * CSR/DMC firmware will stay active, it will power down any HW
3855 * resources as required and also enable deeper system power states
3856 * that would be blocked if the firmware was inactive.
2cd9a689 3857 */
a61d904f
ID		 3858 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
3859 suspend_mode == I915_DRM_SUSPEND_IDLE &&
6dfc4a8f
ID		 3860 dev_priv->csr.dmc_payload != NULL) {
3861 intel_power_domains_verify_state(dev_priv);
2cd9a689 3862 return;
6dfc4a8f 3863 }
2cd9a689 3864
d314cd43
ID		 3865 /*
3866 * Even if power well support was disabled we still want to disable
2cd9a689 3867 * power wells if power domains must be deinitialized for suspend.
d314cd43 3868 */
6dfc4a8f 3869 if (!i915_modparams.disable_power_well) {
d314cd43 3870 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
6dfc4a8f
ID		 3871 intel_power_domains_verify_state(dev_priv);
3872 }
2622d79b 3873
ad186f3f
PZ		 3874 if (IS_ICELAKE(dev_priv))
3875 icl_display_core_uninit(dev_priv);
3876 else if (IS_CANNONLAKE(dev_priv))
d8d4a512
VS		 3877 cnl_display_core_uninit(dev_priv);
3878 else if (IS_GEN9_BC(dev_priv))
2622d79b 3879 skl_display_core_uninit(dev_priv);
b817c440 3880 else if (IS_GEN9_LP(dev_priv))
d7d7c9ee 3881 bxt_display_core_uninit(dev_priv);
2cd9a689
ID		 3882
3883 power_domains->display_core_suspended = true;
3884}
3885
3886/**
3887 * intel_power_domains_resume - resume power domain state
3888 * @dev_priv: i915 device instance
3889 *
3890 * This function resume the hardware power domain state during system resume.
3891 *
3892 * It will return with power domain support disabled (to be enabled later by
3893 * intel_power_domains_enable()) and must be paired with
3894 * intel_power_domains_suspend().
3895 */
3896void intel_power_domains_resume(struct drm_i915_private *dev_priv)
3897{
3898 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3899
3900 if (power_domains->display_core_suspended) {
3901 intel_power_domains_init_hw(dev_priv, true);
3902 power_domains->display_core_suspended = false;
6dfc4a8f
ID		 3903 } else {
3904 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2cd9a689
ID		 3905 }
3906
6dfc4a8f 3907 intel_power_domains_verify_state(dev_priv);
73dfc227
ID		 3908}
3909
6dfc4a8f
ID		 3910#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
3911
8d8c386c
ID		 3912static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
3913{
3914 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3915 struct i915_power_well *power_well;
3916
3917 for_each_power_well(dev_priv, power_well) {
3918 enum intel_display_power_domain domain;
3919
3920 DRM_DEBUG_DRIVER("%-25s %d\n",
f28ec6f4 3921 power_well->desc->name, power_well->count);
8d8c386c 3922
f28ec6f4 3923 for_each_power_domain(domain, power_well->desc->domains)
8d8c386c
ID		 3924 DRM_DEBUG_DRIVER(" %-23s %d\n",
3925 intel_display_power_domain_str(domain),
3926 power_domains->domain_use_count[domain]);
3927 }
3928}
3929
3930/**
3931 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
3932 * @dev_priv: i915 device instance
3933 *
3934 * Verify if the reference count of each power well matches its HW enabled
3935 * state and the total refcount of the domains it belongs to. This must be
3936 * called after modeset HW state sanitization, which is responsible for
3937 * acquiring reference counts for any power wells in use and disabling the
3938 * ones left on by BIOS but not required by any active output.
3939 */
6dfc4a8f 3940static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
8d8c386c
ID		 3941{
3942 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3943 struct i915_power_well *power_well;
3944 bool dump_domain_info;
3945
3946 mutex_lock(&power_domains->lock);
3947
3948 dump_domain_info = false;
3949 for_each_power_well(dev_priv, power_well) {
3950 enum intel_display_power_domain domain;
3951 int domains_count;
3952 bool enabled;
3953
3954 /*
3955 * Power wells not belonging to any domain (like the MISC_IO
3956 * and PW1 power wells) are under FW control, so ignore them,
3957 * since their state can change asynchronously.
3958 */
f28ec6f4 3959 if (!power_well->desc->domains)
8d8c386c
ID		 3960 continue;
3961
f28ec6f4
ID		 3962 enabled = power_well->desc->ops->is_enabled(dev_priv,
3963 power_well);
3964 if ((power_well->count || power_well->desc->always_on) !=
3965 enabled)
8d8c386c 3966 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
f28ec6f4
ID		 3967 power_well->desc->name,
3968 power_well->count, enabled);
8d8c386c
ID		 3969
3970 domains_count = 0;
f28ec6f4 3971 for_each_power_domain(domain, power_well->desc->domains)
8d8c386c
ID		 3972 domains_count += power_domains->domain_use_count[domain];
3973
3974 if (power_well->count != domains_count) {
3975 DRM_ERROR("power well %s refcount/domain refcount mismatch "
3976 "(refcount %d/domains refcount %d)\n",
f28ec6f4 3977 power_well->desc->name, power_well->count,
8d8c386c
ID		 3978 domains_count);
3979 dump_domain_info = true;
3980 }
3981 }
3982
3983 if (dump_domain_info) {
3984 static bool dumped;
3985
3986 if (!dumped) {
3987 intel_power_domains_dump_info(dev_priv);
3988 dumped = true;
3989 }
3990 }
3991
3992 mutex_unlock(&power_domains->lock);
3993}
3994
6dfc4a8f
ID		 3995#else
3996
3997static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
3998{
3999}
4000
4001#endif
4002
e4e7684f
SV		 4003/**
4004 * intel_runtime_pm_get - grab a runtime pm reference
4005 * @dev_priv: i915 device instance
4006 *
4007 * This function grabs a device-level runtime pm reference (mostly used for GEM
4008 * code to ensure the GTT or GT is on) and ensures that it is powered up.
4009 *
4010 * Any runtime pm reference obtained by this function must have a symmetric
4011 * call to intel_runtime_pm_put() to release the reference again.
4012 */
9c065a7d
SV		 4013void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
4014{
52a05c30
DW		 4015 struct pci_dev *pdev = dev_priv->drm.pdev;
4016 struct device *kdev = &pdev->dev;
f5073824 4017 int ret;
9c065a7d 4018
f5073824
ID		 4019 ret = pm_runtime_get_sync(kdev);
4020 WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
1f814dac 4021
ad1443f0 4022 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
c9b8846a 4023 assert_rpm_wakelock_held(dev_priv);
9c065a7d
SV		 4024}
4025
09731280
ID		 4026/**
4027 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
4028 * @dev_priv: i915 device instance
4029 *
4030 * This function grabs a device-level runtime pm reference if the device is
acb79148
CW		 4031 * already in use and ensures that it is powered up. It is illegal to try
4032 * and access the HW should intel_runtime_pm_get_if_in_use() report failure.
09731280
ID		 4033 *
4034 * Any runtime pm reference obtained by this function must have a symmetric
4035 * call to intel_runtime_pm_put() to release the reference again.
acb79148
CW		 4036 *
4037 * Returns: True if the wakeref was acquired, or False otherwise.
09731280
ID		 4038 */
4039bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
4040{
135dc79e 4041 if (IS_ENABLED(CONFIG_PM)) {
acb79148
CW		 4042 struct pci_dev *pdev = dev_priv->drm.pdev;
4043 struct device *kdev = &pdev->dev;
09731280 4044
135dc79e
CW		 4045 /*
4046 * In cases runtime PM is disabled by the RPM core and we get
4047 * an -EINVAL return value we are not supposed to call this
4048 * function, since the power state is undefined. This applies
4049 * atm to the late/early system suspend/resume handlers.
4050 */
acb79148 4051 if (pm_runtime_get_if_in_use(kdev) <= 0)
135dc79e
CW		 4052 return false;
4053 }
09731280 4054
ad1443f0 4055 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
09731280
ID		 4056 assert_rpm_wakelock_held(dev_priv);
4057
4058 return true;
4059}
4060
e4e7684f
SV		 4061/**
4062 * intel_runtime_pm_get_noresume - grab a runtime pm reference
4063 * @dev_priv: i915 device instance
4064 *
4065 * This function grabs a device-level runtime pm reference (mostly used for GEM
4066 * code to ensure the GTT or GT is on).
4067 *
4068 * It will _not_ power up the device but instead only check that it's powered
4069 * on. Therefore it is only valid to call this functions from contexts where
4070 * the device is known to be powered up and where trying to power it up would
4071 * result in hilarity and deadlocks. That pretty much means only the system
4072 * suspend/resume code where this is used to grab runtime pm references for
4073 * delayed setup down in work items.
4074 *
4075 * Any runtime pm reference obtained by this function must have a symmetric
4076 * call to intel_runtime_pm_put() to release the reference again.
4077 */
9c065a7d
SV		 4078void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
4079{
52a05c30
DW		 4080 struct pci_dev *pdev = dev_priv->drm.pdev;
4081 struct device *kdev = &pdev->dev;
9c065a7d 4082
c9b8846a 4083 assert_rpm_wakelock_held(dev_priv);
c49d13ee 4084 pm_runtime_get_noresume(kdev);
1f814dac 4085
ad1443f0 4086 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
9c065a7d
SV		 4087}
4088
e4e7684f
SV		 4089/**
4090 * intel_runtime_pm_put - release a runtime pm reference
4091 * @dev_priv: i915 device instance
4092 *
4093 * This function drops the device-level runtime pm reference obtained by
4094 * intel_runtime_pm_get() and might power down the corresponding
4095 * hardware block right away if this is the last reference.
4096 */
9c065a7d
SV		 4097void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
4098{
52a05c30
DW		 4099 struct pci_dev *pdev = dev_priv->drm.pdev;
4100 struct device *kdev = &pdev->dev;
9c065a7d 4101
542db3cd 4102 assert_rpm_wakelock_held(dev_priv);
ad1443f0 4103 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1f814dac 4104
c49d13ee
DW		 4105 pm_runtime_mark_last_busy(kdev);
4106 pm_runtime_put_autosuspend(kdev);
9c065a7d
SV		 4107}
4108
e4e7684f
SV		 4109/**
4110 * intel_runtime_pm_enable - enable runtime pm
4111 * @dev_priv: i915 device instance
4112 *
4113 * This function enables runtime pm at the end of the driver load sequence.
4114 *
4115 * Note that this function does currently not enable runtime pm for the
2cd9a689
ID		 4116 * subordinate display power domains. That is done by
4117 * intel_power_domains_enable().
e4e7684f 4118 */
f458ebbc 4119void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d 4120{
52a05c30 4121 struct pci_dev *pdev = dev_priv->drm.pdev;
52a05c30 4122 struct device *kdev = &pdev->dev;
9c065a7d 4123
07d80572
CW		 4124 /*
4125 * Disable the system suspend direct complete optimization, which can
4126 * leave the device suspended skipping the driver's suspend handlers
4127 * if the device was already runtime suspended. This is needed due to
4128 * the difference in our runtime and system suspend sequence and
4129 * becaue the HDA driver may require us to enable the audio power
4130 * domain during system suspend.
4131 */
4132 dev_pm_set_driver_flags(kdev, DPM_FLAG_NEVER_SKIP);
4133
c49d13ee
DW		 4134 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
4135 pm_runtime_mark_last_busy(kdev);
cbc68dc9 4136
25b181b4
ID		 4137 /*
4138 * Take a permanent reference to disable the RPM functionality and drop
4139 * it only when unloading the driver. Use the low level get/put helpers,
4140 * so the driver's own RPM reference tracking asserts also work on
4141 * platforms without RPM support.
4142 */
6772ffe0 4143 if (!HAS_RUNTIME_PM(dev_priv)) {
f5073824
ID		 4144 int ret;
4145
c49d13ee 4146 pm_runtime_dont_use_autosuspend(kdev);
f5073824
ID		 4147 ret = pm_runtime_get_sync(kdev);
4148 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
cbc68dc9 4149 } else {
c49d13ee 4150 pm_runtime_use_autosuspend(kdev);
cbc68dc9 4151 }
9c065a7d 4152
aabee1bb
ID		 4153 /*
4154 * The core calls the driver load handler with an RPM reference held.
4155 * We drop that here and will reacquire it during unloading in
4156 * intel_power_domains_fini().
4157 */
c49d13ee 4158 pm_runtime_put_autosuspend(kdev);
9c065a7d 4159}
07d80572
CW		 4160
4161void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
4162{
4163 struct pci_dev *pdev = dev_priv->drm.pdev;
4164 struct device *kdev = &pdev->dev;
4165
4166 /* Transfer rpm ownership back to core */
4167 WARN(pm_runtime_get_sync(&dev_priv->drm.pdev->dev) < 0,
4168 "Failed to pass rpm ownership back to core\n");
4169
4170 pm_runtime_dont_use_autosuspend(kdev);
4171
4172 if (!HAS_RUNTIME_PM(dev_priv))
4173 pm_runtime_put(kdev);
4174}
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