[linux.git] / drivers / gpu / drm / i915 / gvt / mmio_context.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Eddie Dong <[email protected]>
 *    Kevin Tian <[email protected]>
 *
 * Contributors:
 *    Zhi Wang <[email protected]>
 *    Changbin Du <[email protected]>
 *    Zhenyu Wang <[email protected]>
 *    Tina Zhang <[email protected]>
 *    Bing Niu <[email protected]>
 *
 */

#include "i915_drv.h"
#include "gvt.h"
#include "trace.h"

#define GEN9_MOCS_SIZE		64

/* Raw offset is appened to each line for convenience. */
static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */

	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
};

static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */

	{RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
	{RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
	{RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
	{RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
	{RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
	{RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
	{RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
	{RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
	{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
	{RCS, TRVADR, 0, false}, /* 0x4df0 */
	{RCS, TRTTE, 0, false}, /* 0x4df4 */

	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */

	{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */

	{VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */

	{RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	{RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
	{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */

	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */

	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
	{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
};

static struct {
	bool initialized;
	u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
	u32 l3cc_table[GEN9_MOCS_SIZE / 2];
} gen9_render_mocs;

static void load_render_mocs(struct drm_i915_private *dev_priv)
{
	i915_reg_t offset;
	u32 regs[] = {
		[RCS] = 0xc800,
		[VCS] = 0xc900,
		[VCS2] = 0xca00,
		[BCS] = 0xcc00,
		[VECS] = 0xcb00,
	};
	int ring_id, i;

	for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
		if (!HAS_ENGINE(dev_priv, ring_id))
			continue;
		offset.reg = regs[ring_id];
		for (i = 0; i < GEN9_MOCS_SIZE; i++) {
			gen9_render_mocs.control_table[ring_id][i] =
				I915_READ_FW(offset);
			offset.reg += 4;
		}
	}

	offset.reg = 0xb020;
	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
		gen9_render_mocs.l3cc_table[i] =
			I915_READ_FW(offset);
		offset.reg += 4;
	}
	gen9_render_mocs.initialized = true;
}

static int
restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
				 struct i915_request *req)
{
	u32 *cs;
	int ret;
	struct engine_mmio *mmio;
	struct intel_gvt *gvt = vgpu->gvt;
	int ring_id = req->engine->id;
	int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];

	if (count == 0)
		return 0;

	ret = req->engine->emit_flush(req, EMIT_BARRIER);
	if (ret)
		return ret;

	cs = intel_ring_begin(req, count * 2 + 2);
	if (IS_ERR(cs))
		return PTR_ERR(cs);

	*cs++ = MI_LOAD_REGISTER_IMM(count);
	for (mmio = gvt->engine_mmio_list.mmio;
	     i915_mmio_reg_valid(mmio->reg); mmio++) {
		if (mmio->ring_id != ring_id ||
		    !mmio->in_context)
			continue;

		*cs++ = i915_mmio_reg_offset(mmio->reg);
		*cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
				(mmio->mask << 16);
		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
			      *(cs-2), *(cs-1), vgpu->id, ring_id);
	}

	*cs++ = MI_NOOP;
	intel_ring_advance(req, cs);

	ret = req->engine->emit_flush(req, EMIT_BARRIER);
	if (ret)
		return ret;

	return 0;
}

static int
restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
					struct i915_request *req)
{
	unsigned int index;
	u32 *cs;

	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
	if (IS_ERR(cs))
		return PTR_ERR(cs);

	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);

	for (index = 0; index < GEN9_MOCS_SIZE; index++) {
		*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
		*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);

	}

	*cs++ = MI_NOOP;
	intel_ring_advance(req, cs);

	return 0;
}

static int
restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
				     struct i915_request *req)
{
	unsigned int index;
	u32 *cs;

	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
	if (IS_ERR(cs))
		return PTR_ERR(cs);

	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);

	for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
		*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
		*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);

	}

	*cs++ = MI_NOOP;
	intel_ring_advance(req, cs);

	return 0;
}

/*
 * Use lri command to initialize the mmio which is in context state image for
 * inhibit context, it contains tracked engine mmio, render_mocs and
 * render_mocs_l3cc.
 */
int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
				       struct i915_request *req)
{
	int ret;
	u32 *cs;

	cs = intel_ring_begin(req, 2);
	if (IS_ERR(cs))
		return PTR_ERR(cs);

	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
	*cs++ = MI_NOOP;
	intel_ring_advance(req, cs);

	ret = restore_context_mmio_for_inhibit(vgpu, req);
	if (ret)
		goto out;

	/* no MOCS register in context except render engine */
	if (req->engine->id != RCS)
		goto out;

	ret = restore_render_mocs_control_for_inhibit(vgpu, req);
	if (ret)
		goto out;

	ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
	if (ret)
		goto out;

out:
	cs = intel_ring_begin(req, 2);
	if (IS_ERR(cs))
		return PTR_ERR(cs);

	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
	*cs++ = MI_NOOP;
	intel_ring_advance(req, cs);

	return ret;
}

static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	struct intel_vgpu_submission *s = &vgpu->submission;
	enum forcewake_domains fw;
	i915_reg_t reg;
	u32 regs[] = {
		[RCS] = 0x4260,
		[VCS] = 0x4264,
		[VCS2] = 0x4268,
		[BCS] = 0x426c,
		[VECS] = 0x4270,
	};

	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
		return;

	if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
		return;

	reg = _MMIO(regs[ring_id]);

	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
	 * we need to put a forcewake when invalidating RCS TLB caches,
	 * otherwise device can go to RC6 state and interrupt invalidation
	 * process
	 */
	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
					    FW_REG_READ | FW_REG_WRITE);
	if (ring_id == RCS && (IS_SKYLAKE(dev_priv) ||
			IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)))
		fw |= FORCEWAKE_RENDER;

	intel_uncore_forcewake_get(dev_priv, fw);

	I915_WRITE_FW(reg, 0x1);

	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
		gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
	else
		vgpu_vreg_t(vgpu, reg) = 0;

	intel_uncore_forcewake_put(dev_priv, fw);

	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
}

static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
			int ring_id)
{
	struct drm_i915_private *dev_priv;
	i915_reg_t offset, l3_offset;
	u32 old_v, new_v;

	u32 regs[] = {
		[RCS] = 0xc800,
		[VCS] = 0xc900,
		[VCS2] = 0xca00,
		[BCS] = 0xcc00,
		[VECS] = 0xcb00,
	};
	int i;

	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
		return;

	if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)) && ring_id == RCS)
		return;

	if (!pre && !gen9_render_mocs.initialized)
		load_render_mocs(dev_priv);

	offset.reg = regs[ring_id];
	for (i = 0; i < GEN9_MOCS_SIZE; i++) {
		if (pre)
			old_v = vgpu_vreg_t(pre, offset);
		else
			old_v = gen9_render_mocs.control_table[ring_id][i];
		if (next)
			new_v = vgpu_vreg_t(next, offset);
		else
			new_v = gen9_render_mocs.control_table[ring_id][i];

		if (old_v != new_v)
			I915_WRITE_FW(offset, new_v);

		offset.reg += 4;
	}

	if (ring_id == RCS) {
		l3_offset.reg = 0xb020;
		for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
			if (pre)
				old_v = vgpu_vreg_t(pre, l3_offset);
			else
				old_v = gen9_render_mocs.l3cc_table[i];
			if (next)
				new_v = vgpu_vreg_t(next, l3_offset);
			else
				new_v = gen9_render_mocs.l3cc_table[i];

			if (old_v != new_v)
				I915_WRITE_FW(l3_offset, new_v);

			l3_offset.reg += 4;
		}
	}
}

#define CTX_CONTEXT_CONTROL_VAL	0x03

bool is_inhibit_context(struct intel_context *ce)
{
	const u32 *reg_state = ce->lrc_reg_state;
	u32 inhibit_mask =
		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);

	return inhibit_mask ==
		(reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
}

/* Switch ring mmio values (context). */
static void switch_mmio(struct intel_vgpu *pre,
			struct intel_vgpu *next,
			int ring_id)
{
	struct drm_i915_private *dev_priv;
	struct intel_vgpu_submission *s;
	struct engine_mmio *mmio;
	u32 old_v, new_v;

	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
	if (IS_SKYLAKE(dev_priv)
		|| IS_KABYLAKE(dev_priv)
		|| IS_BROXTON(dev_priv))
		switch_mocs(pre, next, ring_id);

	for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
	     i915_mmio_reg_valid(mmio->reg); mmio++) {
		if (mmio->ring_id != ring_id)
			continue;
		/*
		 * No need to do save or restore of the mmio which is in context
		 * state image on kabylake, it's initialized by lri command and
		 * save or restore with context together.
		 */
		if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv))
			&& mmio->in_context)
			continue;

		// save
		if (pre) {
			vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
			if (mmio->mask)
				vgpu_vreg_t(pre, mmio->reg) &=
						~(mmio->mask << 16);
			old_v = vgpu_vreg_t(pre, mmio->reg);
		} else
			old_v = mmio->value = I915_READ_FW(mmio->reg);

		// restore
		if (next) {
			s = &next->submission;
			/*
			 * No need to restore the mmio which is in context state
			 * image if it's not inhibit context, it will restore
			 * itself.
			 */
			if (mmio->in_context &&
			    !is_inhibit_context(&s->shadow_ctx->__engine[ring_id]))
				continue;

			if (mmio->mask)
				new_v = vgpu_vreg_t(next, mmio->reg) |
							(mmio->mask << 16);
			else
				new_v = vgpu_vreg_t(next, mmio->reg);
		} else {
			if (mmio->in_context)
				continue;
			if (mmio->mask)
				new_v = mmio->value | (mmio->mask << 16);
			else
				new_v = mmio->value;
		}

		I915_WRITE_FW(mmio->reg, new_v);

		trace_render_mmio(pre ? pre->id : 0,
				  next ? next->id : 0,
				  "switch",
				  i915_mmio_reg_offset(mmio->reg),
				  old_v, new_v);
	}

	if (next)
		handle_tlb_pending_event(next, ring_id);
}

/**
 * intel_gvt_switch_render_mmio - switch mmio context of specific engine
 * @pre: the last vGPU that own the engine
 * @next: the vGPU to switch to
 * @ring_id: specify the engine
 *
 * If pre is null indicates that host own the engine. If next is null
 * indicates that we are switching to host workload.
 */
void intel_gvt_switch_mmio(struct intel_vgpu *pre,
			   struct intel_vgpu *next, int ring_id)
{
	struct drm_i915_private *dev_priv;

	if (WARN_ON(!pre && !next))
		return;

	gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
		       pre ? "vGPU" : "host", next ? "vGPU" : "HOST");

	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;

	/**
	 * We are using raw mmio access wrapper to improve the
	 * performace for batch mmio read/write, so we need
	 * handle forcewake mannually.
	 */
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
	switch_mmio(pre, next, ring_id);
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

/**
 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
 * @gvt: GVT device
 *
 */
void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
{
	struct engine_mmio *mmio;

	if (IS_SKYLAKE(gvt->dev_priv) ||
		IS_KABYLAKE(gvt->dev_priv) ||
		IS_BROXTON(gvt->dev_priv))
		gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
	else
		gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;

	for (mmio = gvt->engine_mmio_list.mmio;
	     i915_mmio_reg_valid(mmio->reg); mmio++) {
		if (mmio->in_context) {
			gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
			intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
		}
	}
}
Commit	Line	Data
17865713 ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Eddie Dong <[email protected]>
	25	* Kevin Tian <[email protected]>
	26	*
	27	* Contributors:
	28	* Zhi Wang <[email protected]>
	29	* Changbin Du <[email protected]>
	30	* Zhenyu Wang <[email protected]>
	31	* Tina Zhang <[email protected]>
	32	* Bing Niu <[email protected]>
	33	*
	34	*/
	35
	36	#include "i915_drv.h"
feddf6e8	37	#include "gvt.h"
7fb6a7d6	38	#include "trace.h"
17865713	39
f9a651c0 WL	40	#define GEN9_MOCS_SIZE 64
f9a651c0 WL	41
4447f423	42	/* Raw offset is appened to each line for convenience. */
83164886	43	static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
4447f423 CD	44	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	45	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	46	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	47	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	48	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	49	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	50	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	51	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	52	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	53	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	54	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	55	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	56	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	57	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	58	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	59	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	60	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	61	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	62	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	63	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	64	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	65	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
	66
	67	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	68	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	69	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	70	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	71	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
d9df2c09	72	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
17865713 ZW	73	};
17865713 ZW	74
83164886	75	static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
4447f423 CD	76	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	77	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	78	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	79	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	80	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	81	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	82	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	83	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	84	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	85	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	86	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	87	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	88	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	89	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	90	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	91	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	92	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	93	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	94	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	95	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	96	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	97	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
	98
	99	{RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
	100	{RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
	101	{RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
	102	{RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
	103	{RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
	104	{RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
	105	{RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
	106	{RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
	107	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
	108	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
	109	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
37ad4e68	110	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
4447f423 CD	111	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
	112	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
	113	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
	114	{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
	115	{RCS, TRVADR, 0, false}, /* 0x4df0 */
	116	{RCS, TRTTE, 0, false}, /* 0x4df4 */
	117
	118	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	119	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	120	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	121	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	122	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
	123
	124	{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
	125
	126	{VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
	127
	128	{RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
	129	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	130	{RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
	131	{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
	132
	133	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
606a7459	134	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
4447f423 CD	135
	136	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
	137	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
	138	{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
d9df2c09	139	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
17865713 ZW	140	};
17865713 ZW	141
b05b3397 WL	142	static struct {
b05b3397 WL	143	bool initialized;
f9a651c0 WL	144	u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
f9a651c0 WL	145	u32 l3cc_table[GEN9_MOCS_SIZE / 2];
b05b3397 WL	146	} gen9_render_mocs;
	147
	148	static void load_render_mocs(struct drm_i915_private *dev_priv)
	149	{
	150	i915_reg_t offset;
	151	u32 regs[] = {
	152	[RCS] = 0xc800,
	153	[VCS] = 0xc900,
	154	[VCS2] = 0xca00,
	155	[BCS] = 0xcc00,
	156	[VECS] = 0xcb00,
	157	};
	158	int ring_id, i;
	159
8466169a	160	for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
def40774 XL	161	if (!HAS_ENGINE(dev_priv, ring_id))
def40774 XL	162	continue;
b05b3397	163	offset.reg = regs[ring_id];
f9a651c0	164	for (i = 0; i < GEN9_MOCS_SIZE; i++) {
b05b3397 WL	165	gen9_render_mocs.control_table[ring_id][i] =
	166	I915_READ_FW(offset);
	167	offset.reg += 4;
	168	}
	169	}
	170
	171	offset.reg = 0xb020;
f9a651c0	172	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
b05b3397 WL	173	gen9_render_mocs.l3cc_table[i] =
	174	I915_READ_FW(offset);
	175	offset.reg += 4;
	176	}
	177	gen9_render_mocs.initialized = true;
	178	}
17865713	179
cd7e61b9 WL	180	static int
	181	restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
	182	struct i915_request *req)
	183	{
	184	u32 *cs;
	185	int ret;
	186	struct engine_mmio *mmio;
	187	struct intel_gvt *gvt = vgpu->gvt;
	188	int ring_id = req->engine->id;
	189	int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
	190
	191	if (count == 0)
	192	return 0;
	193
	194	ret = req->engine->emit_flush(req, EMIT_BARRIER);
	195	if (ret)
	196	return ret;
	197
	198	cs = intel_ring_begin(req, count * 2 + 2);
	199	if (IS_ERR(cs))
	200	return PTR_ERR(cs);
	201
	202	*cs++ = MI_LOAD_REGISTER_IMM(count);
	203	for (mmio = gvt->engine_mmio_list.mmio;
	204	i915_mmio_reg_valid(mmio->reg); mmio++) {
	205	if (mmio->ring_id != ring_id \|\|
	206	!mmio->in_context)
	207	continue;
	208
	209	*cs++ = i915_mmio_reg_offset(mmio->reg);
	210	*cs++ = vgpu_vreg_t(vgpu, mmio->reg) \|
	211	(mmio->mask << 16);
	212	gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
	213	(cs-2), (cs-1), vgpu->id, ring_id);
	214	}
	215
	216	*cs++ = MI_NOOP;
	217	intel_ring_advance(req, cs);
	218
	219	ret = req->engine->emit_flush(req, EMIT_BARRIER);
	220	if (ret)
	221	return ret;
	222
	223	return 0;
	224	}
	225
	226	static int
	227	restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
	228	struct i915_request *req)
	229	{
	230	unsigned int index;
	231	u32 *cs;
	232
	233	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
	234	if (IS_ERR(cs))
	235	return PTR_ERR(cs);
	236
	237	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
	238
	239	for (index = 0; index < GEN9_MOCS_SIZE; index++) {
	240	*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
	241	*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
	242	gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
	243	(cs-2), (cs-1), vgpu->id, req->engine->id);
244
245	}
246
247	*cs++ = MI_NOOP;
248	intel_ring_advance(req, cs);
249
250	return 0;
251	}
252
253	static int
254	restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
255	struct i915_request *req)
256	{
257	unsigned int index;
258	u32 *cs;
259
260	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
261	if (IS_ERR(cs))
262	return PTR_ERR(cs);
263
264	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
265
266	for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
267	*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
268	*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
269	gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
270	(cs-2), (cs-1), vgpu->id, req->engine->id);
271
272	}
273
274	*cs++ = MI_NOOP;
275	intel_ring_advance(req, cs);
276
277	return 0;
278	}
279
280	/*
281	* Use lri command to initialize the mmio which is in context state image for
282	* inhibit context, it contains tracked engine mmio, render_mocs and
283	* render_mocs_l3cc.
284	*/
285	int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
286	struct i915_request *req)
287	{
288	int ret;
289	u32 *cs;
290
291	cs = intel_ring_begin(req, 2);
292	if (IS_ERR(cs))
293	return PTR_ERR(cs);
294
295	*cs++ = MI_ARB_ON_OFF \| MI_ARB_DISABLE;
296	*cs++ = MI_NOOP;
297	intel_ring_advance(req, cs);
298
299	ret = restore_context_mmio_for_inhibit(vgpu, req);
300	if (ret)
301	goto out;
302
303	/* no MOCS register in context except render engine */
304	if (req->engine->id != RCS)
305	goto out;
306
307	ret = restore_render_mocs_control_for_inhibit(vgpu, req);
308	if (ret)
309	goto out;
310
311	ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
312	if (ret)
313	goto out;
314
315	out:
316	cs = intel_ring_begin(req, 2);
317	if (IS_ERR(cs))
318	return PTR_ERR(cs);
319
320	*cs++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;
321	*cs++ = MI_NOOP;
322	intel_ring_advance(req, cs);
323
324	return ret;
325	}
326
17865713 ZW	327	static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
	328	{
	329	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
91d5d854	330	struct intel_vgpu_submission *s = &vgpu->submission;
1c860a30	331	enum forcewake_domains fw;
17865713 ZW	332	i915_reg_t reg;
	333	u32 regs[] = {
	334	[RCS] = 0x4260,
	335	[VCS] = 0x4264,
	336	[VCS2] = 0x4268,
	337	[BCS] = 0x426c,
	338	[VECS] = 0x4270,
	339	};
	340
	341	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
	342	return;
	343
91d5d854	344	if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
17865713 ZW	345	return;
	346
	347	reg = _MMIO(regs[ring_id]);
	348
1c860a30 AH	349	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
	350	* we need to put a forcewake when invalidating RCS TLB caches,
	351	* otherwise device can go to RC6 state and interrupt invalidation
	352	* process
	353	*/
	354	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
	355	FW_REG_READ \| FW_REG_WRITE);
a94cf2e0 CX	356	if (ring_id == RCS && (IS_SKYLAKE(dev_priv) \|\|
a94cf2e0 CX	357	IS_KABYLAKE(dev_priv) \|\| IS_BROXTON(dev_priv)))
1c860a30	358	fw \|= FORCEWAKE_RENDER;
17865713	359
1c860a30 AH	360	intel_uncore_forcewake_get(dev_priv, fw);
	361
	362	I915_WRITE_FW(reg, 0x1);
	363
	364	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
695fbc08	365	gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
f24940e0	366	else
90551a12	367	vgpu_vreg_t(vgpu, reg) = 0;
17865713	368
1c860a30 AH	369	intel_uncore_forcewake_put(dev_priv, fw);
1c860a30 AH	370
17865713 ZW	371	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
	372	}
	373
e47107ad WL	374	static void switch_mocs(struct intel_vgpu pre, struct intel_vgpu next,
e47107ad WL	375	int ring_id)
17865713	376	{
e47107ad	377	struct drm_i915_private *dev_priv;
17865713	378	i915_reg_t offset, l3_offset;
f402f2d6 WL	379	u32 old_v, new_v;
f402f2d6 WL	380
17865713 ZW	381	u32 regs[] = {
	382	[RCS] = 0xc800,
	383	[VCS] = 0xc900,
	384	[VCS2] = 0xca00,
	385	[BCS] = 0xcc00,
	386	[VECS] = 0xcb00,
	387	};
	388	int i;
	389
e47107ad	390	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
17865713 ZW	391	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
	392	return;
	393
a94cf2e0	394	if ((IS_KABYLAKE(dev_priv) \|\| IS_BROXTON(dev_priv)) && ring_id == RCS)
cd7e61b9 WL	395	return;
cd7e61b9 WL	396
b05b3397 WL	397	if (!pre && !gen9_render_mocs.initialized)
b05b3397 WL	398	load_render_mocs(dev_priv);
17865713	399
b05b3397	400	offset.reg = regs[ring_id];
f9a651c0	401	for (i = 0; i < GEN9_MOCS_SIZE; i++) {
e47107ad	402	if (pre)
90551a12	403	old_v = vgpu_vreg_t(pre, offset);
e47107ad	404	else
b05b3397	405	old_v = gen9_render_mocs.control_table[ring_id][i];
e47107ad	406	if (next)
90551a12	407	new_v = vgpu_vreg_t(next, offset);
e47107ad	408	else
b05b3397	409	new_v = gen9_render_mocs.control_table[ring_id][i];
f402f2d6 WL	410
	411	if (old_v != new_v)
	412	I915_WRITE_FW(offset, new_v);
17865713	413
17865713 ZW	414	offset.reg += 4;
	415	}
	416
	417	if (ring_id == RCS) {
	418	l3_offset.reg = 0xb020;
f9a651c0	419	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
e47107ad	420	if (pre)
90551a12	421	old_v = vgpu_vreg_t(pre, l3_offset);
e47107ad	422	else
b05b3397	423	old_v = gen9_render_mocs.l3cc_table[i];
e47107ad	424	if (next)
90551a12	425	new_v = vgpu_vreg_t(next, l3_offset);
e47107ad	426	else
b05b3397	427	new_v = gen9_render_mocs.l3cc_table[i];
f402f2d6 WL	428
	429	if (old_v != new_v)
	430	I915_WRITE_FW(l3_offset, new_v);
e47107ad	431
17865713 ZW	432	l3_offset.reg += 4;
	433	}
	434	}
	435	}
	436
bc6a1c85 CD	437	#define CTX_CONTEXT_CONTROL_VAL 0x03
bc6a1c85 CD	438
1fc44d9b	439	bool is_inhibit_context(struct intel_context *ce)
64f46f55	440	{
1fc44d9b	441	const u32 *reg_state = ce->lrc_reg_state;
64f46f55 WL	442	u32 inhibit_mask =
	443	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
	444
	445	return inhibit_mask ==
	446	(reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
	447	}
	448
e47107ad WL	449	/* Switch ring mmio values (context). */
	450	static void switch_mmio(struct intel_vgpu *pre,
	451	struct intel_vgpu *next,
	452	int ring_id)
17865713	453	{
e47107ad WL	454	struct drm_i915_private *dev_priv;
e47107ad WL	455	struct intel_vgpu_submission *s;
83164886	456	struct engine_mmio *mmio;
e47107ad	457	u32 old_v, new_v;
17865713	458
e47107ad	459	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
a94cf2e0 CX	460	if (IS_SKYLAKE(dev_priv)
	461	\|\| IS_KABYLAKE(dev_priv)
	462	\|\| IS_BROXTON(dev_priv))
e47107ad	463	switch_mocs(pre, next, ring_id);
17865713	464
cd7e61b9	465	for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
d9df2c09	466	i915_mmio_reg_valid(mmio->reg); mmio++) {
17865713 ZW	467	if (mmio->ring_id != ring_id)
17865713 ZW	468	continue;
cd7e61b9 WL	469	/*
	470	* No need to do save or restore of the mmio which is in context
	471	* state image on kabylake, it's initialized by lri command and
	472	* save or restore with context together.
	473	*/
a94cf2e0 CX	474	if ((IS_KABYLAKE(dev_priv) \|\| IS_BROXTON(dev_priv))
a94cf2e0 CX	475	&& mmio->in_context)
cd7e61b9 WL	476	continue;
cd7e61b9 WL	477
e47107ad WL	478	// save
e47107ad WL	479	if (pre) {
90551a12	480	vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
e47107ad	481	if (mmio->mask)
90551a12	482	vgpu_vreg_t(pre, mmio->reg) &=
e47107ad	483	~(mmio->mask << 16);
90551a12	484	old_v = vgpu_vreg_t(pre, mmio->reg);
17865713	485	} else
e47107ad WL	486	old_v = mmio->value = I915_READ_FW(mmio->reg);
	487
	488	// restore
	489	if (next) {
	490	s = &next->submission;
e47107ad	491	/*
64f46f55 WL	492	* No need to restore the mmio which is in context state
	493	* image if it's not inhibit context, it will restore
	494	* itself.
e47107ad WL	495	*/
e47107ad WL	496	if (mmio->in_context &&
1fc44d9b	497	!is_inhibit_context(&s->shadow_ctx->__engine[ring_id]))
e47107ad WL	498	continue;
	499
	500	if (mmio->mask)
90551a12	501	new_v = vgpu_vreg_t(next, mmio->reg) \|
e47107ad WL	502	(mmio->mask << 16);
e47107ad WL	503	else
90551a12	504	new_v = vgpu_vreg_t(next, mmio->reg);
e47107ad WL	505	} else {
	506	if (mmio->in_context)
	507	continue;
	508	if (mmio->mask)
	509	new_v = mmio->value \| (mmio->mask << 16);
	510	else
	511	new_v = mmio->value;
	512	}
2345ab1d	513
e47107ad	514	I915_WRITE_FW(mmio->reg, new_v);
17865713	515
e47107ad WL	516	trace_render_mmio(pre ? pre->id : 0,
	517	next ? next->id : 0,
	518	"switch",
7fb6a7d6	519	i915_mmio_reg_offset(mmio->reg),
e47107ad	520	old_v, new_v);
17865713	521	}
e47107ad WL	522
	523	if (next)
	524	handle_tlb_pending_event(next, ring_id);
17865713	525	}
0e86cc9c CD	526
	527	/**
	528	* intel_gvt_switch_render_mmio - switch mmio context of specific engine
	529	* @pre: the last vGPU that own the engine
	530	* @next: the vGPU to switch to
	531	* @ring_id: specify the engine
	532	*
	533	* If pre is null indicates that host own the engine. If next is null
	534	* indicates that we are switching to host workload.
	535	*/
	536	void intel_gvt_switch_mmio(struct intel_vgpu *pre,
	537	struct intel_vgpu *next, int ring_id)
	538	{
4671ea20 CD	539	struct drm_i915_private *dev_priv;
4671ea20 CD	540
0e86cc9c CD	541	if (WARN_ON(!pre && !next))
	542	return;
	543
	544	gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
	545	pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
	546
4671ea20 CD	547	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
	548
	549	/**
	550	* We are using raw mmio access wrapper to improve the
	551	* performace for batch mmio read/write, so we need
	552	* handle forcewake mannually.
	553	*/
	554	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
e47107ad	555	switch_mmio(pre, next, ring_id);
4671ea20	556	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0e86cc9c	557	}
83164886 CD	558
	559	/**
	560	* intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
	561	* @gvt: GVT device
	562	*
	563	*/
	564	void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
	565	{
cd7e61b9 WL	566	struct engine_mmio *mmio;
cd7e61b9 WL	567
a94cf2e0 CX	568	if (IS_SKYLAKE(gvt->dev_priv) \|\|
	569	IS_KABYLAKE(gvt->dev_priv) \|\|
	570	IS_BROXTON(gvt->dev_priv))
cd7e61b9	571	gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
83164886	572	else
cd7e61b9 WL	573	gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
	574
	575	for (mmio = gvt->engine_mmio_list.mmio;
	576	i915_mmio_reg_valid(mmio->reg); mmio++) {
6cef21a1	577	if (mmio->in_context) {
cd7e61b9	578	gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
6cef21a1 HY	579	intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
6cef21a1 HY	580	}
cd7e61b9	581	}
83164886	582	}