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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / gpu / drm / i915 / gvt / gtt.c
CommitLineData
2707e444
ZW		 1/*
2 * GTT virtualization
3 *
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Zhi Wang <[email protected]>
27 * Zhenyu Wang <[email protected]>
28 * Xiao Zheng <[email protected]>
29 *
30 * Contributors:
31 * Min He <[email protected]>
32 * Bing Niu <[email protected]>
33 *
34 */
35
36#include "i915_drv.h"
feddf6e8
ZW		 37#include "gvt.h"
38#include "i915_pvinfo.h"
2707e444
ZW		 39#include "trace.h"
40
bc37ab56
CD		 41#if defined(VERBOSE_DEBUG)
42#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
43#else
44#define gvt_vdbg_mm(fmt, args...)
45#endif
46
2707e444
ZW		 47static bool enable_out_of_sync = false;
48static int preallocated_oos_pages = 8192;
49
50/*
51 * validate a gm address and related range size,
52 * translate it to host gm address
53 */
54bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
55{
56 if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
57 && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
695fbc08
TZ		 58 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
59 addr, size);
2707e444
ZW		 60 return false;
61 }
62 return true;
63}
64
65/* translate a guest gmadr to host gmadr */
66int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
67{
68 if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
69 "invalid guest gmadr %llx\n", g_addr))
70 return -EACCES;
71
72 if (vgpu_gmadr_is_aperture(vgpu, g_addr))
73 *h_addr = vgpu_aperture_gmadr_base(vgpu)
74 + (g_addr - vgpu_aperture_offset(vgpu));
75 else
76 *h_addr = vgpu_hidden_gmadr_base(vgpu)
77 + (g_addr - vgpu_hidden_offset(vgpu));
78 return 0;
79}
80
81/* translate a host gmadr to guest gmadr */
82int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
83{
84 if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
85 "invalid host gmadr %llx\n", h_addr))
86 return -EACCES;
87
88 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
89 *g_addr = vgpu_aperture_gmadr_base(vgpu)
90 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
91 else
92 *g_addr = vgpu_hidden_gmadr_base(vgpu)
93 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
94 return 0;
95}
96
97int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
98 unsigned long *h_index)
99{
100 u64 h_addr;
101 int ret;
102
9556e118 103 ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 104 &h_addr);
105 if (ret)
106 return ret;
107
9556e118 108 *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
2707e444
ZW		 109 return 0;
110}
111
112int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
113 unsigned long *g_index)
114{
115 u64 g_addr;
116 int ret;
117
9556e118 118 ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 119 &g_addr);
120 if (ret)
121 return ret;
122
9556e118 123 *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
2707e444
ZW		 124 return 0;
125}
126
127#define gtt_type_is_entry(type) \
128 (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
129 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
130 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
131
132#define gtt_type_is_pt(type) \
133 (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
134
135#define gtt_type_is_pte_pt(type) \
136 (type == GTT_TYPE_PPGTT_PTE_PT)
137
138#define gtt_type_is_root_pointer(type) \
139 (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
140
141#define gtt_init_entry(e, t, p, v) do { \
142 (e)->type = t; \
143 (e)->pdev = p; \
144 memcpy(&(e)->val64, &v, sizeof(v)); \
145} while (0)
146
2707e444
ZW		 147/*
148 * Mappings between GTT_TYPE* enumerations.
149 * Following information can be found according to the given type:
150 * - type of next level page table
151 * - type of entry inside this level page table
152 * - type of entry with PSE set
153 *
154 * If the given type doesn't have such a kind of information,
155 * e.g. give a l4 root entry type, then request to get its PSE type,
156 * give a PTE page table type, then request to get its next level page
157 * table type, as we know l4 root entry doesn't have a PSE bit,
158 * and a PTE page table doesn't have a next level page table type,
159 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
160 * page table.
161 */
162
163struct gtt_type_table_entry {
164 int entry_type;
054f4eba 165 int pt_type;
2707e444
ZW		 166 int next_pt_type;
167 int pse_entry_type;
168};
169
054f4eba 170#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
2707e444
ZW		 171 [type] = { \
172 .entry_type = e_type, \
054f4eba 173 .pt_type = cpt_type, \
2707e444
ZW		 174 .next_pt_type = npt_type, \
175 .pse_entry_type = pse_type, \
176 }
177
178static struct gtt_type_table_entry gtt_type_table[] = {
179 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
180 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
054f4eba 181 GTT_TYPE_INVALID,
2707e444
ZW		 182 GTT_TYPE_PPGTT_PML4_PT,
183 GTT_TYPE_INVALID),
184 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
185 GTT_TYPE_PPGTT_PML4_ENTRY,
054f4eba 186 GTT_TYPE_PPGTT_PML4_PT,
2707e444
ZW		 187 GTT_TYPE_PPGTT_PDP_PT,
188 GTT_TYPE_INVALID),
189 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
190 GTT_TYPE_PPGTT_PML4_ENTRY,
054f4eba 191 GTT_TYPE_PPGTT_PML4_PT,
2707e444
ZW		 192 GTT_TYPE_PPGTT_PDP_PT,
193 GTT_TYPE_INVALID),
194 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
195 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 196 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 197 GTT_TYPE_PPGTT_PDE_PT,
198 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
199 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
200 GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
054f4eba 201 GTT_TYPE_INVALID,
2707e444
ZW		 202 GTT_TYPE_PPGTT_PDE_PT,
203 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
204 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
205 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 206 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 207 GTT_TYPE_PPGTT_PDE_PT,
208 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
209 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
210 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 211 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 212 GTT_TYPE_PPGTT_PTE_PT,
213 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
214 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
215 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 216 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 217 GTT_TYPE_PPGTT_PTE_PT,
218 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
b294657d 219 /* We take IPS bit as 'PSE' for PTE level. */
2707e444
ZW		 220 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
221 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
054f4eba 222 GTT_TYPE_PPGTT_PTE_PT,
2707e444 223 GTT_TYPE_INVALID,
b294657d 224 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
2707e444
ZW		 225 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
226 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
054f4eba 227 GTT_TYPE_PPGTT_PTE_PT,
2707e444 228 GTT_TYPE_INVALID,
b294657d
CD		 229 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
230 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
231 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
232 GTT_TYPE_PPGTT_PTE_PT,
233 GTT_TYPE_INVALID,
234 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
2707e444
ZW		 235 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
236 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 237 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 238 GTT_TYPE_INVALID,
239 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
240 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
241 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 242 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 243 GTT_TYPE_INVALID,
244 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
245 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
246 GTT_TYPE_GGTT_PTE,
247 GTT_TYPE_INVALID,
054f4eba 248 GTT_TYPE_INVALID,
2707e444
ZW		 249 GTT_TYPE_INVALID),
250};
251
252static inline int get_next_pt_type(int type)
253{
254 return gtt_type_table[type].next_pt_type;
255}
256
054f4eba
ZW		 257static inline int get_pt_type(int type)
258{
259 return gtt_type_table[type].pt_type;
260}
261
2707e444
ZW		 262static inline int get_entry_type(int type)
263{
264 return gtt_type_table[type].entry_type;
265}
266
267static inline int get_pse_type(int type)
268{
269 return gtt_type_table[type].pse_entry_type;
270}
271
272static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
273{
321927db 274 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
905a5035
CD		 275
276 return readq(addr);
2707e444
ZW		 277}
278
a143cef7 279static void ggtt_invalidate(struct drm_i915_private *dev_priv)
af2c6399
CD		 280{
281 mmio_hw_access_pre(dev_priv);
282 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
283 mmio_hw_access_post(dev_priv);
284}
285
2707e444
ZW		 286static void write_pte64(struct drm_i915_private *dev_priv,
287 unsigned long index, u64 pte)
288{
321927db 289 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
2707e444 290
2707e444 291 writeq(pte, addr);
2707e444
ZW		 292}
293
4b2dbbc2 294static inline int gtt_get_entry64(void *pt,
2707e444
ZW		 295 struct intel_gvt_gtt_entry *e,
296 unsigned long index, bool hypervisor_access, unsigned long gpa,
297 struct intel_vgpu *vgpu)
298{
299 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
300 int ret;
301
302 if (WARN_ON(info->gtt_entry_size != 8))
4b2dbbc2 303 return -EINVAL;
2707e444
ZW		 304
305 if (hypervisor_access) {
306 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
307 (index << info->gtt_entry_size_shift),
308 &e->val64, 8);
4b2dbbc2
CD		 309 if (WARN_ON(ret))
310 return ret;
2707e444
ZW		 311 } else if (!pt) {
312 e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
313 } else {
314 e->val64 = *((u64 *)pt + index);
315 }
4b2dbbc2 316 return 0;
2707e444
ZW		 317}
318
4b2dbbc2 319static inline int gtt_set_entry64(void *pt,
2707e444
ZW		 320 struct intel_gvt_gtt_entry *e,
321 unsigned long index, bool hypervisor_access, unsigned long gpa,
322 struct intel_vgpu *vgpu)
323{
324 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
325 int ret;
326
327 if (WARN_ON(info->gtt_entry_size != 8))
4b2dbbc2 328 return -EINVAL;
2707e444
ZW		 329
330 if (hypervisor_access) {
331 ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
332 (index << info->gtt_entry_size_shift),
333 &e->val64, 8);
4b2dbbc2
CD		 334 if (WARN_ON(ret))
335 return ret;
2707e444
ZW		 336 } else if (!pt) {
337 write_pte64(vgpu->gvt->dev_priv, index, e->val64);
338 } else {
339 *((u64 *)pt + index) = e->val64;
340 }
4b2dbbc2 341 return 0;
2707e444
ZW		 342}
343
344#define GTT_HAW 46
345
420fba78
CD		 346#define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)
347#define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)
b294657d 348#define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)
420fba78 349#define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
2707e444 350
71634848
CD		 351#define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
352#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
353
4c9414d7
CD		 354#define GTT_64K_PTE_STRIDE 16
355
2707e444
ZW		 356static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
357{
358 unsigned long pfn;
359
360 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
d861ca23 361 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
2707e444 362 else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
d861ca23 363 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
b294657d
CD		 364 else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
365 pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
2707e444 366 else
d861ca23 367 pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
2707e444
ZW		 368 return pfn;
369}
370
371static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
372{
373 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
374 e->val64 &= ~ADDR_1G_MASK;
d861ca23 375 pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
2707e444
ZW		 376 } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
377 e->val64 &= ~ADDR_2M_MASK;
d861ca23 378 pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
b294657d
CD		 379 } else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
380 e->val64 &= ~ADDR_64K_MASK;
381 pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
2707e444
ZW		 382 } else {
383 e->val64 &= ~ADDR_4K_MASK;
d861ca23 384 pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
2707e444
ZW		 385 }
386
d861ca23 387 e->val64 |= (pfn << PAGE_SHIFT);
2707e444
ZW		 388}
389
390static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
391{
40b27176 392 return !!(e->val64 & _PAGE_PSE);
2707e444 393}
2707e444 394
c3e69763
CD		 395static void gen8_gtt_clear_pse(struct intel_gvt_gtt_entry *e)
396{
397 if (gen8_gtt_test_pse(e)) {
398 switch (e->type) {
399 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
400 e->val64 &= ~_PAGE_PSE;
401 e->type = GTT_TYPE_PPGTT_PDE_ENTRY;
402 break;
403 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
404 e->type = GTT_TYPE_PPGTT_PDP_ENTRY;
405 e->val64 &= ~_PAGE_PSE;
406 break;
407 default:
408 WARN_ON(1);
409 }
410 }
411}
412
6fd79378
CD		 413static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
414{
415 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
2707e444
ZW		 416 return false;
417
6fd79378
CD		 418 return !!(e->val64 & GEN8_PDE_IPS_64K);
419}
420
421static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
422{
423 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
424 return;
425
426 e->val64 &= ~GEN8_PDE_IPS_64K;
2707e444
ZW		 427}
428
429static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
430{
431 /*
432 * i915 writes PDP root pointer registers without present bit,
433 * it also works, so we need to treat root pointer entry
434 * specifically.
435 */
436 if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
437 || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
438 return (e->val64 != 0);
439 else
d861ca23 440 return (e->val64 & _PAGE_PRESENT);
2707e444
ZW		 441}
442
443static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
444{
d861ca23 445 e->val64 &= ~_PAGE_PRESENT;
2707e444
ZW		 446}
447
655c64ef
ZW		 448static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
449{
d861ca23 450 e->val64 |= _PAGE_PRESENT;
2707e444
ZW		 451}
452
71634848
CD		 453static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
454{
455 return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
456}
457
458static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
459{
460 e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
461}
462
463static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
464{
465 e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
466}
467
2707e444
ZW		 468/*
469 * Per-platform GMA routines.
470 */
471static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
472{
9556e118 473 unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
2707e444
ZW		 474
475 trace_gma_index(__func__, gma, x);
476 return x;
477}
478
479#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
480static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
481{ \
482 unsigned long x = (exp); \
483 trace_gma_index(__func__, gma, x); \
484 return x; \
485}
486
487DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
488DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
489DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
490DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
491DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
492
493static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
494 .get_entry = gtt_get_entry64,
495 .set_entry = gtt_set_entry64,
496 .clear_present = gtt_entry_clear_present,
655c64ef 497 .set_present = gtt_entry_set_present,
2707e444
ZW		 498 .test_present = gen8_gtt_test_present,
499 .test_pse = gen8_gtt_test_pse,
c3e69763 500 .clear_pse = gen8_gtt_clear_pse,
6fd79378
CD		 501 .clear_ips = gen8_gtt_clear_ips,
502 .test_ips = gen8_gtt_test_ips,
71634848
CD		 503 .clear_64k_splited = gen8_gtt_clear_64k_splited,
504 .set_64k_splited = gen8_gtt_set_64k_splited,
505 .test_64k_splited = gen8_gtt_test_64k_splited,
2707e444
ZW		 506 .get_pfn = gen8_gtt_get_pfn,
507 .set_pfn = gen8_gtt_set_pfn,
508};
509
510static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
511 .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
512 .gma_to_pte_index = gen8_gma_to_pte_index,
513 .gma_to_pde_index = gen8_gma_to_pde_index,
514 .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
515 .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
516 .gma_to_pml4_index = gen8_gma_to_pml4_index,
517};
518
40b27176
CD		 519/* Update entry type per pse and ips bit. */
520static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
521 struct intel_gvt_gtt_entry *entry, bool ips)
522{
523 switch (entry->type) {
524 case GTT_TYPE_PPGTT_PDE_ENTRY:
525 case GTT_TYPE_PPGTT_PDP_ENTRY:
526 if (pte_ops->test_pse(entry))
527 entry->type = get_pse_type(entry->type);
528 break;
529 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
530 if (ips)
531 entry->type = get_pse_type(entry->type);
532 break;
533 default:
534 GEM_BUG_ON(!gtt_type_is_entry(entry->type));
535 }
536
537 GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
538}
539
2707e444
ZW		 540/*
541 * MM helpers.
542 */
3aff3512
CD		 543static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
544 struct intel_gvt_gtt_entry *entry, unsigned long index,
545 bool guest)
2707e444 546{
3aff3512 547 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
2707e444 548
3aff3512 549 GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
2707e444 550
3aff3512
CD		 551 entry->type = mm->ppgtt_mm.root_entry_type;
552 pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
553 mm->ppgtt_mm.shadow_pdps,
554 entry, index, false, 0, mm->vgpu);
40b27176 555 update_entry_type_for_real(pte_ops, entry, false);
2707e444
ZW		 556}
557
3aff3512
CD		 558static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
559 struct intel_gvt_gtt_entry *entry, unsigned long index)
2707e444 560{
3aff3512
CD		 561 _ppgtt_get_root_entry(mm, entry, index, true);
562}
563
564static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
565 struct intel_gvt_gtt_entry *entry, unsigned long index)
566{
567 _ppgtt_get_root_entry(mm, entry, index, false);
568}
569
570static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
571 struct intel_gvt_gtt_entry *entry, unsigned long index,
572 bool guest)
573{
574 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
575
576 pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
577 mm->ppgtt_mm.shadow_pdps,
578 entry, index, false, 0, mm->vgpu);
579}
580
581static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
582 struct intel_gvt_gtt_entry *entry, unsigned long index)
583{
584 _ppgtt_set_root_entry(mm, entry, index, true);
585}
586
587static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
588 struct intel_gvt_gtt_entry *entry, unsigned long index)
589{
590 _ppgtt_set_root_entry(mm, entry, index, false);
591}
592
593static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
594 struct intel_gvt_gtt_entry *entry, unsigned long index)
595{
596 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
597
598 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
599
600 entry->type = GTT_TYPE_GGTT_PTE;
601 pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
602 false, 0, mm->vgpu);
603}
604
605static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
606 struct intel_gvt_gtt_entry *entry, unsigned long index)
607{
608 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
609
610 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
611
612 pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
613 false, 0, mm->vgpu);
614}
615
7598e870
CD		 616static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
617 struct intel_gvt_gtt_entry *entry, unsigned long index)
618{
619 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
620
621 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
622
623 pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
624}
625
3aff3512
CD		 626static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
627 struct intel_gvt_gtt_entry *entry, unsigned long index)
628{
629 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
630
631 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
2707e444 632
3aff3512 633 pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
2707e444
ZW		 634}
635
636/*
637 * PPGTT shadow page table helpers.
638 */
4b2dbbc2 639static inline int ppgtt_spt_get_entry(
2707e444
ZW		 640 struct intel_vgpu_ppgtt_spt *spt,
641 void *page_table, int type,
642 struct intel_gvt_gtt_entry *e, unsigned long index,
643 bool guest)
644{
645 struct intel_gvt *gvt = spt->vgpu->gvt;
646 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
4b2dbbc2 647 int ret;
2707e444
ZW		 648
649 e->type = get_entry_type(type);
650
651 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
4b2dbbc2 652 return -EINVAL;
2707e444 653
4b2dbbc2 654 ret = ops->get_entry(page_table, e, index, guest,
e502a2af 655 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
2707e444 656 spt->vgpu);
4b2dbbc2
CD		 657 if (ret)
658 return ret;
659
40b27176
CD		 660 update_entry_type_for_real(ops, e, guest ?
661 spt->guest_page.pde_ips : false);
bc37ab56
CD		 662
663 gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
664 type, e->type, index, e->val64);
4b2dbbc2 665 return 0;
2707e444
ZW		 666}
667
4b2dbbc2 668static inline int ppgtt_spt_set_entry(
2707e444
ZW		 669 struct intel_vgpu_ppgtt_spt *spt,
670 void *page_table, int type,
671 struct intel_gvt_gtt_entry *e, unsigned long index,
672 bool guest)
673{
674 struct intel_gvt *gvt = spt->vgpu->gvt;
675 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
676
677 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
4b2dbbc2 678 return -EINVAL;
2707e444 679
bc37ab56
CD		 680 gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
681 type, e->type, index, e->val64);
682
2707e444 683 return ops->set_entry(page_table, e, index, guest,
e502a2af 684 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 685 spt->vgpu);
686}
687
688#define ppgtt_get_guest_entry(spt, e, index) \
689 ppgtt_spt_get_entry(spt, NULL, \
44b46733 690 spt->guest_page.type, e, index, true)
2707e444
ZW		 691
692#define ppgtt_set_guest_entry(spt, e, index) \
693 ppgtt_spt_set_entry(spt, NULL, \
44b46733 694 spt->guest_page.type, e, index, true)
2707e444
ZW		 695
696#define ppgtt_get_shadow_entry(spt, e, index) \
697 ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
698 spt->shadow_page.type, e, index, false)
699
700#define ppgtt_set_shadow_entry(spt, e, index) \
701 ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
702 spt->shadow_page.type, e, index, false)
703
44b46733 704static void *alloc_spt(gfp_t gfp_mask)
2707e444 705{
44b46733 706 struct intel_vgpu_ppgtt_spt *spt;
2707e444 707
44b46733
CD		 708 spt = kzalloc(sizeof(*spt), gfp_mask);
709 if (!spt)
710 return NULL;
2707e444 711
44b46733
CD		 712 spt->shadow_page.page = alloc_page(gfp_mask);
713 if (!spt->shadow_page.page) {
714 kfree(spt);
715 return NULL;
716 }
717 return spt;
2707e444
ZW		 718}
719
44b46733 720static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 721{
44b46733
CD		 722 __free_page(spt->shadow_page.page);
723 kfree(spt);
2707e444
ZW		 724}
725
7d1e5cdf
ZW		 726static int detach_oos_page(struct intel_vgpu *vgpu,
727 struct intel_vgpu_oos_page *oos_page);
728
d87f5ff3 729static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 730{
44b46733 731 struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
2707e444 732
44b46733 733 trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
7d1e5cdf 734
44b46733
CD		 735 dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
736 PCI_DMA_BIDIRECTIONAL);
b6c126a3
CD		 737
738 radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
2707e444 739
155521c9
CD		 740 if (spt->guest_page.gfn) {
741 if (spt->guest_page.oos_page)
742 detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
2707e444 743
155521c9
CD		 744 intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
745 }
2707e444 746
2707e444 747 list_del_init(&spt->post_shadow_list);
2707e444
ZW		 748 free_spt(spt);
749}
750
d87f5ff3 751static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
2707e444 752{
44b46733 753 struct intel_vgpu_ppgtt_spt *spt;
b6c126a3
CD		 754 struct radix_tree_iter iter;
755 void **slot;
2707e444 756
b6c126a3
CD		 757 radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
758 spt = radix_tree_deref_slot(slot);
d87f5ff3 759 ppgtt_free_spt(spt);
b6c126a3 760 }
2707e444
ZW		 761}
762
7d1e5cdf 763static int ppgtt_handle_guest_write_page_table_bytes(
44b46733 764 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 765 u64 pa, void *p_data, int bytes);
766
e502a2af
CD		 767static int ppgtt_write_protection_handler(
768 struct intel_vgpu_page_track *page_track,
769 u64 gpa, void *data, int bytes)
2707e444 770{
e502a2af
CD		 771 struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;
772
2707e444
ZW		 773 int ret;
774
775 if (bytes != 4 && bytes != 8)
776 return -EINVAL;
777
e502a2af 778 ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
2707e444
ZW		 779 if (ret)
780 return ret;
781 return ret;
782}
783
44b46733
CD		 784/* Find a spt by guest gfn. */
785static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
786 struct intel_vgpu *vgpu, unsigned long gfn)
787{
788 struct intel_vgpu_page_track *track;
789
e502a2af
CD		 790 track = intel_vgpu_find_page_track(vgpu, gfn);
791 if (track && track->handler == ppgtt_write_protection_handler)
792 return track->priv_data;
44b46733
CD		 793
794 return NULL;
795}
796
797/* Find the spt by shadow page mfn. */
b6c126a3 798static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
44b46733
CD		 799 struct intel_vgpu *vgpu, unsigned long mfn)
800{
b6c126a3 801 return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
44b46733
CD		 802}
803
ede9d0cf 804static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
2707e444 805
155521c9 806/* Allocate shadow page table without guest page. */
d87f5ff3 807static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
155521c9 808 struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type)
2707e444 809{
44b46733 810 struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2707e444 811 struct intel_vgpu_ppgtt_spt *spt = NULL;
44b46733 812 dma_addr_t daddr;
e502a2af 813 int ret;
2707e444
ZW		 814
815retry:
816 spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
817 if (!spt) {
ede9d0cf 818 if (reclaim_one_ppgtt_mm(vgpu->gvt))
2707e444
ZW		 819 goto retry;
820
695fbc08 821 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
2707e444
ZW		 822 return ERR_PTR(-ENOMEM);
823 }
824
825 spt->vgpu = vgpu;
2707e444
ZW		 826 atomic_set(&spt->refcount, 1);
827 INIT_LIST_HEAD(&spt->post_shadow_list);
828
829 /*
44b46733 830 * Init shadow_page.
2707e444 831 */
44b46733
CD		 832 spt->shadow_page.type = type;
833 daddr = dma_map_page(kdev, spt->shadow_page.page,
834 0, 4096, PCI_DMA_BIDIRECTIONAL);
835 if (dma_mapping_error(kdev, daddr)) {
836 gvt_vgpu_err("fail to map dma addr\n");
b6c126a3
CD		 837 ret = -EINVAL;
838 goto err_free_spt;
2707e444 839 }
44b46733
CD		 840 spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
841 spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
2707e444 842
b6c126a3
CD		 843 ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
844 if (ret)
155521c9 845 goto err_unmap_dma;
2707e444 846
44b46733 847 return spt;
b6c126a3 848
b6c126a3
CD		 849err_unmap_dma:
850 dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
851err_free_spt:
852 free_spt(spt);
853 return ERR_PTR(ret);
2707e444
ZW		 854}
855
155521c9
CD		 856/* Allocate shadow page table associated with specific gfn. */
857static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt_gfn(
858 struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type,
859 unsigned long gfn, bool guest_pde_ips)
860{
861 struct intel_vgpu_ppgtt_spt *spt;
862 int ret;
863
864 spt = ppgtt_alloc_spt(vgpu, type);
865 if (IS_ERR(spt))
866 return spt;
867
868 /*
869 * Init guest_page.
870 */
871 ret = intel_vgpu_register_page_track(vgpu, gfn,
872 ppgtt_write_protection_handler, spt);
873 if (ret) {
874 ppgtt_free_spt(spt);
875 return ERR_PTR(ret);
876 }
877
878 spt->guest_page.type = type;
879 spt->guest_page.gfn = gfn;
880 spt->guest_page.pde_ips = guest_pde_ips;
881
882 trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
883
884 return spt;
885}
886
2707e444
ZW		 887#define pt_entry_size_shift(spt) \
888 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
889
890#define pt_entries(spt) \
9556e118 891 (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
2707e444
ZW		 892
893#define for_each_present_guest_entry(spt, e, i) \
4c9414d7
CD		 894 for (i = 0; i < pt_entries(spt); \
895 i += spt->guest_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
4b2dbbc2
CD		 896 if (!ppgtt_get_guest_entry(spt, e, i) && \
897 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
2707e444
ZW		 898
899#define for_each_present_shadow_entry(spt, e, i) \
4c9414d7
CD		 900 for (i = 0; i < pt_entries(spt); \
901 i += spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
4b2dbbc2
CD		 902 if (!ppgtt_get_shadow_entry(spt, e, i) && \
903 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
2707e444 904
b901b252
CD		 905#define for_each_shadow_entry(spt, e, i) \
906 for (i = 0; i < pt_entries(spt); \
907 i += (spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1)) \
908 if (!ppgtt_get_shadow_entry(spt, e, i))
909
80e76ea6 910static inline void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 911{
912 int v = atomic_read(&spt->refcount);
913
914 trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
2707e444
ZW		 915 atomic_inc(&spt->refcount);
916}
917
80e76ea6
CD		 918static inline int ppgtt_put_spt(struct intel_vgpu_ppgtt_spt *spt)
919{
920 int v = atomic_read(&spt->refcount);
921
922 trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
923 return atomic_dec_return(&spt->refcount);
924}
925
d87f5ff3 926static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
2707e444 927
d87f5ff3 928static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
2707e444
ZW		 929 struct intel_gvt_gtt_entry *e)
930{
931 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
932 struct intel_vgpu_ppgtt_spt *s;
3b6411c2 933 intel_gvt_gtt_type_t cur_pt_type;
2707e444 934
72f03d7e 935 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
2707e444 936
3b6411c2
PG		 937 if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
938 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
939 cur_pt_type = get_next_pt_type(e->type) + 1;
940 if (ops->get_pfn(e) ==
941 vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
942 return 0;
943 }
44b46733 944 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2707e444 945 if (!s) {
695fbc08
TZ		 946 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
947 ops->get_pfn(e));
2707e444
ZW		 948 return -ENXIO;
949 }
d87f5ff3 950 return ppgtt_invalidate_spt(s);
2707e444
ZW		 951}
952
cf4ee73f
CD		 953static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
954 struct intel_gvt_gtt_entry *entry)
955{
956 struct intel_vgpu *vgpu = spt->vgpu;
957 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
958 unsigned long pfn;
959 int type;
960
961 pfn = ops->get_pfn(entry);
962 type = spt->shadow_page.type;
963
b901b252
CD		 964 /* Uninitialized spte or unshadowed spte. */
965 if (!pfn || pfn == vgpu->gtt.scratch_pt[type].page_mfn)
cf4ee73f
CD		 966 return;
967
968 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
969}
970
d87f5ff3 971static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 972{
695fbc08 973 struct intel_vgpu *vgpu = spt->vgpu;
2707e444
ZW		 974 struct intel_gvt_gtt_entry e;
975 unsigned long index;
976 int ret;
2707e444
ZW		 977
978 trace_spt_change(spt->vgpu->id, "die", spt,
44b46733 979 spt->guest_page.gfn, spt->shadow_page.type);
2707e444 980
80e76ea6 981 if (ppgtt_put_spt(spt) > 0)
2707e444
ZW		 982 return 0;
983
2707e444 984 for_each_present_shadow_entry(spt, &e, index) {
72f03d7e
CD		 985 switch (e.type) {
986 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
987 gvt_vdbg_mm("invalidate 4K entry\n");
cf4ee73f
CD		 988 ppgtt_invalidate_pte(spt, &e);
989 break;
b294657d 990 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
eb3a3530
CD		 991 /* We don't setup 64K shadow entry so far. */
992 WARN(1, "suspicious 64K gtt entry\n");
993 continue;
72f03d7e 994 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
b901b252
CD		 995 gvt_vdbg_mm("invalidate 2M entry\n");
996 continue;
72f03d7e 997 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
b901b252 998 WARN(1, "GVT doesn't support 1GB page\n");
72f03d7e
CD		 999 continue;
1000 case GTT_TYPE_PPGTT_PML4_ENTRY:
1001 case GTT_TYPE_PPGTT_PDP_ENTRY:
1002 case GTT_TYPE_PPGTT_PDE_ENTRY:
1003 gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
d87f5ff3 1004 ret = ppgtt_invalidate_spt_by_shadow_entry(
72f03d7e
CD		 1005 spt->vgpu, &e);
1006 if (ret)
1007 goto fail;
1008 break;
1009 default:
1010 GEM_BUG_ON(1);
2707e444 1011 }
2707e444 1012 }
cf4ee73f 1013
2707e444 1014 trace_spt_change(spt->vgpu->id, "release", spt,
44b46733 1015 spt->guest_page.gfn, spt->shadow_page.type);
d87f5ff3 1016 ppgtt_free_spt(spt);
2707e444
ZW		 1017 return 0;
1018fail:
695fbc08
TZ		 1019 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
1020 spt, e.val64, e.type);
2707e444
ZW		 1021 return ret;
1022}
1023
40b27176
CD		 1024static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
1025{
1026 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1027
1028 if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
1029 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
1030 GAMW_ECO_ENABLE_64K_IPS_FIELD;
1031
1032 return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
1033 } else if (INTEL_GEN(dev_priv) >= 11) {
1034 /* 64K paging only controlled by IPS bit in PTE now. */
1035 return true;
1036 } else
1037 return false;
1038}
1039
d87f5ff3 1040static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
2707e444 1041
d87f5ff3 1042static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
2707e444
ZW		 1043 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
1044{
1045 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
44b46733 1046 struct intel_vgpu_ppgtt_spt *spt = NULL;
40b27176 1047 bool ips = false;
2707e444
ZW		 1048 int ret;
1049
72f03d7e 1050 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
2707e444 1051
54c81653
CD		 1052 if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1053 ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);
1054
44b46733 1055 spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
54c81653 1056 if (spt) {
d87f5ff3 1057 ppgtt_get_spt(spt);
2707e444 1058
54c81653
CD		 1059 if (ips != spt->guest_page.pde_ips) {
1060 spt->guest_page.pde_ips = ips;
1061
1062 gvt_dbg_mm("reshadow PDE since ips changed\n");
1063 clear_page(spt->shadow_page.vaddr);
1064 ret = ppgtt_populate_spt(spt);
80e76ea6
CD		 1065 if (ret) {
1066 ppgtt_put_spt(spt);
1067 goto err;
1068 }
54c81653
CD		 1069 }
1070 } else {
2707e444
ZW		 1071 int type = get_next_pt_type(we->type);
1072
155521c9 1073 spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
44b46733
CD		 1074 if (IS_ERR(spt)) {
1075 ret = PTR_ERR(spt);
80e76ea6 1076 goto err;
2707e444
ZW		 1077 }
1078
e502a2af 1079 ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
2707e444 1080 if (ret)
80e76ea6 1081 goto err_free_spt;
2707e444 1082
d87f5ff3 1083 ret = ppgtt_populate_spt(spt);
2707e444 1084 if (ret)
80e76ea6 1085 goto err_free_spt;
2707e444 1086
44b46733
CD		 1087 trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
1088 spt->shadow_page.type);
2707e444 1089 }
44b46733 1090 return spt;
80e76ea6
CD		 1091
1092err_free_spt:
1093 ppgtt_free_spt(spt);
1094err:
695fbc08 1095 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
44b46733 1096 spt, we->val64, we->type);
2707e444
ZW		 1097 return ERR_PTR(ret);
1098}
1099
1100static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
1101 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
1102{
1103 struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1104
1105 se->type = ge->type;
1106 se->val64 = ge->val64;
1107
eb3a3530
CD		 1108 /* Because we always split 64KB pages, so clear IPS in shadow PDE. */
1109 if (se->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1110 ops->clear_ips(se);
1111
2707e444
ZW		 1112 ops->set_pfn(se, s->shadow_page.mfn);
1113}
1114
b901b252 1115/**
a752b070
ZW		 1116 * Check if can do 2M page
1117 * @vgpu: target vgpu
1118 * @entry: target pfn's gtt entry
1119 *
b901b252
CD		 1120 * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
1121 * negtive if found err.
1122 */
1123static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
1124 struct intel_gvt_gtt_entry *entry)
1125{
1126 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1127 unsigned long pfn;
1128
1129 if (!HAS_PAGE_SIZES(vgpu->gvt->dev_priv, I915_GTT_PAGE_SIZE_2M))
1130 return 0;
1131
1132 pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, ops->get_pfn(entry));
1133 if (pfn == INTEL_GVT_INVALID_ADDR)
1134 return -EINVAL;
1135
1136 return PageTransHuge(pfn_to_page(pfn));
1137}
1138
1139static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
1140 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1141 struct intel_gvt_gtt_entry *se)
1142{
1143 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1144 struct intel_vgpu_ppgtt_spt *sub_spt;
1145 struct intel_gvt_gtt_entry sub_se;
1146 unsigned long start_gfn;
1147 dma_addr_t dma_addr;
1148 unsigned long sub_index;
1149 int ret;
1150
1151 gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
1152
1153 start_gfn = ops->get_pfn(se);
1154
1155 sub_spt = ppgtt_alloc_spt(vgpu, GTT_TYPE_PPGTT_PTE_PT);
1156 if (IS_ERR(sub_spt))
1157 return PTR_ERR(sub_spt);
1158
1159 for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
1160 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu,
1161 start_gfn + sub_index, PAGE_SIZE, &dma_addr);
1162 if (ret) {
1163 ppgtt_invalidate_spt(spt);
1164 return ret;
1165 }
1166 sub_se.val64 = se->val64;
1167
1168 /* Copy the PAT field from PDE. */
1169 sub_se.val64 &= ~_PAGE_PAT;
1170 sub_se.val64 |= (se->val64 & _PAGE_PAT_LARGE) >> 5;
1171
1172 ops->set_pfn(&sub_se, dma_addr >> PAGE_SHIFT);
1173 ppgtt_set_shadow_entry(sub_spt, &sub_se, sub_index);
1174 }
1175
1176 /* Clear dirty field. */
1177 se->val64 &= ~_PAGE_DIRTY;
1178
1179 ops->clear_pse(se);
1180 ops->clear_ips(se);
1181 ops->set_pfn(se, sub_spt->shadow_page.mfn);
1182 ppgtt_set_shadow_entry(spt, se, index);
1183 return 0;
1184}
1185
eb3a3530
CD		 1186static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
1187 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1188 struct intel_gvt_gtt_entry *se)
1189{
1190 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1191 struct intel_gvt_gtt_entry entry = *se;
1192 unsigned long start_gfn;
1193 dma_addr_t dma_addr;
1194 int i, ret;
1195
1196 gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1197
1198 GEM_BUG_ON(index % GTT_64K_PTE_STRIDE);
1199
1200 start_gfn = ops->get_pfn(se);
1201
1202 entry.type = GTT_TYPE_PPGTT_PTE_4K_ENTRY;
1203 ops->set_64k_splited(&entry);
1204
1205 for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1206 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu,
79e542f5 1207 start_gfn + i, PAGE_SIZE, &dma_addr);
eb3a3530
CD		 1208 if (ret)
1209 return ret;
1210
1211 ops->set_pfn(&entry, dma_addr >> PAGE_SHIFT);
1212 ppgtt_set_shadow_entry(spt, &entry, index + i);
1213 }
1214 return 0;
1215}
1216
72f03d7e
CD		 1217static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
1218 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1219 struct intel_gvt_gtt_entry *ge)
1220{
1221 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1222 struct intel_gvt_gtt_entry se = *ge;
b901b252 1223 unsigned long gfn, page_size = PAGE_SIZE;
cf4ee73f
CD		 1224 dma_addr_t dma_addr;
1225 int ret;
72f03d7e
CD		 1226
1227 if (!pte_ops->test_present(ge))
1228 return 0;
1229
1230 gfn = pte_ops->get_pfn(ge);
1231
1232 switch (ge->type) {
1233 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1234 gvt_vdbg_mm("shadow 4K gtt entry\n");
1235 break;
b294657d 1236 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
eb3a3530
CD		 1237 gvt_vdbg_mm("shadow 64K gtt entry\n");
1238 /*
1239 * The layout of 64K page is special, the page size is
1240 * controlled by uper PDE. To be simple, we always split
1241 * 64K page to smaller 4K pages in shadow PT.
1242 */
1243 return split_64KB_gtt_entry(vgpu, spt, index, &se);
72f03d7e 1244 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
b901b252
CD		 1245 gvt_vdbg_mm("shadow 2M gtt entry\n");
1246 ret = is_2MB_gtt_possible(vgpu, ge);
1247 if (ret == 0)
1248 return split_2MB_gtt_entry(vgpu, spt, index, &se);
1249 else if (ret < 0)
1250 return ret;
1251 page_size = I915_GTT_PAGE_SIZE_2M;
1252 break;
72f03d7e 1253 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
b901b252 1254 gvt_vgpu_err("GVT doesn't support 1GB entry\n");
72f03d7e
CD		 1255 return -EINVAL;
1256 default:
1257 GEM_BUG_ON(1);
1258 };
1259
1260 /* direct shadow */
b901b252
CD		 1261 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, page_size,
1262 &dma_addr);
cf4ee73f 1263 if (ret)
72f03d7e
CD		 1264 return -ENXIO;
1265
cf4ee73f 1266 pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
72f03d7e
CD		 1267 ppgtt_set_shadow_entry(spt, &se, index);
1268 return 0;
1269}
1270
d87f5ff3 1271static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 1272{
1273 struct intel_vgpu *vgpu = spt->vgpu;
cc753fbe
HY		 1274 struct intel_gvt *gvt = vgpu->gvt;
1275 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2707e444
ZW		 1276 struct intel_vgpu_ppgtt_spt *s;
1277 struct intel_gvt_gtt_entry se, ge;
cc753fbe 1278 unsigned long gfn, i;
2707e444
ZW		 1279 int ret;
1280
1281 trace_spt_change(spt->vgpu->id, "born", spt,
e502a2af 1282 spt->guest_page.gfn, spt->shadow_page.type);
2707e444 1283
72f03d7e
CD		 1284 for_each_present_guest_entry(spt, &ge, i) {
1285 if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
d87f5ff3 1286 s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
72f03d7e
CD		 1287 if (IS_ERR(s)) {
1288 ret = PTR_ERR(s);
1289 goto fail;
1290 }
1291 ppgtt_get_shadow_entry(spt, &se, i);
1292 ppgtt_generate_shadow_entry(&se, s, &ge);
1293 ppgtt_set_shadow_entry(spt, &se, i);
1294 } else {
cc753fbe 1295 gfn = ops->get_pfn(&ge);
72f03d7e 1296 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
cc753fbe 1297 ops->set_pfn(&se, gvt->gtt.scratch_mfn);
72f03d7e
CD		 1298 ppgtt_set_shadow_entry(spt, &se, i);
1299 continue;
1300 }
2707e444 1301
72f03d7e
CD		 1302 ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
1303 if (ret)
1304 goto fail;
2707e444 1305 }
2707e444
ZW		 1306 }
1307 return 0;
1308fail:
695fbc08
TZ		 1309 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1310 spt, ge.val64, ge.type);
2707e444
ZW		 1311 return ret;
1312}
1313
44b46733 1314static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
6b3816d6 1315 struct intel_gvt_gtt_entry *se, unsigned long index)
2707e444 1316{
2707e444
ZW		 1317 struct intel_vgpu *vgpu = spt->vgpu;
1318 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2707e444
ZW		 1319 int ret;
1320
44b46733
CD		 1321 trace_spt_guest_change(spt->vgpu->id, "remove", spt,
1322 spt->shadow_page.type, se->val64, index);
9baf0920 1323
bc37ab56
CD		 1324 gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1325 se->type, index, se->val64);
1326
6b3816d6 1327 if (!ops->test_present(se))
2707e444
ZW		 1328 return 0;
1329
44b46733
CD		 1330 if (ops->get_pfn(se) ==
1331 vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
2707e444
ZW		 1332 return 0;
1333
6b3816d6 1334 if (gtt_type_is_pt(get_next_pt_type(se->type))) {
9baf0920 1335 struct intel_vgpu_ppgtt_spt *s =
44b46733 1336 intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
9baf0920 1337 if (!s) {
695fbc08 1338 gvt_vgpu_err("fail to find guest page\n");
2707e444
ZW		 1339 ret = -ENXIO;
1340 goto fail;
1341 }
d87f5ff3 1342 ret = ppgtt_invalidate_spt(s);
2707e444
ZW		 1343 if (ret)
1344 goto fail;
eb3a3530
CD		 1345 } else {
1346 /* We don't setup 64K shadow entry so far. */
1347 WARN(se->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY,
1348 "suspicious 64K entry\n");
cf4ee73f 1349 ppgtt_invalidate_pte(spt, se);
eb3a3530 1350 }
cf4ee73f 1351
2707e444
ZW		 1352 return 0;
1353fail:
695fbc08 1354 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
6b3816d6 1355 spt, se->val64, se->type);
2707e444
ZW		 1356 return ret;
1357}
1358
44b46733 1359static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1360 struct intel_gvt_gtt_entry *we, unsigned long index)
1361{
2707e444
ZW		 1362 struct intel_vgpu *vgpu = spt->vgpu;
1363 struct intel_gvt_gtt_entry m;
1364 struct intel_vgpu_ppgtt_spt *s;
1365 int ret;
1366
44b46733
CD		 1367 trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
1368 we->val64, index);
2707e444 1369
bc37ab56
CD		 1370 gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1371 we->type, index, we->val64);
1372
2707e444 1373 if (gtt_type_is_pt(get_next_pt_type(we->type))) {
d87f5ff3 1374 s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
2707e444
ZW		 1375 if (IS_ERR(s)) {
1376 ret = PTR_ERR(s);
1377 goto fail;
1378 }
1379 ppgtt_get_shadow_entry(spt, &m, index);
1380 ppgtt_generate_shadow_entry(&m, s, we);
1381 ppgtt_set_shadow_entry(spt, &m, index);
1382 } else {
72f03d7e 1383 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
2707e444
ZW		 1384 if (ret)
1385 goto fail;
2707e444
ZW		 1386 }
1387 return 0;
1388fail:
695fbc08
TZ		 1389 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1390 spt, we->val64, we->type);
2707e444
ZW		 1391 return ret;
1392}
1393
1394static int sync_oos_page(struct intel_vgpu *vgpu,
1395 struct intel_vgpu_oos_page *oos_page)
1396{
1397 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1398 struct intel_gvt *gvt = vgpu->gvt;
1399 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
44b46733 1400 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
72f03d7e 1401 struct intel_gvt_gtt_entry old, new;
2707e444
ZW		 1402 int index;
1403 int ret;
1404
1405 trace_oos_change(vgpu->id, "sync", oos_page->id,
44b46733 1406 spt, spt->guest_page.type);
2707e444 1407
44b46733 1408 old.type = new.type = get_entry_type(spt->guest_page.type);
2707e444
ZW		 1409 old.val64 = new.val64 = 0;
1410
9556e118
ZW		 1411 for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1412 info->gtt_entry_size_shift); index++) {
2707e444
ZW		 1413 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1414 ops->get_entry(NULL, &new, index, true,
44b46733 1415 spt->guest_page.gfn << PAGE_SHIFT, vgpu);
2707e444
ZW		 1416
1417 if (old.val64 == new.val64
1418 && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1419 continue;
1420
1421 trace_oos_sync(vgpu->id, oos_page->id,
44b46733 1422 spt, spt->guest_page.type,
2707e444
ZW		 1423 new.val64, index);
1424
72f03d7e 1425 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
2707e444
ZW		 1426 if (ret)
1427 return ret;
1428
1429 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
2707e444
ZW		 1430 }
1431
44b46733 1432 spt->guest_page.write_cnt = 0;
2707e444
ZW		 1433 list_del_init(&spt->post_shadow_list);
1434 return 0;
1435}
1436
1437static int detach_oos_page(struct intel_vgpu *vgpu,
1438 struct intel_vgpu_oos_page *oos_page)
1439{
1440 struct intel_gvt *gvt = vgpu->gvt;
44b46733 1441 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
2707e444
ZW		 1442
1443 trace_oos_change(vgpu->id, "detach", oos_page->id,
44b46733 1444 spt, spt->guest_page.type);
2707e444 1445
44b46733
CD		 1446 spt->guest_page.write_cnt = 0;
1447 spt->guest_page.oos_page = NULL;
1448 oos_page->spt = NULL;
2707e444
ZW		 1449
1450 list_del_init(&oos_page->vm_list);
1451 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1452
1453 return 0;
1454}
1455
44b46733
CD		 1456static int attach_oos_page(struct intel_vgpu_oos_page *oos_page,
1457 struct intel_vgpu_ppgtt_spt *spt)
2707e444 1458{
44b46733 1459 struct intel_gvt *gvt = spt->vgpu->gvt;
2707e444
ZW		 1460 int ret;
1461
44b46733
CD		 1462 ret = intel_gvt_hypervisor_read_gpa(spt->vgpu,
1463 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
9556e118 1464 oos_page->mem, I915_GTT_PAGE_SIZE);
2707e444
ZW		 1465 if (ret)
1466 return ret;
1467
44b46733
CD		 1468 oos_page->spt = spt;
1469 spt->guest_page.oos_page = oos_page;
2707e444
ZW		 1470
1471 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1472
44b46733
CD		 1473 trace_oos_change(spt->vgpu->id, "attach", oos_page->id,
1474 spt, spt->guest_page.type);
2707e444
ZW		 1475 return 0;
1476}
1477
44b46733 1478static int ppgtt_set_guest_page_sync(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1479{
44b46733 1480 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1481 int ret;
1482
e502a2af 1483 ret = intel_vgpu_enable_page_track(spt->vgpu, spt->guest_page.gfn);
2707e444
ZW		 1484 if (ret)
1485 return ret;
1486
44b46733
CD		 1487 trace_oos_change(spt->vgpu->id, "set page sync", oos_page->id,
1488 spt, spt->guest_page.type);
2707e444 1489
44b46733
CD		 1490 list_del_init(&oos_page->vm_list);
1491 return sync_oos_page(spt->vgpu, oos_page);
2707e444
ZW		 1492}
1493
44b46733 1494static int ppgtt_allocate_oos_page(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1495{
44b46733 1496 struct intel_gvt *gvt = spt->vgpu->gvt;
2707e444 1497 struct intel_gvt_gtt *gtt = &gvt->gtt;
44b46733 1498 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1499 int ret;
1500
1501 WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1502
1503 if (list_empty(&gtt->oos_page_free_list_head)) {
1504 oos_page = container_of(gtt->oos_page_use_list_head.next,
1505 struct intel_vgpu_oos_page, list);
44b46733 1506 ret = ppgtt_set_guest_page_sync(oos_page->spt);
2707e444
ZW		 1507 if (ret)
1508 return ret;
44b46733 1509 ret = detach_oos_page(spt->vgpu, oos_page);
2707e444
ZW		 1510 if (ret)
1511 return ret;
1512 } else
1513 oos_page = container_of(gtt->oos_page_free_list_head.next,
1514 struct intel_vgpu_oos_page, list);
44b46733 1515 return attach_oos_page(oos_page, spt);
2707e444
ZW		 1516}
1517
44b46733 1518static int ppgtt_set_guest_page_oos(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1519{
44b46733 1520 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1521
1522 if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1523 return -EINVAL;
1524
44b46733
CD		 1525 trace_oos_change(spt->vgpu->id, "set page out of sync", oos_page->id,
1526 spt, spt->guest_page.type);
2707e444 1527
44b46733 1528 list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
e502a2af 1529 return intel_vgpu_disable_page_track(spt->vgpu, spt->guest_page.gfn);
2707e444
ZW		 1530}
1531
1532/**
1533 * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1534 * @vgpu: a vGPU
1535 *
1536 * This function is called before submitting a guest workload to host,
1537 * to sync all the out-of-synced shadow for vGPU
1538 *
1539 * Returns:
1540 * Zero on success, negative error code if failed.
1541 */
1542int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1543{
1544 struct list_head *pos, *n;
1545 struct intel_vgpu_oos_page *oos_page;
1546 int ret;
1547
1548 if (!enable_out_of_sync)
1549 return 0;
1550
1551 list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1552 oos_page = container_of(pos,
1553 struct intel_vgpu_oos_page, vm_list);
44b46733 1554 ret = ppgtt_set_guest_page_sync(oos_page->spt);
2707e444
ZW		 1555 if (ret)
1556 return ret;
1557 }
1558 return 0;
1559}
1560
1561/*
1562 * The heart of PPGTT shadow page table.
1563 */
1564static int ppgtt_handle_guest_write_page_table(
44b46733 1565 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1566 struct intel_gvt_gtt_entry *we, unsigned long index)
1567{
2707e444 1568 struct intel_vgpu *vgpu = spt->vgpu;
6b3816d6 1569 int type = spt->shadow_page.type;
2707e444 1570 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
72f03d7e 1571 struct intel_gvt_gtt_entry old_se;
9baf0920 1572 int new_present;
eb3a3530 1573 int i, ret;
2707e444 1574
2707e444
ZW		 1575 new_present = ops->test_present(we);
1576
6b3816d6
TZ		 1577 /*
1578 * Adding the new entry first and then removing the old one, that can
1579 * guarantee the ppgtt table is validated during the window between
1580 * adding and removal.
1581 */
72f03d7e 1582 ppgtt_get_shadow_entry(spt, &old_se, index);
2707e444 1583
2707e444 1584 if (new_present) {
44b46733 1585 ret = ppgtt_handle_guest_entry_add(spt, we, index);
2707e444
ZW		 1586 if (ret)
1587 goto fail;
1588 }
6b3816d6 1589
44b46733 1590 ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
6b3816d6
TZ		 1591 if (ret)
1592 goto fail;
1593
1594 if (!new_present) {
eb3a3530
CD		 1595 /* For 64KB splited entries, we need clear them all. */
1596 if (ops->test_64k_splited(&old_se) &&
1597 !(index % GTT_64K_PTE_STRIDE)) {
1598 gvt_vdbg_mm("remove splited 64K shadow entries\n");
1599 for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1600 ops->clear_64k_splited(&old_se);
1601 ops->set_pfn(&old_se,
1602 vgpu->gtt.scratch_pt[type].page_mfn);
1603 ppgtt_set_shadow_entry(spt, &old_se, index + i);
1604 }
b901b252
CD		 1605 } else if (old_se.type == GTT_TYPE_PPGTT_PTE_2M_ENTRY ||
1606 old_se.type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
1607 ops->clear_pse(&old_se);
1608 ops->set_pfn(&old_se,
1609 vgpu->gtt.scratch_pt[type].page_mfn);
1610 ppgtt_set_shadow_entry(spt, &old_se, index);
eb3a3530
CD		 1611 } else {
1612 ops->set_pfn(&old_se,
1613 vgpu->gtt.scratch_pt[type].page_mfn);
1614 ppgtt_set_shadow_entry(spt, &old_se, index);
1615 }
6b3816d6
TZ		 1616 }
1617
2707e444
ZW		 1618 return 0;
1619fail:
695fbc08
TZ		 1620 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1621 spt, we->val64, we->type);
2707e444
ZW		 1622 return ret;
1623}
1624
72f03d7e
CD		 1625
1626
44b46733 1627static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 1628{
1629 return enable_out_of_sync
44b46733
CD		 1630 && gtt_type_is_pte_pt(spt->guest_page.type)
1631 && spt->guest_page.write_cnt >= 2;
2707e444
ZW		 1632}
1633
1634static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1635 unsigned long index)
1636{
1637 set_bit(index, spt->post_shadow_bitmap);
1638 if (!list_empty(&spt->post_shadow_list))
1639 return;
1640
1641 list_add_tail(&spt->post_shadow_list,
1642 &spt->vgpu->gtt.post_shadow_list_head);
1643}
1644
1645/**
1646 * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1647 * @vgpu: a vGPU
1648 *
1649 * This function is called before submitting a guest workload to host,
1650 * to flush all the post shadows for a vGPU.
1651 *
1652 * Returns:
1653 * Zero on success, negative error code if failed.
1654 */
1655int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1656{
1657 struct list_head *pos, *n;
1658 struct intel_vgpu_ppgtt_spt *spt;
9baf0920 1659 struct intel_gvt_gtt_entry ge;
2707e444
ZW		 1660 unsigned long index;
1661 int ret;
1662
1663 list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1664 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1665 post_shadow_list);
1666
1667 for_each_set_bit(index, spt->post_shadow_bitmap,
1668 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1669 ppgtt_get_guest_entry(spt, &ge, index);
2707e444 1670
44b46733
CD		 1671 ret = ppgtt_handle_guest_write_page_table(spt,
1672 &ge, index);
2707e444
ZW		 1673 if (ret)
1674 return ret;
1675 clear_bit(index, spt->post_shadow_bitmap);
1676 }
1677 list_del_init(&spt->post_shadow_list);
1678 }
1679 return 0;
1680}
1681
7d1e5cdf 1682static int ppgtt_handle_guest_write_page_table_bytes(
44b46733 1683 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1684 u64 pa, void *p_data, int bytes)
1685{
2707e444
ZW		 1686 struct intel_vgpu *vgpu = spt->vgpu;
1687 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1688 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
6b3816d6 1689 struct intel_gvt_gtt_entry we, se;
2707e444
ZW		 1690 unsigned long index;
1691 int ret;
1692
1693 index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1694
1695 ppgtt_get_guest_entry(spt, &we, index);
2707e444 1696
eb3a3530
CD		 1697 /*
1698 * For page table which has 64K gtt entry, only PTE#0, PTE#16,
1699 * PTE#32, ... PTE#496 are used. Unused PTEs update should be
1700 * ignored.
1701 */
1702 if (we.type == GTT_TYPE_PPGTT_PTE_64K_ENTRY &&
1703 (index % GTT_64K_PTE_STRIDE)) {
1704 gvt_vdbg_mm("Ignore write to unused PTE entry, index %lu\n",
1705 index);
1706 return 0;
1707 }
2707e444
ZW		 1708
1709 if (bytes == info->gtt_entry_size) {
44b46733 1710 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
2707e444
ZW		 1711 if (ret)
1712 return ret;
1713 } else {
2707e444 1714 if (!test_bit(index, spt->post_shadow_bitmap)) {
121d760d
ZW		 1715 int type = spt->shadow_page.type;
1716
6b3816d6 1717 ppgtt_get_shadow_entry(spt, &se, index);
44b46733 1718 ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
2707e444
ZW		 1719 if (ret)
1720 return ret;
121d760d
ZW		 1721 ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1722 ppgtt_set_shadow_entry(spt, &se, index);
2707e444 1723 }
2707e444 1724 ppgtt_set_post_shadow(spt, index);
2707e444
ZW		 1725 }
1726
1727 if (!enable_out_of_sync)
1728 return 0;
1729
44b46733 1730 spt->guest_page.write_cnt++;
2707e444 1731
44b46733
CD		 1732 if (spt->guest_page.oos_page)
1733 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
2707e444
ZW		 1734 false, 0, vgpu);
1735
44b46733
CD		 1736 if (can_do_out_of_sync(spt)) {
1737 if (!spt->guest_page.oos_page)
1738 ppgtt_allocate_oos_page(spt);
2707e444 1739
44b46733 1740 ret = ppgtt_set_guest_page_oos(spt);
2707e444
ZW		 1741 if (ret < 0)
1742 return ret;
1743 }
1744 return 0;
1745}
1746
ede9d0cf 1747static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
2707e444
ZW		 1748{
1749 struct intel_vgpu *vgpu = mm->vgpu;
1750 struct intel_gvt *gvt = vgpu->gvt;
1751 struct intel_gvt_gtt *gtt = &gvt->gtt;
1752 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1753 struct intel_gvt_gtt_entry se;
ede9d0cf 1754 int index;
2707e444 1755
ede9d0cf 1756 if (!mm->ppgtt_mm.shadowed)
2707e444
ZW		 1757 return;
1758
ede9d0cf
CD		 1759 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1760 ppgtt_get_shadow_root_entry(mm, &se, index);
1761
2707e444
ZW		 1762 if (!ops->test_present(&se))
1763 continue;
ede9d0cf 1764
d87f5ff3 1765 ppgtt_invalidate_spt_by_shadow_entry(vgpu, &se);
2707e444 1766 se.val64 = 0;
ede9d0cf 1767 ppgtt_set_shadow_root_entry(mm, &se, index);
2707e444 1768
44b46733
CD		 1769 trace_spt_guest_change(vgpu->id, "destroy root pointer",
1770 NULL, se.type, se.val64, index);
2707e444 1771 }
2707e444 1772
ede9d0cf 1773 mm->ppgtt_mm.shadowed = false;
2707e444
ZW		 1774}
1775
ede9d0cf
CD		 1776
1777static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
2707e444
ZW		 1778{
1779 struct intel_vgpu *vgpu = mm->vgpu;
1780 struct intel_gvt *gvt = vgpu->gvt;
1781 struct intel_gvt_gtt *gtt = &gvt->gtt;
1782 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1783 struct intel_vgpu_ppgtt_spt *spt;
1784 struct intel_gvt_gtt_entry ge, se;
ede9d0cf 1785 int index, ret;
2707e444 1786
ede9d0cf 1787 if (mm->ppgtt_mm.shadowed)
2707e444
ZW		 1788 return 0;
1789
ede9d0cf
CD		 1790 mm->ppgtt_mm.shadowed = true;
1791
1792 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1793 ppgtt_get_guest_root_entry(mm, &ge, index);
2707e444 1794
2707e444
ZW		 1795 if (!ops->test_present(&ge))
1796 continue;
1797
44b46733
CD		 1798 trace_spt_guest_change(vgpu->id, __func__, NULL,
1799 ge.type, ge.val64, index);
2707e444 1800
d87f5ff3 1801 spt = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
2707e444 1802 if (IS_ERR(spt)) {
695fbc08 1803 gvt_vgpu_err("fail to populate guest root pointer\n");
2707e444
ZW		 1804 ret = PTR_ERR(spt);
1805 goto fail;
1806 }
1807 ppgtt_generate_shadow_entry(&se, spt, &ge);
ede9d0cf 1808 ppgtt_set_shadow_root_entry(mm, &se, index);
2707e444 1809
44b46733
CD		 1810 trace_spt_guest_change(vgpu->id, "populate root pointer",
1811 NULL, se.type, se.val64, index);
2707e444 1812 }
ede9d0cf 1813
2707e444
ZW		 1814 return 0;
1815fail:
ede9d0cf 1816 invalidate_ppgtt_mm(mm);
2707e444
ZW		 1817 return ret;
1818}
1819
ede9d0cf
CD		 1820static struct intel_vgpu_mm *vgpu_alloc_mm(struct intel_vgpu *vgpu)
1821{
1822 struct intel_vgpu_mm *mm;
1823
1824 mm = kzalloc(sizeof(*mm), GFP_KERNEL);
1825 if (!mm)
1826 return NULL;
1827
1828 mm->vgpu = vgpu;
1829 kref_init(&mm->ref);
1830 atomic_set(&mm->pincount, 0);
1831
1832 return mm;
1833}
1834
1835static void vgpu_free_mm(struct intel_vgpu_mm *mm)
1836{
1837 kfree(mm);
1838}
1839
2707e444 1840/**
ede9d0cf 1841 * intel_vgpu_create_ppgtt_mm - create a ppgtt mm object for a vGPU
2707e444 1842 * @vgpu: a vGPU
ede9d0cf
CD		 1843 * @root_entry_type: ppgtt root entry type
1844 * @pdps: guest pdps.
2707e444 1845 *
ede9d0cf 1846 * This function is used to create a ppgtt mm object for a vGPU.
2707e444
ZW		 1847 *
1848 * Returns:
1849 * Zero on success, negative error code in pointer if failed.
1850 */
ede9d0cf
CD		 1851struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1852 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2707e444
ZW		 1853{
1854 struct intel_gvt *gvt = vgpu->gvt;
2707e444
ZW		 1855 struct intel_vgpu_mm *mm;
1856 int ret;
1857
ede9d0cf
CD		 1858 mm = vgpu_alloc_mm(vgpu);
1859 if (!mm)
1860 return ERR_PTR(-ENOMEM);
2707e444 1861
ede9d0cf 1862 mm->type = INTEL_GVT_MM_PPGTT;
2707e444 1863
ede9d0cf
CD		 1864 GEM_BUG_ON(root_entry_type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY &&
1865 root_entry_type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY);
1866 mm->ppgtt_mm.root_entry_type = root_entry_type;
2707e444 1867
ede9d0cf
CD		 1868 INIT_LIST_HEAD(&mm->ppgtt_mm.list);
1869 INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
2707e444 1870
ede9d0cf
CD		 1871 if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
1872 mm->ppgtt_mm.guest_pdps[0] = pdps[0];
1873 else
1874 memcpy(mm->ppgtt_mm.guest_pdps, pdps,
1875 sizeof(mm->ppgtt_mm.guest_pdps));
2707e444 1876
ede9d0cf 1877 ret = shadow_ppgtt_mm(mm);
2707e444 1878 if (ret) {
ede9d0cf
CD		 1879 gvt_vgpu_err("failed to shadow ppgtt mm\n");
1880 vgpu_free_mm(mm);
1881 return ERR_PTR(ret);
2707e444
ZW		 1882 }
1883
ede9d0cf
CD		 1884 list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1885 list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1886 return mm;
1887}
2707e444 1888
ede9d0cf
CD		 1889static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1890{
1891 struct intel_vgpu_mm *mm;
1892 unsigned long nr_entries;
2707e444 1893
ede9d0cf
CD		 1894 mm = vgpu_alloc_mm(vgpu);
1895 if (!mm)
1896 return ERR_PTR(-ENOMEM);
1897
1898 mm->type = INTEL_GVT_MM_GGTT;
1899
1900 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
fad953ce
KC		 1901 mm->ggtt_mm.virtual_ggtt =
1902 vzalloc(array_size(nr_entries,
1903 vgpu->gvt->device_info.gtt_entry_size));
ede9d0cf
CD		 1904 if (!mm->ggtt_mm.virtual_ggtt) {
1905 vgpu_free_mm(mm);
1906 return ERR_PTR(-ENOMEM);
2707e444 1907 }
ede9d0cf 1908
2707e444 1909 return mm;
ede9d0cf
CD		 1910}
1911
1912/**
1bc25851 1913 * _intel_vgpu_mm_release - destroy a mm object
ede9d0cf
CD		 1914 * @mm_ref: a kref object
1915 *
1916 * This function is used to destroy a mm object for vGPU
1917 *
1918 */
1bc25851 1919void _intel_vgpu_mm_release(struct kref *mm_ref)
ede9d0cf
CD		 1920{
1921 struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1922
1923 if (GEM_WARN_ON(atomic_read(&mm->pincount)))
1924 gvt_err("vgpu mm pin count bug detected\n");
1925
1926 if (mm->type == INTEL_GVT_MM_PPGTT) {
1927 list_del(&mm->ppgtt_mm.list);
1928 list_del(&mm->ppgtt_mm.lru_list);
1929 invalidate_ppgtt_mm(mm);
1930 } else {
1931 vfree(mm->ggtt_mm.virtual_ggtt);
1932 }
1933
1934 vgpu_free_mm(mm);
2707e444
ZW		 1935}
1936
1937/**
1938 * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1939 * @mm: a vGPU mm object
1940 *
1941 * This function is called when user doesn't want to use a vGPU mm object
1942 */
1943void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
1944{
2707e444
ZW		 1945 atomic_dec(&mm->pincount);
1946}
1947
1948/**
1949 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
a752b070 1950 * @mm: target vgpu mm
2707e444
ZW		 1951 *
1952 * This function is called when user wants to use a vGPU mm object. If this
1953 * mm object hasn't been shadowed yet, the shadow will be populated at this
1954 * time.
1955 *
1956 * Returns:
1957 * Zero on success, negative error code if failed.
1958 */
1959int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
1960{
1961 int ret;
1962
ede9d0cf 1963 atomic_inc(&mm->pincount);
2707e444 1964
ede9d0cf
CD		 1965 if (mm->type == INTEL_GVT_MM_PPGTT) {
1966 ret = shadow_ppgtt_mm(mm);
2707e444
ZW		 1967 if (ret)
1968 return ret;
ede9d0cf
CD		 1969
1970 list_move_tail(&mm->ppgtt_mm.lru_list,
1971 &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
1972
2707e444
ZW		 1973 }
1974
2707e444
ZW		 1975 return 0;
1976}
1977
ede9d0cf 1978static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
2707e444
ZW		 1979{
1980 struct intel_vgpu_mm *mm;
1981 struct list_head *pos, *n;
1982
ede9d0cf
CD		 1983 list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
1984 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
2707e444 1985
2707e444
ZW		 1986 if (atomic_read(&mm->pincount))
1987 continue;
1988
ede9d0cf
CD		 1989 list_del_init(&mm->ppgtt_mm.lru_list);
1990 invalidate_ppgtt_mm(mm);
2707e444
ZW		 1991 return 1;
1992 }
1993 return 0;
1994}
1995
1996/*
1997 * GMA translation APIs.
1998 */
1999static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
2000 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
2001{
2002 struct intel_vgpu *vgpu = mm->vgpu;
2003 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2004 struct intel_vgpu_ppgtt_spt *s;
2005
44b46733 2006 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2707e444
ZW		 2007 if (!s)
2008 return -ENXIO;
2009
2010 if (!guest)
2011 ppgtt_get_shadow_entry(s, e, index);
2012 else
2013 ppgtt_get_guest_entry(s, e, index);
2014 return 0;
2015}
2016
2017/**
2018 * intel_vgpu_gma_to_gpa - translate a gma to GPA
2019 * @mm: mm object. could be a PPGTT or GGTT mm object
2020 * @gma: graphics memory address in this mm object
2021 *
2022 * This function is used to translate a graphics memory address in specific
2023 * graphics memory space to guest physical address.
2024 *
2025 * Returns:
2026 * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
2027 */
2028unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
2029{
2030 struct intel_vgpu *vgpu = mm->vgpu;
2031 struct intel_gvt *gvt = vgpu->gvt;
2032 struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2033 struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2034 unsigned long gpa = INTEL_GVT_INVALID_ADDR;
2035 unsigned long gma_index[4];
2036 struct intel_gvt_gtt_entry e;
ede9d0cf 2037 int i, levels = 0;
2707e444
ZW		 2038 int ret;
2039
ede9d0cf
CD		 2040 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT &&
2041 mm->type != INTEL_GVT_MM_PPGTT);
2707e444
ZW		 2042
2043 if (mm->type == INTEL_GVT_MM_GGTT) {
2044 if (!vgpu_gmadr_is_valid(vgpu, gma))
2045 goto err;
2046
ede9d0cf
CD		 2047 ggtt_get_guest_entry(mm, &e,
2048 gma_ops->gma_to_ggtt_pte_index(gma));
2049
9556e118
ZW		 2050 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
2051 + (gma & ~I915_GTT_PAGE_MASK);
2707e444
ZW		 2052
2053 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
ede9d0cf
CD		 2054 } else {
2055 switch (mm->ppgtt_mm.root_entry_type) {
2056 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2057 ppgtt_get_shadow_root_entry(mm, &e, 0);
2058
2059 gma_index[0] = gma_ops->gma_to_pml4_index(gma);
2060 gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
2061 gma_index[2] = gma_ops->gma_to_pde_index(gma);
2062 gma_index[3] = gma_ops->gma_to_pte_index(gma);
2063 levels = 4;
2064 break;
2065 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2066 ppgtt_get_shadow_root_entry(mm, &e,
2067 gma_ops->gma_to_l3_pdp_index(gma));
2068
2069 gma_index[0] = gma_ops->gma_to_pde_index(gma);
2070 gma_index[1] = gma_ops->gma_to_pte_index(gma);
2071 levels = 2;
2072 break;
2073 default:
2074 GEM_BUG_ON(1);
2075 }
2707e444 2076
ede9d0cf
CD		 2077 /* walk the shadow page table and get gpa from guest entry */
2078 for (i = 0; i < levels; i++) {
2079 ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
2080 (i == levels - 1));
2081 if (ret)
2082 goto err;
4b2dbbc2 2083
ede9d0cf
CD		 2084 if (!pte_ops->test_present(&e)) {
2085 gvt_dbg_core("GMA 0x%lx is not present\n", gma);
2086 goto err;
2087 }
4b2dbbc2 2088 }
2707e444 2089
ede9d0cf
CD		 2090 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT) +
2091 (gma & ~I915_GTT_PAGE_MASK);
2092 trace_gma_translate(vgpu->id, "ppgtt", 0,
2093 mm->ppgtt_mm.root_entry_type, gma, gpa);
2094 }
2707e444 2095
2707e444
ZW		 2096 return gpa;
2097err:
695fbc08 2098 gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
2707e444
ZW		 2099 return INTEL_GVT_INVALID_ADDR;
2100}
2101
a143cef7 2102static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
2707e444
ZW		 2103 unsigned int off, void *p_data, unsigned int bytes)
2104{
2105 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2106 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2107 unsigned long index = off >> info->gtt_entry_size_shift;
2108 struct intel_gvt_gtt_entry e;
2109
2110 if (bytes != 4 && bytes != 8)
2111 return -EINVAL;
2112
2113 ggtt_get_guest_entry(ggtt_mm, &e, index);
2114 memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
2115 bytes);
2116 return 0;
2117}
2118
2119/**
2120 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
2121 * @vgpu: a vGPU
2122 * @off: register offset
2123 * @p_data: data will be returned to guest
2124 * @bytes: data length
2125 *
2126 * This function is used to emulate the GTT MMIO register read
2127 *
2128 * Returns:
2129 * Zero on success, error code if failed.
2130 */
a143cef7 2131int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
2707e444
ZW		 2132 void *p_data, unsigned int bytes)
2133{
2134 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2135 int ret;
2136
2137 if (bytes != 4 && bytes != 8)
2138 return -EINVAL;
2139
2140 off -= info->gtt_start_offset;
a143cef7 2141 ret = emulate_ggtt_mmio_read(vgpu, off, p_data, bytes);
2707e444
ZW		 2142 return ret;
2143}
2144
7598e870
CD		 2145static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
2146 struct intel_gvt_gtt_entry *entry)
2147{
2148 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2149 unsigned long pfn;
2150
2151 pfn = pte_ops->get_pfn(entry);
2152 if (pfn != vgpu->gvt->gtt.scratch_mfn)
2153 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu,
2154 pfn << PAGE_SHIFT);
2155}
2156
a143cef7 2157static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2707e444
ZW		 2158 void *p_data, unsigned int bytes)
2159{
2160 struct intel_gvt *gvt = vgpu->gvt;
2161 const struct intel_gvt_device_info *info = &gvt->device_info;
2162 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2163 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2164 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
cf4ee73f 2165 unsigned long gma, gfn;
2707e444 2166 struct intel_gvt_gtt_entry e, m;
cf4ee73f
CD		 2167 dma_addr_t dma_addr;
2168 int ret;
bc0686ff
HY		 2169 struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2170 bool partial_update = false;
2707e444
ZW		 2171
2172 if (bytes != 4 && bytes != 8)
2173 return -EINVAL;
2174
9556e118 2175 gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
2707e444
ZW		 2176
2177 /* the VM may configure the whole GM space when ballooning is used */
7c28135c 2178 if (!vgpu_gmadr_is_valid(vgpu, gma))
2707e444 2179 return 0;
2707e444 2180
bc0686ff 2181 e.type = GTT_TYPE_GGTT_PTE;
2707e444
ZW		 2182 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
2183 bytes);
2184
510fe10b 2185 /* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
bc0686ff
HY		 2186 * write, save the first 4 bytes in a list and update virtual
2187 * PTE. Only update shadow PTE when the second 4 bytes comes.
510fe10b
ZY		 2188 */
2189 if (bytes < info->gtt_entry_size) {
bc0686ff
HY		 2190 bool found = false;
2191
2192 list_for_each_entry_safe(pos, n,
2193 &ggtt_mm->ggtt_mm.partial_pte_list, list) {
2194 if (g_gtt_index == pos->offset >>
2195 info->gtt_entry_size_shift) {
2196 if (off != pos->offset) {
2197 /* the second partial part*/
2198 int last_off = pos->offset &
2199 (info->gtt_entry_size - 1);
2200
2201 memcpy((void *)&e.val64 + last_off,
2202 (void *)&pos->data + last_off,
2203 bytes);
2204
2205 list_del(&pos->list);
2206 kfree(pos);
2207 found = true;
2208 break;
2209 }
2210
2211 /* update of the first partial part */
2212 pos->data = e.val64;
2213 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2214 return 0;
2215 }
2216 }
510fe10b 2217
bc0686ff
HY		 2218 if (!found) {
2219 /* the first partial part */
2220 partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2221 if (!partial_pte)
2222 return -ENOMEM;
2223 partial_pte->offset = off;
2224 partial_pte->data = e.val64;
2225 list_add_tail(&partial_pte->list,
2226 &ggtt_mm->ggtt_mm.partial_pte_list);
2227 partial_update = true;
510fe10b
ZY		 2228 }
2229 }
2230
bc0686ff 2231 if (!partial_update && (ops->test_present(&e))) {
cc753fbe 2232 gfn = ops->get_pfn(&e);
7598e870 2233 m = e;
cc753fbe
HY		 2234
2235 /* one PTE update may be issued in multiple writes and the
2236 * first write may not construct a valid gfn
2237 */
2238 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
2239 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2240 goto out;
2241 }
2242
cf4ee73f 2243 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn,
79e542f5 2244 PAGE_SIZE, &dma_addr);
cf4ee73f 2245 if (ret) {
72f03d7e 2246 gvt_vgpu_err("fail to populate guest ggtt entry\n");
359b6931
XC		 2247 /* guest driver may read/write the entry when partial
2248 * update the entry in this situation p2m will fail
2249 * settting the shadow entry to point to a scratch page
2250 */
22115cef 2251 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
72f03d7e 2252 } else
cf4ee73f 2253 ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
7598e870 2254 } else {
22115cef 2255 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
7598e870
CD		 2256 ops->clear_present(&m);
2257 }
2707e444 2258
cc753fbe 2259out:
f42259ef
HY		 2260 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2261
2262 ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2263 ggtt_invalidate_pte(vgpu, &e);
2264
3aff3512 2265 ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
a143cef7 2266 ggtt_invalidate(gvt->dev_priv);
2707e444
ZW		 2267 return 0;
2268}
2269
2270/*
a143cef7 2271 * intel_vgpu_emulate_ggtt_mmio_write - emulate GTT MMIO register write
2707e444
ZW		 2272 * @vgpu: a vGPU
2273 * @off: register offset
2274 * @p_data: data from guest write
2275 * @bytes: data length
2276 *
2277 * This function is used to emulate the GTT MMIO register write
2278 *
2279 * Returns:
2280 * Zero on success, error code if failed.
2281 */
a143cef7
CD		 2282int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
2283 unsigned int off, void *p_data, unsigned int bytes)
2707e444
ZW		 2284{
2285 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2286 int ret;
2287
2288 if (bytes != 4 && bytes != 8)
2289 return -EINVAL;
2290
2291 off -= info->gtt_start_offset;
a143cef7 2292 ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
2707e444
ZW		 2293 return ret;
2294}
2295
3b6411c2
PG		 2296static int alloc_scratch_pages(struct intel_vgpu *vgpu,
2297 intel_gvt_gtt_type_t type)
2707e444
ZW		 2298{
2299 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
3b6411c2 2300 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
5c35258d 2301 int page_entry_num = I915_GTT_PAGE_SIZE >>
3b6411c2 2302 vgpu->gvt->device_info.gtt_entry_size_shift;
9631739f 2303 void *scratch_pt;
3b6411c2 2304 int i;
5de6bd4c
CD		 2305 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2306 dma_addr_t daddr;
2707e444 2307
3b6411c2
PG		 2308 if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2309 return -EINVAL;
2310
9631739f 2311 scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
3b6411c2 2312 if (!scratch_pt) {
695fbc08 2313 gvt_vgpu_err("fail to allocate scratch page\n");
2707e444
ZW		 2314 return -ENOMEM;
2315 }
2316
5de6bd4c
CD		 2317 daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
2318 4096, PCI_DMA_BIDIRECTIONAL);
2319 if (dma_mapping_error(dev, daddr)) {
695fbc08 2320 gvt_vgpu_err("fail to dmamap scratch_pt\n");
5de6bd4c
CD		 2321 __free_page(virt_to_page(scratch_pt));
2322 return -ENOMEM;
3b6411c2 2323 }
5de6bd4c 2324 gtt->scratch_pt[type].page_mfn =
5c35258d 2325 (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
9631739f 2326 gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
3b6411c2 2327 gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
5de6bd4c 2328 vgpu->id, type, gtt->scratch_pt[type].page_mfn);
3b6411c2
PG		 2329
2330 /* Build the tree by full filled the scratch pt with the entries which
2331 * point to the next level scratch pt or scratch page. The
2332 * scratch_pt[type] indicate the scratch pt/scratch page used by the
2333 * 'type' pt.
2334 * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
9631739f 2335 * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
3b6411c2
PG		 2336 * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
2337 */
65957195 2338 if (type > GTT_TYPE_PPGTT_PTE_PT) {
3b6411c2
PG		 2339 struct intel_gvt_gtt_entry se;
2340
2341 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
2342 se.type = get_entry_type(type - 1);
2343 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
2344
2345 /* The entry parameters like present/writeable/cache type
2346 * set to the same as i915's scratch page tree.
2347 */
2348 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
2349 if (type == GTT_TYPE_PPGTT_PDE_PT)
c095b97c 2350 se.val64 |= PPAT_CACHED;
3b6411c2
PG		 2351
2352 for (i = 0; i < page_entry_num; i++)
9631739f 2353 ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
3b6411c2
PG		 2354 }
2355
3b6411c2
PG		 2356 return 0;
2357}
2707e444 2358
3b6411c2
PG		 2359static int release_scratch_page_tree(struct intel_vgpu *vgpu)
2360{
2361 int i;
5de6bd4c
CD		 2362 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2363 dma_addr_t daddr;
3b6411c2
PG		 2364
2365 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2366 if (vgpu->gtt.scratch_pt[i].page != NULL) {
5de6bd4c 2367 daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
5c35258d 2368 I915_GTT_PAGE_SHIFT);
5de6bd4c 2369 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
3b6411c2
PG		 2370 __free_page(vgpu->gtt.scratch_pt[i].page);
2371 vgpu->gtt.scratch_pt[i].page = NULL;
2372 vgpu->gtt.scratch_pt[i].page_mfn = 0;
2373 }
2707e444
ZW		 2374 }
2375
2707e444
ZW		 2376 return 0;
2377}
2378
3b6411c2 2379static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2707e444 2380{
3b6411c2
PG		 2381 int i, ret;
2382
2383 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2384 ret = alloc_scratch_pages(vgpu, i);
2385 if (ret)
2386 goto err;
2707e444 2387 }
3b6411c2
PG		 2388
2389 return 0;
2390
2391err:
2392 release_scratch_page_tree(vgpu);
2393 return ret;
2707e444
ZW		 2394}
2395
2396/**
2397 * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2398 * @vgpu: a vGPU
2399 *
2400 * This function is used to initialize per-vGPU graphics memory virtualization
2401 * components.
2402 *
2403 * Returns:
2404 * Zero on success, error code if failed.
2405 */
2406int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2407{
2408 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2707e444 2409
b6c126a3 2410 INIT_RADIX_TREE(&gtt->spt_tree, GFP_KERNEL);
2707e444 2411
ede9d0cf 2412 INIT_LIST_HEAD(&gtt->ppgtt_mm_list_head);
2707e444
ZW		 2413 INIT_LIST_HEAD(&gtt->oos_page_list_head);
2414 INIT_LIST_HEAD(&gtt->post_shadow_list_head);
2415
ede9d0cf
CD		 2416 gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2417 if (IS_ERR(gtt->ggtt_mm)) {
695fbc08 2418 gvt_vgpu_err("fail to create mm for ggtt.\n");
ede9d0cf 2419 return PTR_ERR(gtt->ggtt_mm);
2707e444
ZW		 2420 }
2421
f4c43db3 2422 intel_vgpu_reset_ggtt(vgpu, false);
2707e444 2423
bc0686ff
HY		 2424 INIT_LIST_HEAD(&gtt->ggtt_mm->ggtt_mm.partial_pte_list);
2425
3b6411c2 2426 return create_scratch_page_tree(vgpu);
2707e444
ZW		 2427}
2428
ede9d0cf 2429static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
da9cc8de
PG		 2430{
2431 struct list_head *pos, *n;
2432 struct intel_vgpu_mm *mm;
2433
ede9d0cf
CD		 2434 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2435 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
1bc25851 2436 intel_vgpu_destroy_mm(mm);
da9cc8de 2437 }
ede9d0cf
CD		 2438
2439 if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
84f69ba0 2440 gvt_err("vgpu ppgtt mm is not fully destroyed\n");
ede9d0cf 2441
b6c126a3 2442 if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
ede9d0cf 2443 gvt_err("Why we still has spt not freed?\n");
d87f5ff3 2444 ppgtt_free_all_spt(vgpu);
ede9d0cf
CD		 2445 }
2446}
2447
2448static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2449{
7513edbc 2450 struct intel_gvt_partial_pte *pos, *next;
bc0686ff 2451
7513edbc
CW		 2452 list_for_each_entry_safe(pos, next,
2453 &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list,
2454 list) {
bc0686ff
HY		 2455 gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2456 pos->offset, pos->data);
2457 kfree(pos);
2458 }
1bc25851 2459 intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
ede9d0cf 2460 vgpu->gtt.ggtt_mm = NULL;
da9cc8de
PG		 2461}
2462
2707e444
ZW		 2463/**
2464 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2465 * @vgpu: a vGPU
2466 *
2467 * This function is used to clean up per-vGPU graphics memory virtualization
2468 * components.
2469 *
2470 * Returns:
2471 * Zero on success, error code if failed.
2472 */
2473void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2474{
ede9d0cf
CD		 2475 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2476 intel_vgpu_destroy_ggtt_mm(vgpu);
3b6411c2 2477 release_scratch_page_tree(vgpu);
2707e444
ZW		 2478}
2479
2480static void clean_spt_oos(struct intel_gvt *gvt)
2481{
2482 struct intel_gvt_gtt *gtt = &gvt->gtt;
2483 struct list_head *pos, *n;
2484 struct intel_vgpu_oos_page *oos_page;
2485
2486 WARN(!list_empty(&gtt->oos_page_use_list_head),
2487 "someone is still using oos page\n");
2488
2489 list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
2490 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2491 list_del(&oos_page->list);
2492 kfree(oos_page);
2493 }
2494}
2495
2496static int setup_spt_oos(struct intel_gvt *gvt)
2497{
2498 struct intel_gvt_gtt *gtt = &gvt->gtt;
2499 struct intel_vgpu_oos_page *oos_page;
2500 int i;
2501 int ret;
2502
2503 INIT_LIST_HEAD(&gtt->oos_page_free_list_head);
2504 INIT_LIST_HEAD(&gtt->oos_page_use_list_head);
2505
2506 for (i = 0; i < preallocated_oos_pages; i++) {
2507 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2508 if (!oos_page) {
2707e444
ZW		 2509 ret = -ENOMEM;
2510 goto fail;
2511 }
2512
2513 INIT_LIST_HEAD(&oos_page->list);
2514 INIT_LIST_HEAD(&oos_page->vm_list);
2515 oos_page->id = i;
2516 list_add_tail(&oos_page->list, &gtt->oos_page_free_list_head);
2517 }
2518
2519 gvt_dbg_mm("%d oos pages preallocated\n", i);
2520
2521 return 0;
2522fail:
2523 clean_spt_oos(gvt);
2524 return ret;
2525}
2526
2527/**
2528 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2529 * @vgpu: a vGPU
a752b070 2530 * @pdps: pdp root array
2707e444
ZW		 2531 *
2532 * This function is used to find a PPGTT mm object from mm object pool
2533 *
2534 * Returns:
2535 * pointer to mm object on success, NULL if failed.
2536 */
2537struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
ede9d0cf 2538 u64 pdps[])
2707e444 2539{
2707e444 2540 struct intel_vgpu_mm *mm;
ede9d0cf 2541 struct list_head *pos;
2707e444 2542
ede9d0cf
CD		 2543 list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2544 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2707e444 2545
ede9d0cf
CD		 2546 switch (mm->ppgtt_mm.root_entry_type) {
2547 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2548 if (pdps[0] == mm->ppgtt_mm.guest_pdps[0])
2707e444 2549 return mm;
ede9d0cf
CD		 2550 break;
2551 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2552 if (!memcmp(pdps, mm->ppgtt_mm.guest_pdps,
2553 sizeof(mm->ppgtt_mm.guest_pdps)))
2707e444 2554 return mm;
ede9d0cf
CD		 2555 break;
2556 default:
2557 GEM_BUG_ON(1);
2707e444
ZW		 2558 }
2559 }
2560 return NULL;
2561}
2562
2563/**
e6e9c46f 2564 * intel_vgpu_get_ppgtt_mm - get or create a PPGTT mm object.
2707e444 2565 * @vgpu: a vGPU
ede9d0cf
CD		 2566 * @root_entry_type: ppgtt root entry type
2567 * @pdps: guest pdps
2707e444 2568 *
e6e9c46f 2569 * This function is used to find or create a PPGTT mm object from a guest.
2707e444
ZW		 2570 *
2571 * Returns:
2572 * Zero on success, negative error code if failed.
2573 */
e6e9c46f 2574struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
ede9d0cf 2575 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2707e444 2576{
2707e444
ZW		 2577 struct intel_vgpu_mm *mm;
2578
ede9d0cf 2579 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2707e444 2580 if (mm) {
1bc25851 2581 intel_vgpu_mm_get(mm);
2707e444 2582 } else {
ede9d0cf 2583 mm = intel_vgpu_create_ppgtt_mm(vgpu, root_entry_type, pdps);
e6e9c46f 2584 if (IS_ERR(mm))
695fbc08 2585 gvt_vgpu_err("fail to create mm\n");
2707e444 2586 }
e6e9c46f 2587 return mm;
2707e444
ZW		 2588}
2589
2590/**
e6e9c46f 2591 * intel_vgpu_put_ppgtt_mm - find and put a PPGTT mm object.
2707e444 2592 * @vgpu: a vGPU
ede9d0cf 2593 * @pdps: guest pdps
2707e444 2594 *
e6e9c46f 2595 * This function is used to find a PPGTT mm object from a guest and destroy it.
2707e444
ZW		 2596 *
2597 * Returns:
2598 * Zero on success, negative error code if failed.
2599 */
e6e9c46f 2600int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])
2707e444 2601{
2707e444
ZW		 2602 struct intel_vgpu_mm *mm;
2603
ede9d0cf 2604 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2707e444 2605 if (!mm) {
695fbc08 2606 gvt_vgpu_err("fail to find ppgtt instance.\n");
2707e444
ZW		 2607 return -EINVAL;
2608 }
1bc25851 2609 intel_vgpu_mm_put(mm);
2707e444
ZW		 2610 return 0;
2611}
2612
2613/**
2614 * intel_gvt_init_gtt - initialize mm components of a GVT device
2615 * @gvt: GVT device
2616 *
2617 * This function is called at the initialization stage, to initialize
2618 * the mm components of a GVT device.
2619 *
2620 * Returns:
2621 * zero on success, negative error code if failed.
2622 */
2623int intel_gvt_init_gtt(struct intel_gvt *gvt)
2624{
2625 int ret;
9631739f 2626 void *page;
5de6bd4c
CD		 2627 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2628 dma_addr_t daddr;
2707e444
ZW		 2629
2630 gvt_dbg_core("init gtt\n");
2631
665004b8
CX		 2632 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2633 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2707e444 2634
9631739f
JS		 2635 page = (void *)get_zeroed_page(GFP_KERNEL);
2636 if (!page) {
d650ac06
PG		 2637 gvt_err("fail to allocate scratch ggtt page\n");
2638 return -ENOMEM;
2639 }
2640
5de6bd4c
CD		 2641 daddr = dma_map_page(dev, virt_to_page(page), 0,
2642 4096, PCI_DMA_BIDIRECTIONAL);
2643 if (dma_mapping_error(dev, daddr)) {
2644 gvt_err("fail to dmamap scratch ggtt page\n");
2645 __free_page(virt_to_page(page));
2646 return -ENOMEM;
d650ac06 2647 }
22115cef
ZW		 2648
2649 gvt->gtt.scratch_page = virt_to_page(page);
2650 gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
d650ac06 2651
2707e444
ZW		 2652 if (enable_out_of_sync) {
2653 ret = setup_spt_oos(gvt);
2654 if (ret) {
2655 gvt_err("fail to initialize SPT oos\n");
0de98709 2656 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
22115cef 2657 __free_page(gvt->gtt.scratch_page);
2707e444
ZW		 2658 return ret;
2659 }
2660 }
ede9d0cf 2661 INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2707e444
ZW		 2662 return 0;
2663}
2664
2665/**
2666 * intel_gvt_clean_gtt - clean up mm components of a GVT device
2667 * @gvt: GVT device
2668 *
2669 * This function is called at the driver unloading stage, to clean up the
2670 * the mm components of a GVT device.
2671 *
2672 */
2673void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2674{
5de6bd4c 2675 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
22115cef 2676 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
9556e118 2677 I915_GTT_PAGE_SHIFT);
5de6bd4c
CD		 2678
2679 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2680
22115cef 2681 __free_page(gvt->gtt.scratch_page);
d650ac06 2682
2707e444
ZW		 2683 if (enable_out_of_sync)
2684 clean_spt_oos(gvt);
2685}
d650ac06 2686
730c8ead
ZW		 2687/**
2688 * intel_vgpu_invalidate_ppgtt - invalidate PPGTT instances
2689 * @vgpu: a vGPU
2690 *
2691 * This function is called when invalidate all PPGTT instances of a vGPU.
2692 *
2693 */
2694void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
2695{
2696 struct list_head *pos, *n;
2697 struct intel_vgpu_mm *mm;
2698
2699 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2700 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2701 if (mm->type == INTEL_GVT_MM_PPGTT) {
2702 list_del_init(&mm->ppgtt_mm.lru_list);
2703 if (mm->ppgtt_mm.shadowed)
2704 invalidate_ppgtt_mm(mm);
2705 }
2706 }
2707}
2708
d650ac06
PG		 2709/**
2710 * intel_vgpu_reset_ggtt - reset the GGTT entry
2711 * @vgpu: a vGPU
f4c43db3 2712 * @invalidate_old: invalidate old entries
d650ac06
PG		 2713 *
2714 * This function is called at the vGPU create stage
2715 * to reset all the GGTT entries.
2716 *
2717 */
f4c43db3 2718void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
d650ac06
PG		 2719{
2720 struct intel_gvt *gvt = vgpu->gvt;
5ad59bf0 2721 struct drm_i915_private *dev_priv = gvt->dev_priv;
b0c766bf
CD		 2722 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2723 struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
f4c43db3 2724 struct intel_gvt_gtt_entry old_entry;
d650ac06 2725 u32 index;
d650ac06 2726 u32 num_entries;
d650ac06 2727
b0c766bf
CD		 2728 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2729 pte_ops->set_present(&entry);
d650ac06
PG		 2730
2731 index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2732 num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
f4c43db3
CD		 2733 while (num_entries--) {
2734 if (invalidate_old) {
2735 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2736 ggtt_invalidate_pte(vgpu, &old_entry);
2737 }
b0c766bf 2738 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
f4c43db3 2739 }
d650ac06
PG		 2740
2741 index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2742 num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
f4c43db3
CD		 2743 while (num_entries--) {
2744 if (invalidate_old) {
2745 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2746 ggtt_invalidate_pte(vgpu, &old_entry);
2747 }
b0c766bf 2748 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
f4c43db3 2749 }
5ad59bf0 2750
a143cef7 2751 ggtt_invalidate(dev_priv);
d650ac06 2752}
b611581b
CD		 2753
2754/**
2755 * intel_vgpu_reset_gtt - reset the all GTT related status
2756 * @vgpu: a vGPU
b611581b
CD		 2757 *
2758 * This function is called from vfio core to reset reset all
2759 * GTT related status, including GGTT, PPGTT, scratch page.
2760 *
2761 */
4d3e67bb 2762void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
b611581b 2763{
da9cc8de
PG		 2764 /* Shadow pages are only created when there is no page
2765 * table tracking data, so remove page tracking data after
2766 * removing the shadow pages.
2767 */
ede9d0cf 2768 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
f4c43db3 2769 intel_vgpu_reset_ggtt(vgpu, true);
b611581b 2770}
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