[linux.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __AMDGPU_DM_H__
#define __AMDGPU_DM_H__

#include <drm/drmP.h>
#include <drm/drm_atomic.h>

/*
 * This file contains the definition for amdgpu_display_manager
 * and its API for amdgpu driver's use.
 * This component provides all the display related functionality
 * and this is the only component that calls DAL API.
 * The API contained here intended for amdgpu driver use.
 * The API that is called directly from KMS framework is located
 * in amdgpu_dm_kms.h file
 */

#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
/*
#include "include/amdgpu_dal_power_if.h"
#include "amdgpu_dm_irq.h"
*/

#include "irq_types.h"
#include "signal_types.h"

/* Forward declarations */
struct amdgpu_device;
struct drm_device;
struct amdgpu_dm_irq_handler_data;
struct dc;

struct common_irq_params {
	struct amdgpu_device *adev;
	enum dc_irq_source irq_src;
};

struct irq_list_head {
	struct list_head head;
	/* In case this interrupt needs post-processing, 'work' will be queued*/
	struct work_struct work;
};

struct dm_comressor_info {
	void *cpu_addr;
	struct amdgpu_bo *bo_ptr;
	uint64_t gpu_addr;
};

struct amdgpu_display_manager {
	struct dc *dc;
	struct cgs_device *cgs_device;

	struct amdgpu_device *adev;	/*AMD base driver*/
	struct drm_device *ddev;	/*DRM base driver*/
	u16 display_indexes_num;

	/*
	 * 'irq_source_handler_table' holds a list of handlers
	 * per (DAL) IRQ source.
	 *
	 * Each IRQ source may need to be handled at different contexts.
	 * By 'context' we mean, for example:
	 * - The ISR context, which is the direct interrupt handler.
	 * - The 'deferred' context - this is the post-processing of the
	 *	interrupt, but at a lower priority.
	 *
	 * Note that handlers are called in the same order as they were
	 * registered (FIFO).
	 */
	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];

	struct common_irq_params
	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];

	struct common_irq_params
	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];

	/* this spin lock synchronizes access to 'irq_handler_list_table' */
	spinlock_t irq_handler_list_table_lock;

	struct backlight_device *backlight_dev;

	const struct dc_link *backlight_link;

	struct mod_freesync *freesync_module;

	/**
	 * Caches device atomic state for suspend/resume
	 */
	struct drm_atomic_state *cached_state;

	struct dm_comressor_info compressor;

	const struct firmware *fw_dmcu;
	uint32_t dmcu_fw_version;
};

struct amdgpu_dm_connector {

	struct drm_connector base;
	uint32_t connector_id;

	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;

	/* shared with amdgpu */
	struct amdgpu_hpd hpd;

	/* number of modes generated from EDID at 'dc_sink' */
	int num_modes;

	/* The 'old' sink - before an HPD.
	 * The 'current' sink is in dc_link->sink. */
	struct dc_sink *dc_sink;
	struct dc_link *dc_link;
	struct dc_sink *dc_em_sink;

	/* DM only */
	struct drm_dp_mst_topology_mgr mst_mgr;
	struct amdgpu_dm_dp_aux dm_dp_aux;
	struct drm_dp_mst_port *port;
	struct amdgpu_dm_connector *mst_port;
	struct amdgpu_encoder *mst_encoder;

	/* TODO see if we can merge with ddc_bus or make a dm_connector */
	struct amdgpu_i2c_adapter *i2c;

	/* Monitor range limits */
	int min_vfreq ;
	int max_vfreq ;
	int pixel_clock_mhz;

	struct mutex hpd_lock;

	bool fake_enable;
};

#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)

extern const struct amdgpu_ip_block_version dm_ip_block;

struct amdgpu_framebuffer;
struct amdgpu_display_manager;
struct dc_validation_set;
struct dc_plane_state;

struct dm_plane_state {
	struct drm_plane_state base;
	struct dc_plane_state *dc_state;
};

struct dm_crtc_state {
	struct drm_crtc_state base;
	struct dc_stream_state *stream;

	int crc_skip_count;
	bool crc_enabled;

	bool freesync_enabled;
	struct dc_crtc_timing_adjust adjust;
	struct dc_info_packet vrr_infopacket;
};

#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)

struct dm_atomic_state {
	struct drm_atomic_state base;

	struct dc_state *context;
};

#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)

struct dm_connector_state {
	struct drm_connector_state base;

	enum amdgpu_rmx_type scaling;
	uint8_t underscan_vborder;
	uint8_t underscan_hborder;
	uint8_t max_bpc;
	bool underscan_enable;
	bool freesync_enable;
	bool freesync_capable;
};

#define to_dm_connector_state(x)\
	container_of((x), struct dm_connector_state, base)

void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
struct drm_connector_state *
amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
					    struct drm_connector_state *state,
					    struct drm_property *property,
					    uint64_t val);

int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
					    const struct drm_connector_state *state,
					    struct drm_property *property,
					    uint64_t *val);

int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);

void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
				     struct amdgpu_dm_connector *aconnector,
				     int connector_type,
				     struct dc_link *link,
				     int link_index);

enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
				   struct drm_display_mode *mode);

void dm_restore_drm_connector_state(struct drm_device *dev,
				    struct drm_connector *connector);

void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
					struct edid *edid);

/* amdgpu_dm_crc.c */
#ifdef CONFIG_DEBUG_FS
int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
				     const char *src_name,
				     size_t *values_cnt);
void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
#else
#define amdgpu_dm_crtc_set_crc_source NULL
#define amdgpu_dm_crtc_verify_crc_source NULL
#define amdgpu_dm_crtc_handle_crc_irq(x)
#endif

#define MAX_COLOR_LUT_ENTRIES 4096
/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
#define MAX_COLOR_LEGACY_LUT_ENTRIES 256

void amdgpu_dm_init_color_mod(void);
int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
			      struct dc_plane_state *dc_plane_state);
void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);

extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;

#endif /* __AMDGPU_DM_H__ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __AMDGPU_DM_H__
	27	#define __AMDGPU_DM_H__
	28
e7b07cee HW	29	#include <drm/drmP.h>
e7b07cee HW	30	#include <drm/drm_atomic.h>
4562236b HW	31
	32	/*
	33	* This file contains the definition for amdgpu_display_manager
	34	* and its API for amdgpu driver's use.
	35	* This component provides all the display related functionality
	36	* and this is the only component that calls DAL API.
	37	* The API contained here intended for amdgpu driver use.
	38	* The API that is called directly from KMS framework is located
	39	* in amdgpu_dm_kms.h file
	40	*/
	41
	42	#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
	43	/*
	44	#include "include/amdgpu_dal_power_if.h"
	45	#include "amdgpu_dm_irq.h"
	46	*/
	47
	48	#include "irq_types.h"
	49	#include "signal_types.h"
	50
	51	/* Forward declarations */
	52	struct amdgpu_device;
	53	struct drm_device;
	54	struct amdgpu_dm_irq_handler_data;
c99c7d6e	55	struct dc;
4562236b	56
4562236b HW	57	struct common_irq_params {
	58	struct amdgpu_device *adev;
	59	enum dc_irq_source irq_src;
	60	};
	61
	62	struct irq_list_head {
	63	struct list_head head;
	64	/* In case this interrupt needs post-processing, 'work' will be queued*/
	65	struct work_struct work;
	66	};
	67
a32e24b4 RL	68	struct dm_comressor_info {
	69	void *cpu_addr;
	70	struct amdgpu_bo *bo_ptr;
	71	uint64_t gpu_addr;
	72	};
a32e24b4	73
4562236b	74	struct amdgpu_display_manager {
4562236b HW	75	struct dc *dc;
4562236b HW	76	struct cgs_device *cgs_device;
4562236b HW	77
	78	struct amdgpu_device adev; /AMD base driver*/
	79	struct drm_device ddev; /DRM base driver*/
	80	u16 display_indexes_num;
	81
4562236b HW	82	/*
	83	* 'irq_source_handler_table' holds a list of handlers
	84	* per (DAL) IRQ source.
	85	*
	86	* Each IRQ source may need to be handled at different contexts.
	87	* By 'context' we mean, for example:
	88	* - The ISR context, which is the direct interrupt handler.
	89	* - The 'deferred' context - this is the post-processing of the
	90	* interrupt, but at a lower priority.
	91	*
	92	* Note that handlers are called in the same order as they were
	93	* registered (FIFO).
	94	*/
	95	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
	96	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
	97
	98	struct common_irq_params
	99	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
	100
	101	struct common_irq_params
b57de80a	102	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
4562236b HW	103
	104	/* this spin lock synchronizes access to 'irq_handler_list_table' */
	105	spinlock_t irq_handler_list_table_lock;
	106
4562236b HW	107	struct backlight_device *backlight_dev;
	108
	109	const struct dc_link *backlight_link;
	110
4562236b	111	struct mod_freesync *freesync_module;
a3621485 AG	112
	113	/**
	114	* Caches device atomic state for suspend/resume
	115	*/
	116	struct drm_atomic_state *cached_state;
5099114b	117
a32e24b4	118	struct dm_comressor_info compressor;
a94d5569 DF	119
a94d5569 DF	120	const struct firmware *fw_dmcu;
ee6e89c0	121	uint32_t dmcu_fw_version;
4562236b HW	122	};
4562236b HW	123
c84dec2f HW	124	struct amdgpu_dm_connector {
	125
	126	struct drm_connector base;
	127	uint32_t connector_id;
	128
	129	/* we need to mind the EDID between detect
	130	and get modes due to analog/digital/tvencoder */
	131	struct edid *edid;
	132
	133	/* shared with amdgpu */
	134	struct amdgpu_hpd hpd;
	135
	136	/* number of modes generated from EDID at 'dc_sink' */
	137	int num_modes;
	138
	139	/* The 'old' sink - before an HPD.
	140	* The 'current' sink is in dc_link->sink. */
	141	struct dc_sink *dc_sink;
	142	struct dc_link *dc_link;
	143	struct dc_sink *dc_em_sink;
	144
	145	/* DM only */
	146	struct drm_dp_mst_topology_mgr mst_mgr;
	147	struct amdgpu_dm_dp_aux dm_dp_aux;
	148	struct drm_dp_mst_port *port;
	149	struct amdgpu_dm_connector *mst_port;
	150	struct amdgpu_encoder *mst_encoder;
	151
	152	/* TODO see if we can merge with ddc_bus or make a dm_connector */
	153	struct amdgpu_i2c_adapter *i2c;
	154
	155	/* Monitor range limits */
	156	int min_vfreq ;
	157	int max_vfreq ;
	158	int pixel_clock_mhz;
	159
c84dec2f	160	struct mutex hpd_lock;
2e0ac3d6 HW	161
2e0ac3d6 HW	162	bool fake_enable;
c84dec2f HW	163	};
	164
	165	#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
	166
4562236b HW	167	extern const struct amdgpu_ip_block_version dm_ip_block;
4562236b HW	168
e7b07cee HW	169	struct amdgpu_framebuffer;
	170	struct amdgpu_display_manager;
	171	struct dc_validation_set;
c9614aeb	172	struct dc_plane_state;
e7b07cee	173
e7b07cee HW	174	struct dm_plane_state {
e7b07cee HW	175	struct drm_plane_state base;
3be5262e	176	struct dc_plane_state *dc_state;
e7b07cee HW	177	};
	178
	179	struct dm_crtc_state {
	180	struct drm_crtc_state base;
0971c40e	181	struct dc_stream_state *stream;
31aec354	182
a0a31ec4	183	int crc_skip_count;
d1bd7d61	184	bool crc_enabled;
98e6436d AK	185
	186	bool freesync_enabled;
	187	struct dc_crtc_timing_adjust adjust;
	188	struct dc_info_packet vrr_infopacket;
e7b07cee HW	189	};
e7b07cee HW	190
98e6436d	191	#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
e7b07cee HW	192
	193	struct dm_atomic_state {
	194	struct drm_atomic_state base;
	195
608ac7bb	196	struct dc_state *context;
e7b07cee HW	197	};
	198
	199	#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
	200
b3734397 HW	201	struct dm_connector_state {
	202	struct drm_connector_state base;
	203
	204	enum amdgpu_rmx_type scaling;
	205	uint8_t underscan_vborder;
	206	uint8_t underscan_hborder;
07e3a1cf	207	uint8_t max_bpc;
b3734397	208	bool underscan_enable;
98e6436d	209	bool freesync_enable;
8218d7f1	210	bool freesync_capable;
b3734397 HW	211	};
	212
	213	#define to_dm_connector_state(x)\
	214	container_of((x), struct dm_connector_state, base)
e7b07cee	215
e7b07cee	216	void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
3ee6b26b AD	217	struct drm_connector_state *
	218	amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
	219	int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
	220	struct drm_connector_state *state,
	221	struct drm_property *property,
	222	uint64_t val);
	223
	224	int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
	225	const struct drm_connector_state *state,
	226	struct drm_property *property,
	227	uint64_t *val);
e7b07cee HW	228
	229	int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
	230
3ee6b26b AD	231	void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
	232	struct amdgpu_dm_connector *aconnector,
	233	int connector_type,
	234	struct dc_link *link,
	235	int link_index);
e7b07cee	236
ba9ca088	237	enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b	238	struct drm_display_mode *mode);
e7b07cee	239
3ee6b26b AD	240	void dm_restore_drm_connector_state(struct drm_device *dev,
3ee6b26b AD	241	struct drm_connector *connector);
e7b07cee	242
98e6436d AK	243	void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
98e6436d AK	244	struct edid *edid);
e7b07cee	245
31aec354 LSL	246	/* amdgpu_dm_crc.c */
31aec354 LSL	247	#ifdef CONFIG_DEBUG_FS
c0811a7d	248	int amdgpu_dm_crtc_set_crc_source(struct drm_crtc crtc, const char src_name);
3b3b8448 MK	249	int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
	250	const char *src_name,
	251	size_t *values_cnt);
31aec354 LSL	252	void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
	253	#else
	254	#define amdgpu_dm_crtc_set_crc_source NULL
3b3b8448	255	#define amdgpu_dm_crtc_verify_crc_source NULL
fdb401d0	256	#define amdgpu_dm_crtc_handle_crc_irq(x)
31aec354 LSL	257	#endif
31aec354 LSL	258
086247a4 LSL	259	#define MAX_COLOR_LUT_ENTRIES 4096
	260	/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
	261	#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
236d0e4f	262
e277adc5	263	void amdgpu_dm_init_color_mod(void);
303afd2d LSL	264	int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
	265	struct dc_plane_state *dc_plane_state);
	266	void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
	267	int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);
	268
e7b07cee HW	269	extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
e7b07cee HW	270
4562236b	271	#endif /* __AMDGPU_DM_H__ */