[linux.git] / drivers / gpu / drm / amd / amdgpu / gfxhub_v1_0.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "gfxhub_v1_0.h"

#include "gc/gc_9_0_offset.h"
#include "gc/gc_9_0_sh_mask.h"
#include "gc/gc_9_0_default.h"
#include "vega10_enum.h"

#include "soc15_common.h"

u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
{
	return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
}

static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
{
	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);

	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
		     lower_32_bits(value));

	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
		     upper_32_bits(value));
}

static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
{
	gfxhub_v1_0_init_gart_pt_regs(adev);

	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
		     (u32)(adev->gmc.gart_start >> 12));
	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
		     (u32)(adev->gmc.gart_start >> 44));

	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
		     (u32)(adev->gmc.gart_end >> 12));
	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
		     (u32)(adev->gmc.gart_end >> 44));
}

static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
{
	uint64_t value;

	/* Program the AGP BAR */
	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
	WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

	/* Program the system aperture low logical page number. */
	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);

	if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
		/*
		 * Raven2 has a HW issue that it is unable to use the vram which
		 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
		 * workaround that increase system aperture high address (add 1)
		 * to get rid of the VM fault and hardware hang.
		 */
		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
			     max((adev->gmc.fb_end >> 18) + 0x1,
				 adev->gmc.agp_end >> 18));
	else
		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);

	/* Set default page address. */
	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
		+ adev->vm_manager.vram_base_offset;
	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
		     (u32)(value >> 12));
	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
		     (u32)(value >> 44));

	/* Program "protection fault". */
	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
		     (u32)(adev->dummy_page_addr >> 12));
	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
		     (u32)((u64)adev->dummy_page_addr >> 44));

	WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
		       ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
}

static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
{
	uint32_t tmp;

	/* Setup TLB control */
	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
			    MTYPE, MTYPE_UC);/* XXX for emulation. */
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
}

static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
{
	uint32_t tmp;

	/* Setup L2 cache */
	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
	/* XXX for emulation, Refer to closed source code.*/
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
			    0);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
	WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);

	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);

	tmp = mmVM_L2_CNTL3_DEFAULT;
	if (adev->gmc.translate_further) {
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
	} else {
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
	}
	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);

	tmp = mmVM_L2_CNTL4_DEFAULT;
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
	WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
}

static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
{
	uint32_t tmp;

	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
}

static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
{
	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
		     0XFFFFFFFF);
	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
		     0x0000000F);

	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
		     0);
	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
		     0);

	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);

}

static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
{
	unsigned num_level, block_size;
	uint32_t tmp;
	int i;

	num_level = adev->vm_manager.num_level;
	block_size = adev->vm_manager.block_size;
	if (adev->gmc.translate_further)
		num_level -= 1;
	else
		block_size -= 9;

	for (i = 0; i <= 14; i++) {
		tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
				    num_level);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
				    1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    PAGE_TABLE_BLOCK_SIZE,
				    block_size);
		/* Send no-retry XNACK on fault to suppress VM fault storm. */
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
			lower_32_bits(adev->vm_manager.max_pfn - 1));
		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
			upper_32_bits(adev->vm_manager.max_pfn - 1));
	}
}

static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
{
	unsigned i;

	for (i = 0 ; i < 18; ++i) {
		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
				    2 * i, 0xffffffff);
		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
				    2 * i, 0x1f);
	}
}

int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{
	if (amdgpu_sriov_vf(adev)) {
		/*
		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
		 * VF copy registers so vbios post doesn't program them, for
		 * SRIOV driver need to program them
		 */
		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE,
			     adev->gmc.vram_start >> 24);
		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP,
			     adev->gmc.vram_end >> 24);
	}

	/* GART Enable. */
	gfxhub_v1_0_init_gart_aperture_regs(adev);
	gfxhub_v1_0_init_system_aperture_regs(adev);
	gfxhub_v1_0_init_tlb_regs(adev);
	gfxhub_v1_0_init_cache_regs(adev);

	gfxhub_v1_0_enable_system_domain(adev);
	gfxhub_v1_0_disable_identity_aperture(adev);
	gfxhub_v1_0_setup_vmid_config(adev);
	gfxhub_v1_0_program_invalidation(adev);

	return 0;
}

void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
{
	u32 tmp;
	u32 i;

	/* Disable all tables */
	for (i = 0; i < 16; i++)
		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);

	/* Setup TLB control */
	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				ENABLE_ADVANCED_DRIVER_MODEL,
				0);
	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

	/* Setup L2 cache */
	WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
}

/**
 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 *
 * @adev: amdgpu_device pointer
 * @value: true redirects VM faults to the default page
 */
void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
					  bool value)
{
	u32 tmp;
	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp,
			VM_L2_PROTECTION_FAULT_CNTL,
			TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
			value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	if (!value) {
		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
				CRASH_ON_NO_RETRY_FAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
				CRASH_ON_RETRY_FAULT, 1);
    }
	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
}

void gfxhub_v1_0_init(struct amdgpu_device *adev)
{
	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];

	hub->ctx0_ptb_addr_lo32 =
		SOC15_REG_OFFSET(GC, 0,
				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	hub->ctx0_ptb_addr_hi32 =
		SOC15_REG_OFFSET(GC, 0,
				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	hub->vm_inv_eng0_req =
		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
	hub->vm_inv_eng0_ack =
		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
	hub->vm_context0_cntl =
		SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
	hub->vm_l2_pro_fault_status =
		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
	hub->vm_l2_pro_fault_cntl =
		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
}
Commit	Line	Data
e60f8db5 AX	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "gfxhub_v1_0.h"
	25
cde5c34f FX	26	#include "gc/gc_9_0_offset.h"
	27	#include "gc/gc_9_0_sh_mask.h"
	28	#include "gc/gc_9_0_default.h"
fb960bd2	29	#include "vega10_enum.h"
e60f8db5 AX	30
	31	#include "soc15_common.h"
	32
2d8e898e CZ	33	u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
2d8e898e CZ	34	{
f7047402	35	return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
2d8e898e CZ	36	}
2d8e898e CZ	37
a51dca4f HR	38	static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
a51dca4f HR	39	{
11c3a249	40	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
a51dca4f	41
89f99ceb HR	42	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
89f99ceb HR	43	lower_32_bits(value));
a51dca4f	44
89f99ceb HR	45	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
89f99ceb HR	46	upper_32_bits(value));
a51dca4f HR	47	}
a51dca4f HR	48
9bbad6fd HR	49	static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
	50	{
	51	gfxhub_v1_0_init_gart_pt_regs(adev);
	52
89f99ceb	53	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
770d13b1	54	(u32)(adev->gmc.gart_start >> 12));
89f99ceb	55	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
770d13b1	56	(u32)(adev->gmc.gart_start >> 44));
89f99ceb HR	57
89f99ceb HR	58	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
770d13b1	59	(u32)(adev->gmc.gart_end >> 12));
89f99ceb	60	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
770d13b1	61	(u32)(adev->gmc.gart_end >> 44));
9bbad6fd HR	62	}
9bbad6fd HR	63
fc4b884b	64	static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
e60f8db5	65	{
fc4b884b	66	uint64_t value;
e60f8db5	67
c3e1b43c	68	/* Program the AGP BAR */
89f99ceb	69	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
c3e1b43c CK	70	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
c3e1b43c CK	71	WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
a51dca4f	72
fc4b884b	73	/* Program the system aperture low logical page number. */
89f99ceb	74	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
5581c670	75	min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
76006776 HR	76
	77	if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
	78	/*
	79	* Raven2 has a HW issue that it is unable to use the vram which
	80	* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
	81	* workaround that increase system aperture high address (add 1)
	82	* to get rid of the VM fault and hardware hang.
	83	*/
	84	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
5581c670	85	max((adev->gmc.fb_end >> 18) + 0x1,
75986276	86	adev->gmc.agp_end >> 18));
76006776 HR	87	else
76006776 HR	88	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
5581c670	89	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
e60f8db5	90
fc4b884b	91	/* Set default page address. */
770d13b1	92	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
e60f8db5	93	+ adev->vm_manager.vram_base_offset;
89f99ceb HR	94	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
	95	(u32)(value >> 12));
	96	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
	97	(u32)(value >> 44));
fc4b884b HR	98
fc4b884b HR	99	/* Program "protection fault". */
89f99ceb	100	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
92e71b06	101	(u32)(adev->dummy_page_addr >> 12));
89f99ceb	102	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
92e71b06	103	(u32)((u64)adev->dummy_page_addr >> 44));
89f99ceb	104
805cb75c TSD	105	WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
805cb75c TSD	106	ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
fc4b884b HR	107	}
fc4b884b HR	108
34269839 HR	109	static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
	110	{
	111	uint32_t tmp;
	112
	113	/* Setup TLB control */
89f99ceb	114	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
34269839 HR	115
	116	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	117	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
	118	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
	119	ENABLE_ADVANCED_DRIVER_MODEL, 1);
	120	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
	121	SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
	122	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
	123	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
	124	MTYPE, MTYPE_UC);/* XXX for emulation. */
	125	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
	126
89f99ceb	127	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
34269839 HR	128	}
34269839 HR	129
41f6f311 HR	130	static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
41f6f311 HR	131	{
a3ce3645	132	uint32_t tmp;
41f6f311 HR	133
41f6f311 HR	134	/* Setup L2 cache */
89f99ceb	135	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
41f6f311	136	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
6be7adb3	137	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
41f6f311 HR	138	/* XXX for emulation, Refer to closed source code.*/
	139	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
	140	0);
	141	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
	142	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
	143	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
89f99ceb	144	WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
41f6f311	145
89f99ceb	146	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
41f6f311 HR	147	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
41f6f311 HR	148	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
89f99ceb	149	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
41f6f311 HR	150
41f6f311 HR	151	tmp = mmVM_L2_CNTL3_DEFAULT;
770d13b1	152	if (adev->gmc.translate_further) {
6a42fd6f CK	153	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
	154	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
	155	L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
	156	} else {
	157	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
	158	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
	159	L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
	160	}
89f99ceb	161	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
41f6f311 HR	162
	163	tmp = mmVM_L2_CNTL4_DEFAULT;
	164	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
	165	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
89f99ceb	166	WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
41f6f311 HR	167	}
41f6f311 HR	168
02c4704b HR	169	static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
	170	{
	171	uint32_t tmp;
	172
89f99ceb	173	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
02c4704b HR	174	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
02c4704b HR	175	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
89f99ceb	176	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
02c4704b HR	177	}
02c4704b HR	178
d5c87390 HR	179	static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
d5c87390 HR	180	{
89f99ceb HR	181	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
	182	0XFFFFFFFF);
	183	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
	184	0x0000000F);
	185
	186	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
	187	0);
	188	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
	189	0);
	190
	191	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
	192	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
d5c87390 HR	193
	194	}
	195
3dff4cc4	196	static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
fc4b884b	197	{
6a42fd6f	198	unsigned num_level, block_size;
3dff4cc4	199	uint32_t tmp;
6a42fd6f CK	200	int i;
	201
	202	num_level = adev->vm_manager.num_level;
	203	block_size = adev->vm_manager.block_size;
770d13b1	204	if (adev->gmc.translate_further)
6a42fd6f CK	205	num_level -= 1;
	206	else
	207	block_size -= 9;
e60f8db5 AX	208
e60f8db5 AX	209	for (i = 0; i <= 14; i++) {
f7047402	210	tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
e60f8db5	211	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
4fb1cf3a	212	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
6a42fd6f	213	num_level);
e60f8db5	214	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f	215	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
e60f8db5	216	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f CK	217	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
6a42fd6f CK	218	1);
e60f8db5	219	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f	220	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
e60f8db5	221	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f	222	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
e60f8db5	223	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f	224	READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
e60f8db5	225	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f	226	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
e60f8db5	227	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f	228	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
e60f8db5	229	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
6a42fd6f CK	230	PAGE_TABLE_BLOCK_SIZE,
6a42fd6f CK	231	block_size);
9f57f7b4 JC	232	/* Send no-retry XNACK on fault to suppress VM fault storm. */
	233	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	234	RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
f7047402 TSD	235	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
	236	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
	237	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
	238	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
22770e5a	239	lower_32_bits(adev->vm_manager.max_pfn - 1));
f7047402	240	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
22770e5a	241	upper_32_bits(adev->vm_manager.max_pfn - 1));
e60f8db5	242	}
3dff4cc4 HR	243	}
3dff4cc4 HR	244
1e4eccda HR	245	static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
	246	{
	247	unsigned i;
	248
	249	for (i = 0 ; i < 18; ++i) {
f7047402 TSD	250	WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
	251	2 * i, 0xffffffff);
	252	WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
	253	2 * i, 0x1f);
1e4eccda HR	254	}
	255	}
	256
3dff4cc4 HR	257	int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
	258	{
	259	if (amdgpu_sriov_vf(adev)) {
	260	/*
	261	* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
	262	* VF copy registers so vbios post doesn't program them, for
	263	* SRIOV driver need to program them
	264	*/
89f99ceb	265	WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE,
770d13b1	266	adev->gmc.vram_start >> 24);
89f99ceb	267	WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP,
770d13b1	268	adev->gmc.vram_end >> 24);
3dff4cc4 HR	269	}
	270
	271	/* GART Enable. */
	272	gfxhub_v1_0_init_gart_aperture_regs(adev);
	273	gfxhub_v1_0_init_system_aperture_regs(adev);
	274	gfxhub_v1_0_init_tlb_regs(adev);
	275	gfxhub_v1_0_init_cache_regs(adev);
e60f8db5	276
3dff4cc4 HR	277	gfxhub_v1_0_enable_system_domain(adev);
	278	gfxhub_v1_0_disable_identity_aperture(adev);
	279	gfxhub_v1_0_setup_vmid_config(adev);
1e4eccda	280	gfxhub_v1_0_program_invalidation(adev);
e60f8db5 AX	281
	282	return 0;
	283	}
	284
	285	void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
	286	{
	287	u32 tmp;
	288	u32 i;
	289
	290	/* Disable all tables */
	291	for (i = 0; i < 16; i++)
f7047402	292	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
e60f8db5 AX	293
e60f8db5 AX	294	/* Setup TLB control */
89f99ceb	295	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
e60f8db5 AX	296	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	297	tmp = REG_SET_FIELD(tmp,
	298	MC_VM_MX_L1_TLB_CNTL,
	299	ENABLE_ADVANCED_DRIVER_MODEL,
	300	0);
89f99ceb	301	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
e60f8db5 AX	302
e60f8db5 AX	303	/* Setup L2 cache */
805cb75c	304	WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
89f99ceb	305	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
e60f8db5 AX	306	}
	307
	308	/**
	309	* gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
	310	*
	311	* @adev: amdgpu_device pointer
	312	* @value: true redirects VM faults to the default page
	313	*/
	314	void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
	315	bool value)
	316	{
	317	u32 tmp;
89f99ceb	318	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
e60f8db5 AX	319	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	320	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	321	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	322	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	323	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	324	PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	325	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	326	PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	327	tmp = REG_SET_FIELD(tmp,
	328	VM_L2_PROTECTION_FAULT_CNTL,
	329	TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
	330	value);
	331	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	332	NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	333	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	334	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	335	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	336	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	337	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	338	READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	339	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	340	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	341	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	342	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
4bd9a67e ML	343	if (!value) {
	344	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	345	CRASH_ON_NO_RETRY_FAULT, 1);
	346	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	347	CRASH_ON_RETRY_FAULT, 1);
	348	}
89f99ceb	349	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
e60f8db5 AX	350	}
e60f8db5 AX	351
0c8c0847	352	void gfxhub_v1_0_init(struct amdgpu_device *adev)
e60f8db5	353	{
e60f8db5 AX	354	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
	355
	356	hub->ctx0_ptb_addr_lo32 =
	357	SOC15_REG_OFFSET(GC, 0,
	358	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	359	hub->ctx0_ptb_addr_hi32 =
	360	SOC15_REG_OFFSET(GC, 0,
	361	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	362	hub->vm_inv_eng0_req =
	363	SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
	364	hub->vm_inv_eng0_ack =
	365	SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
	366	hub->vm_context0_cntl =
	367	SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
	368	hub->vm_l2_pro_fault_status =
	369	SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
	370	hub->vm_l2_pro_fault_cntl =
	371	SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
0c8c0847	372	}