[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_mode.h

/*
 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
 *                VA Linux Systems Inc., Fremont, California.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Original Authors:
 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
 *
 * Kernel port Author: Dave Airlie
 */

#ifndef AMDGPU_MODE_H
#define AMDGPU_MODE_H

#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_fixed.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/hrtimer.h>
#include "amdgpu_irq.h"

#include <drm/drm_dp_mst_helper.h>
#include "modules/inc/mod_freesync.h"

struct amdgpu_bo;
struct amdgpu_device;
struct amdgpu_encoder;
struct amdgpu_router;
struct amdgpu_hpd;

#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
#define to_amdgpu_plane(x)	container_of(x, struct amdgpu_plane, base)

#define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base);

#define AMDGPU_MAX_HPD_PINS 6
#define AMDGPU_MAX_CRTCS 6
#define AMDGPU_MAX_PLANES 6
#define AMDGPU_MAX_AFMT_BLOCKS 9

enum amdgpu_rmx_type {
	RMX_OFF,
	RMX_FULL,
	RMX_CENTER,
	RMX_ASPECT
};

enum amdgpu_underscan_type {
	UNDERSCAN_OFF,
	UNDERSCAN_ON,
	UNDERSCAN_AUTO,
};

#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10

enum amdgpu_hpd_id {
	AMDGPU_HPD_1 = 0,
	AMDGPU_HPD_2,
	AMDGPU_HPD_3,
	AMDGPU_HPD_4,
	AMDGPU_HPD_5,
	AMDGPU_HPD_6,
	AMDGPU_HPD_NONE = 0xff,
};

enum amdgpu_crtc_irq {
	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	AMDGPU_CRTC_IRQ_VBLANK2,
	AMDGPU_CRTC_IRQ_VBLANK3,
	AMDGPU_CRTC_IRQ_VBLANK4,
	AMDGPU_CRTC_IRQ_VBLANK5,
	AMDGPU_CRTC_IRQ_VBLANK6,
	AMDGPU_CRTC_IRQ_VLINE1,
	AMDGPU_CRTC_IRQ_VLINE2,
	AMDGPU_CRTC_IRQ_VLINE3,
	AMDGPU_CRTC_IRQ_VLINE4,
	AMDGPU_CRTC_IRQ_VLINE5,
	AMDGPU_CRTC_IRQ_VLINE6,
	AMDGPU_CRTC_IRQ_NONE = 0xff
};

enum amdgpu_pageflip_irq {
	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	AMDGPU_PAGEFLIP_IRQ_D2,
	AMDGPU_PAGEFLIP_IRQ_D3,
	AMDGPU_PAGEFLIP_IRQ_D4,
	AMDGPU_PAGEFLIP_IRQ_D5,
	AMDGPU_PAGEFLIP_IRQ_D6,
	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
};

enum amdgpu_flip_status {
	AMDGPU_FLIP_NONE,
	AMDGPU_FLIP_PENDING,
	AMDGPU_FLIP_SUBMITTED
};

#define AMDGPU_MAX_I2C_BUS 16

/* amdgpu gpio-based i2c
 * 1. "mask" reg and bits
 *    grabs the gpio pins for software use
 *    0=not held  1=held
 * 2. "a" reg and bits
 *    output pin value
 *    0=low 1=high
 * 3. "en" reg and bits
 *    sets the pin direction
 *    0=input 1=output
 * 4. "y" reg and bits
 *    input pin value
 *    0=low 1=high
 */
struct amdgpu_i2c_bus_rec {
	bool valid;
	/* id used by atom */
	uint8_t i2c_id;
	/* id used by atom */
	enum amdgpu_hpd_id hpd;
	/* can be used with hw i2c engine */
	bool hw_capable;
	/* uses multi-media i2c engine */
	bool mm_i2c;
	/* regs and bits */
	uint32_t mask_clk_reg;
	uint32_t mask_data_reg;
	uint32_t a_clk_reg;
	uint32_t a_data_reg;
	uint32_t en_clk_reg;
	uint32_t en_data_reg;
	uint32_t y_clk_reg;
	uint32_t y_data_reg;
	uint32_t mask_clk_mask;
	uint32_t mask_data_mask;
	uint32_t a_clk_mask;
	uint32_t a_data_mask;
	uint32_t en_clk_mask;
	uint32_t en_data_mask;
	uint32_t y_clk_mask;
	uint32_t y_data_mask;
};

#define AMDGPU_MAX_BIOS_CONNECTOR 16

/* pll flags */
#define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
#define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
#define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
#define AMDGPU_PLL_LEGACY               (1 << 3)
#define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
#define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
#define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
#define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
#define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
#define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
#define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
#define AMDGPU_PLL_IS_LCD               (1 << 13)
#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)

struct amdgpu_pll {
	/* reference frequency */
	uint32_t reference_freq;

	/* fixed dividers */
	uint32_t reference_div;
	uint32_t post_div;

	/* pll in/out limits */
	uint32_t pll_in_min;
	uint32_t pll_in_max;
	uint32_t pll_out_min;
	uint32_t pll_out_max;
	uint32_t lcd_pll_out_min;
	uint32_t lcd_pll_out_max;
	uint32_t best_vco;

	/* divider limits */
	uint32_t min_ref_div;
	uint32_t max_ref_div;
	uint32_t min_post_div;
	uint32_t max_post_div;
	uint32_t min_feedback_div;
	uint32_t max_feedback_div;
	uint32_t min_frac_feedback_div;
	uint32_t max_frac_feedback_div;

	/* flags for the current clock */
	uint32_t flags;

	/* pll id */
	uint32_t id;
};

struct amdgpu_i2c_chan {
	struct i2c_adapter adapter;
	struct drm_device *dev;
	struct i2c_algo_bit_data bit;
	struct amdgpu_i2c_bus_rec rec;
	struct drm_dp_aux aux;
	bool has_aux;
	struct mutex mutex;
};

struct amdgpu_fbdev;

struct amdgpu_afmt {
	bool enabled;
	int offset;
	bool last_buffer_filled_status;
	int id;
	struct amdgpu_audio_pin *pin;
};

/*
 * Audio
 */
struct amdgpu_audio_pin {
	int			channels;
	int			rate;
	int			bits_per_sample;
	u8			status_bits;
	u8			category_code;
	u32			offset;
	bool			connected;
	u32			id;
};

struct amdgpu_audio {
	bool enabled;
	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
	int num_pins;
};

struct amdgpu_display_funcs {
	/* display watermarks */
	void (*bandwidth_update)(struct amdgpu_device *adev);
	/* get frame count */
	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
	/* set backlight level */
	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
				    u8 level);
	/* get backlight level */
	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
	/* hotplug detect */
	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
	void (*hpd_set_polarity)(struct amdgpu_device *adev,
				 enum amdgpu_hpd_id hpd);
	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
	/* pageflipping */
	void (*page_flip)(struct amdgpu_device *adev,
			  int crtc_id, u64 crtc_base, bool async);
	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
					u32 *vbl, u32 *position);
	/* display topology setup */
	void (*add_encoder)(struct amdgpu_device *adev,
			    uint32_t encoder_enum,
			    uint32_t supported_device,
			    u16 caps);
	void (*add_connector)(struct amdgpu_device *adev,
			      uint32_t connector_id,
			      uint32_t supported_device,
			      int connector_type,
			      struct amdgpu_i2c_bus_rec *i2c_bus,
			      uint16_t connector_object_id,
			      struct amdgpu_hpd *hpd,
			      struct amdgpu_router *router);
	/* it is used to enter or exit into free sync mode */
	int (*notify_freesync)(struct drm_device *dev, void *data,
			       struct drm_file *filp);
	/* it is used to allow enablement of freesync mode */
	int (*set_freesync_property)(struct drm_connector *connector,
				     struct drm_property *property,
				     uint64_t val);


};

struct amdgpu_framebuffer {
	struct drm_framebuffer base;

	/* caching for later use */
	uint64_t address;
};

struct amdgpu_fbdev {
	struct drm_fb_helper helper;
	struct amdgpu_framebuffer rfb;
	struct list_head fbdev_list;
	struct amdgpu_device *adev;
};

struct amdgpu_mode_info {
	struct atom_context *atom_context;
	struct card_info *atom_card_info;
	bool mode_config_initialized;
	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
	/* DVI-I properties */
	struct drm_property *coherent_mode_property;
	/* DAC enable load detect */
	struct drm_property *load_detect_property;
	/* underscan */
	struct drm_property *underscan_property;
	struct drm_property *underscan_hborder_property;
	struct drm_property *underscan_vborder_property;
	/* audio */
	struct drm_property *audio_property;
	/* FMT dithering */
	struct drm_property *dither_property;
	/* maximum number of bits per channel for monitor color */
	struct drm_property *max_bpc_property;
	/* hardcoded DFP edid from BIOS */
	struct edid *bios_hardcoded_edid;
	int bios_hardcoded_edid_size;

	/* pointer to fbdev info structure */
	struct amdgpu_fbdev *rfbdev;
	/* firmware flags */
	u16 firmware_flags;
	/* pointer to backlight encoder */
	struct amdgpu_encoder *bl_encoder;
	u8 bl_level; /* saved backlight level */
	struct amdgpu_audio	audio; /* audio stuff */
	int			num_crtc; /* number of crtcs */
	int			num_hpd; /* number of hpd pins */
	int			num_dig; /* number of dig blocks */
	int			disp_priority;
	const struct amdgpu_display_funcs *funcs;
	const enum drm_plane_type *plane_type;
};

#define AMDGPU_MAX_BL_LEVEL 0xFF

#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

struct amdgpu_backlight_privdata {
	struct amdgpu_encoder *encoder;
	uint8_t negative;
};

#endif

struct amdgpu_atom_ss {
	uint16_t percentage;
	uint16_t percentage_divider;
	uint8_t type;
	uint16_t step;
	uint8_t delay;
	uint8_t range;
	uint8_t refdiv;
	/* asic_ss */
	uint16_t rate;
	uint16_t amount;
};

struct amdgpu_crtc {
	struct drm_crtc base;
	int crtc_id;
	bool enabled;
	bool can_tile;
	uint32_t crtc_offset;
	struct drm_gem_object *cursor_bo;
	uint64_t cursor_addr;
	int cursor_x;
	int cursor_y;
	int cursor_hot_x;
	int cursor_hot_y;
	int cursor_width;
	int cursor_height;
	int max_cursor_width;
	int max_cursor_height;
	enum amdgpu_rmx_type rmx_type;
	u8 h_border;
	u8 v_border;
	fixed20_12 vsc;
	fixed20_12 hsc;
	struct drm_display_mode native_mode;
	u32 pll_id;
	/* page flipping */
	struct amdgpu_flip_work *pflip_works;
	enum amdgpu_flip_status pflip_status;
	int deferred_flip_completion;
	/* pll sharing */
	struct amdgpu_atom_ss ss;
	bool ss_enabled;
	u32 adjusted_clock;
	int bpc;
	u32 pll_reference_div;
	u32 pll_post_div;
	u32 pll_flags;
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	/* for dpm */
	u32 line_time;
	u32 wm_low;
	u32 wm_high;
	u32 lb_vblank_lead_lines;
	struct drm_display_mode hw_mode;
	/* for virtual dce */
	struct hrtimer vblank_timer;
	enum amdgpu_interrupt_state vsync_timer_enabled;

	int otg_inst;
	struct drm_pending_vblank_event *event;
};

struct amdgpu_plane {
	struct drm_plane base;
	enum drm_plane_type plane_type;
};

struct amdgpu_encoder_atom_dig {
	bool linkb;
	/* atom dig */
	bool coherent_mode;
	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	/* atom lvds/edp */
	uint32_t lcd_misc;
	uint16_t panel_pwr_delay;
	uint32_t lcd_ss_id;
	/* panel mode */
	struct drm_display_mode native_mode;
	struct backlight_device *bl_dev;
	int dpms_mode;
	uint8_t backlight_level;
	int panel_mode;
	struct amdgpu_afmt *afmt;
};

struct amdgpu_encoder {
	struct drm_encoder base;
	uint32_t encoder_enum;
	uint32_t encoder_id;
	uint32_t devices;
	uint32_t active_device;
	uint32_t flags;
	uint32_t pixel_clock;
	enum amdgpu_rmx_type rmx_type;
	enum amdgpu_underscan_type underscan_type;
	uint32_t underscan_hborder;
	uint32_t underscan_vborder;
	struct drm_display_mode native_mode;
	void *enc_priv;
	int audio_polling_active;
	bool is_ext_encoder;
	u16 caps;
};

struct amdgpu_connector_atom_dig {
	/* displayport */
	u8 dpcd[DP_RECEIVER_CAP_SIZE];
	u8 dp_sink_type;
	int dp_clock;
	int dp_lane_count;
	bool edp_on;
};

struct amdgpu_gpio_rec {
	bool valid;
	u8 id;
	u32 reg;
	u32 mask;
	u32 shift;
};

struct amdgpu_hpd {
	enum amdgpu_hpd_id hpd;
	u8 plugged_state;
	struct amdgpu_gpio_rec gpio;
};

struct amdgpu_router {
	u32 router_id;
	struct amdgpu_i2c_bus_rec i2c_info;
	u8 i2c_addr;
	/* i2c mux */
	bool ddc_valid;
	u8 ddc_mux_type;
	u8 ddc_mux_control_pin;
	u8 ddc_mux_state;
	/* clock/data mux */
	bool cd_valid;
	u8 cd_mux_type;
	u8 cd_mux_control_pin;
	u8 cd_mux_state;
};

enum amdgpu_connector_audio {
	AMDGPU_AUDIO_DISABLE = 0,
	AMDGPU_AUDIO_ENABLE = 1,
	AMDGPU_AUDIO_AUTO = 2
};

enum amdgpu_connector_dither {
	AMDGPU_FMT_DITHER_DISABLE = 0,
	AMDGPU_FMT_DITHER_ENABLE = 1,
};

struct amdgpu_dm_dp_aux {
	struct drm_dp_aux aux;
	struct ddc_service *ddc_service;
};

struct amdgpu_i2c_adapter {
	struct i2c_adapter base;

	struct ddc_service *ddc_service;
};

#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)

struct amdgpu_connector {
	struct drm_connector base;
	uint32_t connector_id;
	uint32_t devices;
	struct amdgpu_i2c_chan *ddc_bus;
	/* some systems have an hdmi and vga port with a shared ddc line */
	bool shared_ddc;
	bool use_digital;
	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;
	void *con_priv;
	bool dac_load_detect;
	bool detected_by_load; /* if the connection status was determined by load */
	uint16_t connector_object_id;
	struct amdgpu_hpd hpd;
	struct amdgpu_router router;
	struct amdgpu_i2c_chan *router_bus;
	enum amdgpu_connector_audio audio;
	enum amdgpu_connector_dither dither;
	unsigned pixelclock_for_modeset;
};

/* TODO: start to use this struct and remove same field from base one */
struct amdgpu_mst_connector {
	struct amdgpu_connector base;

	struct drm_dp_mst_topology_mgr mst_mgr;
	struct amdgpu_dm_dp_aux dm_dp_aux;
	struct drm_dp_mst_port *port;
	struct amdgpu_connector *mst_port;
	bool is_mst_connector;
	struct amdgpu_encoder *mst_encoder;
};

#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
				((em) == ATOM_ENCODER_MODE_DP_MST))

/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
#define DRM_SCANOUTPOS_VALID        (1 << 0)
#define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
#define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
#define USE_REAL_VBLANKSTART		(1 << 30)
#define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)

void amdgpu_link_encoder_connector(struct drm_device *dev);

struct drm_connector *
amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
struct drm_connector *
amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
				    u32 pixel_clock);

u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);

bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
			      bool use_aux);

void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);

int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
			unsigned int pipe, unsigned int flags, int *vpos,
			int *hpos, ktime_t *stime, ktime_t *etime,
			const struct drm_display_mode *mode);

int amdgpu_display_framebuffer_init(struct drm_device *dev,
				    struct amdgpu_framebuffer *rfb,
				    const struct drm_mode_fb_cmd2 *mode_cmd,
				    struct drm_gem_object *obj);

int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);

void amdgpu_enc_destroy(struct drm_encoder *encoder);
void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
				const struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode);
void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
			     struct drm_display_mode *adjusted_mode);
int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);

/* fbdev layer */
int amdgpu_fbdev_init(struct amdgpu_device *adev);
void amdgpu_fbdev_fini(struct amdgpu_device *adev);
void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);

int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);

/* amdgpu_display.c */
void amdgpu_display_print_display_setup(struct drm_device *dev);
int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
				   struct drm_modeset_acquire_ctx *ctx);
int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				struct drm_pending_vblank_event *event,
				uint32_t page_flip_flags, uint32_t target,
				struct drm_modeset_acquire_ctx *ctx);
extern const struct drm_mode_config_funcs amdgpu_mode_funcs;

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
	3	* VA Linux Systems Inc., Fremont, California.
	4	* Copyright 2008 Red Hat Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Original Authors:
	25	* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
	26	*
	27	* Kernel port Author: Dave Airlie
	28	*/
	29
	30	#ifndef AMDGPU_MODE_H
	31	#define AMDGPU_MODE_H
	32
	33	#include <drm/drm_crtc.h>
	34	#include <drm/drm_edid.h>
9338203c	35	#include <drm/drm_encoder.h>
d38ceaf9 AD	36	#include <drm/drm_dp_helper.h>
	37	#include <drm/drm_fixed.h>
	38	#include <drm/drm_crtc_helper.h>
b516a9ef	39	#include <drm/drm_fb_helper.h>
d38ceaf9	40	#include <drm/drm_plane_helper.h>
4562236b	41	#include <drm/drm_fb_helper.h>
d38ceaf9 AD	42	#include <linux/i2c.h>
d38ceaf9 AD	43	#include <linux/i2c-algo-bit.h>
46ac3622 ED	44	#include <linux/hrtimer.h>
46ac3622 ED	45	#include "amdgpu_irq.h"
d38ceaf9	46
4562236b HW	47	#include <drm/drm_dp_mst_helper.h>
	48	#include "modules/inc/mod_freesync.h"
	49
d38ceaf9 AD	50	struct amdgpu_bo;
	51	struct amdgpu_device;
	52	struct amdgpu_encoder;
	53	struct amdgpu_router;
	54	struct amdgpu_hpd;
	55
	56	#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
	57	#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
	58	#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
	59	#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
64d8b780	60	#define to_amdgpu_plane(x) container_of(x, struct amdgpu_plane, base)
d38ceaf9	61
0604b36c AG	62	#define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base);
0604b36c AG	63
d38ceaf9 AD	64	#define AMDGPU_MAX_HPD_PINS 6
d38ceaf9 AD	65	#define AMDGPU_MAX_CRTCS 6
d4e13b0d	66	#define AMDGPU_MAX_PLANES 6
22384459	67	#define AMDGPU_MAX_AFMT_BLOCKS 9
d38ceaf9 AD	68
	69	enum amdgpu_rmx_type {
	70	RMX_OFF,
	71	RMX_FULL,
	72	RMX_CENTER,
	73	RMX_ASPECT
	74	};
	75
	76	enum amdgpu_underscan_type {
	77	UNDERSCAN_OFF,
	78	UNDERSCAN_ON,
	79	UNDERSCAN_AUTO,
	80	};
	81
	82	#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
	83	#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
	84
	85	enum amdgpu_hpd_id {
	86	AMDGPU_HPD_1 = 0,
	87	AMDGPU_HPD_2,
	88	AMDGPU_HPD_3,
	89	AMDGPU_HPD_4,
	90	AMDGPU_HPD_5,
	91	AMDGPU_HPD_6,
d38ceaf9 AD	92	AMDGPU_HPD_NONE = 0xff,
	93	};
	94
	95	enum amdgpu_crtc_irq {
	96	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	97	AMDGPU_CRTC_IRQ_VBLANK2,
	98	AMDGPU_CRTC_IRQ_VBLANK3,
	99	AMDGPU_CRTC_IRQ_VBLANK4,
	100	AMDGPU_CRTC_IRQ_VBLANK5,
	101	AMDGPU_CRTC_IRQ_VBLANK6,
	102	AMDGPU_CRTC_IRQ_VLINE1,
	103	AMDGPU_CRTC_IRQ_VLINE2,
	104	AMDGPU_CRTC_IRQ_VLINE3,
	105	AMDGPU_CRTC_IRQ_VLINE4,
	106	AMDGPU_CRTC_IRQ_VLINE5,
	107	AMDGPU_CRTC_IRQ_VLINE6,
d38ceaf9 AD	108	AMDGPU_CRTC_IRQ_NONE = 0xff
	109	};
	110
	111	enum amdgpu_pageflip_irq {
	112	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	113	AMDGPU_PAGEFLIP_IRQ_D2,
	114	AMDGPU_PAGEFLIP_IRQ_D3,
	115	AMDGPU_PAGEFLIP_IRQ_D4,
	116	AMDGPU_PAGEFLIP_IRQ_D5,
	117	AMDGPU_PAGEFLIP_IRQ_D6,
d38ceaf9 AD	118	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
	119	};
	120
	121	enum amdgpu_flip_status {
	122	AMDGPU_FLIP_NONE,
	123	AMDGPU_FLIP_PENDING,
	124	AMDGPU_FLIP_SUBMITTED
	125	};
	126
	127	#define AMDGPU_MAX_I2C_BUS 16
	128
	129	/* amdgpu gpio-based i2c
	130	* 1. "mask" reg and bits
	131	* grabs the gpio pins for software use
	132	* 0=not held 1=held
	133	* 2. "a" reg and bits
	134	* output pin value
	135	* 0=low 1=high
	136	* 3. "en" reg and bits
	137	* sets the pin direction
	138	* 0=input 1=output
	139	* 4. "y" reg and bits
	140	* input pin value
	141	* 0=low 1=high
	142	*/
	143	struct amdgpu_i2c_bus_rec {
	144	bool valid;
	145	/* id used by atom */
	146	uint8_t i2c_id;
	147	/* id used by atom */
	148	enum amdgpu_hpd_id hpd;
	149	/* can be used with hw i2c engine */
	150	bool hw_capable;
	151	/* uses multi-media i2c engine */
	152	bool mm_i2c;
	153	/* regs and bits */
	154	uint32_t mask_clk_reg;
	155	uint32_t mask_data_reg;
	156	uint32_t a_clk_reg;
	157	uint32_t a_data_reg;
	158	uint32_t en_clk_reg;
	159	uint32_t en_data_reg;
	160	uint32_t y_clk_reg;
	161	uint32_t y_data_reg;
	162	uint32_t mask_clk_mask;
	163	uint32_t mask_data_mask;
	164	uint32_t a_clk_mask;
	165	uint32_t a_data_mask;
	166	uint32_t en_clk_mask;
	167	uint32_t en_data_mask;
	168	uint32_t y_clk_mask;
	169	uint32_t y_data_mask;
	170	};
	171
	172	#define AMDGPU_MAX_BIOS_CONNECTOR 16
	173
	174	/* pll flags */
	175	#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
	176	#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
	177	#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
	178	#define AMDGPU_PLL_LEGACY (1 << 3)
	179	#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
	180	#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
	181	#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
182	#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
183	#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
184	#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
185	#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
186	#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
187	#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
188	#define AMDGPU_PLL_IS_LCD (1 << 13)
189	#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
190
191	struct amdgpu_pll {
192	/* reference frequency */
193	uint32_t reference_freq;
194
195	/* fixed dividers */
196	uint32_t reference_div;
197	uint32_t post_div;
198
199	/* pll in/out limits */
200	uint32_t pll_in_min;
201	uint32_t pll_in_max;
202	uint32_t pll_out_min;
203	uint32_t pll_out_max;
204	uint32_t lcd_pll_out_min;
205	uint32_t lcd_pll_out_max;
206	uint32_t best_vco;
207
208	/* divider limits */
209	uint32_t min_ref_div;
210	uint32_t max_ref_div;
211	uint32_t min_post_div;
212	uint32_t max_post_div;
213	uint32_t min_feedback_div;
214	uint32_t max_feedback_div;
215	uint32_t min_frac_feedback_div;
216	uint32_t max_frac_feedback_div;
217
218	/* flags for the current clock */
219	uint32_t flags;
220
221	/* pll id */
222	uint32_t id;
223	};
224
225	struct amdgpu_i2c_chan {
226	struct i2c_adapter adapter;
227	struct drm_device *dev;
228	struct i2c_algo_bit_data bit;
229	struct amdgpu_i2c_bus_rec rec;
230	struct drm_dp_aux aux;
231	bool has_aux;
232	struct mutex mutex;
233	};
234
235	struct amdgpu_fbdev;
236
237	struct amdgpu_afmt {
238	bool enabled;
239	int offset;
240	bool last_buffer_filled_status;
241	int id;
242	struct amdgpu_audio_pin *pin;
243	};
244
245	/*
246	* Audio
247	*/
248	struct amdgpu_audio_pin {
249	int channels;
250	int rate;
251	int bits_per_sample;
252	u8 status_bits;
253	u8 category_code;
254	u32 offset;
255	bool connected;
256	u32 id;
257	};
258
259	struct amdgpu_audio {
260	bool enabled;
261	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
262	int num_pins;
263	};
264
d38ceaf9	265	struct amdgpu_display_funcs {
d38ceaf9 AD	266	/* display watermarks */
	267	void (bandwidth_update)(struct amdgpu_device adev);
	268	/* get frame count */
	269	u32 (vblank_get_counter)(struct amdgpu_device adev, int crtc);
d38ceaf9 AD	270	/* set backlight level */
	271	void (backlight_set_level)(struct amdgpu_encoder amdgpu_encoder,
	272	u8 level);
	273	/* get backlight level */
	274	u8 (backlight_get_level)(struct amdgpu_encoder amdgpu_encoder);
	275	/* hotplug detect */
	276	bool (hpd_sense)(struct amdgpu_device adev, enum amdgpu_hpd_id hpd);
	277	void (hpd_set_polarity)(struct amdgpu_device adev,
	278	enum amdgpu_hpd_id hpd);
	279	u32 (hpd_get_gpio_reg)(struct amdgpu_device adev);
	280	/* pageflipping */
	281	void (page_flip)(struct amdgpu_device adev,
cb9e59d7	282	int crtc_id, u64 crtc_base, bool async);
d38ceaf9 AD	283	int (page_flip_get_scanoutpos)(struct amdgpu_device adev, int crtc,
	284	u32 vbl, u32 position);
	285	/* display topology setup */
	286	void (add_encoder)(struct amdgpu_device adev,
	287	uint32_t encoder_enum,
	288	uint32_t supported_device,
	289	u16 caps);
	290	void (add_connector)(struct amdgpu_device adev,
	291	uint32_t connector_id,
	292	uint32_t supported_device,
	293	int connector_type,
	294	struct amdgpu_i2c_bus_rec *i2c_bus,
	295	uint16_t connector_object_id,
	296	struct amdgpu_hpd *hpd,
	297	struct amdgpu_router *router);
4562236b HW	298	/* it is used to enter or exit into free sync mode */
	299	int (notify_freesync)(struct drm_device dev, void *data,
	300	struct drm_file *filp);
	301	/* it is used to allow enablement of freesync mode */
	302	int (set_freesync_property)(struct drm_connector connector,
	303	struct drm_property *property,
	304	uint64_t val);
	305
	306
	307	};
	308
	309	struct amdgpu_framebuffer {
	310	struct drm_framebuffer base;
dd55d12c AG	311
	312	/* caching for later use */
	313	uint64_t address;
4562236b HW	314	};
	315
	316	struct amdgpu_fbdev {
	317	struct drm_fb_helper helper;
	318	struct amdgpu_framebuffer rfb;
	319	struct list_head fbdev_list;
	320	struct amdgpu_device *adev;
d38ceaf9 AD	321	};
	322
	323	struct amdgpu_mode_info {
	324	struct atom_context *atom_context;
	325	struct card_info *atom_card_info;
	326	bool mode_config_initialized;
f195038c	327	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
d4e13b0d	328	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
f195038c	329	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
d38ceaf9 AD	330	/* DVI-I properties */
	331	struct drm_property *coherent_mode_property;
	332	/* DAC enable load detect */
	333	struct drm_property *load_detect_property;
	334	/* underscan */
	335	struct drm_property *underscan_property;
	336	struct drm_property *underscan_hborder_property;
	337	struct drm_property *underscan_vborder_property;
	338	/* audio */
	339	struct drm_property *audio_property;
	340	/* FMT dithering */
	341	struct drm_property *dither_property;
69756c6f NK	342	/* maximum number of bits per channel for monitor color */
69756c6f NK	343	struct drm_property *max_bpc_property;
d38ceaf9 AD	344	/* hardcoded DFP edid from BIOS */
	345	struct edid *bios_hardcoded_edid;
	346	int bios_hardcoded_edid_size;
	347
	348	/* pointer to fbdev info structure */
	349	struct amdgpu_fbdev *rfbdev;
	350	/* firmware flags */
	351	u16 firmware_flags;
	352	/* pointer to backlight encoder */
	353	struct amdgpu_encoder *bl_encoder;
a59b3c80	354	u8 bl_level; /* saved backlight level */
d38ceaf9 AD	355	struct amdgpu_audio audio; /* audio stuff */
	356	int num_crtc; /* number of crtcs */
	357	int num_hpd; /* number of hpd pins */
	358	int num_dig; /* number of dig blocks */
	359	int disp_priority;
	360	const struct amdgpu_display_funcs *funcs;
e04a6123	361	const enum drm_plane_type *plane_type;
d38ceaf9 AD	362	};
	363
	364	#define AMDGPU_MAX_BL_LEVEL 0xFF
	365
	366	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\| defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
	367
	368	struct amdgpu_backlight_privdata {
	369	struct amdgpu_encoder *encoder;
	370	uint8_t negative;
	371	};
	372
	373	#endif
	374
	375	struct amdgpu_atom_ss {
	376	uint16_t percentage;
	377	uint16_t percentage_divider;
	378	uint8_t type;
	379	uint16_t step;
	380	uint8_t delay;
	381	uint8_t range;
	382	uint8_t refdiv;
	383	/* asic_ss */
	384	uint16_t rate;
	385	uint16_t amount;
	386	};
	387
	388	struct amdgpu_crtc {
	389	struct drm_crtc base;
	390	int crtc_id;
d38ceaf9 AD	391	bool enabled;
	392	bool can_tile;
	393	uint32_t crtc_offset;
	394	struct drm_gem_object *cursor_bo;
	395	uint64_t cursor_addr;
29275a9b AD	396	int cursor_x;
	397	int cursor_y;
	398	int cursor_hot_x;
	399	int cursor_hot_y;
d38ceaf9 AD	400	int cursor_width;
	401	int cursor_height;
	402	int max_cursor_width;
	403	int max_cursor_height;
	404	enum amdgpu_rmx_type rmx_type;
	405	u8 h_border;
	406	u8 v_border;
	407	fixed20_12 vsc;
	408	fixed20_12 hsc;
	409	struct drm_display_mode native_mode;
	410	u32 pll_id;
	411	/* page flipping */
d38ceaf9 AD	412	struct amdgpu_flip_work *pflip_works;
	413	enum amdgpu_flip_status pflip_status;
	414	int deferred_flip_completion;
	415	/* pll sharing */
	416	struct amdgpu_atom_ss ss;
	417	bool ss_enabled;
	418	u32 adjusted_clock;
	419	int bpc;
	420	u32 pll_reference_div;
	421	u32 pll_post_div;
	422	u32 pll_flags;
	423	struct drm_encoder *encoder;
	424	struct drm_connector *connector;
	425	/* for dpm */
	426	u32 line_time;
	427	u32 wm_low;
	428	u32 wm_high;
8e36f9d3	429	u32 lb_vblank_lead_lines;
d38ceaf9	430	struct drm_display_mode hw_mode;
0f66356d ED	431	/* for virtual dce */
	432	struct hrtimer vblank_timer;
	433	enum amdgpu_interrupt_state vsync_timer_enabled;
4562236b HW	434
4562236b HW	435	int otg_inst;
dd55d12c	436	struct drm_pending_vblank_event *event;
d38ceaf9 AD	437	};
d38ceaf9 AD	438
d4e13b0d AD	439	struct amdgpu_plane {
	440	struct drm_plane base;
	441	enum drm_plane_type plane_type;
	442	};
	443
d38ceaf9 AD	444	struct amdgpu_encoder_atom_dig {
	445	bool linkb;
	446	/* atom dig */
	447	bool coherent_mode;
	448	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	449	/* atom lvds/edp */
	450	uint32_t lcd_misc;
	451	uint16_t panel_pwr_delay;
	452	uint32_t lcd_ss_id;
	453	/* panel mode */
	454	struct drm_display_mode native_mode;
	455	struct backlight_device *bl_dev;
	456	int dpms_mode;
	457	uint8_t backlight_level;
	458	int panel_mode;
	459	struct amdgpu_afmt *afmt;
	460	};
	461
	462	struct amdgpu_encoder {
	463	struct drm_encoder base;
	464	uint32_t encoder_enum;
	465	uint32_t encoder_id;
	466	uint32_t devices;
	467	uint32_t active_device;
	468	uint32_t flags;
	469	uint32_t pixel_clock;
	470	enum amdgpu_rmx_type rmx_type;
	471	enum amdgpu_underscan_type underscan_type;
	472	uint32_t underscan_hborder;
	473	uint32_t underscan_vborder;
	474	struct drm_display_mode native_mode;
	475	void *enc_priv;
	476	int audio_polling_active;
	477	bool is_ext_encoder;
	478	u16 caps;
	479	};
	480
	481	struct amdgpu_connector_atom_dig {
	482	/* displayport */
	483	u8 dpcd[DP_RECEIVER_CAP_SIZE];
	484	u8 dp_sink_type;
	485	int dp_clock;
	486	int dp_lane_count;
	487	bool edp_on;
	488	};
	489
	490	struct amdgpu_gpio_rec {
	491	bool valid;
	492	u8 id;
	493	u32 reg;
	494	u32 mask;
	495	u32 shift;
	496	};
	497
	498	struct amdgpu_hpd {
	499	enum amdgpu_hpd_id hpd;
	500	u8 plugged_state;
	501	struct amdgpu_gpio_rec gpio;
	502	};
	503
	504	struct amdgpu_router {
	505	u32 router_id;
	506	struct amdgpu_i2c_bus_rec i2c_info;
	507	u8 i2c_addr;
508	/* i2c mux */
509	bool ddc_valid;
510	u8 ddc_mux_type;
511	u8 ddc_mux_control_pin;
512	u8 ddc_mux_state;
513	/* clock/data mux */
514	bool cd_valid;
515	u8 cd_mux_type;
516	u8 cd_mux_control_pin;
517	u8 cd_mux_state;
518	};
519
520	enum amdgpu_connector_audio {
521	AMDGPU_AUDIO_DISABLE = 0,
522	AMDGPU_AUDIO_ENABLE = 1,
523	AMDGPU_AUDIO_AUTO = 2
524	};
525
526	enum amdgpu_connector_dither {
527	AMDGPU_FMT_DITHER_DISABLE = 0,
528	AMDGPU_FMT_DITHER_ENABLE = 1,
529	};
530
4562236b HW	531	struct amdgpu_dm_dp_aux {
4562236b HW	532	struct drm_dp_aux aux;
46df790c	533	struct ddc_service *ddc_service;
4562236b HW	534	};
	535
	536	struct amdgpu_i2c_adapter {
	537	struct i2c_adapter base;
46df790c AG	538
46df790c AG	539	struct ddc_service *ddc_service;
4562236b HW	540	};
	541
	542	#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
	543
d38ceaf9 AD	544	struct amdgpu_connector {
	545	struct drm_connector base;
	546	uint32_t connector_id;
	547	uint32_t devices;
	548	struct amdgpu_i2c_chan *ddc_bus;
	549	/* some systems have an hdmi and vga port with a shared ddc line */
	550	bool shared_ddc;
	551	bool use_digital;
	552	/* we need to mind the EDID between detect
	553	and get modes due to analog/digital/tvencoder */
	554	struct edid *edid;
	555	void *con_priv;
	556	bool dac_load_detect;
	557	bool detected_by_load; /* if the connection status was determined by load */
	558	uint16_t connector_object_id;
	559	struct amdgpu_hpd hpd;
	560	struct amdgpu_router router;
	561	struct amdgpu_i2c_chan *router_bus;
	562	enum amdgpu_connector_audio audio;
	563	enum amdgpu_connector_dither dither;
	564	unsigned pixelclock_for_modeset;
	565	};
	566
4562236b HW	567	/* TODO: start to use this struct and remove same field from base one */
	568	struct amdgpu_mst_connector {
	569	struct amdgpu_connector base;
	570
	571	struct drm_dp_mst_topology_mgr mst_mgr;
	572	struct amdgpu_dm_dp_aux dm_dp_aux;
	573	struct drm_dp_mst_port *port;
	574	struct amdgpu_connector *mst_port;
	575	bool is_mst_connector;
	576	struct amdgpu_encoder *mst_encoder;
d38ceaf9 AD	577	};
	578
	579	#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) \|\| \
	580	((em) == ATOM_ENCODER_MODE_DP_MST))
	581
aa8e286a	582	/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
1bf6ad62 SV	583	#define DRM_SCANOUTPOS_VALID (1 << 0)
	584	#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
	585	#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
edf600da	586	#define USE_REAL_VBLANKSTART (1 << 30)
8e36f9d3 AD	587	#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
8e36f9d3 AD	588
d38ceaf9 AD	589	void amdgpu_link_encoder_connector(struct drm_device *dev);
	590
	591	struct drm_connector *
	592	amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
	593	struct drm_connector *
	594	amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
	595	bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
	596	u32 pixel_clock);
	597
	598	u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
	599	struct drm_encoder amdgpu_get_external_encoder(struct drm_encoder encoder);
	600
e0b5b5ec SL	601	bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
e0b5b5ec SL	602	bool use_aux);
d38ceaf9 AD	603
	604	void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
	605
aa8e286a SL	606	int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
	607	unsigned int pipe, unsigned int flags, int *vpos,
	608	int hpos, ktime_t stime, ktime_t *etime,
	609	const struct drm_display_mode *mode);
d38ceaf9	610
9da3f2d9 SL	611	int amdgpu_display_framebuffer_init(struct drm_device *dev,
	612	struct amdgpu_framebuffer *rfb,
	613	const struct drm_mode_fb_cmd2 *mode_cmd,
	614	struct drm_gem_object *obj);
d38ceaf9 AD	615
	616	int amdgpufb_remove(struct drm_device dev, struct drm_framebuffer fb);
	617
	618	void amdgpu_enc_destroy(struct drm_encoder *encoder);
	619	void amdgpu_copy_fb(struct drm_device dev, struct drm_gem_object dst_obj);
0c16443a SL	620	bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
	621	const struct drm_display_mode *mode,
	622	struct drm_display_mode *adjusted_mode);
d38ceaf9 AD	623	void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
d38ceaf9 AD	624	struct drm_display_mode *adjusted_mode);
734dd01d	625	int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
d38ceaf9 AD	626
	627	/* fbdev layer */
	628	int amdgpu_fbdev_init(struct amdgpu_device *adev);
	629	void amdgpu_fbdev_fini(struct amdgpu_device *adev);
	630	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
	631	int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
	632	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj);
d38ceaf9 AD	633
	634	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
	635
	636	/* amdgpu_display.c */
50af9193	637	void amdgpu_display_print_display_setup(struct drm_device *dev);
3dc9b1ce	638	int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
775a8364 SL	639	int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
775a8364 SL	640	struct drm_modeset_acquire_ctx *ctx);
0cd11932 SL	641	int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
	642	struct drm_framebuffer *fb,
	643	struct drm_pending_vblank_event *event,
	644	uint32_t page_flip_flags, uint32_t target,
	645	struct drm_modeset_acquire_ctx *ctx);
d38ceaf9 AD	646	extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
	647
	648	#endif