[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include "amdgpu_amdkfd.h"
#include "amd_shared.h"
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_gfx.h"
#include <linux/module.h>

const struct kgd2kfd_calls *kgd2kfd;

static const unsigned int compute_vmid_bitmap = 0xFF00;

int amdgpu_amdkfd_init(void)
{
	int ret;

#ifdef CONFIG_HSA_AMD
	ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
	if (ret)
		kgd2kfd = NULL;
	amdgpu_amdkfd_gpuvm_init_mem_limits();
#else
	kgd2kfd = NULL;
	ret = -ENOENT;
#endif

	return ret;
}

void amdgpu_amdkfd_fini(void)
{
	if (kgd2kfd)
		kgd2kfd->exit();
}

void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
{
	const struct kfd2kgd_calls *kfd2kgd;

	if (!kgd2kfd)
		return;

	switch (adev->asic_type) {
#ifdef CONFIG_DRM_AMDGPU_CIK
	case CHIP_KAVERI:
	case CHIP_HAWAII:
		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
		break;
#endif
	case CHIP_CARRIZO:
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_POLARIS10:
	case CHIP_POLARIS11:
		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
		break;
	case CHIP_VEGA10:
	case CHIP_VEGA20:
	case CHIP_RAVEN:
		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
		break;
	default:
		dev_info(adev->dev, "kfd not supported on this ASIC\n");
		return;
	}

	adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
				   adev->pdev, kfd2kgd);
}

/**
 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 *                                setup amdkfd
 *
 * @adev: amdgpu_device pointer
 * @aperture_base: output returning doorbell aperture base physical address
 * @aperture_size: output returning doorbell aperture size in bytes
 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 *
 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 * takes doorbells required for its own rings and reports the setup to amdkfd.
 * amdgpu reserved doorbells are at the start of the doorbell aperture.
 */
static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
					 phys_addr_t *aperture_base,
					 size_t *aperture_size,
					 size_t *start_offset)
{
	/*
	 * The first num_doorbells are used by amdgpu.
	 * amdkfd takes whatever's left in the aperture.
	 */
	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
		*aperture_base = adev->doorbell.base;
		*aperture_size = adev->doorbell.size;
		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
	} else {
		*aperture_base = 0;
		*aperture_size = 0;
		*start_offset = 0;
	}
}

void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
{
	int i, n;
	int last_valid_bit;
	if (adev->kfd) {
		struct kgd2kfd_shared_resources gpu_resources = {
			.compute_vmid_bitmap = compute_vmid_bitmap,
			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
			.gpuvm_size = min(adev->vm_manager.max_pfn
					  << AMDGPU_GPU_PAGE_SHIFT,
					  AMDGPU_GMC_HOLE_START),
			.drm_render_minor = adev->ddev->render->index
		};

		/* this is going to have a few of the MSBs set that we need to
		 * clear */
		bitmap_complement(gpu_resources.queue_bitmap,
				  adev->gfx.mec.queue_bitmap,
				  KGD_MAX_QUEUES);

		/* remove the KIQ bit as well */
		if (adev->gfx.kiq.ring.ready)
			clear_bit(amdgpu_gfx_queue_to_bit(adev,
							  adev->gfx.kiq.ring.me - 1,
							  adev->gfx.kiq.ring.pipe,
							  adev->gfx.kiq.ring.queue),
				  gpu_resources.queue_bitmap);

		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
		 * nbits is not compile time constant */
		last_valid_bit = 1 /* only first MEC can have compute queues */
				* adev->gfx.mec.num_pipe_per_mec
				* adev->gfx.mec.num_queue_per_pipe;
		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
			clear_bit(i, gpu_resources.queue_bitmap);

		amdgpu_doorbell_get_kfd_info(adev,
				&gpu_resources.doorbell_physical_address,
				&gpu_resources.doorbell_aperture_size,
				&gpu_resources.doorbell_start_offset);

		if (adev->asic_type < CHIP_VEGA10) {
			kgd2kfd->device_init(adev->kfd, &gpu_resources);
			return;
		}

		n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;

		for (i = 0; i < n; i += 2) {
			/* On SOC15 the BIF is involved in routing
			 * doorbells using the low 12 bits of the
			 * address. Communicate the assignments to
			 * KFD. KFD uses two doorbell pages per
			 * process in case of 64-bit doorbells so we
			 * can use each doorbell assignment twice.
			 */
			if (adev->asic_type == CHIP_VEGA10) {
				gpu_resources.sdma_doorbell[0][i] =
					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
				gpu_resources.sdma_doorbell[0][i+1] =
					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
				gpu_resources.sdma_doorbell[1][i] =
					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
				gpu_resources.sdma_doorbell[1][i+1] =
					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
			} else {
				gpu_resources.sdma_doorbell[0][i] =
					AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
				gpu_resources.sdma_doorbell[0][i+1] =
					AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
				gpu_resources.sdma_doorbell[1][i] =
					AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
				gpu_resources.sdma_doorbell[1][i+1] =
					AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
			}
		}
		/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
		 * SDMA, IH and VCN. So don't use them for the CP.
		 */
		gpu_resources.reserved_doorbell_mask = 0x1e0;
		gpu_resources.reserved_doorbell_val  = 0x0e0;

		kgd2kfd->device_init(adev->kfd, &gpu_resources);
	}
}

void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
{
	if (adev->kfd) {
		kgd2kfd->device_exit(adev->kfd);
		adev->kfd = NULL;
	}
}

void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
		const void *ih_ring_entry)
{
	if (adev->kfd)
		kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
}

void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
{
	if (adev->kfd)
		kgd2kfd->suspend(adev->kfd);
}

int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
{
	int r = 0;

	if (adev->kfd)
		r = kgd2kfd->resume(adev->kfd);

	return r;
}

int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
{
	int r = 0;

	if (adev->kfd)
		r = kgd2kfd->pre_reset(adev->kfd);

	return r;
}

int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
{
	int r = 0;

	if (adev->kfd)
		r = kgd2kfd->post_reset(adev->kfd);

	return r;
}

void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	if (amdgpu_device_should_recover_gpu(adev))
		amdgpu_device_gpu_recover(adev, NULL);
}

int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
			void **mem_obj, uint64_t *gpu_addr,
			void **cpu_ptr, bool mqd_gfx9)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	struct amdgpu_bo *bo = NULL;
	struct amdgpu_bo_param bp;
	int r;
	void *cpu_ptr_tmp = NULL;

	memset(&bp, 0, sizeof(bp));
	bp.size = size;
	bp.byte_align = PAGE_SIZE;
	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
	bp.type = ttm_bo_type_kernel;
	bp.resv = NULL;

	if (mqd_gfx9)
		bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;

	r = amdgpu_bo_create(adev, &bp, &bo);
	if (r) {
		dev_err(adev->dev,
			"failed to allocate BO for amdkfd (%d)\n", r);
		return r;
	}

	/* map the buffer */
	r = amdgpu_bo_reserve(bo, true);
	if (r) {
		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
		goto allocate_mem_reserve_bo_failed;
	}

	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
	if (r) {
		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
		goto allocate_mem_pin_bo_failed;
	}

	r = amdgpu_ttm_alloc_gart(&bo->tbo);
	if (r) {
		dev_err(adev->dev, "%p bind failed\n", bo);
		goto allocate_mem_kmap_bo_failed;
	}

	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
	if (r) {
		dev_err(adev->dev,
			"(%d) failed to map bo to kernel for amdkfd\n", r);
		goto allocate_mem_kmap_bo_failed;
	}

	*mem_obj = bo;
	*gpu_addr = amdgpu_bo_gpu_offset(bo);
	*cpu_ptr = cpu_ptr_tmp;

	amdgpu_bo_unreserve(bo);

	return 0;

allocate_mem_kmap_bo_failed:
	amdgpu_bo_unpin(bo);
allocate_mem_pin_bo_failed:
	amdgpu_bo_unreserve(bo);
allocate_mem_reserve_bo_failed:
	amdgpu_bo_unref(&bo);

	return r;
}

void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
{
	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;

	amdgpu_bo_reserve(bo, true);
	amdgpu_bo_kunmap(bo);
	amdgpu_bo_unpin(bo);
	amdgpu_bo_unreserve(bo);
	amdgpu_bo_unref(&(bo));
}

void get_local_mem_info(struct kgd_dev *kgd,
			struct kfd_local_mem_info *mem_info)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
					     ~((1ULL << 32) - 1);
	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;

	memset(mem_info, 0, sizeof(*mem_info));
	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
		mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
		mem_info->local_mem_size_private = adev->gmc.real_vram_size -
				adev->gmc.visible_vram_size;
	} else {
		mem_info->local_mem_size_public = 0;
		mem_info->local_mem_size_private = adev->gmc.real_vram_size;
	}
	mem_info->vram_width = adev->gmc.vram_width;

	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
			&adev->gmc.aper_base, &aper_limit,
			mem_info->local_mem_size_public,
			mem_info->local_mem_size_private);

	if (amdgpu_sriov_vf(adev))
		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
	else if (adev->powerplay.pp_funcs)
		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
	else
		mem_info->mem_clk_max = 100;
}

uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	if (adev->gfx.funcs->get_gpu_clock_counter)
		return adev->gfx.funcs->get_gpu_clock_counter(adev);
	return 0;
}

uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	/* the sclk is in quantas of 10kHz */
	if (amdgpu_sriov_vf(adev))
		return adev->clock.default_sclk / 100;
	else if (adev->powerplay.pp_funcs)
		return amdgpu_dpm_get_sclk(adev, false) / 100;
	else
		return 100;
}

void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;

	memset(cu_info, 0, sizeof(*cu_info));
	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
		return;

	cu_info->cu_active_number = acu_info.number;
	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
	       sizeof(acu_info.bitmap));
	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
	cu_info->simd_per_cu = acu_info.simd_per_cu;
	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
	cu_info->wave_front_size = acu_info.wave_front_size;
	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
	cu_info->lds_size = acu_info.lds_size;
}

uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
}

uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	return adev->gmc.xgmi.hive_id;
}

int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
				uint32_t vmid, uint64_t gpu_addr,
				uint32_t *ib_cmd, uint32_t ib_len)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	struct amdgpu_job *job;
	struct amdgpu_ib *ib;
	struct amdgpu_ring *ring;
	struct dma_fence *f = NULL;
	int ret;

	switch (engine) {
	case KGD_ENGINE_MEC1:
		ring = &adev->gfx.compute_ring[0];
		break;
	case KGD_ENGINE_SDMA1:
		ring = &adev->sdma.instance[0].ring;
		break;
	case KGD_ENGINE_SDMA2:
		ring = &adev->sdma.instance[1].ring;
		break;
	default:
		pr_err("Invalid engine in IB submission: %d\n", engine);
		ret = -EINVAL;
		goto err;
	}

	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
	if (ret)
		goto err;

	ib = &job->ibs[0];
	memset(ib, 0, sizeof(struct amdgpu_ib));

	ib->gpu_addr = gpu_addr;
	ib->ptr = ib_cmd;
	ib->length_dw = ib_len;
	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
	job->vmid = vmid;

	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
	if (ret) {
		DRM_ERROR("amdgpu: failed to schedule IB.\n");
		goto err_ib_sched;
	}

	ret = dma_fence_wait(f, false);

err_ib_sched:
	dma_fence_put(f);
	amdgpu_job_free(job);
err:
	return ret;
}

void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	if (adev->powerplay.pp_funcs &&
	    adev->powerplay.pp_funcs->switch_power_profile)
		amdgpu_dpm_switch_power_profile(adev,
						PP_SMC_POWER_PROFILE_COMPUTE,
						!idle);
}

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
{
	if (adev->kfd) {
		if ((1 << vmid) & compute_vmid_bitmap)
			return true;
	}

	return false;
}

#ifndef CONFIG_HSA_AMD
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
{
	return false;
}

void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
{
}

void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
					struct amdgpu_vm *vm)
{
}

struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
{
	return NULL;
}

int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
{
	return 0;
}

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
{
	return NULL;
}

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
{
	return NULL;
}

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
{
	return NULL;
}
#endif
Commit	Line	Data
130e0371 OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#include "amdgpu_amdkfd.h"
2f7d10b3	24	#include "amd_shared.h"
130e0371 OG	25	#include <drm/drmP.h>
130e0371 OG	26	#include "amdgpu.h"
2db0cdbe	27	#include "amdgpu_gfx.h"
130e0371 OG	28	#include <linux/module.h>
130e0371 OG	29
130e0371	30	const struct kgd2kfd_calls *kgd2kfd;
130e0371	31
155494db FK	32	static const unsigned int compute_vmid_bitmap = 0xFF00;
155494db FK	33
efb1c658	34	int amdgpu_amdkfd_init(void)
130e0371	35	{
efb1c658 OG	36	int ret;
efb1c658 OG	37
82b7b619	38	#ifdef CONFIG_HSA_AMD
efb1c658 OG	39	ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
	40	if (ret)
	41	kgd2kfd = NULL;
82b7b619	42	amdgpu_amdkfd_gpuvm_init_mem_limits();
efb1c658	43	#else
fcdfa432	44	kgd2kfd = NULL;
efb1c658	45	ret = -ENOENT;
130e0371	46	#endif
fcdfa432	47
efb1c658	48	return ret;
130e0371 OG	49	}
130e0371 OG	50
5c33f214 FK	51	void amdgpu_amdkfd_fini(void)
5c33f214 FK	52	{
03a1c08d	53	if (kgd2kfd)
5c33f214	54	kgd2kfd->exit();
5c33f214 FK	55	}
	56
	57	void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
130e0371	58	{
5c33f214 FK	59	const struct kfd2kgd_calls *kfd2kgd;
	60
	61	if (!kgd2kfd)
	62	return;
	63
dc102c43	64	switch (adev->asic_type) {
41548ef7	65	#ifdef CONFIG_DRM_AMDGPU_CIK
130e0371	66	case CHIP_KAVERI:
30d13424	67	case CHIP_HAWAII:
32c22e99 OG	68	kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
32c22e99 OG	69	break;
41548ef7	70	#endif
ff758a12	71	case CHIP_CARRIZO:
30d13424 FK	72	case CHIP_TONGA:
	73	case CHIP_FIJI:
	74	case CHIP_POLARIS10:
	75	case CHIP_POLARIS11:
ff758a12 BG	76	kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
ff758a12 BG	77	break;
d5a114a6	78	case CHIP_VEGA10:
ba0f2841	79	case CHIP_VEGA20:
d5a114a6 FK	80	case CHIP_RAVEN:
	81	kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
	82	break;
130e0371	83	default:
c3032fd9	84	dev_info(adev->dev, "kfd not supported on this ASIC\n");
5c33f214	85	return;
130e0371 OG	86	}
130e0371 OG	87
5c33f214 FK	88	adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
5c33f214 FK	89	adev->pdev, kfd2kgd);
130e0371 OG	90	}
130e0371 OG	91
22cb0164 AD	92	/**
	93	* amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
	94	* setup amdkfd
	95	*
	96	* @adev: amdgpu_device pointer
	97	* @aperture_base: output returning doorbell aperture base physical address
	98	* @aperture_size: output returning doorbell aperture size in bytes
	99	* @start_offset: output returning # of doorbell bytes reserved for amdgpu.
	100	*
	101	* amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
	102	* takes doorbells required for its own rings and reports the setup to amdkfd.
	103	* amdgpu reserved doorbells are at the start of the doorbell aperture.
	104	*/
	105	static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
	106	phys_addr_t *aperture_base,
	107	size_t *aperture_size,
	108	size_t *start_offset)
	109	{
	110	/*
	111	* The first num_doorbells are used by amdgpu.
	112	* amdkfd takes whatever's left in the aperture.
	113	*/
	114	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
	115	*aperture_base = adev->doorbell.base;
	116	*aperture_size = adev->doorbell.size;
	117	start_offset = adev->doorbell.num_doorbells sizeof(u32);
	118	} else {
	119	*aperture_base = 0;
	120	*aperture_size = 0;
	121	*start_offset = 0;
	122	}
	123	}
	124
dc102c43	125	void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
130e0371	126	{
c5892230	127	int i, n;
d0b63bb3	128	int last_valid_bit;
dc102c43	129	if (adev->kfd) {
130e0371	130	struct kgd2kfd_shared_resources gpu_resources = {
155494db	131	.compute_vmid_bitmap = compute_vmid_bitmap,
d0b63bb3	132	.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
155494db FK	133	.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
	134	.gpuvm_size = min(adev->vm_manager.max_pfn
	135	<< AMDGPU_GPU_PAGE_SHIFT,
ad9a5b78	136	AMDGPU_GMC_HOLE_START),
155494db	137	.drm_render_minor = adev->ddev->render->index
130e0371 OG	138	};
130e0371 OG	139
d0b63bb3 AR	140	/* this is going to have a few of the MSBs set that we need to
	141	* clear */
	142	bitmap_complement(gpu_resources.queue_bitmap,
	143	adev->gfx.mec.queue_bitmap,
	144	KGD_MAX_QUEUES);
	145
7b2124a5 AR	146	/* remove the KIQ bit as well */
7b2124a5 AR	147	if (adev->gfx.kiq.ring.ready)
2db0cdbe AD	148	clear_bit(amdgpu_gfx_queue_to_bit(adev,
	149	adev->gfx.kiq.ring.me - 1,
	150	adev->gfx.kiq.ring.pipe,
	151	adev->gfx.kiq.ring.queue),
7b2124a5 AR	152	gpu_resources.queue_bitmap);
7b2124a5 AR	153
d0b63bb3 AR	154	/* According to linux/bitmap.h we shouldn't use bitmap_clear if
d0b63bb3 AR	155	* nbits is not compile time constant */
3447d220	156	last_valid_bit = 1 /* only first MEC can have compute queues */
d0b63bb3 AR	157	* adev->gfx.mec.num_pipe_per_mec
	158	* adev->gfx.mec.num_queue_per_pipe;
	159	for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
	160	clear_bit(i, gpu_resources.queue_bitmap);
	161
dc102c43	162	amdgpu_doorbell_get_kfd_info(adev,
130e0371 OG	163	&gpu_resources.doorbell_physical_address,
	164	&gpu_resources.doorbell_aperture_size,
	165	&gpu_resources.doorbell_start_offset);
c5892230 SL	166
	167	if (adev->asic_type < CHIP_VEGA10) {
	168	kgd2kfd->device_init(adev->kfd, &gpu_resources);
	169	return;
	170	}
	171
	172	n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
	173
	174	for (i = 0; i < n; i += 2) {
642a0e80 FK	175	/* On SOC15 the BIF is involved in routing
	176	* doorbells using the low 12 bits of the
	177	* address. Communicate the assignments to
	178	* KFD. KFD uses two doorbell pages per
	179	* process in case of 64-bit doorbells so we
	180	* can use each doorbell assignment twice.
	181	*/
a2a8fb51 ED	182	if (adev->asic_type == CHIP_VEGA10) {
	183	gpu_resources.sdma_doorbell[0][i] =
	184	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
	185	gpu_resources.sdma_doorbell[0][i+1] =
	186	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
	187	gpu_resources.sdma_doorbell[1][i] =
	188	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
	189	gpu_resources.sdma_doorbell[1][i+1] =
	190	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
	191	} else {
	192	gpu_resources.sdma_doorbell[0][i] =
	193	AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
	194	gpu_resources.sdma_doorbell[0][i+1] =
	195	AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
	196	gpu_resources.sdma_doorbell[1][i] =
	197	AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
	198	gpu_resources.sdma_doorbell[1][i+1] =
	199	AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
	200	}
642a0e80	201	}
c5892230 SL	202	/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
	203	* SDMA, IH and VCN. So don't use them for the CP.
	204	*/
	205	gpu_resources.reserved_doorbell_mask = 0x1e0;
	206	gpu_resources.reserved_doorbell_val = 0x0e0;
130e0371	207
dc102c43	208	kgd2kfd->device_init(adev->kfd, &gpu_resources);
130e0371 OG	209	}
	210	}
	211
dc102c43	212	void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
130e0371	213	{
dc102c43 AR	214	if (adev->kfd) {
	215	kgd2kfd->device_exit(adev->kfd);
	216	adev->kfd = NULL;
130e0371 OG	217	}
	218	}
	219
dc102c43	220	void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
130e0371 OG	221	const void *ih_ring_entry)
130e0371 OG	222	{
dc102c43 AR	223	if (adev->kfd)
dc102c43 AR	224	kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
130e0371 OG	225	}
130e0371 OG	226
dc102c43	227	void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
130e0371	228	{
dc102c43 AR	229	if (adev->kfd)
dc102c43 AR	230	kgd2kfd->suspend(adev->kfd);
130e0371 OG	231	}
130e0371 OG	232
dc102c43	233	int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
130e0371 OG	234	{
	235	int r = 0;
	236
dc102c43 AR	237	if (adev->kfd)
dc102c43 AR	238	r = kgd2kfd->resume(adev->kfd);
130e0371 OG	239
	240	return r;
	241	}
	242
5c6dd71e SL	243	int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
	244	{
	245	int r = 0;
	246
	247	if (adev->kfd)
	248	r = kgd2kfd->pre_reset(adev->kfd);
	249
	250	return r;
	251	}
	252
	253	int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
	254	{
	255	int r = 0;
	256
	257	if (adev->kfd)
	258	r = kgd2kfd->post_reset(adev->kfd);
	259
	260	return r;
	261	}
	262
24da5a9c SL	263	void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
	264	{
	265	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	266
12938fad CK	267	if (amdgpu_device_should_recover_gpu(adev))
12938fad CK	268	amdgpu_device_gpu_recover(adev, NULL);
24da5a9c SL	269	}
24da5a9c SL	270
130e0371 OG	271	int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
130e0371 OG	272	void *mem_obj, uint64_t gpu_addr,
15426dbb	273	void **cpu_ptr, bool mqd_gfx9)
130e0371	274	{
dc102c43	275	struct amdgpu_device adev = (struct amdgpu_device )kgd;
473fee47	276	struct amdgpu_bo *bo = NULL;
3216c6b7	277	struct amdgpu_bo_param bp;
130e0371	278	int r;
473fee47	279	void *cpu_ptr_tmp = NULL;
130e0371	280
3216c6b7 CZ	281	memset(&bp, 0, sizeof(bp));
	282	bp.size = size;
	283	bp.byte_align = PAGE_SIZE;
	284	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
	285	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
	286	bp.type = ttm_bo_type_kernel;
	287	bp.resv = NULL;
15426dbb YZ	288
	289	if (mqd_gfx9)
	290	bp.flags \|= AMDGPU_GEM_CREATE_MQD_GFX9;
	291
3216c6b7	292	r = amdgpu_bo_create(adev, &bp, &bo);
130e0371	293	if (r) {
dc102c43	294	dev_err(adev->dev,
130e0371 OG	295	"failed to allocate BO for amdkfd (%d)\n", r);
	296	return r;
	297	}
	298
	299	/* map the buffer */
473fee47	300	r = amdgpu_bo_reserve(bo, true);
130e0371	301	if (r) {
dc102c43	302	dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
130e0371 OG	303	goto allocate_mem_reserve_bo_failed;
	304	}
	305
7b7c6c81	306	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
130e0371	307	if (r) {
dc102c43	308	dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
130e0371 OG	309	goto allocate_mem_pin_bo_failed;
130e0371 OG	310	}
130e0371	311
bb812f1e JZ	312	r = amdgpu_ttm_alloc_gart(&bo->tbo);
	313	if (r) {
	314	dev_err(adev->dev, "%p bind failed\n", bo);
	315	goto allocate_mem_kmap_bo_failed;
	316	}
	317
473fee47	318	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
130e0371	319	if (r) {
dc102c43	320	dev_err(adev->dev,
130e0371 OG	321	"(%d) failed to map bo to kernel for amdkfd\n", r);
	322	goto allocate_mem_kmap_bo_failed;
	323	}
130e0371	324
473fee47	325	*mem_obj = bo;
7b7c6c81	326	*gpu_addr = amdgpu_bo_gpu_offset(bo);
473fee47 YZ	327	*cpu_ptr = cpu_ptr_tmp;
	328
	329	amdgpu_bo_unreserve(bo);
130e0371 OG	330
	331	return 0;
	332
	333	allocate_mem_kmap_bo_failed:
473fee47	334	amdgpu_bo_unpin(bo);
130e0371	335	allocate_mem_pin_bo_failed:
473fee47	336	amdgpu_bo_unreserve(bo);
130e0371	337	allocate_mem_reserve_bo_failed:
473fee47	338	amdgpu_bo_unref(&bo);
130e0371 OG	339
	340	return r;
	341	}
	342
	343	void free_gtt_mem(struct kgd_dev kgd, void mem_obj)
	344	{
473fee47 YZ	345	struct amdgpu_bo bo = (struct amdgpu_bo ) mem_obj;
	346
	347	amdgpu_bo_reserve(bo, true);
	348	amdgpu_bo_kunmap(bo);
	349	amdgpu_bo_unpin(bo);
	350	amdgpu_bo_unreserve(bo);
	351	amdgpu_bo_unref(&(bo));
130e0371 OG	352	}
130e0371 OG	353
30f1c042 HK	354	void get_local_mem_info(struct kgd_dev *kgd,
	355	struct kfd_local_mem_info *mem_info)
	356	{
	357	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	358	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
	359	~((1ULL << 32) - 1);
770d13b1	360	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
30f1c042 HK	361
30f1c042 HK	362	memset(mem_info, 0, sizeof(*mem_info));
770d13b1 CK	363	if (!(adev->gmc.aper_base & address_mask \|\| aper_limit & address_mask)) {
	364	mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
	365	mem_info->local_mem_size_private = adev->gmc.real_vram_size -
	366	adev->gmc.visible_vram_size;
30f1c042 HK	367	} else {
30f1c042 HK	368	mem_info->local_mem_size_public = 0;
770d13b1	369	mem_info->local_mem_size_private = adev->gmc.real_vram_size;
30f1c042	370	}
770d13b1	371	mem_info->vram_width = adev->gmc.vram_width;
30f1c042	372
fb8baefc	373	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
770d13b1	374	&adev->gmc.aper_base, &aper_limit,
30f1c042 HK	375	mem_info->local_mem_size_public,
	376	mem_info->local_mem_size_private);
	377
	378	if (amdgpu_sriov_vf(adev))
	379	mem_info->mem_clk_max = adev->clock.default_mclk / 100;
7ba01f9e	380	else if (adev->powerplay.pp_funcs)
30f1c042	381	mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
7ba01f9e SL	382	else
7ba01f9e SL	383	mem_info->mem_clk_max = 100;
30f1c042 HK	384	}
30f1c042 HK	385
130e0371 OG	386	uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
130e0371 OG	387	{
dc102c43	388	struct amdgpu_device adev = (struct amdgpu_device )kgd;
130e0371	389
dc102c43 AR	390	if (adev->gfx.funcs->get_gpu_clock_counter)
dc102c43 AR	391	return adev->gfx.funcs->get_gpu_clock_counter(adev);
130e0371 OG	392	return 0;
	393	}
	394
	395	uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
	396	{
dc102c43	397	struct amdgpu_device adev = (struct amdgpu_device )kgd;
130e0371	398
a9efcc19 FK	399	/* the sclk is in quantas of 10kHz */
	400	if (amdgpu_sriov_vf(adev))
	401	return adev->clock.default_sclk / 100;
7ba01f9e SL	402	else if (adev->powerplay.pp_funcs)
	403	return amdgpu_dpm_get_sclk(adev, false) / 100;
	404	else
	405	return 100;
130e0371	406	}
ebdebf42 FC	407
	408	void get_cu_info(struct kgd_dev kgd, struct kfd_cu_info cu_info)
	409	{
	410	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	411	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
	412
	413	memset(cu_info, 0, sizeof(*cu_info));
	414	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
	415	return;
	416
	417	cu_info->cu_active_number = acu_info.number;
	418	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
	419	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
	420	sizeof(acu_info.bitmap));
	421	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
	422	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
	423	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
	424	cu_info->simd_per_cu = acu_info.simd_per_cu;
	425	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
	426	cu_info->wave_front_size = acu_info.wave_front_size;
	427	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
	428	cu_info->lds_size = acu_info.lds_size;
	429	}
9f0a0b41 KR	430
	431	uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
	432	{
	433	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	434
	435	return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
	436	}
155494db	437
db8b62c0 SL	438	uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
	439	{
	440	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	441
	442	return adev->gmc.xgmi.hive_id;
	443	}
	444
4c660c8f FK	445	int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
	446	uint32_t vmid, uint64_t gpu_addr,
	447	uint32_t *ib_cmd, uint32_t ib_len)
	448	{
	449	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	450	struct amdgpu_job *job;
	451	struct amdgpu_ib *ib;
	452	struct amdgpu_ring *ring;
	453	struct dma_fence *f = NULL;
	454	int ret;
	455
	456	switch (engine) {
	457	case KGD_ENGINE_MEC1:
	458	ring = &adev->gfx.compute_ring[0];
	459	break;
	460	case KGD_ENGINE_SDMA1:
	461	ring = &adev->sdma.instance[0].ring;
	462	break;
	463	case KGD_ENGINE_SDMA2:
	464	ring = &adev->sdma.instance[1].ring;
	465	break;
	466	default:
	467	pr_err("Invalid engine in IB submission: %d\n", engine);
	468	ret = -EINVAL;
	469	goto err;
	470	}
	471
	472	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
	473	if (ret)
	474	goto err;
	475
	476	ib = &job->ibs[0];
	477	memset(ib, 0, sizeof(struct amdgpu_ib));
	478
	479	ib->gpu_addr = gpu_addr;
	480	ib->ptr = ib_cmd;
	481	ib->length_dw = ib_len;
	482	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
	483	job->vmid = vmid;
	484
	485	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
	486	if (ret) {
	487	DRM_ERROR("amdgpu: failed to schedule IB.\n");
	488	goto err_ib_sched;
	489	}
	490
	491	ret = dma_fence_wait(f, false);
	492
	493	err_ib_sched:
	494	dma_fence_put(f);
	495	amdgpu_job_free(job);
	496	err:
	497	return ret;
	498	}
	499
01c097db FK	500	void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
	501	{
	502	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	503
919a52fc FK	504	if (adev->powerplay.pp_funcs &&
	505	adev->powerplay.pp_funcs->switch_power_profile)
	506	amdgpu_dpm_switch_power_profile(adev,
	507	PP_SMC_POWER_PROFILE_COMPUTE,
	508	!idle);
01c097db FK	509	}
01c097db FK	510
155494db FK	511	bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
	512	{
	513	if (adev->kfd) {
	514	if ((1 << vmid) & compute_vmid_bitmap)
	515	return true;
	516	}
	517
	518	return false;
	519	}
fcdfa432	520
82b7b619	521	#ifndef CONFIG_HSA_AMD
fcdfa432 OG	522	bool amdkfd_fence_check_mm(struct dma_fence f, struct mm_struct mm)
	523	{
	524	return false;
	525	}
	526
	527	void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
	528	{
	529	}
	530
	531	void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
	532	struct amdgpu_vm *vm)
	533	{
	534	}
	535
	536	struct amdgpu_amdkfd_fence to_amdgpu_amdkfd_fence(struct dma_fence f)
	537	{
	538	return NULL;
	539	}
	540
	541	int amdgpu_amdkfd_evict_userptr(struct kgd_mem mem, struct mm_struct mm)
	542	{
	543	return 0;
	544	}
	545
	546	struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
	547	{
	548	return NULL;
	549	}
	550
	551	struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
	552	{
	553	return NULL;
	554	}
	555
	556	struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
	557	{
	558	return NULL;
	559	}
	560	#endif