[linux.git] / arch / riscv / kernel / cpu.c

/*
 * Copyright (C) 2012 Regents of the University of California
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 */

#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/of.h>
#include <asm/smp.h>

/*
 * Returns the hart ID of the given device tree node, or -1 if the device tree
 * node isn't a RISC-V hart.
 */
int riscv_of_processor_hartid(struct device_node *node)
{
	const char *isa, *status;
	u32 hart;

	if (!of_device_is_compatible(node, "riscv")) {
		pr_warn("Found incompatible CPU\n");
		return -(ENODEV);
	}

	if (of_property_read_u32(node, "reg", &hart)) {
		pr_warn("Found CPU without hart ID\n");
		return -(ENODEV);
	}
	if (hart >= NR_CPUS) {
		pr_info("Found hart ID %d, which is above NR_CPUs.  Disabling this hart\n", hart);
		return -(ENODEV);
	}

	if (of_property_read_string(node, "status", &status)) {
		pr_warn("CPU with hartid=%d has no \"status\" property\n", hart);
		return -(ENODEV);
	}
	if (strcmp(status, "okay")) {
		pr_info("CPU with hartid=%d has a non-okay status of \"%s\"\n", hart, status);
		return -(ENODEV);
	}

	if (of_property_read_string(node, "riscv,isa", &isa)) {
		pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart);
		return -(ENODEV);
	}
	if (isa[0] != 'r' || isa[1] != 'v') {
		pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa);
		return -(ENODEV);
	}

	return hart;
}

#ifdef CONFIG_PROC_FS

static void print_isa(struct seq_file *f, const char *orig_isa)
{
	static const char *ext = "mafdcsu";
	const char *isa = orig_isa;
	const char *e;

	/*
	 * Linux doesn't support rv32e or rv128i, and we only support booting
	 * kernels on harts with the same ISA that the kernel is compiled for.
	 */
#if defined(CONFIG_32BIT)
	if (strncmp(isa, "rv32i", 5) != 0)
		return;
#elif defined(CONFIG_64BIT)
	if (strncmp(isa, "rv64i", 5) != 0)
		return;
#endif

	/* Print the base ISA, as we already know it's legal. */
	seq_puts(f, "isa\t\t: ");
	seq_write(f, isa, 5);
	isa += 5;

	/*
	 * Check the rest of the ISA string for valid extensions, printing those
	 * we find.  RISC-V ISA strings define an order, so we only print the
	 * extension bits when they're in order. Hide the supervisor (S)
	 * extension from userspace as it's not accessible from there.
	 */
	for (e = ext; *e != '\0'; ++e) {
		if (isa[0] == e[0]) {
			if (isa[0] != 's')
				seq_write(f, isa, 1);

			isa++;
		}
	}
	seq_puts(f, "\n");

	/*
	 * If we were given an unsupported ISA in the device tree then print
	 * a bit of info describing what went wrong.
	 */
	if (isa[0] != '\0')
		pr_info("unsupported ISA \"%s\" in device tree", orig_isa);
}

static void print_mmu(struct seq_file *f, const char *mmu_type)
{
#if defined(CONFIG_32BIT)
	if (strcmp(mmu_type, "riscv,sv32") != 0)
		return;
#elif defined(CONFIG_64BIT)
	if (strcmp(mmu_type, "riscv,sv39") != 0 &&
	    strcmp(mmu_type, "riscv,sv48") != 0)
		return;
#endif

	seq_printf(f, "mmu\t\t: %s\n", mmu_type+6);
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	*pos = cpumask_next(*pos - 1, cpu_online_mask);
	if ((*pos) < nr_cpu_ids)
		return (void *)(uintptr_t)(1 + *pos);
	return NULL;
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	(*pos)++;
	return c_start(m, pos);
}

static void c_stop(struct seq_file *m, void *v)
{
}

static int c_show(struct seq_file *m, void *v)
{
	unsigned long cpu_id = (unsigned long)v - 1;
	struct device_node *node = of_get_cpu_node(cpuid_to_hartid_map(cpu_id),
						   NULL);
	const char *compat, *isa, *mmu;

	seq_printf(m, "processor\t: %lu\n", cpu_id);
	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
	if (!of_property_read_string(node, "riscv,isa", &isa))
		print_isa(m, isa);
	if (!of_property_read_string(node, "mmu-type", &mmu))
		print_mmu(m, mmu);
	if (!of_property_read_string(node, "compatible", &compat)
	    && strcmp(compat, "riscv"))
		seq_printf(m, "uarch\t\t: %s\n", compat);
	seq_puts(m, "\n");

	return 0;
}

const struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= c_show
};

#endif /* CONFIG_PROC_FS */
Commit	Line	Data
76d2a049 PD	1	/*
	2	* Copyright (C) 2012 Regents of the University of California
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/seq_file.h>
	16	#include <linux/of.h>
f99fb607	17	#include <asm/smp.h>
76d2a049	18
b2f8cfa7 PD	19	/*
	20	* Returns the hart ID of the given device tree node, or -1 if the device tree
	21	* node isn't a RISC-V hart.
	22	*/
	23	int riscv_of_processor_hartid(struct device_node *node)
76d2a049 PD	24	{
	25	const char isa, status;
	26	u32 hart;
	27
	28	if (!of_device_is_compatible(node, "riscv")) {
	29	pr_warn("Found incompatible CPU\n");
	30	return -(ENODEV);
	31	}
	32
	33	if (of_property_read_u32(node, "reg", &hart)) {
	34	pr_warn("Found CPU without hart ID\n");
	35	return -(ENODEV);
	36	}
	37	if (hart >= NR_CPUS) {
	38	pr_info("Found hart ID %d, which is above NR_CPUs. Disabling this hart\n", hart);
	39	return -(ENODEV);
	40	}
	41
	42	if (of_property_read_string(node, "status", &status)) {
	43	pr_warn("CPU with hartid=%d has no \"status\" property\n", hart);
	44	return -(ENODEV);
	45	}
	46	if (strcmp(status, "okay")) {
	47	pr_info("CPU with hartid=%d has a non-okay status of \"%s\"\n", hart, status);
	48	return -(ENODEV);
	49	}
	50
	51	if (of_property_read_string(node, "riscv,isa", &isa)) {
	52	pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart);
	53	return -(ENODEV);
	54	}
	55	if (isa[0] != 'r' \|\| isa[1] != 'v') {
	56	pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa);
	57	return -(ENODEV);
	58	}
	59
	60	return hart;
	61	}
	62
	63	#ifdef CONFIG_PROC_FS
	64
19ccf29b PD	65	static void print_isa(struct seq_file f, const char orig_isa)
19ccf29b PD	66	{
5d8f81ba	67	static const char *ext = "mafdcsu";
19ccf29b PD	68	const char *isa = orig_isa;
	69	const char *e;
	70
	71	/*
	72	* Linux doesn't support rv32e or rv128i, and we only support booting
	73	* kernels on harts with the same ISA that the kernel is compiled for.
	74	*/
	75	#if defined(CONFIG_32BIT)
	76	if (strncmp(isa, "rv32i", 5) != 0)
	77	return;
	78	#elif defined(CONFIG_64BIT)
	79	if (strncmp(isa, "rv64i", 5) != 0)
	80	return;
	81	#endif
	82
	83	/* Print the base ISA, as we already know it's legal. */
4b26d22f	84	seq_puts(f, "isa\t\t: ");
19ccf29b PD	85	seq_write(f, isa, 5);
	86	isa += 5;
	87
	88	/*
	89	* Check the rest of the ISA string for valid extensions, printing those
	90	* we find. RISC-V ISA strings define an order, so we only print the
5d8f81ba PS	91	* extension bits when they're in order. Hide the supervisor (S)
5d8f81ba PS	92	* extension from userspace as it's not accessible from there.
19ccf29b PD	93	*/
	94	for (e = ext; *e != '\0'; ++e) {
	95	if (isa[0] == e[0]) {
5d8f81ba PS	96	if (isa[0] != 's')
	97	seq_write(f, isa, 1);
	98
19ccf29b PD	99	isa++;
	100	}
	101	}
4b26d22f	102	seq_puts(f, "\n");
19ccf29b PD	103
	104	/*
	105	* If we were given an unsupported ISA in the device tree then print
	106	* a bit of info describing what went wrong.
	107	*/
	108	if (isa[0] != '\0')
	109	pr_info("unsupported ISA \"%s\" in device tree", orig_isa);
	110	}
	111
	112	static void print_mmu(struct seq_file f, const char mmu_type)
	113	{
	114	#if defined(CONFIG_32BIT)
	115	if (strcmp(mmu_type, "riscv,sv32") != 0)
	116	return;
	117	#elif defined(CONFIG_64BIT)
	118	if (strcmp(mmu_type, "riscv,sv39") != 0 &&
	119	strcmp(mmu_type, "riscv,sv48") != 0)
	120	return;
	121	#endif
	122
4b26d22f	123	seq_printf(f, "mmu\t\t: %s\n", mmu_type+6);
19ccf29b PD	124	}
19ccf29b PD	125
76d2a049 PD	126	static void c_start(struct seq_file m, loff_t *pos)
	127	{
	128	pos = cpumask_next(pos - 1, cpu_online_mask);
	129	if ((*pos) < nr_cpu_ids)
	130	return (void )(uintptr_t)(1 + pos);
	131	return NULL;
	132	}
	133
	134	static void c_next(struct seq_file m, void v, loff_t pos)
	135	{
	136	(*pos)++;
	137	return c_start(m, pos);
	138	}
	139
	140	static void c_stop(struct seq_file m, void v)
	141	{
	142	}
	143
	144	static int c_show(struct seq_file m, void v)
	145	{
f99fb607 AP	146	unsigned long cpu_id = (unsigned long)v - 1;
	147	struct device_node *node = of_get_cpu_node(cpuid_to_hartid_map(cpu_id),
	148	NULL);
76d2a049 PD	149	const char compat, isa, *mmu;
76d2a049 PD	150
4b26d22f AP	151	seq_printf(m, "processor\t: %lu\n", cpu_id);
4b26d22f AP	152	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
19ccf29b PD	153	if (!of_property_read_string(node, "riscv,isa", &isa))
	154	print_isa(m, isa);
	155	if (!of_property_read_string(node, "mmu-type", &mmu))
	156	print_mmu(m, mmu);
76d2a049 PD	157	if (!of_property_read_string(node, "compatible", &compat)
76d2a049 PD	158	&& strcmp(compat, "riscv"))
4b26d22f	159	seq_printf(m, "uarch\t\t: %s\n", compat);
76d2a049 PD	160	seq_puts(m, "\n");
	161
	162	return 0;
	163	}
	164
	165	const struct seq_operations cpuinfo_op = {
	166	.start = c_start,
	167	.next = c_next,
	168	.stop = c_stop,
	169	.show = c_show
	170	};
	171
	172	#endif /* CONFIG_PROC_FS */