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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/vfp/vfpmodule.c | |
3 | * | |
4 | * Copyright (C) 2004 ARM Limited. | |
5 | * Written by Deep Blue Solutions Limited. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 | 11 | #include <linux/types.h> |
90b44199 | 12 | #include <linux/cpu.h> |
746a9d19 | 13 | #include <linux/cpu_pm.h> |
998de4ac | 14 | #include <linux/hardirq.h> |
1da177e4 | 15 | #include <linux/kernel.h> |
90b44199 | 16 | #include <linux/notifier.h> |
1da177e4 | 17 | #include <linux/signal.h> |
3f07c014 | 18 | #include <linux/sched/signal.h> |
90b44199 | 19 | #include <linux/smp.h> |
1da177e4 | 20 | #include <linux/init.h> |
2498814f WD |
21 | #include <linux/uaccess.h> |
22 | #include <linux/user.h> | |
73c132c1 | 23 | #include <linux/export.h> |
d6551e88 | 24 | |
15d07dc9 | 25 | #include <asm/cp15.h> |
5aaf2544 | 26 | #include <asm/cputype.h> |
9f97da78 | 27 | #include <asm/system_info.h> |
d6551e88 | 28 | #include <asm/thread_notify.h> |
1da177e4 LT |
29 | #include <asm/vfp.h> |
30 | ||
31 | #include "vfpinstr.h" | |
32 | #include "vfp.h" | |
33 | ||
34 | /* | |
35 | * Our undef handlers (in entry.S) | |
36 | */ | |
a85b2257 NP |
37 | asmlinkage void vfp_testing_entry(void); |
38 | asmlinkage void vfp_support_entry(void); | |
39 | asmlinkage void vfp_null_entry(void); | |
1da177e4 | 40 | |
a85b2257 | 41 | asmlinkage void (*vfp_vector)(void) = vfp_null_entry; |
af61bdf0 | 42 | |
f8f2a852 RK |
43 | /* |
44 | * Dual-use variable. | |
45 | * Used in startup: set to non-zero if VFP checks fail | |
46 | * After startup, holds VFP architecture | |
47 | */ | |
48 | unsigned int VFP_arch; | |
49 | ||
af61bdf0 RK |
50 | /* |
51 | * The pointer to the vfpstate structure of the thread which currently | |
52 | * owns the context held in the VFP hardware, or NULL if the hardware | |
53 | * context is invalid. | |
f8f2a852 RK |
54 | * |
55 | * For UP, this is sufficient to tell which thread owns the VFP context. | |
56 | * However, for SMP, we also need to check the CPU number stored in the | |
57 | * saved state too to catch migrations. | |
af61bdf0 RK |
58 | */ |
59 | union vfp_state *vfp_current_hw_state[NR_CPUS]; | |
1da177e4 LT |
60 | |
61 | /* | |
f8f2a852 RK |
62 | * Is 'thread's most up to date state stored in this CPUs hardware? |
63 | * Must be called from non-preemptible context. | |
1da177e4 | 64 | */ |
f8f2a852 RK |
65 | static bool vfp_state_in_hw(unsigned int cpu, struct thread_info *thread) |
66 | { | |
67 | #ifdef CONFIG_SMP | |
68 | if (thread->vfpstate.hard.cpu != cpu) | |
69 | return false; | |
70 | #endif | |
71 | return vfp_current_hw_state[cpu] == &thread->vfpstate; | |
72 | } | |
73 | ||
74 | /* | |
75 | * Force a reload of the VFP context from the thread structure. We do | |
76 | * this by ensuring that access to the VFP hardware is disabled, and | |
48af9fea | 77 | * clear vfp_current_hw_state. Must be called from non-preemptible context. |
f8f2a852 RK |
78 | */ |
79 | static void vfp_force_reload(unsigned int cpu, struct thread_info *thread) | |
80 | { | |
81 | if (vfp_state_in_hw(cpu, thread)) { | |
82 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
83 | vfp_current_hw_state[cpu] = NULL; | |
84 | } | |
85 | #ifdef CONFIG_SMP | |
86 | thread->vfpstate.hard.cpu = NR_CPUS; | |
87 | #endif | |
88 | } | |
1da177e4 | 89 | |
0d782dc4 RK |
90 | /* |
91 | * Per-thread VFP initialization. | |
92 | */ | |
93 | static void vfp_thread_flush(struct thread_info *thread) | |
94 | { | |
95 | union vfp_state *vfp = &thread->vfpstate; | |
96 | unsigned int cpu; | |
97 | ||
0d782dc4 RK |
98 | /* |
99 | * Disable VFP to ensure we initialize it first. We must ensure | |
19dad35f RK |
100 | * that the modification of vfp_current_hw_state[] and hardware |
101 | * disable are done for the same CPU and without preemption. | |
102 | * | |
103 | * Do this first to ensure that preemption won't overwrite our | |
104 | * state saving should access to the VFP be enabled at this point. | |
0d782dc4 RK |
105 | */ |
106 | cpu = get_cpu(); | |
af61bdf0 RK |
107 | if (vfp_current_hw_state[cpu] == vfp) |
108 | vfp_current_hw_state[cpu] = NULL; | |
0d782dc4 RK |
109 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); |
110 | put_cpu(); | |
19dad35f RK |
111 | |
112 | memset(vfp, 0, sizeof(union vfp_state)); | |
113 | ||
114 | vfp->hard.fpexc = FPEXC_EN; | |
115 | vfp->hard.fpscr = FPSCR_ROUND_NEAREST; | |
116 | #ifdef CONFIG_SMP | |
117 | vfp->hard.cpu = NR_CPUS; | |
118 | #endif | |
0d782dc4 RK |
119 | } |
120 | ||
797245f5 | 121 | static void vfp_thread_exit(struct thread_info *thread) |
0d782dc4 RK |
122 | { |
123 | /* release case: Per-thread VFP cleanup. */ | |
124 | union vfp_state *vfp = &thread->vfpstate; | |
797245f5 | 125 | unsigned int cpu = get_cpu(); |
0d782dc4 | 126 | |
af61bdf0 RK |
127 | if (vfp_current_hw_state[cpu] == vfp) |
128 | vfp_current_hw_state[cpu] = NULL; | |
797245f5 | 129 | put_cpu(); |
0d782dc4 RK |
130 | } |
131 | ||
c98c0977 CM |
132 | static void vfp_thread_copy(struct thread_info *thread) |
133 | { | |
134 | struct thread_info *parent = current_thread_info(); | |
135 | ||
136 | vfp_sync_hwstate(parent); | |
137 | thread->vfpstate = parent->vfpstate; | |
f8f2a852 RK |
138 | #ifdef CONFIG_SMP |
139 | thread->vfpstate.hard.cpu = NR_CPUS; | |
140 | #endif | |
c98c0977 CM |
141 | } |
142 | ||
0d782dc4 RK |
143 | /* |
144 | * When this function is called with the following 'cmd's, the following | |
145 | * is true while this function is being run: | |
146 | * THREAD_NOFTIFY_SWTICH: | |
147 | * - the previously running thread will not be scheduled onto another CPU. | |
148 | * - the next thread to be run (v) will not be running on another CPU. | |
149 | * - thread->cpu is the local CPU number | |
150 | * - not preemptible as we're called in the middle of a thread switch | |
151 | * THREAD_NOTIFY_FLUSH: | |
152 | * - the thread (v) will be running on the local CPU, so | |
153 | * v === current_thread_info() | |
154 | * - thread->cpu is the local CPU number at the time it is accessed, | |
155 | * but may change at any time. | |
156 | * - we could be preempted if tree preempt rcu is enabled, so | |
157 | * it is unsafe to use thread->cpu. | |
797245f5 | 158 | * THREAD_NOTIFY_EXIT |
797245f5 RK |
159 | * - we could be preempted if tree preempt rcu is enabled, so |
160 | * it is unsafe to use thread->cpu. | |
0d782dc4 | 161 | */ |
d6551e88 | 162 | static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
1da177e4 | 163 | { |
d6551e88 | 164 | struct thread_info *thread = v; |
2e82669a CM |
165 | u32 fpexc; |
166 | #ifdef CONFIG_SMP | |
167 | unsigned int cpu; | |
168 | #endif | |
1da177e4 | 169 | |
2e82669a CM |
170 | switch (cmd) { |
171 | case THREAD_NOTIFY_SWITCH: | |
172 | fpexc = fmrx(FPEXC); | |
c6428464 CM |
173 | |
174 | #ifdef CONFIG_SMP | |
2e82669a | 175 | cpu = thread->cpu; |
0d782dc4 | 176 | |
c6428464 CM |
177 | /* |
178 | * On SMP, if VFP is enabled, save the old state in | |
179 | * case the thread migrates to a different CPU. The | |
180 | * restoring is done lazily. | |
181 | */ | |
f8f2a852 | 182 | if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) |
af61bdf0 | 183 | vfp_save_state(vfp_current_hw_state[cpu], fpexc); |
c6428464 CM |
184 | #endif |
185 | ||
681a4991 RK |
186 | /* |
187 | * Always disable VFP so we can lazily save/restore the | |
188 | * old state. | |
189 | */ | |
228adef1 | 190 | fmxr(FPEXC, fpexc & ~FPEXC_EN); |
2e82669a | 191 | break; |
681a4991 | 192 | |
2e82669a | 193 | case THREAD_NOTIFY_FLUSH: |
0d782dc4 | 194 | vfp_thread_flush(thread); |
2e82669a CM |
195 | break; |
196 | ||
197 | case THREAD_NOTIFY_EXIT: | |
797245f5 | 198 | vfp_thread_exit(thread); |
c98c0977 CM |
199 | break; |
200 | ||
201 | case THREAD_NOTIFY_COPY: | |
202 | vfp_thread_copy(thread); | |
2e82669a CM |
203 | break; |
204 | } | |
681a4991 | 205 | |
d6551e88 | 206 | return NOTIFY_DONE; |
1da177e4 LT |
207 | } |
208 | ||
d6551e88 RK |
209 | static struct notifier_block vfp_notifier_block = { |
210 | .notifier_call = vfp_notifier, | |
211 | }; | |
212 | ||
1da177e4 LT |
213 | /* |
214 | * Raise a SIGFPE for the current process. | |
215 | * sicode describes the signal being raised. | |
216 | */ | |
2bbd7e9b | 217 | static void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) |
1da177e4 | 218 | { |
1da177e4 LT |
219 | /* |
220 | * This is the same as NWFPE, because it's not clear what | |
221 | * this is used for | |
222 | */ | |
223 | current->thread.error_code = 0; | |
224 | current->thread.trap_no = 6; | |
225 | ||
b0594548 EB |
226 | send_sig_fault(SIGFPE, sicode, |
227 | (void __user *)(instruction_pointer(regs) - 4), | |
228 | current); | |
1da177e4 LT |
229 | } |
230 | ||
c98929c0 | 231 | static void vfp_panic(char *reason, u32 inst) |
1da177e4 LT |
232 | { |
233 | int i; | |
234 | ||
dc457078 NP |
235 | pr_err("VFP: Error: %s\n", reason); |
236 | pr_err("VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", | |
c98929c0 | 237 | fmrx(FPEXC), fmrx(FPSCR), inst); |
1da177e4 | 238 | for (i = 0; i < 32; i += 2) |
dc457078 | 239 | pr_err("VFP: s%2u: 0x%08x s%2u: 0x%08x\n", |
1da177e4 LT |
240 | i, vfp_get_float(i), i+1, vfp_get_float(i+1)); |
241 | } | |
242 | ||
243 | /* | |
244 | * Process bitmask of exception conditions. | |
245 | */ | |
246 | static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs) | |
247 | { | |
248 | int si_code = 0; | |
249 | ||
250 | pr_debug("VFP: raising exceptions %08x\n", exceptions); | |
251 | ||
7c6f2514 | 252 | if (exceptions == VFP_EXCEPTION_ERROR) { |
c98929c0 | 253 | vfp_panic("unhandled bounce", inst); |
92d44a42 | 254 | vfp_raise_sigfpe(FPE_FLTINV, regs); |
1da177e4 LT |
255 | return; |
256 | } | |
257 | ||
258 | /* | |
dbead405 | 259 | * If any of the status flags are set, update the FPSCR. |
1da177e4 LT |
260 | * Comparison instructions always return at least one of |
261 | * these flags set. | |
262 | */ | |
dbead405 CM |
263 | if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V)) |
264 | fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V); | |
265 | ||
1da177e4 LT |
266 | fpscr |= exceptions; |
267 | ||
268 | fmxr(FPSCR, fpscr); | |
269 | ||
270 | #define RAISE(stat,en,sig) \ | |
271 | if (exceptions & stat && fpscr & en) \ | |
272 | si_code = sig; | |
273 | ||
274 | /* | |
275 | * These are arranged in priority order, least to highest. | |
276 | */ | |
e0f205d9 | 277 | RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV); |
1da177e4 LT |
278 | RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES); |
279 | RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND); | |
280 | RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF); | |
281 | RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV); | |
282 | ||
283 | if (si_code) | |
284 | vfp_raise_sigfpe(si_code, regs); | |
285 | } | |
286 | ||
287 | /* | |
288 | * Emulate a VFP instruction. | |
289 | */ | |
290 | static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs) | |
291 | { | |
7c6f2514 | 292 | u32 exceptions = VFP_EXCEPTION_ERROR; |
1da177e4 LT |
293 | |
294 | pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr); | |
295 | ||
296 | if (INST_CPRTDO(inst)) { | |
297 | if (!INST_CPRT(inst)) { | |
298 | /* | |
299 | * CPDO | |
300 | */ | |
301 | if (vfp_single(inst)) { | |
302 | exceptions = vfp_single_cpdo(inst, fpscr); | |
303 | } else { | |
304 | exceptions = vfp_double_cpdo(inst, fpscr); | |
305 | } | |
306 | } else { | |
307 | /* | |
308 | * A CPRT instruction can not appear in FPINST2, nor | |
309 | * can it cause an exception. Therefore, we do not | |
310 | * have to emulate it. | |
311 | */ | |
312 | } | |
313 | } else { | |
314 | /* | |
315 | * A CPDT instruction can not appear in FPINST2, nor can | |
316 | * it cause an exception. Therefore, we do not have to | |
317 | * emulate it. | |
318 | */ | |
319 | } | |
928bd1b4 | 320 | return exceptions & ~VFP_NAN_FLAG; |
1da177e4 LT |
321 | } |
322 | ||
323 | /* | |
324 | * Package up a bounce condition. | |
325 | */ | |
c98929c0 | 326 | void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) |
1da177e4 | 327 | { |
c98929c0 | 328 | u32 fpscr, orig_fpscr, fpsid, exceptions; |
1da177e4 LT |
329 | |
330 | pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc); | |
331 | ||
332 | /* | |
c98929c0 CM |
333 | * At this point, FPEXC can have the following configuration: |
334 | * | |
335 | * EX DEX IXE | |
336 | * 0 1 x - synchronous exception | |
337 | * 1 x 0 - asynchronous exception | |
338 | * 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later | |
339 | * 0 0 1 - synchronous on VFP9 (non-standard subarch 1 | |
340 | * implementation), undefined otherwise | |
341 | * | |
342 | * Clear various bits and enable access to the VFP so we can | |
343 | * handle the bounce. | |
1da177e4 | 344 | */ |
c98929c0 | 345 | fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK)); |
1da177e4 | 346 | |
c98929c0 | 347 | fpsid = fmrx(FPSID); |
1da177e4 LT |
348 | orig_fpscr = fpscr = fmrx(FPSCR); |
349 | ||
350 | /* | |
c98929c0 | 351 | * Check for the special VFP subarch 1 and FPSCR.IXE bit case |
1da177e4 | 352 | */ |
c98929c0 CM |
353 | if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT) |
354 | && (fpscr & FPSCR_IXE)) { | |
355 | /* | |
356 | * Synchronous exception, emulate the trigger instruction | |
357 | */ | |
1da177e4 LT |
358 | goto emulate; |
359 | } | |
360 | ||
c98929c0 | 361 | if (fpexc & FPEXC_EX) { |
85d6943a | 362 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 CM |
363 | /* |
364 | * Asynchronous exception. The instruction is read from FPINST | |
365 | * and the interrupted instruction has to be restarted. | |
366 | */ | |
367 | trigger = fmrx(FPINST); | |
368 | regs->ARM_pc -= 4; | |
85d6943a | 369 | #endif |
c98929c0 CM |
370 | } else if (!(fpexc & FPEXC_DEX)) { |
371 | /* | |
372 | * Illegal combination of bits. It can be caused by an | |
373 | * unallocated VFP instruction but with FPSCR.IXE set and not | |
374 | * on VFP subarch 1. | |
375 | */ | |
376 | vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs); | |
f2255be8 | 377 | goto exit; |
c98929c0 | 378 | } |
1da177e4 LT |
379 | |
380 | /* | |
c98929c0 CM |
381 | * Modify fpscr to indicate the number of iterations remaining. |
382 | * If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates | |
383 | * whether FPEXC.VECITR or FPSCR.LEN is used. | |
1da177e4 | 384 | */ |
c98929c0 | 385 | if (fpexc & (FPEXC_EX | FPEXC_VV)) { |
1da177e4 LT |
386 | u32 len; |
387 | ||
388 | len = fpexc + (1 << FPEXC_LENGTH_BIT); | |
389 | ||
390 | fpscr &= ~FPSCR_LENGTH_MASK; | |
391 | fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT); | |
392 | } | |
393 | ||
394 | /* | |
395 | * Handle the first FP instruction. We used to take note of the | |
396 | * FPEXC bounce reason, but this appears to be unreliable. | |
397 | * Emulate the bounced instruction instead. | |
398 | */ | |
c98929c0 | 399 | exceptions = vfp_emulate_instruction(trigger, fpscr, regs); |
1da177e4 | 400 | if (exceptions) |
c98929c0 | 401 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); |
1da177e4 LT |
402 | |
403 | /* | |
c98929c0 CM |
404 | * If there isn't a second FP instruction, exit now. Note that |
405 | * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1. | |
1da177e4 | 406 | */ |
5e4ba617 | 407 | if ((fpexc & (FPEXC_EX | FPEXC_FP2V)) != (FPEXC_EX | FPEXC_FP2V)) |
f2255be8 | 408 | goto exit; |
1da177e4 LT |
409 | |
410 | /* | |
411 | * The barrier() here prevents fpinst2 being read | |
412 | * before the condition above. | |
413 | */ | |
414 | barrier(); | |
415 | trigger = fmrx(FPINST2); | |
1da177e4 LT |
416 | |
417 | emulate: | |
c98929c0 | 418 | exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs); |
1da177e4 LT |
419 | if (exceptions) |
420 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); | |
f2255be8 GD |
421 | exit: |
422 | preempt_enable(); | |
1da177e4 | 423 | } |
efe90d27 | 424 | |
8e140362 RK |
425 | static void vfp_enable(void *unused) |
426 | { | |
998de4ac WD |
427 | u32 access; |
428 | ||
429 | BUG_ON(preemptible()); | |
430 | access = get_copro_access(); | |
8e140362 RK |
431 | |
432 | /* | |
433 | * Enable full access to VFP (cp10 and cp11) | |
434 | */ | |
435 | set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); | |
436 | } | |
437 | ||
7d7d7a41 FF |
438 | /* Called by platforms on which we want to disable VFP because it may not be |
439 | * present on all CPUs within a SMP complex. Needs to be called prior to | |
440 | * vfp_init(). | |
441 | */ | |
442 | void vfp_disable(void) | |
443 | { | |
444 | if (VFP_arch) { | |
445 | pr_debug("%s: should be called prior to vfp_init\n", __func__); | |
446 | return; | |
447 | } | |
448 | VFP_arch = 1; | |
449 | } | |
450 | ||
746a9d19 | 451 | #ifdef CONFIG_CPU_PM |
328f5cc3 | 452 | static int vfp_pm_suspend(void) |
fc0b7a20 BD |
453 | { |
454 | struct thread_info *ti = current_thread_info(); | |
455 | u32 fpexc = fmrx(FPEXC); | |
456 | ||
457 | /* if vfp is on, then save state for resumption */ | |
458 | if (fpexc & FPEXC_EN) { | |
dc457078 | 459 | pr_debug("%s: saving vfp state\n", __func__); |
fc0b7a20 BD |
460 | vfp_save_state(&ti->vfpstate, fpexc); |
461 | ||
462 | /* disable, just in case */ | |
463 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
24b35521 CC |
464 | } else if (vfp_current_hw_state[ti->cpu]) { |
465 | #ifndef CONFIG_SMP | |
466 | fmxr(FPEXC, fpexc | FPEXC_EN); | |
467 | vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc); | |
468 | fmxr(FPEXC, fpexc); | |
469 | #endif | |
fc0b7a20 BD |
470 | } |
471 | ||
472 | /* clear any information we had about last context state */ | |
a84b895a | 473 | vfp_current_hw_state[ti->cpu] = NULL; |
fc0b7a20 BD |
474 | |
475 | return 0; | |
476 | } | |
477 | ||
328f5cc3 | 478 | static void vfp_pm_resume(void) |
fc0b7a20 BD |
479 | { |
480 | /* ensure we have access to the vfp */ | |
481 | vfp_enable(NULL); | |
482 | ||
483 | /* and disable it to ensure the next usage restores the state */ | |
484 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
fc0b7a20 BD |
485 | } |
486 | ||
746a9d19 CC |
487 | static int vfp_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, |
488 | void *v) | |
489 | { | |
490 | switch (cmd) { | |
491 | case CPU_PM_ENTER: | |
492 | vfp_pm_suspend(); | |
493 | break; | |
494 | case CPU_PM_ENTER_FAILED: | |
495 | case CPU_PM_EXIT: | |
496 | vfp_pm_resume(); | |
497 | break; | |
498 | } | |
499 | return NOTIFY_OK; | |
500 | } | |
501 | ||
502 | static struct notifier_block vfp_cpu_pm_notifier_block = { | |
503 | .notifier_call = vfp_cpu_pm_notifier, | |
fc0b7a20 BD |
504 | }; |
505 | ||
fc0b7a20 BD |
506 | static void vfp_pm_init(void) |
507 | { | |
746a9d19 | 508 | cpu_pm_register_notifier(&vfp_cpu_pm_notifier_block); |
fc0b7a20 BD |
509 | } |
510 | ||
fc0b7a20 BD |
511 | #else |
512 | static inline void vfp_pm_init(void) { } | |
746a9d19 | 513 | #endif /* CONFIG_CPU_PM */ |
fc0b7a20 | 514 | |
f8f2a852 RK |
515 | /* |
516 | * Ensure that the VFP state stored in 'thread->vfpstate' is up to date | |
517 | * with the hardware state. | |
518 | */ | |
ad187f95 | 519 | void vfp_sync_hwstate(struct thread_info *thread) |
3d1228ea CM |
520 | { |
521 | unsigned int cpu = get_cpu(); | |
3d1228ea | 522 | |
f8f2a852 | 523 | if (vfp_state_in_hw(cpu, thread)) { |
54cb3dbb | 524 | u32 fpexc = fmrx(FPEXC); |
3d1228ea | 525 | |
54cb3dbb RK |
526 | /* |
527 | * Save the last VFP state on this CPU. | |
528 | */ | |
529 | fmxr(FPEXC, fpexc | FPEXC_EN); | |
530 | vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN); | |
ad187f95 RK |
531 | fmxr(FPEXC, fpexc); |
532 | } | |
3d1228ea | 533 | |
ad187f95 RK |
534 | put_cpu(); |
535 | } | |
536 | ||
f8f2a852 | 537 | /* Ensure that the thread reloads the hardware VFP state on the next use. */ |
ad187f95 RK |
538 | void vfp_flush_hwstate(struct thread_info *thread) |
539 | { | |
540 | unsigned int cpu = get_cpu(); | |
3d1228ea | 541 | |
f8f2a852 | 542 | vfp_force_reload(cpu, thread); |
ad187f95 | 543 | |
3d1228ea CM |
544 | put_cpu(); |
545 | } | |
3d1228ea | 546 | |
2498814f WD |
547 | /* |
548 | * Save the current VFP state into the provided structures and prepare | |
549 | * for entry into a new function (signal handler). | |
550 | */ | |
3aa2df6e JT |
551 | int vfp_preserve_user_clear_hwstate(struct user_vfp *ufp, |
552 | struct user_vfp_exc *ufp_exc) | |
2498814f WD |
553 | { |
554 | struct thread_info *thread = current_thread_info(); | |
555 | struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; | |
2498814f WD |
556 | |
557 | /* Ensure that the saved hwstate is up-to-date. */ | |
558 | vfp_sync_hwstate(thread); | |
559 | ||
560 | /* | |
561 | * Copy the floating point registers. There can be unused | |
562 | * registers see asm/hwcap.h for details. | |
563 | */ | |
3aa2df6e JT |
564 | memcpy(&ufp->fpregs, &hwstate->fpregs, sizeof(hwstate->fpregs)); |
565 | ||
2498814f WD |
566 | /* |
567 | * Copy the status and control register. | |
568 | */ | |
3aa2df6e | 569 | ufp->fpscr = hwstate->fpscr; |
2498814f WD |
570 | |
571 | /* | |
572 | * Copy the exception registers. | |
573 | */ | |
3aa2df6e JT |
574 | ufp_exc->fpexc = hwstate->fpexc; |
575 | ufp_exc->fpinst = hwstate->fpinst; | |
5df7a99b | 576 | ufp_exc->fpinst2 = hwstate->fpinst2; |
ff9a184c WD |
577 | |
578 | /* Ensure that VFP is disabled. */ | |
579 | vfp_flush_hwstate(thread); | |
580 | ||
581 | /* | |
582 | * As per the PCS, clear the length and stride bits for function | |
583 | * entry. | |
584 | */ | |
585 | hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK); | |
2498814f WD |
586 | return 0; |
587 | } | |
588 | ||
589 | /* Sanitise and restore the current VFP state from the provided structures. */ | |
42019fc5 | 590 | int vfp_restore_user_hwstate(struct user_vfp *ufp, struct user_vfp_exc *ufp_exc) |
2498814f WD |
591 | { |
592 | struct thread_info *thread = current_thread_info(); | |
593 | struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; | |
594 | unsigned long fpexc; | |
2498814f | 595 | |
56cb2484 WD |
596 | /* Disable VFP to avoid corrupting the new thread state. */ |
597 | vfp_flush_hwstate(thread); | |
2498814f WD |
598 | |
599 | /* | |
600 | * Copy the floating point registers. There can be unused | |
601 | * registers see asm/hwcap.h for details. | |
602 | */ | |
42019fc5 | 603 | memcpy(&hwstate->fpregs, &ufp->fpregs, sizeof(hwstate->fpregs)); |
2498814f WD |
604 | /* |
605 | * Copy the status and control register. | |
606 | */ | |
42019fc5 | 607 | hwstate->fpscr = ufp->fpscr; |
2498814f WD |
608 | |
609 | /* | |
610 | * Sanitise and restore the exception registers. | |
611 | */ | |
42019fc5 | 612 | fpexc = ufp_exc->fpexc; |
2498814f WD |
613 | |
614 | /* Ensure the VFP is enabled. */ | |
615 | fpexc |= FPEXC_EN; | |
616 | ||
617 | /* Ensure FPINST2 is invalid and the exception flag is cleared. */ | |
618 | fpexc &= ~(FPEXC_EX | FPEXC_FP2V); | |
619 | hwstate->fpexc = fpexc; | |
620 | ||
42019fc5 RK |
621 | hwstate->fpinst = ufp_exc->fpinst; |
622 | hwstate->fpinst2 = ufp_exc->fpinst2; | |
2498814f | 623 | |
42019fc5 | 624 | return 0; |
2498814f WD |
625 | } |
626 | ||
90b44199 RK |
627 | /* |
628 | * VFP hardware can lose all context when a CPU goes offline. | |
74c25bee RK |
629 | * As we will be running in SMP mode with CPU hotplug, we will save the |
630 | * hardware state at every thread switch. We clear our held state when | |
631 | * a CPU has been killed, indicating that the VFP hardware doesn't contain | |
632 | * a threads VFP state. When a CPU starts up, we re-enable access to the | |
e5b61baf | 633 | * VFP hardware. The callbacks below are called on the CPU which |
90b44199 RK |
634 | * is being offlined/onlined. |
635 | */ | |
e5b61baf | 636 | static int vfp_dying_cpu(unsigned int cpu) |
90b44199 | 637 | { |
1328f020 | 638 | vfp_current_hw_state[cpu] = NULL; |
e5b61baf TG |
639 | return 0; |
640 | } | |
641 | ||
642 | static int vfp_starting_cpu(unsigned int unused) | |
643 | { | |
644 | vfp_enable(NULL); | |
645 | return 0; | |
90b44199 | 646 | } |
8e140362 | 647 | |
ab3da156 AB |
648 | void vfp_kmode_exception(void) |
649 | { | |
650 | /* | |
651 | * If we reach this point, a floating point exception has been raised | |
652 | * while running in kernel mode. If the NEON/VFP unit was enabled at the | |
653 | * time, it means a VFP instruction has been issued that requires | |
654 | * software assistance to complete, something which is not currently | |
655 | * supported in kernel mode. | |
656 | * If the NEON/VFP unit was disabled, and the location pointed to below | |
657 | * is properly preceded by a call to kernel_neon_begin(), something has | |
658 | * caused the task to be scheduled out and back in again. In this case, | |
659 | * rebuilding and running with CONFIG_DEBUG_ATOMIC_SLEEP enabled should | |
660 | * be helpful in localizing the problem. | |
661 | */ | |
662 | if (fmrx(FPEXC) & FPEXC_EN) | |
663 | pr_crit("BUG: unsupported FP instruction in kernel mode\n"); | |
664 | else | |
665 | pr_crit("BUG: FP instruction issued in kernel mode with FP unit disabled\n"); | |
666 | } | |
667 | ||
73c132c1 AB |
668 | #ifdef CONFIG_KERNEL_MODE_NEON |
669 | ||
670 | /* | |
671 | * Kernel-side NEON support functions | |
672 | */ | |
673 | void kernel_neon_begin(void) | |
674 | { | |
675 | struct thread_info *thread = current_thread_info(); | |
676 | unsigned int cpu; | |
677 | u32 fpexc; | |
678 | ||
679 | /* | |
680 | * Kernel mode NEON is only allowed outside of interrupt context | |
681 | * with preemption disabled. This will make sure that the kernel | |
682 | * mode NEON register contents never need to be preserved. | |
683 | */ | |
684 | BUG_ON(in_interrupt()); | |
685 | cpu = get_cpu(); | |
686 | ||
687 | fpexc = fmrx(FPEXC) | FPEXC_EN; | |
688 | fmxr(FPEXC, fpexc); | |
689 | ||
690 | /* | |
691 | * Save the userland NEON/VFP state. Under UP, | |
692 | * the owner could be a task other than 'current' | |
693 | */ | |
694 | if (vfp_state_in_hw(cpu, thread)) | |
695 | vfp_save_state(&thread->vfpstate, fpexc); | |
696 | #ifndef CONFIG_SMP | |
697 | else if (vfp_current_hw_state[cpu] != NULL) | |
698 | vfp_save_state(vfp_current_hw_state[cpu], fpexc); | |
699 | #endif | |
700 | vfp_current_hw_state[cpu] = NULL; | |
701 | } | |
702 | EXPORT_SYMBOL(kernel_neon_begin); | |
703 | ||
704 | void kernel_neon_end(void) | |
705 | { | |
706 | /* Disable the NEON/VFP unit. */ | |
707 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
708 | put_cpu(); | |
709 | } | |
710 | EXPORT_SYMBOL(kernel_neon_end); | |
711 | ||
712 | #endif /* CONFIG_KERNEL_MODE_NEON */ | |
713 | ||
1da177e4 LT |
714 | /* |
715 | * VFP support code initialisation. | |
716 | */ | |
717 | static int __init vfp_init(void) | |
718 | { | |
719 | unsigned int vfpsid; | |
efe90d27 | 720 | unsigned int cpu_arch = cpu_architecture(); |
efe90d27 | 721 | |
e5b61baf TG |
722 | /* |
723 | * Enable the access to the VFP on all online CPUs so the | |
724 | * following test on FPSID will succeed. | |
725 | */ | |
c98929c0 | 726 | if (cpu_arch >= CPU_ARCH_ARMv6) |
998de4ac | 727 | on_each_cpu(vfp_enable, NULL, 1); |
1da177e4 LT |
728 | |
729 | /* | |
730 | * First check that there is a VFP that we can use. | |
731 | * The handler is already setup to just log calls, so | |
732 | * we just need to read the VFPSID register. | |
733 | */ | |
5d4cae5f | 734 | vfp_vector = vfp_testing_entry; |
b9338a78 | 735 | barrier(); |
1da177e4 | 736 | vfpsid = fmrx(FPSID); |
8e140362 | 737 | barrier(); |
5d4cae5f | 738 | vfp_vector = vfp_null_entry; |
1da177e4 | 739 | |
dc457078 | 740 | pr_info("VFP support v0.3: "); |
6c96a4a6 | 741 | if (VFP_arch) { |
dc457078 | 742 | pr_cont("not present\n"); |
6c96a4a6 SB |
743 | return 0; |
744 | /* Extract the architecture on CPUID scheme */ | |
745 | } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { | |
746 | VFP_arch = vfpsid & FPSID_CPUID_ARCH_MASK; | |
747 | VFP_arch >>= FPSID_ARCH_BIT; | |
efe90d27 | 748 | /* |
6c96a4a6 SB |
749 | * Check for the presence of the Advanced SIMD |
750 | * load/store instructions, integer and single | |
751 | * precision floating point operations. Only check | |
752 | * for NEON if the hardware has the MVFR registers. | |
efe90d27 | 753 | */ |
2b94fe2a SB |
754 | if (IS_ENABLED(CONFIG_NEON) && |
755 | (fmrx(MVFR1) & 0x000fff00) == 0x00011100) | |
6c96a4a6 | 756 | elf_hwcap |= HWCAP_NEON; |
6c96a4a6 | 757 | |
2b94fe2a SB |
758 | if (IS_ENABLED(CONFIG_VFPv3)) { |
759 | u32 mvfr0 = fmrx(MVFR0); | |
760 | if (((mvfr0 & MVFR0_DP_MASK) >> MVFR0_DP_BIT) == 0x2 || | |
761 | ((mvfr0 & MVFR0_SP_MASK) >> MVFR0_SP_BIT) == 0x2) { | |
762 | elf_hwcap |= HWCAP_VFPv3; | |
763 | /* | |
764 | * Check for VFPv3 D16 and VFPv4 D16. CPUs in | |
765 | * this configuration only have 16 x 64bit | |
766 | * registers. | |
767 | */ | |
768 | if ((mvfr0 & MVFR0_A_SIMD_MASK) == 1) | |
769 | /* also v4-D16 */ | |
770 | elf_hwcap |= HWCAP_VFPv3D16; | |
771 | else | |
772 | elf_hwcap |= HWCAP_VFPD32; | |
773 | } | |
774 | ||
775 | if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000) | |
776 | elf_hwcap |= HWCAP_VFPv4; | |
777 | } | |
6c96a4a6 SB |
778 | /* Extract the architecture version on pre-cpuid scheme */ |
779 | } else { | |
780 | if (vfpsid & FPSID_NODOUBLE) { | |
781 | pr_cont("no double precision support\n"); | |
782 | return 0; | |
18b9dc13 | 783 | } |
6c96a4a6 SB |
784 | |
785 | VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; | |
1da177e4 | 786 | } |
6c96a4a6 | 787 | |
e5b61baf | 788 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM_VFP_STARTING, |
73c1b41e | 789 | "arm/vfp:starting", vfp_starting_cpu, |
e5b61baf | 790 | vfp_dying_cpu); |
6c96a4a6 SB |
791 | |
792 | vfp_vector = vfp_support_entry; | |
793 | ||
794 | thread_register_notifier(&vfp_notifier_block); | |
795 | vfp_pm_init(); | |
796 | ||
797 | /* | |
798 | * We detected VFP, and the support code is | |
799 | * in place; report VFP support to userspace. | |
800 | */ | |
801 | elf_hwcap |= HWCAP_VFP; | |
802 | ||
803 | pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n", | |
804 | (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT, | |
805 | VFP_arch, | |
806 | (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, | |
807 | (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT, | |
808 | (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT); | |
809 | ||
1da177e4 LT |
810 | return 0; |
811 | } | |
812 | ||
0773d73d | 813 | core_initcall(vfp_init); |